Compal LA-5152P KAT00 UMA POITIER Montevina DA80000E510 0G913P Dell Studio 1745 PDF

A B C D E
Model Name: KAT00 UMA

1 PCB NO: LA-5152P 1
BOM P/N: 43169631L01
/
/x
su
2 2
Compal Confidential
p.
om
Schematic Document
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m
POITIER Montevina
//
3 3
p:
2008 / 06 / 15 Rev:1.0
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h
MB PCB
4 Part Number Description 4
DA80000E510 PCB 080 LA-5152P

REV1 UMA M/B
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A00
LA-5152P
Date: Monday, June 15, 2009 Sheet 1 of 51
A B C D E
5 4 3 2 1
Block Diagram Clock Generator

CPU ITP Port CK505
Compal confidential FAN Thermal Pentium-M ICS9LPRS387AKLFT
+1.05VS_CK505 P.7 +3VS_CK505
Model : KAT00 +5V_ALW EMC1402 Penryn -4MB (Socket P) +1.05VS_CK505
P.7 +1.5VS P.6
+3V_ALW uFCPGA CPU
+3.3V_ALW P.7 +1.05V_VCCP
+VCC_CORE 478pin P.7,8,9
D
Memory BUS (DDR3) DDRIII-DIMM X2 D
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
H_A#(3..35) H_D#(0..63) P.17,18
System Bus
CRT CONN VGA +1.5V
+5VS P.35 FSB 1066 MHz
INTEL Right Front Side. To Card-reader

LVDS CONN LVDS +1.5V 1066 MHz USB Port X1
+LCDVDD +5V_ALW subboard P.30
+3.3V_ALW P.35 Cantiga
Right behind side.
DPB +1.5VS 1329pin BGA USB Port1 X1 To Single USB
DP CONN +1.05V_VCCP
+5V_ALW
subboard P.30
+5VS P.37
/
DPC +3.3VS
HDMI P.10,11,12,13,14,15,16
Level shift Bluetooth
/x
HDMI CONN P.29
+5VS P.36 +5VS P.36
DMI
Touch Screen
su
+1.5VS P.32
C C
100MHz
To Card-reader subboard P.30
Camera
p.
P.30
USB2.0
8 IN 1 CONN +5V_ALW INTEL
S-ATA(1)
CardBus +5VS
ICH9-M Charge USB/E-SATA
om
+3VS
+RTC_CELL PCI-E
+3VS
OZ888GS0 +3.3VS
Ports X1
IEEE1394 +1.8VS 676pin BGA Azalia I/F +5V_ALW P.30
+3.3V_ALW_ICH
+1.5VS S-ATA(3)
yc
PCI Express BUS +1.05V_VCCP
P.19,20,21,22,23
Express Card SATA2 SATA1 SATA0 RTL8111DL RJ45
GPIO5
m
P.29 +3.3V_ALW P.24
LPC BUS E-ODD S-HDD-2 S-HDD-1
+3VS +3VS +3VS
FFS
PCIE3 PCIE2 PCIE1
// +3VS
+5VS P.28 +5VS P.28 +5VS P.28
33MHz
B P.20 Azalia Codec AMP Speaker
B
Mini Card 3 Mini Card 2 Mini Card 1 92HD73C MAX9736A

p:
+3.3VS B+ P.26
TV Tunner WLAN WWAN +VDDA P.25
+3VS +3VS +3VS
+1.5VS P.28 +1.5VS P.27 +1.5VS P.27 SPI Flash ROM
ENE KBC AMP
tt
P.30
MAX9736A Subwoofer
USB[x] USB[x] USB[x] KB926QFD3 16Mx1sector
AMP
h
B+ P.26
+RTC_CELL
MMB MAX4411x2
+3.3V_ALW P.30
P.32 P.25
DC IN To MMB subboard Dig. MIC

P.38
HeadPhone & P.29
MIC Jack
DC/DC Interface BATT IN 1.5V/0.75V +3.3VS
P.37~44 P.44 P.42 Int.KBD & Touch Pad
A BL P.31 P.31
A
Power Sequence ME & LED CHARGER 3V/5V

P.39 P.40 DELL CONFIDENTIAL/PROPRIETARY
P.34
1.05V/1.8V PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
P.41 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Block Diagram
LA-5152P
5 4 3 2 1
A
O MEANS ON X MEANS OFF

Voltage Rails
Symbol Note :
/
power +5VS : means Digital Ground
plane +3VS
/x
+1.8VS
+5VALW +1.5V
+1.5VS : means Analog Ground
+B
+1.1VS
+3VALW
su
+VCCP @ : means just reserve , no build
+0.75VS DEBUG@ : means just reserve for debug.
State
+CPU_CORE
p.
om
USB Port Device SATA Port Device PCIE Port Device
S0 0 0 1
1 O O O O USB&ESATA JSATA2 JWWAN1 1
1 Reader/BD 1 JSATA1 2 JWLAN1
yc
S1 2 2 3
O O O O USB board JESA1 JWPAN1
3 NC 3 JODD 4 Reader/BD (OZ888)
S3 4 5
O O O X WLAN JEXP1
m
5 WWAN 6 RTL8111DL
S5 S4/AC 6
O O X X WPAN
7 Express
S5 S4/ Battery only
//
O 8 NC
X X X 9 Touch screen
S5 S4/AC & Battery 10 Bluetooth
X X X X
p:
don't exist
11 Camera
tt
h
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Note List
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1A
LA-5152P
A
5 4 3 2 1
7700mA
D 44000mA D
VR_ON SI4392DY
ISL6266ACRZ-T +1.5VS
+CPU_CORE (Q45)
(PU10)
ADAPTER
9794mA ?mA
SYSON TPS51117RGYR SUSP# RT9026
B+ +1.5V +0.75VS
(PU8) (PU11)
BATTERY
/
/x
9857mA
SUSP# TPS51117RGYR 0 Ohm
+1.05V_VCCPP +1.05VS_CK505
(PU6)
CHARGER
su
C C
SUSP# TPS51427
(PU5)
p.
om
+5VALW +3VALW
R03 modify
R03 modify
SUSP USB_EN# EN_EOL# SUSP SUSP SUSP#
4800BDY TPS2062ADR SI3456BDY FBM-11-160808-601-T SI4392DY RT9025
yc
(Q5) (U17) (Q3) (L29) (Q50) (PU13)
4400mA
2000mA 160mA 20mA 7700mA 669mA
+LAN_IO +EC_AVCC +3VS +1.8VS
m
+5VS +5V_CHGUSB EN_EOL#
VDDEN
// RTL8111DL 0 Ohm SI2310BDS-T1-E3
B
FUSE (U9) +3VS_CK505 B
+CRT_VCC (Q25)
+LAN_VDD 0 Ohm
p:
0 Ohm +DVDD_AUDIO +LCDVDD

+AVDD_AUDIO
0 Ohm
tt
0 Ohm +3V_WLAN
+5VS_KBL
h
0 Ohm
+3V_WLAN
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
LA-5152P
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
+3VALW +3.3VS
D 2.2K 2.2K D
G16 ICH_SMBCLK ICH_SM_DA 200

2N7002 ICH_SM_CLK
A13 ICH_SMBDATA 202 DIMMA SMBUS Address 0xA0
2N7002
10K
ICH9-M 200
202 SMBUS Address 0XA4
DIMMB
10 SMBUS Address Read D3 (H)

CLK GEN
9 SMBUS Address Write D2 (H)
/
/x
FFS
4.7K
+3VALW
su
C
4.7K C
77 EC_SMB_CK1 100 ohm 7

SCL1 BATTERY
78 EC_SMB_DA1 100 ohm 6
p.
SDA1 CONN
4.7K
om
4.7K +3VS Need make sure EC will disable this SMB port in S5 /AC mode.
KBC SCL2 112 EC_SMB_CK2 32
30
WLAN SMBUS Address [TBD]
111 EC_SMB_DA2
SDA2
yc
32
KB926QFD3 4.7K 30 WPAN SMBUS Address [TBD]
m
+3VS
4.7K
32
17 EC_FB_SCLK 30
WWAN SMBUS Address [TBD]
18 EC_FB_DATA
// MMB
B B
32
EXPRESS
SMBUS Address [TBD]
p:
30 CARD
tt
8
Thermal
7 Sensor SMBUS Address: 100_1100 b
h
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SMBUS TOPOLOGY
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 3.0
LA-5152P
5 4 3 2 1
5 4 3 2 1
U1 +3VS_CK505
Routing the trace at least 10mil Level shift on ICH side. R1
+3VS 1 2
@ R4 1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2 0_0402_5%
22U_0805_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CLK_XTAL_OUT 9 CLK_SMBDATA 0_0805_5%
SDATA ICH_SM_DA <17,18,20,21>
+3VS_CK505 6 1 1 1 1 1 1 1
VDDREF
2
@ CLK_XTAL_IN
SCLK 10 CLK_SMBCLK @ R3 1 2 0_0402_5% ICH_SM_CLK <17,18,20,21>
C2
C1
C3
C4
C5
C6
C7
R2 19
0_0402_5% VDD48
@ R5 2 2 2 2 2 2 2 2
72 VDDCPU CPUT0_LPR_F 71 R_CPU_BCLK 1 0_0402_5%
CLK_CPU_BCLK <7>
1 Y1 CPU
2 1 12 70 R_CPU_BCLK# @ R6 2 1 0_0402_5%
VDDPCI CPUC0_LPR_F CLK_CPU_BCLK# <7>
14.318MHZ_16PF_7A14300083 27 +1.05V_VCCP
VDDPLL3 @ R7 1 2 0_0402_5%
22P_0402_50V8J~D
22P_0402_50V8J~D
2 2 68 R_MCH_BCLK
CPUT1_LPR_F CLK_MCH_BCLK <10> +1.05VS_CK505
55
VDDSRC MCH
@ R8 1 2 0_0402_5%
C8
D D
C9
67 R_MCH_BCLK# R13
CPUC1_LPR_F CLK_MCH_BCLK# <10>
1 2
1 1
22U_0805_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+1.05VS_CK505 52 VDDSRC_IO 0_0805_5%
24 R_MCH_DREFCLK @R10 1
@R10 2 0_0402_5% 1 1 1 1 1 1 1
SRCT0_LPR/DOTT_96_LPR CLK_MCH_DREFCLK <11>
38
C10
C11
VDDSRC_IO
C12
C14
C15
C13
C16
25 R_MCH_DREFCLK# @R12
@R12 1 2 0_0402_5% VGA (UMA)
SRCC0_LPR/DOTC_96_LPR CLK_MCH_DREFCLK# <11>
62
+3VS_CK505 VDDSRC_IO 2 2 2 2 2 2 2
31 28
VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 MCH_SSCDREFCLK <11>
66 29
VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2 MCH_SSCDREFCLK# <11>
1
1
@R548
@ R548 @ R549 23 VDD96_IO @ R42 1
10K_0402_5% 10K_0402_5%
SRCT2_LPR/SATAT_LPR 32 R_CLK_SATA 2 0_0402_5%
CLK_PCIE_SATA <19>
33 R_CLK_SATA# @ R43 1 2 0_0402_5% SATA +3VS
2
H_STP_CPU# SRCC2_LPR/SATAC_LPR CLK_PCIE_SATA# <19>

<21> H_STP_CPU# 53 CPU_STOP# EXP_CLKREQ# R34 1 2 10K_0402_5%
CPU_STP <21> H_STP_PCI# 54 35 R_CLK_EXPR @ R16 1 2 0_0402_5%
H_STP_PCI# PCI_STOP# SRCT3_LPR CLK_PCIE_EXPR <28> R32 1
WLAN_CLKREQ# 2 10K_0402_5%
36 R_CLK_EXPR# @ R17 1 2 0_0402_5% Express Card
SRCC3_LPR CLK_PCIE_EXPR# <28>
/
WWAN_CLKREQ# R25 1 2 10K_0402_5%
13 39 R_CLK_PCIE_WLAN @ R18 1 2 0_0402_5% CB_CLKREQ# R22 1 2 10K_0402_5%

PCI1 SRCT4_LPR CLK_PCIE_WLAN <27>
WLAN
/x
R941 1 2 33_0402_1% PCI2_TME 14 40 R_CLK_PCIE_WLAN#@ R19 1 2 0_0402_5% GLAN_CLKREQ# R30 1 2 10K_0402_5%
<27> CLK_DEBUG_PORT PCI2/TME SRCC4_LPR CLK_PCIE_WLAN# <27>
R20 1 2 33_0402_1% R_CLK_PCI_EC 15 WPAN_CLKREQ# R27 1 2 10K_0402_5%
<31> CLK_PCI_EC PCI3 @ R21 1
SRCT6_LPR 57 R_CLK_WAN 2 0_0402_5%
CLK_PCIE_WAN <27> R36 1
27_SEL 16 PCI4/27_SELECT WWAN MCH_CLKREQ# 2 10K_0402_5%
56 R_CLK_WAN# @ R23 1 2 0_0402_5%
su
SRCC6_LPR CLK_PCIE_WAN# <27> R29 1
R24 1 2 33_0402_1% ITP_EN 17 PCI_F5/ITP_EN
CLKSATAREQ# 2 10K_0402_5%
C <20> PCI_CLK C
61 R_CLK_CB @ R26 1 2 0_0402_5%
SRCT7_LPR CLK_PCIE_CB <30>
<21> CK_PWRGD 1 CK_PWRGD/PD# Cardbus
SRCC7_LPR 60 R_CLK_CB# @ R28 1 2 0_0402_5% CLK_PCIE_CB# <30>
R02 RF reserve part. Port Device REQ# REQ#_NAME
p.
10P_0402_50V8J~D
10P_0402_50V8J~D
1 1
C1534
C1533
CLK_XTAL_IN 5 X1 CPUT2_ITP_LPR/SRCT8_LPR 64 R_DMI_ICH @ R31 1 2 0_0402_5% SRC0 PCIE_VGA

CLK_DMI_ICH <22>
DMI (ICH)
CLK_XTAL_OUT 4
X2 CPUC2_ITP_LPR/SRCC8_LPR
63 R_DMI_ICH# @ R33 1 2 0_0402_5% CLK_DMI_ICH# <22> SRC2 PCIE_SATA REQ_A# CLKSATAREQ#
2 2
om
@ @ SRC3 PCIE_EXPR REQ#3 EXP_CLKREQ#
11 44 R_CLK_PCIE_GLAN @ R35 1 2 0_0402_5%
NC SRCT9_LPR CLK_PCIE_GLAN <24>
GLAN SRC4 PCIE_WLAN REQ#4 WLAN_CLKREQ#
45 R_CLK_PCIE_GLAN#@ R37 1 2 0_0402_5%
SRCC9_LPR CLK_PCIE_GLAN# <24>
SRC6 PCIE_WWAN REQ#6 WAN_CLKREQ#
R38 1 2 33_0402_1% FSA 20
<21> CLK_48M_ICH USB_48MHz/FSLA @ R40 1
50 R_CLK_WPAN 2 0_0402_5% SRC7 PCIE_CB REQ#7 CB_CLKREQ#
(14.318 reference output) FSB SRCT10_LPR CLK_PCIE_WPAN <28>
2
FSLB/TEST_MODE WPAN
@ R39 1 2 0_0402_5%
yc
51 R_CLK_WPAN# SRC8 DMI_ICH
R41 FSC SRCC10_LPR CLK_PCIE_WPAN# <28>
1 2 33_0402_1% 7
FSLC/TEST_SEL/REF0
<21> CLK_14M_ICH
SRC9 PCIE_GLAN REQ#9 GLAN_CLKREQ#
@ R14 1 2 0_0402_5%
10P_0402_50V8J~D
10P_0402_50V8J~D
1 @ 1 @ PAD T1 8 48 R_MCH_3GPLL
REF1 SRCT11_LPR CLK_MCH_3GPLL <11>
MCH_3GPLL SRC10 PCIE_WPAN REQ#10 WPAN_CLKREQ#
C1540
C1531
47 R_MCH_3GPLL# @ R15 1 2 0_0402_5%

SRCC11_LPR CLK_MCH_3GPLL# <11>
m
2 2
SRC11 MCH_3GPLL REQ#11 MCH_CLKREQ#
69
GNDCPU
3 37 EXP_CLKREQ# <28>
GNDREF CR#3
0 = SRC8/SRC8#
*
18
GNDPCI
// CR#4
41 WLAN_CLKREQ# <27> ITP_EN
1 = ITP/ITP#
R02 RF reserve part. 22 58
B GND48 CR#6 WWAN_CLKREQ# <27> B
30 65 27_SEL 0 = PIN 24/25 : DOT96 / DOT96#
26
GND
B version P/N :
CR7#
43
CB_CLKREQ# <30>
* PIN 28/29 : LCDCLK / LCDCLK#
0103 modify it.
p:
GND CR#9 GLAN_CLKREQ# <24>

1 = PIN 24/25 : SRC_0 / SRC_0#
34
GNDSRC
SA000020H10 CR10#
49 WPAN_CLKREQ# <28> PIN 28/29 : 27M / 27M_SS
59 46 MCH_CLKREQ# <11>
GNDSRC CR#11
0 = Overclocking of CPU and SRC Allowed
tt
42 21 @ R44 1 2 0_0402_5% PCI2_TME

GNDSRC CR#A CLKSATAREQ# <21>
1 = Overclocking of CPU and SRC NOT allowed
ICS9LPRS387BKLFT_MLF72_10x10
*
+3VS_CK505 +3VS_CK505 +3VS_CK505
h
2
R45 @ R46 @ R47
FSA R48 1 2 2.2K_0402_5% R49 1 2 1K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
FSC FSB FSA CPU SRC PCI REF DOT_96 USB MCH_CLKSEL0 <11>
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz
1
<8> CPU_BSEL0 ITP_EN 27_SEL PCI2_TME
0 0 0 266 100 33.3 14.318 96.0 48.0
* FSB R53 1 2 1K_0402_5%
MCH_CLKSEL1 <11>
2
0 0 1 133 100 33.3 14.318 96.0 48.0 R54 1
R50 R51 R52 @
<8> CPU_BSEL1 2 0_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
0 1 0 200 100 33.3 14.318 96.0 48.0 0103 modify it.
1
FSC R55 1 2 10K_0402_5% R56 1 2 1K_0402_5%
A MCH_CLKSEL2 <11> A
0 1 1 166 100 33.3 14.318 96.0 48.0
<8> CPU_BSEL2
1 0 0 333 100 33.3 14.318 96.0 48.0
1 0 1 100 100 33.3 14.318 96.0 48.0
1 1 0 400 100 33.3 14.318 96.0 48.0 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Clock Generator CK505
1 1 1 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
Reserved PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A00
LA-5152P
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP
XDP / ITP
XDP_TDI R57 1 2 54.9_0402_1%
XDP_TMS R58 1 2 54.9_0402_1%
XDP_TRST# R59 1 2 54.9_0402_1%
XDP_TCK R60 1 2 54.9_0402_1%

D D
This shall place near CPU
<10> H_A#[3..16]
CONN@
JCPU1A
Control Thermal
+1.05V_VCCP
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# <10>
1
+1.05V_VCCP
ADDR GROUP 0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# <10>
H_A#5 L4 G5 H_BPRI# @ R61
@R61
H_A#6 A[5]# BPRI# H_BPRI# <10>
K5 56_0402_5%
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# <10>
2
H_A#8 N2 F21 H_DRDY#
H_DRDY# <10>
2 2
H_A#9 A[8]# DRDY# H_DBSY# R62
J1 A[9]# DBSY# E1 H_DBSY# <10> Qual core 50 ohm
B
H_A#10 N3 49.9_0402_1%
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# <10>
E
H_A#12 P2 H_PROCHOT# 3 1 OCP#
1
A[12]# OCP# <21>
/
CONTROL
C
H_A#13 L2 D20 H_IERR# @ Q1
H_A#14 A[13]# IERR# H_INIT# H_IERR# MMBT3904_SOT23
P4 A[14]# INIT# B3 H_INIT# <19>
H_A#15 P1
H_A#16 A[15]# H_LOCK#
/x
R1 A[16]# LOCK# H4 H_LOCK# <10>
H_ADSTB#0 M1
<10> H_ADSTB#0 ADSTB[0]# H_RESET#
RESET# C1 H_RESET# <10>
H_REQ#0 K3 F3 H_RS#0 H_RS#0 <10>
<10> H_REQ#0 H_REQ#1 REQ[0]# RS[0]# H_RS#1
<10> H_REQ#1 H2 REQ[1]# RS[1]# F4 H_RS#1 <10>
H_REQ#2 K2 G3 H_RS#2 H_RS#2 <10>
<10> H_REQ#2 H_REQ#3 REQ[2]# RS[2]# H_TRDY#
J3 G2
su
<10> H_REQ#3 H_REQ#4 REQ[3]# TRDY# H_TRDY# <10>
L1
C <10> H_REQ#4
<10> H_A#[17..35] H_A#17 Y2
REQ[4]#
HIT# G6
E4
H_HIT#
H_HITM# H_HIT# <10>
+3VS
Thermal Sensor EMC1402-1-ACZL-TR C
H_A#18 A[17]# HITM# H_HITM# <10>

U5 A[18]#
H_A#19 R3 AD4
A[19]# BPM[0]#
ADDR GROUP 1
H_A#20
0.1U_0402_10V7K~D
W6 A[20]# BPM[1]# AD3 1
p.
H_A#21 U4 AD1
A[21]# BPM[2]#
XDP/ITP SIGNALS
C17
H_A#22 Y5 AC4
H_A#23 A[22]# BPM[3]# U2
U1 AC2
H_A#24 A[23]# PRDY# 2
R4 AC1
H_A#25 A[24]# PREQ# XDP_TCK
T5 AC5
A[25]# TCK
om
H_A#26 T3 AA6 XDP_TDI 1 8 EC_SMB_CK2
A[26]# TDI VDD SMCLK EC_SMB_CK2 <27,28,31>
H_A#27 W2 AB3 XDP_TDO
A[27]# TDO T2
H_A#28 W5 AB5 XDP_TMS H_THERMDA 2 7 EC_SMB_DA2
H_A#29 A[28]# TMS XDP_TRST# DP SMDATA EC_SMB_DA2 <27,28,31>
Y4 AB6
H_A#30 A[29]# TRST# XDP_DBRESET#
U2
A[30]# DBR#
C20 C18 1 2 2200P_0402_50V7K~D H_THERMDC 3 DN ALERT#
6
H_A#31 XDP_DBRESET# <21>
V4 R64
H_A#32 A[31]# CPU_THERM_STP# 4
W3 +3VS 1 2 5
H_A#33 A[32]# H_PROCHOT# R63 THERM# GND
AA4
A[33]# THERMAL 2 1 68_0402_5% +1.05V_VCCP 10K_0402_5%
yc
H_A#34 AB2
H_A#35 A[34]# CPU_THERM_STP#
AA3 D21
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA EMC1402-1-ACZL-TR_MSOP8
<10> H_ADSTB#1 V1
ADSTB[1]# THERMDA
A24
H_THERMDC
H_THERMDA, H_THERMDC
H_A20M# THERMDC
B25
routing together,Trace width / To power
<19> H_A20M# A6
A20M#
Address:100_1100
ICH
H_FERR# A5 C7 H_THERMTRIP# Spacing = 10 / 10 mil

<19> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <11,19>
m
H_IGNNE# C4 Q29
<19> H_IGNNE# IGNNE# CLK_CPU_BCLK 2N7002W-7-F_SOT323-3~D
CLK_CPU_BCLK <6>
H_STPCLK# D5 R237
<19> H_STPCLK# STPCLK#
1
D
H_INTR C6 H CLK CPU_THERM_STP# 3 1 1 2
<19> H_INTR H_NMI LINT0 MAINPWON <40,44>
<19> H_NMI B4 A22 0_0402_5%
LINT1 BCLK[0]
<19> H_SMI#
H_SMI# A3
SMI# BCLK[1]
A21 R932 Qual
100_0402_1%
core request
//
G
2
M4
2
B RSVD[01] VR_ON B
N5 <31,43> VR_ON
RSVD[02] CLK_CPU_BCLK#
T2 CLK_CPU_BCLK# <6>
RSVD[03]
V3
RSVD[04]
B2
p:
RESERVED
RSVD[05] +FAN1_POWER
C3
RSVD[06]
D2
RSVD[07] C19 +5VS
D22
D3
F6
RSVD[08]
RSVD[09] FAN Control circuit 10U_0805_10V4Z~D
2 1 1 2
tt
RSVD[10] C21 10U_0805_10V4Z~D
C20 U3
Penryn 2 1 1 8
VEN GND
h
2 7
1000P_0402_50V7K~D VIN GND
3 6
EN_DFAN1 VO GND
<31> EN_DFAN1 4 5
VSET GND
+3VS RT9027BPS_SO8
1
40mil
R65
10K_0402_5%
JFAN1
+FAN1_POWER 1
2
1
2 4
<31> FAN_SPEED1 2 G
2 3 5
3 G
C22 MOLEX_53261-0371~D
0.1U_0402_16V4Z~D CONN@
1
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Penryn(1/3)-AGTL+/ITP-XDP
LA-5152P
5 4 3 2 1
5 4 3 2 1
+CPU_CORE +CPU_CORE
CONN@
JCPU1C
A7 AB20
VCC[001] VCC[068]
A9 VCC[002] VCC[069] AB7
A10 VCC[003] VCC[070] AC7
CONN@ A12 AC9
<10> H_D#[0..15] H_D#[32..47] <10> VCC[004] VCC[071]
JCPU1B A13 AC12
H_D#0 H_D#32 VCC[005] VCC[072]
E22 D[0]# D[32]# Y22 A15 VCC[006] VCC[073] AC13
H_D#1 F24 AB24 H_D#33 A17 AC15
H_D#2 D[1]# D[33]# H_D#34 VCC[007] VCC[074]
E26 V24 A18 AC17
H_D#3 D[2]# D[34]# H_D#35 VCC[008] VCC[075]
G22 V26 A20 AC18
D[3]# D[35]# VCC[009] VCC[076]
DATA GRP 0
D H_D#4 H_D#36 D
F23 D[4]# D[36]# V23 B7 VCC[010] VCC[077] AD7
H_D#5 G25 T22 H_D#37 B9 AD9
H_D#6 D[5]# D[37]# H_D#38 VCC[011] VCC[078]
E25 D[6]# D[38]# U25 B10 VCC[012] VCC[079] AD10
H_D#7 E23 U23 H_D#39 B12 AD12
H_D#8 D[7]# D[39]# H_D#40 VCC[013] VCC[080]
K24 Y25 B14 AD14
DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[014] VCC[081]
G24 W22 B15 AD15
H_D#10 D[9]# D[41]# H_D#42 VCC[015] VCC[082]
J24 Y23 B17 AD17
H_D#11 D[10]# D[42]# H_D#43 VCC[016] VCC[083]
J23 W24 B18 AD18
H_D#12 D[11]# D[43]# H_D#44 VCC[017] VCC[084]
H22 W25 B20 AE9
H_D#13 D[12]# D[44]# H_D#45 VCC[018] VCC[085]
F26 AA23 C9 AE10
H_D#14 D[13]# D[45]# H_D#46 VCC[019] VCC[086]
K22 AA24 C10 AE12
H_D#15 D[14]# D[46]# H_D#47 VCC[020] VCC[087]
H23 D[15]# D[47]# AB25 C12 VCC[021] VCC[088] AE13
H_DSTBN#0 J26 Y26 H_DSTBN#2 C13 AE15
<10> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <10> VCC[022] VCC[089]
H_DSTBP#0 H26 AA26 H_DSTBP#2 C15 AE17
<10> H_DSTBP#0 H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2 H_DSTBP#2 <10> VCC[023] VCC[090]
<10> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <10> C17 VCC[024] VCC[091] AE18
<10> H_D#[16..31] H_D#[48..63] <10> C18 VCC[025] VCC[092] AE20
D9 VCC[026] VCC[093] AF9
H_D#16 N22 AE24 H_D#48 D10 AF10
H_D#17 D[16]# D[48]# H_D#49 VCC[027] VCC[094]
K25 D[17]# D[49]# AD24 D12 VCC[028] VCC[095] AF12
H_D#18 P26 AA21 H_D#50 D14 AF14
H_D#19 D[18]# D[50]# H_D#51 VCC[029] VCC[096]
R23 D[19]# D[51]# AB22 D15 VCC[030] VCC[097] AF15
/
H_D#20 L23 AB21 H_D#52 D17 AF17
D[20]# D[52]# VCC[031] VCC[098]
DATA GRP 1
H_D#21 M24 AC26 H_D#53 D18 AF18
H_D#22 D[21]# D[53]# H_D#54 VCC[032] VCC[099] +1.05V_VCCP
L22 D[22]# D[54]# AD20 E7 VCC[033] VCC[100] AF20
H_D#23 H_D#55
/x
M23 D[23]# D[55]# AE22 E9 VCC[034]
H_D#24 P25 AF23 H_D#56 E10 G21
H_D#25 D[24]# D[56]# H_D#57 VCC[035] VCCP[01]
220U_D2_4VY_R15M~D
P23 D[25]# D[57]# AC25 E12 VCC[036] VCCP[02] V6
H_D#26 P22 AE21 H_D#58 E13 J6
DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[037] VCCP[03]
T24 D[27]# D[59]# AD21 E15 VCC[038] VCCP[04] K6 1
H_D#28 R24 AC22 H_D#60 E17 M6
D[28]# D[60]# VCC[039] VCCP[05]
C23
H_D#29 L25 AD23 H_D#61 E18 J21 +
su
H_D#30 D[29]# D[61]# H_D#62 VCC[040] VCCP[06]
T25 D[30]# D[62]# AF22 E20 VCC[041] VCCP[07] K21
C H_D#31 H_D#63 C
N25 D[31]# D[63]# AC23 F7 VCC[042] VCCP[08] M21
H_DSTBN#1 H_DSTBN#3 2
<10> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <10> F9 VCC[043] VCCP[09] N21
H_DSTBP#1 M26 AF24 H_DSTBP#3 F10 N6
<10> H_DSTBP#1 H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 H_DSTBP#3 <10> VCC[044] VCCP[10]
<10> H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 <10> F12 VCC[045] VCCP[11] R21
F14 VCC[046] VCCP[12] R6
p.
+V_CPU_GTLREF AD26 R26 COMP0 F15 T21
TEST1 GTLREF COMP[0] COMP1 VCC[047] VCCP[13]
T3 C23 TEST1 MISC COMP[1] U26 F17 VCC[048] VCCP[14] T6
TEST2 D25 AA1 COMP2 F18 V21
T4 TEST3 TEST2 COMP[2] COMP3 VCC[049] VCCP[15]
T5 C24 Y1 F20 W21
TEST4 TEST3 COMP[3] VCC[050] VCCP[16]
T6 AF26 AA7
TEST4 VCC[051]
om
TEST5 AF1 E5 H_DPRSTP# AA9 B26
T7 TEST5 DPRSTP# H_DPRSTP# <11,19,43> VCC[052] VCCA[01] +1.5VS
TEST6 A26 B5 H_DPSLP# AA10 C26
10U_0805_6.3V6M~D
T8 TEST6 DPSLP# H_DPSLP# <19> VCC[053] VCCA[02]
0.01U_0402_16V7K~D
49.9_0402_1%
24.9_0402_1%
49.9_0402_1%
24.9_0402_1%
D24 H_DPWR# AA12
DPWR# H_DPWR# <10> VCC[054]
1
CPU_BSEL0 B22 D6 H_PWRGOOD AA13 AD6
<6> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD <19> VCC[055] VID[0] CPU_VID0 <43>
R69
R67
R68
CPU_BSEL1 H_CPUSLP#
R66
B23 D7 H_CPUSLP# <10> AA15 AF5 1 1
<6> CPU_BSEL1 CPU_BSEL2 BSEL[1] SLP# H_PSI# VCC[056] VID[1] CPU_VID1 <43>
C21 AE6 AA17 AE5
<6> CPU_BSEL2 BSEL[2] PSI# H_PSI# <43> VCC[057] VID[2] CPU_VID2 <43>
C25
C24
AA18 AF4
Penryn VCC[058] VID[3] CPU_VID3 <43>
AA20 AE3
2
VCC[059] VID[4] CPU_VID4 <43> 2 2
yc
AB9 AF3
VCC[060] VID[5] CPU_VID5 <43>
AC10 AE2
VCC[061] VID[6] CPU_VID6 <43>
AB10
VCC[062]
layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU AB12
VCC[063]
AB14 AF7 VCCSENSE Near pin B26
VCC[064] VCCSENSE VCCSENSE <43>
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs Qual core value AB15
VCC[065]
m
AB17
VCC[066] VSSSENSE
AB18 AE7
VCC[067] VSSSENSE VSSSENSE <43>
Penryn
.
//
B B
FSB BCLK BSEL2 BSEL1 BSEL0
For 8 layer condition.
533 133 0 0 1 Length match within 25 mils.
p:
The trace width/space/other

667 166 0 1 1 is 20/7/25. Zo = 27.4 ohm.
tt
800 200 0 1 0 +CPU_CORE
1067 266 0 0 0
h
R70 1 2 100_0402_1% VCCSENSE
R71 1 2 100_0402_1% VSSSENSE
Close to CPU pin

within 500mils.
+1.05V_VCCP
Close to CPU pin AD26
1
within 500mils. Zo = 55 ohm

R72
+V_CPU_GTLREF 1K_0402_1%
2
+V_CPU_GTLREF
1
A A
Cpu Quad Core, R=1.74K_0402_1% R73

1.74K_0402_1%
Cpu Dual Core, R=2K_0402_1% DELL CONFIDENTIAL/PROPRIETARY
2

LA-5152P
5 4 3 2 1
5 4 3 2 1
High Frequence Decoupling

10uF 0805 X5R -> 85 degree.
+CPU_CORE
D D
CONN@ 1 1 1 1 1 1 1 1 1 1
JCPU1D
A4 P6 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35
VSS[001] VSS[082] 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
A8 P21
VSS[002] VSS[083] 2 2 2 2 2 2 2 2 2 2
A11 P24
VSS[003] VSS[084]
A14 R2
VSS[004] VSS[085]
A16 R5
VSS[005] VSS[086]
A19 R22
VSS[006] VSS[087]
A23 R25
VSS[007] VSS[088]
AF2 T1
VSS[008] VSS[089]
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 T26 +CPU_CORE
VSS[011] VSS[092]
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21 1 1 1 1 1 1 1 1 1 1
B21 VSS[015] VSS[096] U24
B24 V2 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45
VSS[016] VSS[097] 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
C5 VSS[017] VSS[098] V5
2 2 2 2 2 2 2 2 2 2
C8 VSS[018] VSS[099] V22
/
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
/x
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 Y6 +CPU_CORE
VSS[025] VSS[106]
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 AA2 1 1 1 1 1 1
su
VSS[028] VSS[109]
D11 VSS[029] VSS[110] AA5
C C46 C47 C48 C49 C50 C51 C
D13 VSS[030] VSS[111] AA8
D16 AA11 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
VSS[031] VSS[112] 2 2 2 2 2 2
D19 VSS[032] VSS[113] AA14
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
p.
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 AB1
VSS[037] VSS[118]
E11 AB4
VSS[038] VSS[119]
E14 AB8
VSS[039] VSS[120]
om
E16 AB11 +CPU_CORE
VSS[040] VSS[121]
E19 AB13
VSS[041] VSS[122]
E21 AB16
VSS[042] VSS[123]
E24 AB19 1 1 1 1 1 1
VSS[043] VSS[124]
F5 AB23
VSS[044] VSS[125] C52 C53 C54 C55 C56 C57
F8 AB26
VSS[045] VSS[126] 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
F11 AC3
VSS[046] VSS[127] 2 2 2 2 2 2
F13 AC6
VSS[047] VSS[128]
yc
F16 AC8
VSS[048] VSS[129]
F19 AC11
VSS[049] VSS[130]
F2 AC14
VSS[050] VSS[131]
F22 AC16
VSS[051] VSS[132]
F25 AC19
VSS[052] VSS[133]
G4 AC21
VSS[053] VSS[134]
m
G1 AC24
VSS[054] VSS[135]
G23 AD2
VSS[055] VSS[136] +CPU_CORE
G26 AD5
VSS[056] VSS[137]
H3 AD8
H6
VSS[057] VSS[138]
AD11 ESR <= 1.5m ohm
VSS[058] VSS[139]
H21
VSS[059] VSS[140]
AD13
//
330U_D2E_2.5VM_R9~D
330U_D2E_2.5VM_R9~D
330U_D2E_2.5VM_R9~D
330U_D2E_2.5VM_R9~D
H24 AD16
J2
VSS[060] VSS[141]
AD19 1 1 1 1
Capacitor > 880 uF
B VSS[061] VSS[142] B
J5 AD22
VSS[062] VSS[143]
C58
C59
C60
C61
J22 AD25 + + + +
VSS[063] VSS[144]
J25 AE1
VSS[064] VSS[145]
K1 AE4
p:
VSS[065] VSS[146] 2 2 2 2
K4 AE8
VSS[066] VSS[147]
K23 AE11
VSS[067] VSS[148]
K26 AE14
VSS[068] VSS[149]
L3 AE16
VSS[069] VSS[150]
L6 AE19
tt
VSS[070] VSS[151]
L21 AE23
VSS[071] VSS[152]
L24 AE26
VSS[072] VSS[153]
M2 A2
VSS[073] VSS[154]
M5 AF6
VSS[074] VSS[155]
h
M22 AF8
VSS[075] VSS[156]
M25 AF11
VSS[076] VSS[157]
N1 AF13
VSS[077] VSS[158] +1.05V_VCCP
N4 AF16
VSS[078] VSS[159]
N23 AF19
VSS[079] VSS[160]
N26 AF21
VSS[080] VSS[161]
P3 A25
VSS[081] VSS[162]
AF25 1 1 1 1 1 1
VSS[163]
Penryn C62 C63 C64 C65 C66 C67
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
2 2 2 2 2 2
A A
LA-5152P
5 4 3 2 1
5 4 3 2 1
H_A#[3..35] <7>
U4A
<8> H_D#[0..63]
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
Layout Note : H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
D F8 H_D#_2 H_A#_6 H13 D
H_RCOMP / H_VREF / H_SWNG H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
Trace width and spacing is 10 / 20 G2 H_D#_4 H_A#_8 M16
H_D#5 H6 J13 H_A#9
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
+1.05V_VCCP H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
1
H_D#15 J6 J16 H_A#19
R74 H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
221_0402_1% H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
2
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_SW NG H_D#21 H_A#25
/
0.1U_0402_10V7K~D M5 H_D#_21 H_A#_25 B17
H_D#22 J3 L16 H_A#26
H_D#23 H_D#_22 H_A#_26 H_A#27
Near C5 pin 1
N2 H_D#_23 H_A#_27 C21
75_0402_1%
/x
1 H_D#24 R1 J17 H_A#28
H_D#25 H_D#_24 H_A#_28 H_A#29
R75 Qual core N5 H_D#_25 H_A#_29 H20
C68
H_D#26 N6 B18 H_A#30

H_D#27 H_D#_26 H_A#_30 H_A#31
P13 H_D#_27 H_A#_31 K17
2 H_D#28 H_A#32
N8 B20
2
H_D#29 H_D#_28 H_A#_32 H_A#33

L7 H_D#_29 H_A#_33 F21
su
H_D#30 N10 K21 H_A#34
C H_D#31 H_D#_30 H_A#_34 H_A#35 C
M3 H_D#_31 H_A#_35 L20
H_D#32 Y3
H_D#33 H_D#_32 H_ADS#
AD14 H_D#_33 H_ADS# H12 H_ADS# <7>
H_D#34 Y6 B16 H_ADSTB#0 H_ADSTB#0 <7>
H_D#35 H_D#_34 H_ADSTB#_0 H_ADSTB#1
Y10 G17
p.
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <7>
R76 1 2 16.9_0402_1% H_RCOMP H_D#36 Y12 A9 H_BNR# H_BNR# <7>
H_D#_36 H_BNR#
HOST
H_D#37 Y14 F11 H_BPRI#
H_D#38 H_D#_37 H_BPRI# H_BR0# H_BPRI# <7>
Qual core H_D#39
Y7 H_D#_38 H_BREQ# G12
H_DEFER#
H_BR0# <7>
W2 H_D#_39 H_DEFER# E9 H_DEFER# <7>
om
H_D#40 AA8 B10 H_DBSY#
+1.05V_VCCP H_D#_40 H_DBSY# H_DBSY# <7>
H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK <6>
H_D#42 AA13 AH6 CLK_MCH_BCLK# CLK_MCH_BCLK# <6>
H_D#43 H_D#_42 HPLL_CLK# H_DPW R#
AA9 H_D#_43 H_DPWR# J11 H_DPW R# <8>
H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# <7>
1
H_D#45 AD11 H9 H_HIT# H_HIT# <7>

R77 H_D#46 H_D#_45 H_HIT# H_HITM#
AD10 H_D#_46 H_HITM# E12 H_HITM# <7>
1K_0402_1% H_D#47 AD13 H11 H_LOCK#
yc
H_D#_47 H_LOCK# H_LOCK# <7>
H_D#48 AE12 C9 H_TRDY#
H_D#49 H_D#_48 H_TRDY# H_TRDY# <7>
AE9
2
H_D#50 H_D#_49
AA2 H_D#_50
+H_VREF H_D#51 AD8
H_D#52 H_D#_51
AA3
m
H_D#53 H_D#_52 H_DINV#0
AD3 H_D#_53 H_DINV#_0 J8 H_DINV#0 <8>
1
H_D#54 AD7 L3 H_DINV#1

@1 R78 H_D#55 H_D#_54 H_DINV#_1 H_DINV#2
H_DINV#1 <8>
AE14 H_D#_55 H_DINV#_2 Y13 H_DINV#2 <8>
C69 2K_0402_1% H_D#56 AF3 Y1 H_DINV#3
H_D#_56 H_DINV#_3 H_DINV#3 <8>
0.1U_0402_10V7K~D H_D#57
2
// H_D#58
AC1
AE3
H_D#_57
L10 H_DSTBN#0 H_DSTBN#0 <8>
2
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1

AC3 H_D#_59 H_DSTBN#_1 M7 H_DSTBN#1 <8>
B H_D#60 H_DSTBN#2 B
AE11 H_D#_60 H_DSTBN#_2 AA5 H_DSTBN#2 <8>
H_D#61 AE8 AE6 H_DSTBN#3 H_DSTBN#3 <8>
H_D#62 H_D#_61 H_DSTBN#_3
AG2 H_D#_62
p:
H_D#63 AD6 L9 H_DSTBP#0 H_DSTBP#0 <8>

H_D#_63 H_DSTBP#_0 H_DSTBP#1
Within 100 mils from NB H_DSTBP#_1 M8
H_DSTBP#2
H_DSTBP#1 <8>
H_DSTBP#_2 AA6 H_DSTBP#2 <8>
H_SW NG C5 AE5 H_DSTBP#3 H_DSTBP#3 <8>
H_RCOMP H_SWING H_DSTBP#_3
E3 H_RCOMP
tt
B15 H_REQ#0
H_REQ#_0 H_REQ#0 <7>
K13 H_REQ#1
F13 H_REQ#2
H_RCOMP Dual core 24.9 ohm_1% pull down B13 H_REQ#3
h

<7> H_RESET# H_RESET# C12 B14 H_REQ#4
Qual core 16.9 ohm_1% pull down H_CPURST# H_REQ#_4 H_REQ#4 <7>
H_CPUSLP# E11
<8> H_CPUSLP# H_CPUSLP#
B6 H_RS#0
H_SWNG Dual core 100 ohm_1% pull down H_RS#_0 H_RS#1
H_RS#0 <7>
H_RS#_1 F12 H_RS#1 <7>
Qual core 75 ohm_1% pull down A11 H_AVREF H_RS#_2 C8 H_RS#2
H_RS#2 <7>
+H_VREF B11 H_DVREF
CANTIGA ES_FCBGA1329
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cantiga(1 of 7)
LA-5152P
5 4 3 2 1
5 4 3 2 1
U4B
M_CLK_DDR0
T10
T11
M36
N36
RSVD1 SA_CK_0
AP24
AT21 M_CLK_DDR1 M_CLK_DDR0 <17> Compensation
RSVD2 SA_CK_1 M_CLK_DDR1 <17>
T12 R33 AV24 M_CLK_DDR2 DDR3
RSVD3 SB_CK_0 M_CLK_DDR2 <18>
T20 T33 AU20 M_CLK_DDR3
RSVD4 SB_CK_1 M_CLK_DDR3 <18>
COMPENSATION
T21 AH9
RSVD5 M_CLK_DDR#0 +1.5V
T22 AH10 RSVD6 SA_CK#_0 AR24 M_CLK_DDR#0 <17>
AH12 AR21 M_CLK_DDR#1
T23 RSVD7 SA_CK#_1 M_CLK_DDR#1 <17> R83 2
T13 AH13 AU24 M_CLK_DDR#2
M_CLK_DDR#2 <18>
SMRCOMP 180.6_0402_1%
RSVD8 SB_CK#_0 M_CLK_DDR#3
T24 K12 RSVD9 SB_CK#_1 AV20 M_CLK_DDR#3 <18>
CFG AL34 SMRCOMP# R84 2 1 80.6_0402_1%
T14 RSVD10
AK34 BC28 DDR_CKE0_DIMMA
T25 RSVD11 SA_CKE_0 DDR_CKE0_DIMMA <17>
T15 AN35 AY28 DDR_CKE1_DIMMA
RSVD12 SA_CKE_1 DDR_CKE1_DIMMA <17>
@R79 1
@R79 2 2.21K_0402_1% CFG5 AM35 AY36 DDR_CKE2_DIMMB
D T26 RSVD13 SB_CKE_0 DDR_CKE2_DIMMB <18> D
T24 BB36 DDR_CKE3_DIMMB
T27 RSVD14 SB_CKE_1 DDR_CKE3_DIMMB <18>
@R85 1
@R85 2 2.21K_0402_1% CFG6
BA17 DDR_CS0_DIMMA#
SA_CS#_0 DDR_CS0_DIMMA# <17>
@R80 1
@R80 2 2.21K_0402_1% CFG7 AY16 DDR_CS1_DIMMA# DDR3
SA_CS#_1 DDR_CS2_DIMMB# DDR_CS1_DIMMA# <17>
T28 B31 AV16 DDR_CS2_DIMMB# <18>
@R86
@R86 1 2.21K_0402_1% CFG9 RSVD15 SB_CS#_0 DDR_CS3_DIMMB#
2 T16 B2
RSVD16 SB_CS#_1
AR13 DDR_CS3_DIMMB# <18> +1.5V
DDR CLK/ CONTROL/

T17 M1
RSVD17
RSVD
@R81
@R81 1 2 2.21K_0402_1% CFG16 BD17 M_ODT0_DIMMA
SA_ODT_0 M_ODT1_DIMMA M_ODT0_DIMMA <17>
AY17 M_ODT1_DIMMA <17>
SA_ODT_1
1
1K_0402_1%
CFG[5:16] have internal pullup T18 AY21 BF15 M_ODT2_DIMMB
RSVD20 SB_ODT_O M_ODT3_DIMMB M_ODT2_DIMMB <18>
AY13
R82
SB_ODT_1 M_ODT3_DIMMB <18>
BG22 SMRCOMP
SM_RCOMP SMRCOMP#
T29 BG23 BH21
2
RSVD22 SM_RCOMP# SMRCOMP_VOH
T19 BF23 RSVD23
+3VS
2.2U_0603_6.3V6K~D
0.01U_0402_16V7K~D
T30 BH18 BF28 SMRCOMP_VOH
RSVD24 SM_RCOMP_VOH SMRCOMP_VOL +V_DDR_MCH_REF
T31 BF18 RSVD25 SM_RCOMP_VOL BH28 1 1
@ R87 1 2 4.02K_0402_1% CFG19
3.01K_0402_1%
C71
1
C70
SM_VREF AV42 +V_DDR_MCH_REF
@ R88 1 4.02K_0402_1% CFG20 AR36 SM_PWROK
0.1U_0402_10V7K~D
2
SM_PWROK 2 2
R89
BF17 R90 1 2 499_0402_1%
SM_REXT
/
CFG[19:20] have internal pulldown SM_DRAMRST# BC36 DDR3_DRAMRST# DDR3_DRAMRST# <17,18> 1
C72
2
CLK_MCH_DREFCLK
/x
DPLL_REF_CLK B38 CLK_MCH_DREFCLK <6>
A38 CLK_MCH_DREFCLK# 2 SMRCOMP_VOL
DPLL_REF_CLK# CLK_MCH_DREFCLK# <6>
2.2U_0603_6.3V6K~D
0.01U_0402_16V7K~D
E41 MCH_SSCDREFCLK
Strap Pin Table DPLL_REF_SSCLK MCH_SSCDREFCLK <6>
1
1K_0402_1%
F41 MCH_SSCDREFCLK# MCH_SSCDREFCLK# <6> 1 1
DPLL_REF_SSCLK#
CLK
R91
C74
C73
Low = DMI x 2 F43 CLK_MCH_3GPLL CLK_MCH_3GPLL <6> Reserve for UMA
PEG_CLK CLK_MCH_3GPLL#
CFG5 DMI X2 Select E43 CLK_MCH_3GPLL# <6>
su
PEG_CLK# 2 2
High = DMI x 4 (Default)
2
C C
iTPM Host Low = iTPM enable

CFG6 AE41 DMI_MRX_ITX_N0
Interface High = iTPM disable(Defult)
DMI_RXN_0
AE37 DMI_MRX_ITX_N1 DMI_MRX_ITX_N0 <22>
DMI_RXN_1 DMI_MRX_ITX_N2 DMI_MRX_ITX_N1 <22>
DMI_RXN_2 AE47 DMI_MRX_ITX_N2 <22>
p.
Management Low = TLS cipher suite with no confidentiality AH39 DMI_MRX_ITX_N3
DMI_RXN_3 DMI_MRX_ITX_N3 <22>
CFG7 Engine Crypto High = TLS cipher suite with AE40 DMI_MRX_ITX_P0
DMI_RXP_0 DMI_MRX_ITX_P0 <22>
Strap confidentiality(Default) <6> MCH_CLKSEL0 T25
CFG_0 DMI_RXP_1
AE38 DMI_MRX_ITX_P1
DMI_MRX_ITX_P1 <22>
R25 AE48 DMI_MRX_ITX_P2
<6> MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_MRX_ITX_P2 <22>
om
PCI Express Low = Reverse Lane P25 AH40 DMI_MRX_ITX_P3 Use for DDR3 signls, +3VALW
<6> MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_MRX_ITX_P3 <22>
CFG9 Graphic Lane T32 P20
CFG_3 if support DDR2 need
High = Normal Operation(Default) P24 AE35 DMI_MTX_IRX_N0
T33 CFG_4 DMI_TXN_0 DMI_MTX_IRX_N0 <22>
CFG5 DMI_MTX_IRX_N1 connect to GND C75 1 20.1U_0402_10V7K~D
DMI
C25 AE43 DMI_MTX_IRX_N1 <22>
CFG6 CFG_5 DMI_TXN_1 DMI_MTX_IRX_N2
N24 AE46 DMI_MTX_IRX_N2 <22>
CFG7 CFG_6 DMI_TXN_2 DMI_MTX_IRX_N3
FSB Dynamic Low=Dynamic ODT Disable M24
CFG_7 DMI_TXN_3
AH42 DMI_MTX_IRX_N3 <22>
5
CFG
CFG16 T34 E21 R92 U5
ODT High=Dynamic ODT Enable(default) CFG9 C23
CFG_8
AD35 DMI_MTX_IRX_P0 12K_0402_1% 1
P
CFG_9 DMI_TXP_0 DMI_MTX_IRX_P0 <22> IN1 1.5V_PGOOD <42>
yc
DMI_MTX_IRX_P1 SM_PWROK
T35 C24
CFG_10 DMI_TXP_1
AE44 DMI_MTX_IRX_P1 <22> 1 2 4
O R94 @
CFG19 DMI Lane Low=Normal (default) N21 AF46 DMI_MTX_IRX_P2 2 2 1
T36 CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 <22> IN2 SLP_S4# <21,31>
G
1
10K_0402_5%
P21 AH43 DMI_MTX_IRX_P3 0_0402_5%
Reversal T37 CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 <22>
High=Lane Reversed T38 T21
R93
3
CFG_13 74AHC1G08GW_SOT353-5~D
T39 R20
CFG_14
Low=Only digital display port (SDVO/DP/iHDMI) or T40 M20
CFG_15
m
Digital Display CFG16 L21
PCIe is operational (default)
2
CFG_16
CFG20 Port T41 H21
CFG_17
High = Digital display port (SDVO/DP/iHDMI) and T42 P29
GRAPHICS VID
CFG_18
Concurrent PCIe are operating simultaneously via the PEG
CFG19 R28
CFG_19 Follow MiniCooper
CFG20 T28 B33 GFX_VID0
Operation CFG_20 GFX_VID_0 T43
port
// GFX_VID_1
GFX_VID_2
B32
G33
GFX_VID1
GFX_VID2
T44
T45
SDVO_CRTL_DATA Low=No SDVO Device Present F33 GFX_VID3
B GFX_VID_3 T46 B
PM_SYNC# R29 E33 GFX_VID4 T47
(default) <21> PM_SYNC#
H_DPRSTP# B7
PM_SYNC# GFX_VID_4
<8,19,43> H_DPRSTP# PM_EXTTS#0 PM_DPRSTP#
High=SDVO Device Present <17> PM_EXTTS#0 N33
PM_EXT_TS#_0
PM
PM_EXTTS#1 P32
p:
<18> PM_EXTTS#1 PM_EXT_TS#_1

Low=DisplayPort disabled (default) PM_PWROK_R AT40 C34 GFX_VR_ON T48
PLT_RST#_NB PWROK GFX_VR_EN
DDPC_CTRLDATA AT11
RSTIN# +1.05V_VCCP
High=DisplayPort device present <7,19> H_THERMTRIP# H_THERMTRIP# T20
DPRSLPVR THERMTRIP#
<21,43> DPRSLPVR R32
DPRSLPVR
tt
1
BG48 AH37 CL_CLK0 R95
NC_1 CL_CLK CL_CLK0 <21>
PM BF48 AH36 CL_DATA0 1K_0402_1%
NC_2 CL_DATA CL_DATA0 <21>
ME
BD48 AN36 M_PWROK
NC_3 CL_PWROK M_PWROK <21>
h
BC48 AJ35 CL_RST#

CL_RST# <21>
2
NC_4 CL_RST# +CL_VREF
BH47 AH34
R96 2 NC_5 CL_VREF
1 10K_0402_5%
0.1U_0402_10V7K~D
PM_EXTTS#0 BG47
+3VS NC_6
BE47 R03 modify it.
NC_7
2
R97 2 1 10K_0402_5%
511_0402_1%
PM_EXTTS#1 BH46 N28 HDMI_C_CLK 1
+3VS NC_8 DDPC_CTRLCLK HDMI_C_CLK <36>
R98
NC
BF46 M28 HDMI_C_DATA

NC_9 DDPC_CTRLDATA HDMI_C_DATA <36>
C76
BG45 G36 HDMI_B_CLK
NC_10 SDVO_CTRLCLK HDMI_B_CLK <37>
BH44 E36 HDMI_B_DATA
NC_11 SDVO_CTRLDATA HDMI_B_DATA <37> 2
@ BH43 K36 MCH_CLKREQ#
MCH_CLKREQ# <6>
1
NC_12 CLKREQ#
MISC
R99 2 1 0_0402_5% PM_PWROK_R BH6 H36 MCH_ICH_SYNC#

<21,31> ICH_PWROK NC_13 ICH_SYNC# MCH_ICH_SYNC# <21>
BH5
NC_14
<21,31,43> VGATE
@R100
@R100 2 1 0_0402_5% BG4
NC_15 MCH_TSATN# R101 1
BH3 B12 2 56_0402_5% +1.05V_VCCP
NC_16 TSATN#
BF3
R102 2 PLT_RST#_NB NC_17
<20,27,30,31> PLT_RST# 1 100_0402_5% BH2 Thermal Sensor Aux Trip Notification: Output from the
NC_18
BG2
NC_19 R103 (G)MCH to the EC indicating the Aux2 trip point (SW
BE2 B28 MCH_HDA_BITCLK 2 1 33_0402_1% HDA_BITCLK_NB <19>
NC_20 HDA_BCLK R104
BG1 B30 MCH_HDA_RST# 2 1 33_0402_1% HDA_RST_NB# <19> programmable) has been crossed.
NC_21 HDA_RST# MCH_HDA_SDIN2_R R105
BF1 NC_22 HDA_SDI B29 2 1 0_0402_5% HDA_SDIN1 <19>
A
BD1 NC_23 HDA_SDO C29 MCH_HDA_SDOUT R106 2 1 33_0402_1% HDA_SDOUT_NB <19>
(If not used, terminated 56 ohm pull up to VCCP) A
BC1 A28 MCH_HDA_SYNC R107 2 1 33_0402_1%
HDA
NC_24 HDA_SYNC HDA_SYNC_NB <19>

F1 NC_25
A47 12.30 modify it
@ C957 1 2 0.1U_0402_10V7K~D H_DPRSTP# NC_26 DELL CONFIDENTIAL/PROPRIETARY
Reserve for CPU, reference HPB For HDA UMA support 1.5V
LA-5152P
5 4 3 2 1
5 4 3 2 1
Note: All LVDS data

+VCC_PEG
signals/and it's compliments
should be routed Place the resistor within 500mils of the GMCH
Differentially PEGCOMP trace widht and spacing is 20/25 mils.
2
D D
R108
U4C 49.9_0402_1%
check it VGA_PWM L32
<35> VGA_PWM
1
GMCH_ENBKL L_BKLT_CTRL PEGCOMP
G32 T37
<31> GMCH_ENBKL R551 1 L_BKLT_EN PEG_COMPI
+3VS 2 10K_0402_5% M32 T36
R550 1 L_CTRL_CLK PEG_COMPO
2 10K_0402_5% M33
L_CTRL_DATA
<35> LVDS_DDC_CLK K33
L_DDC_CLK
<35> LVDS_DDC_DATA J33 H44
GM_ENVDD L_DDC_DATA PEG_RX#_0
<35> GM_ENVDD M29 J46
L_VDD_EN PEG_RX#_1 DPB_AUX#
PEG_RX#_2 L44
R109 1 DPB_AUX# <37>
2 2.4K_0402_1% C44 LVDS_IBG PEG_RX#_3 L40
For Cantiga:2.4kohm B43 LVDS_VBG PEG_RX#_4 N41
E37 LVDS_VREFH PEG_RX#_5 P48
E38 LVDS_VREFL PEG_RX#_6 N44
PEG_RX#_7 T43
LVDS_ACLK- C41 U43
<35> LVDS_ACLK- LVDS_ACLK+ LVDSA_CLK# PEG_RX#_8
C40 LVDSA_CLK PEG_RX#_9 Y43
R02 modify <35> LVDS_ACLK+ LVDS_BCLK- B37 LVDSB_CLK# PEG_RX#_10 Y48
<35> LVDS_BCLK- LVDS_BCLK+
<35> LVDS_BCLK+ A37 LVDSB_CLK PEG_RX#_11 Y36
/
LVDS
PEG_RX#_12 AA43
LVDS_A0- H47 AD37
<35> LVDS_A0- LVDS_A1- LVDSA_DATA#_0 PEG_RX#_13
E46 LVDSA_DATA#_1 PEG_RX#_14 AC47
<35> LVDS_A1- LVDS_A2-
/x
G40 LVDSA_DATA#_2 PEG_RX#_15 AD39
<35> LVDS_A2-
A40 LVDSA_DATA#_3
PEG_RX_0 H43
LVDS_A0+ H48 J44
<35> LVDS_A0+ LVDS_A1+ LVDSA_DATA_0 PEG_RX_1 DPB_AUX
D45 LVDSA_DATA_1 PEG_RX_2 L43
<35> LVDS_A1+ LVDS_A2+ DPB_HPD# DPB_AUX <37>
F40 L41
GRAPHICS
<35> LVDS_A2+ LVDSA_DATA_2 PEG_RX_3 DPB_HPD# <37>
For UMA use B40 N40
su
LVDSA_DATA_3 PEG_RX_4
PEG_RX_5 P47
C LVDS_B0- C
A41 LVDSB_DATA#_0 PEG_RX_6 N43
<35> LVDS_B0- LVDS_B1- HDC_HPD#
H38 LVDSB_DATA#_1 PEG_RX_7 T42
<35> LVDS_B1- LVDS_B2- HDC_HPD# <36>
G37 LVDSB_DATA#_2 PEG_RX_8 U42
<35> LVDS_B2-
J37 LVDSB_DATA#_3 PEG_RX_9 Y42
PEG_RX_10 W47
p.
LVDS_B0+ B42 Y37
<35> LVDS_B0+ LVDS_B1+ LVDSB_DATA_0 PEG_RX_11
G38 LVDSB_DATA_1 PEG_RX_12 AA42
<35> LVDS_B1+ LVDS_B2+ F37 AD36
<35> LVDS_B2+ LVDSB_DATA_2 PEG_RX_13
K37 AC48
LVDSB_DATA_3 PEG_RX_14
PCI-EXPRESS
AD40
PEG_RX_15
om
J41 DPB_LANE_N0 C78 1 2 0.1U_0402_10V7K~D
PEG_TX#_0 DPB_LANE_N1 C80 0.1U_0402_10V7K~D DPB_LANE_N0_C <37>
M46 1 2
R1536 1 TVA_DAC PEG_TX#_1 DPB_LANE_N2 DPB_LANE_N1_C <37>
2 75_0402_1% F25 M47 C82 1 2 0.1U_0402_10V7K~D
R1537 1 TVB_DAC TVA_DAC PEG_TX#_2 DPB_LANE_N3 DPB_LANE_N2_C <37>
2 75_0402_1% H25
TVB_DAC PEG_TX#_3
M40 C84 1 2 0.1U_0402_10V7K~D
R1538 1 TVC_DAC HDC_DATA_N2 DPB_LANE_N3_C <37>
2 75_0402_1% K25 M42 C86 1 2 0.1U_0402_10V7K~D
TVC_DAC PEG_TX#_4 HDC_DATA_N1 C88 0.1U_0402_10V7K~D HDC_DATA_N2_C <36>
R48 1 2
PEG_TX#_5 HDC_DATA_N1_C <36>
TV
H24 N38 HDC_DATA_N0 C90 1 2 0.1U_0402_10V7K~D
TV_RTN PEG_TX#_6 HDC_DATA_N0_C <36>
yc
12.30 modify it T40 HDC_CLK_N C92 1 2 0.1U_0402_10V7K~D
PEG_TX#_7 HDC_CLK_N_C <36>
U37
PEG_TX#_8
U40
PEG_TX#_9
C31 Y40
TV_DCONSEL_0 PEG_TX#_10
E32 AA46
TV_DCONSEL_1 PEG_TX#_11
AA37
PEG_TX#_12
m
AA40
PEG_TX#_13
AD43
PEG_TX#_14
AC46
Layout Note: Place 150 Ω termination PEG_TX#_15
VGA_CRT_B DPB_LANE_P0 C77 0.1U_0402_10V7K~D
resistors close to GMCH <35> VGA_CRT_B
E28
CRT_BLUE PEG_TX_0
J42 1 2
DPB_LANE_P0_C <37>
R113 1 2 150_0402_1% VGA_CRT_R
<35> VGA_CRT_G
// VGA_CRT_G G28
CRT_GREEN
PEG_TX_1
PEG_TX_2
L46
M48
DPB_LANE_P1
DPB_LANE_P2
C79
C81
1
1
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D DPB_LANE_P1_C <37>
DPB_LANE_P2_C <37>
R114 1 2 150_0402_1% VGA_CRT_G M39 DPB_LANE_P3 C83 1 2 0.1U_0402_10V7K~D
PEG_TX_3 DPB_LANE_P3_C <37>
VGA
B R115 1 150_0402_1% VGA_CRT_B VGA_CRT_R HDC_DATA_P2 C85 0.1U_0402_10V7K~D B
2 J28
CRT_RED PEG_TX_4
M43 1 2
<35> VGA_CRT_R HDC_DATA_P1 C87 0.1U_0402_10V7K~D HDC_DATA_P2_C <36>
R47 1 2
PEG_TX_5 HDC_DATA_P0 0.1U_0402_10V7K~D HDC_DATA_P1_C <36>
G29 N37 C89 1 2
CRT_IRTN PEG_TX_6 HDC_CLK_P C91 0.1U_0402_10V7K~D HDC_DATA_P0_C <36>
T39 1 2
p:
CRT_DDC_CLK PEG_TX_7 HDC_CLK_P_C <36>

<35> CRT_DDC_CLK H32 U36
CRT_DDC_DATA CRT_DDC_CLK PEG_TX_8
R116 <35> CRT_DDC_DATA J32 U39
CRT_HSYNC CRT_DDC_DATA PEG_TX_9
J29 Y39
<35> CRT_HSYNC_R CRT_IREF CRT_HSYNC PEG_TX_10
30_0402_1% E29 Y46
CRT_TVO_IREF PEG_TX_11
AA36
20mil
tt
PEG_TX_12
R117 AA39
CRT_VSYNC PEG_TX_13
L29 AD42
<35> CRT_VSYNC_R CRT_VSYNC PEG_TX_14
30_0402_1% AD46
PEG_TX_15
1
h
R118 CANTIGA ES_FCBGA1329

1K_0402_1%
2
01.06 modify it
A A
LA-5152P
5 4 3 2 1
5 4 3 2 1
D D
<17> DDR_A_D[0..63]
U4D
DDR_A_D0 <18> DDR_B_D[0..63]
AJ38 SA_DQ_0 SA_BS_0 BD21 DDR_A_BS0 DDR_A_BS0 <17>
U4E
DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D0 AK47 BC16 DDR_B_BS0
SA_DQ_1 SA_BS_1 DDR_A_BS1 <17> SB_DQ_0 SB_BS_0 DDR_B_BS0 <18>
DDR_A_D2 AN38 AT25 DDR_A_BS2 DDR_B_D1 AH46 BB17 DDR_B_BS1
DDR_A_D3 SA_DQ_2 SA_BS_2 DDR_A_BS2 <17> DDR_B_D2 SB_DQ_1 SB_BS_1 DDR_B_BS2 DDR_B_BS1 <18>
AM38 SA_DQ_3 AP47 SB_DQ_2 SB_BS_2 BB33 DDR_B_BS2 <18>
DDR_A_D4 AJ36 BB20 DDR_A_RAS# DDR_B_D3 AP46
DDR_A_D5 SA_DQ_4 SA_RAS# DDR_A_RAS# <17> SB_DQ_3
AJ40 SA_DQ_5 SA_CAS# BD20 DDR_A_CAS# DDR_A_CAS# <17>
DDR_B_D4 AJ46 SB_DQ_4
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
DDR_A_D7 SA_DQ_6 SA_WE# DDR_A_WE# <17> DDR_B_D6 SB_DQ_5 SB_RAS# DDR_B_CAS# DDR_B_RAS# <18>
AM42 SA_DQ_7 AM48 SB_DQ_6 SB_CAS# BG16 DDR_B_CAS# <18>
DDR_A_D8 AN43 DDR_B_D7 AP48 BF14 DDR_B_WE#
SA_DQ_8 SB_DQ_7 SB_WE# DDR_B_WE# <18>
DDR_A_D9 AN44 DDR_B_D8 AU47
SA_DQ_9 SB_DQ_8
/
DDR_A_D10 AU40 DDR_B_D9 AU46
DDR_A_D11 SA_DQ_10 DDR_B_D10 SB_DQ_9
AT38 SA_DQ_11 DDR_A_DM[0..7] <17> BA48 SB_DQ_10
DDR_A_D12 AN41 DDR_B_D11 AY48
DDR_A_D13 SA_DQ_12 DDR_A_DM0 DDR_B_D12 SB_DQ_11
/x
AN39 SA_DQ_13 SA_DM_0 AM37 AT47 SB_DQ_12
DDR_A_D14 AU44 AT41 DDR_A_DM1 DDR_B_D13 AR47
DDR_A_D15 SA_DQ_14 SA_DM_1 DDR_A_DM2 DDR_B_D14 SB_DQ_13 DDR_B_DM[0..7] <18>
AU42 SA_DQ_15 SA_DM_2 AY41 BA47 SB_DQ_14
DDR_A_D16 AV39 AU39 DDR_A_DM3 DDR_B_D15 BC47 AM47 DDR_B_DM0
DDR_A_D17 SA_DQ_16 SA_DM_3 DDR_A_DM4 DDR_B_D16 SB_DQ_15 SB_DM_0 DDR_B_DM1
AY44 SA_DQ_17 SA_DM_4 BB12 BC46 SB_DQ_16 SB_DM_1 AY47
DDR_A_D18 BA40 AY6 DDR_A_DM5 DDR_B_D17 BC44 BD40 DDR_B_DM2
BD43 AT7 BG43 BF35
su
AV41 SA_DQ_20 SA_DM_7 AJ5 BF43 SB_DQ_19 SB_DM_4 BG11
C DDR_A_D21 DDR_B_D20 DDR_B_DM5 C
AY43 SA_DQ_21 BE45 SB_DQ_20 SB_DM_5 BA3
DDR_A_D22 DDR_B_D21 DDR_B_DM6
A
BB41 SA_DQ_22 DDR_A_DQS[0..7] <17> BC41 SB_DQ_21 SB_DM_6 AP1
B
DDR_A_D23 BC40 AJ44 DDR_A_DQS0 DDR_B_D22 BF40 AK2 DDR_B_DM7
DDR_A_D24 SA_DQ_23 SA_DQS_0 DDR_A_DQS1 DDR_B_D23 SB_DQ_22 SB_DM_7
AY37 SA_DQ_24 SA_DQS_1 AT44 BF41 SB_DQ_23
DDR_A_D25 BD38 BA43 DDR_A_DQS2 DDR_B_D24 BG38
SA_DQ_25 SA_DQS_2 SB_DQ_24 DDR_B_DQS[0..7] <18>
p.
DDR_A_D26 AV37 BC37 DDR_A_DQS3 DDR_B_D25 BF38 AL47 DDR_B_DQS0
MEMORY
DDR_A_D27 SA_DQ_26 SA_DQS_3 DDR_A_DQS4 DDR_B_D26 SB_DQ_25 SB_DQS_0 DDR_B_DQS1
MEMORY
AT36 SA_DQ_27 SA_DQS_4 AW12 BH35 SB_DQ_26 SB_DQS_1 AV48
DDR_A_D28 AY38 BC8 DDR_A_DQS5 DDR_B_D27 BG35 BG41 DDR_B_DQS2
BB38 AU8 BH40 BG37
AV36 AM7 BG39 BH9
SA_DQ_30 SA_DQS_7 SB_DQ_29 SB_DQS_4
om
DDR_A_D31 AW36 DDR_B_D30 BG34 BB2 DDR_B_DQS5
DDR_A_D32 SA_DQ_31 DDR_B_D31 SB_DQ_30 SB_DQS_5 DDR_B_DQS6
BD13 DDR_A_DQS#[0..7] <17> BH34 AU1
DDR_A_D33 SA_DQ_32 DDR_A_DQS#0 DDR_B_D32 SB_DQ_31 SB_DQS_6 DDR_B_DQS7
AU11 AJ43 BH14 AN6
DDR_A_D34 SA_DQ_33 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D33 SB_DQ_32 SB_DQS_7
BC11 AT43 BG12
DDR_A_D35 SA_DQ_34 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D34 SB_DQ_33
BA12 BA44 BH11 DDR_B_DQS#[0..7] <18>
DDR_A_D36 SA_DQ_35 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D35 SB_DQ_34 DDR_B_DQS#0
SYSTEM
AU13 BD37 BG8 AL46

SA_DQ_36 SA_DQS#_3 SB_DQ_35 SB_DQS#_0
SYSTEM
DDR_A_D37 AV13 AY12 DDR_A_DQS#4 DDR_B_D36 BH12 AV47 DDR_B_DQS#1
DDR_A_D38 SA_DQ_37 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D37 SB_DQ_36 SB_DQS#_1 DDR_B_DQS#2
BD12 BD8 BF11 BH41
SA_DQ_38 SA_DQS#_5 SB_DQ_37 SB_DQS#_2
yc
DDR_A_D39 BC12 AU9 DDR_A_DQS#6 DDR_B_D38 BF8 BH37 DDR_B_DQS#3
DDR_A_D40 SA_DQ_39 SA_DQS#_6 DDR_A_DQS#7 DDR_B_D39 SB_DQ_38 SB_DQS#_3 DDR_B_DQS#4
BB9 AM8 BG7 BG9
DDR_A_D41 SA_DQ_40 SA_DQS#_7 DDR_B_D40 SB_DQ_39 SB_DQS#_4 DDR_B_DQS#5
BA9 BC5 BC2
DDR_A_D42 SA_DQ_41 DDR_B_D41 SB_DQ_40 SB_DQS#_5 DDR_B_DQS#6
AU10 DDR_A_MA[0..14] <17> BC6 AT2
DDR_A_D43 SA_DQ_42 DDR_B_D42 SB_DQ_41 SB_DQS#_6 DDR_B_DQS#7
AV9 AY3 AN5
DDR_A_D44 SA_DQ_43 DDR_A_MA0 DDR_B_D43 SB_DQ_42 SB_DQS#_7
BA11 BA21 AY1 DDR_B_MA[0..14] <18>
SA_DQ_44 SA_MA_0 SB_DQ_43
m
DDR_A_D45 BD9 BC24 DDR_A_MA1 DDR_B_D44 BF6
SA_DQ_45 SA_MA_1 SB_DQ_44
DDR
DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D45 BF5 AV17 DDR_B_MA0
DDR
DDR_A_D47 SA_DQ_46 SA_MA_2 DDR_A_MA3 DDR_B_D46 SB_DQ_45 SB_MA_0 DDR_B_MA1
BA6 BH24 BA1 BA25
AV5 BG25 BD3 BC25
AV7 BA24 AV2 AU25
SA_DQ_49 SA_MA_5 SB_DQ_48 SB_MA_3
DDR_A_D50
DDR_A_D51
AT9
AN8
SA_DQ_50
SA_DQ_51
SA_MA_6
SA_MA_7
BD24
BG27
DDR_A_MA6
DDR_A_MA7
// DDR_B_D49
DDR_B_D50
AU3
AR3
SB_DQ_49
SB_DQ_50
SB_MA_4
SB_MA_5
AW25
BB28
DDR_B_MA4
DDR_B_MA5
DDR_A_D52 AU5 BF25 DDR_A_MA8 DDR_B_D51 AN2 AU28 DDR_B_MA6
B DDR_A_D53 SA_DQ_52 SA_MA_8 DDR_A_MA9 DDR_B_D52 SB_DQ_51 SB_MA_6 DDR_B_MA7 B
AU6 AW24 AY2 AW28
AT5 BC21 AV1 AT33
AN10 BG26 AP3 BD33
AM11 BH26 AR1 BB16
p:

AM5 BH17 AL1 AW33
AJ9 AY25 AL2 AY33
DDR_A_D59 SA_DQ_58 SA_MA_14 DDR_B_D58 SB_DQ_57 SB_MA_12 DDR_B_MA13
AJ8 AJ1 BH15
DDR_A_D60 SA_DQ_59 DDR_B_D59 SB_DQ_58 SB_MA_13 DDR_B_MA14
AN12 AH1 AU33
DDR_A_D61 SA_DQ_60 DDR_B_D60 SB_DQ_59 SB_MA_14
AM13 AM2
tt

AJ11 AM3
AJ12 AH3
SA_DQ_63 DDR_B_D63 SB_DQ_62
AJ3
CANTIGA ES_FCBGA1329 SB_DQ_63
h
A A
LA-5152P
5 4 3 2 1
5 4 3 2 1
U4F
+AXG_CORE
1067M 4140mA VCC_AXG_NTCF_1 W28

DDR3 800M 3162mA AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26
+1.5V BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26 Extnal Graphic: 3060mA
BG32 W25 integrated Graphic: 2898mA
22U_0805_6.3V6M~D
VCC_SM_4 VCC_AXG_NCTF_5
0.47U_0402_10V4Z~D
+1.05V_VCCP
330U_D2_2.5VY_R9M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
1U_0603_10V6K~D
BF32 VCC_SM_5 VCC_AXG_NCTF_6 V25
1 BD32 W24 1 1 1 1 U4G
1 1 2 BC32 V24
C1503
C111
C1502
C1506
D + D
C114
C115
C109
C110
BB32 VCC_SM_8 VCC_AXG_NCTF_9 W23 AG34 VCC_1
VCC
BA32 V23 AC34
VCC_SM_9 VCC_AXG_NCTF_10 2 2 2 2 VCC_2
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21 AB34 VCC_3
2 2 2 1
AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21 AA34 VCC_4
AV32 AK21 Y34
VCC_SM_12 VCC_AXG_NCTF_13 VCC_5
AU32 W21 V34
VCC CORE
AT32 V21 U34
SM
AR32 U21 AM33
AP32 AM20 AK33
AN32
AK20 Layout Note: Inside GMC AJ33
VCC_10
BH31 W20 AG33
BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20 AF33 VCC_12
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19 AE33 VCC_13
BF29 AH19 AC33
220U_D2_4VY_R15M~D
330U_D2_2.5VY_R15M
330U_D2_2.5VY_R15M
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
0.1U_0402_10V7K~D
BD29 VCC_SM_25 VCC_AXG_NCTF_26 AG19 AA33 VCC_15
10U_0805_10V4Z~D
BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19 1 1 Layout Note: 1 Y33 VCC_16
@ C1500
@ C1501
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 1 1 1 1 W33 VCC_17
+ + Place close to GMCH +
C116
BA29 AB19 V33
POWER
C117
C118
C119
C120
AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19 U33 VCC_19
AW29 Y19 AH28
GFX NCTF
VCC_SM_30 VCC_AXG_NCTF_31 2 2 2 2 2 2 2 VCC_20
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 AF28 VCC_21
/x
AU29 VCC_SM_32 VCC_AXG_NCTF_33 V19 AC28 VCC_22
AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19 AA28 VCC_23
AR29 VCC_SM_34 VCC_AXG_NCTF_35 AM17 AJ26 VCC_24
AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17 AG26 VCC_25
VCC_AXG_NCTF_37 AH17 AE26 VCC_26
VCC_AXG_NCTF_38 AG17 AC26 VCC_27
AF17 AH25 +1.05V_VCCP
su
VCC_AXG_NCTF_39 VCC_28
BA36 VCC_SM_36/NC VCC_AXG_NCTF_40 AE17 AG25 VCC_29
C C
BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17 AF25 VCC_30
VCC
BD16 VCC_SM_38/NC VCC_AXG_NCTF_42 AB17 AG24 VCC_31 VCC_NCTF_1 AM32
BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17 AJ23 VCC_32 VCC_NCTF_2 AL32
AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17 AH23 VCC_33 VCC_NCTF_3 AK32
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17 AF23 VCC_34 VCC_NCTF_4 AJ32
p.
AT13 VCC_SM_42/NC VCC_AXG_NCTF_46 AM16 T32 VCC_35 VCC_NCTF_5 AH32
VCC_AXG_NCTF_47 AL16 VCC_NCTF_6 AG32
+1.05V_VCCP +AXG_CORE AK16 AE32
VCC_AXG_NCTF_48 VCC_NCTF_7
POWER
J1 AJ16 AC32
AH16 AA32
om
1 2 AG16 Y32
1 2 VCC_AXG_NCTF_51 VCC_NCTF_10
8700mA VCC_AXG_NCTF_52
AF16
VCC_NCTF_11
W32
Y26 AE16 U32
JUMP_43X118 VCC_AXG_1 VCC_AXG_NCTF_53 VCC_NCTF_12
AE25 AC16 AM30
VCC_AXG_2 VCC_AXG_NCTF_54 VCC_NCTF_13
J2 AB25 AB16 AL30
AA25 AA16 AK30
1 2 AE24 Y16 AH30
1 2 VCC_AXG_5 VCC_AXG_NCTF_57 VCC_NCTF_16
AC24 W16 AG30
+AXG_CORE VCC_AXG_6 VCC_AXG_NCTF_58 VCC_NCTF_17
yc
AA24 V16 AF30
JUMP_43X118 VCC_AXG_7 VCC_AXG_NCTF_59 VCC_NCTF_18
Y24 U16 AE30
AE23 AC30
NCTF
VCC_AXG_9 VCC_NCTF_20
AC23 AB30
1U_0603_10V6K~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_10V7K~D
AB23 AA30
1 1 1 1 AA23 Y30
m
AJ21 W30
C121
C123
C124
C125
AG21 V30
AE21 U30
2 2 2 2 VCC_AXG_15 VCC_NCTF_26
VCC
AC21 AL29
AA21 AK29
Y21
VCC_AXG_18
// VCC_NCTF_29
AJ29
VCC
AH20 AH29
AF20 AG29
B VCC_AXG_20 VCC_NCTF_31 B
AE20 AE29
AC20 AC29
AB20 AA29
AA20 Y29
GFX
p:
T17 W29
T16 V29
AM15 AL28
AL15 AK28
AE15 AL26
tt
AJ15 AK26
AH15 AK25
AG15 AK24
AF15 AK23
h
AB15
VCC_AXG_34
AA15
VCC_AXG_35
Y15
VCC_AXG_36
V15
VCC_AXG_37
U15
VCC_AXG_38
AN14
VCC_AXG_39
AM14
VCC_AXG_40
U14 AV44 VCCSM_LF1
VCC SM LF
VCC_AXG_41 VCC_SM_LF1
T14 BA37 VCCSM_LF2
VCC_AXG_42 VCC_SM_LF2
AM40 VCCSM_LF3 CANTIGA ES_FCBGA1329
VCC_SM_LF3
AV21 VCCSM_LF4
VCC_SM_LF4
AY5 VCCSM_LF5
VCC_SM_LF5
PAD T53 AJ14 AM10 VCCSM_LF6
VCC_AXG_SENSE VCC_SM_LF6
PAD T54 AH14 BB13 VCCSM_LF7
VSS_AXG_SENSE VCC_SM_LF7
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
.47U_0402_6.3V6-K~D
1 1 1 1 1 1 1
C128
C129
C126
C127
C130
C131
C132
2 2 2 2 2 2 2
A A
LA-5152P
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP R119 +1.05V_M_HPLL

0_0603_5%
1 2 U4H +1.05V_VCCP
0.1U_0402_10V7K~D
1 1
4.7U_0603_6.3V6M~D
852mA
+3.3V_CRT_DAC
C133
C134
VTT_1 U13
+3VS +3.3V_CRT_DAC
220U_D2_4VY_R15M~D
B27 VCCA_CRT_DAC_1 VTT_2 T13
+3.3V_CRT_DAC 2 2
4.7U_0603_6.3V6M~D
L1 A26 U12 1
VCCA_CRT_DAC_2 VTT_3
1 2 T12 1
+3.3V_CRT_DAC VTT_4
C138
+
0.01U_0402_25V7K~D
BLM18PG181SN1_0603~D
0.1U_0402_10V7K~D
U11
C139
VTT_5
0.01U_0402_25V7K~D
0.1U_0402_10V7K~D
T11
VTT_6
CRT
1 1 1 1 A25 U10
D VCCA_DAC_BG VTT_7 2 2 D
C140
T10
C135
C141
C136
VTT_8
B25 U9
+1.05V_VCCP +1.05V_M_MPLL VSSA_DAC_BG VTT_9
VTT_10 T9
2 2 2 2
L2 VTT_11 U8
1 2 64.8mA VTT_12
T8
VTT
BLM18AG121SN1D_0603~D +1.05V_M_DPLLA F47 U7
VCCA_DPLLA VTT_13
2
0_0603_5%
64.8mA VTT_14
T7
R120
0.1U_0402_10V7K~D
.47U_0402_6.3V6-K~D
2.2U_0603_10V6K~D
4.7U_0603_6.3V6M~D
1 +1.05V_M_DPLLB L48 U6
VCCA_DPLLB VTT_15
Place close to U4H.B27 and A26 Place close to U4H.A25 VTT_16
T6 1 1 1
C137
C144
PLL
24mA
C142
AD1 U5
C143
VCCA_HPLL VTT_17
T5
22U_0805_6.3V6M~D
1
2 VTT_18
1 139.2mA AE1 VCCA_MPLL VTT_19 V3
2 2 2
Place close to U4H.F47 Place close to U4H.J48 VTT_20 U3
C145
13.2mA VTT_21 V2
+1.05V_M_DPLLA
A PEG A LVDS
+1.05V_VCCP +VCC_TX_LVDS J48 U2
L1500 +1.8VS +VCC_TX_LVDS 2 VCCA_LVDS VTT_22
VTT_23 T2
64.8mA Max. 2 1 L1501 J47 V1
VSSA_LVDS VTT_24
0.1U_0402_10V7K~D
10UH_LB2012T100MR_20%_0805~D 2 1 U1
220U_D2_4VY_R15M~D
VTT_25
1000P_0402_50V7K~D
22U_0805_6.3V6M~D
1 HK1608R10J-T_0603~D R121 414uA
1 +1.5VS 2 1 +VCCA_PEG_BG AD48 VCCA_PEG_BG
0.1U_0402_10V7K~D
+
1 1 0_0402_5% 1
/
C1505
C1504
C1508
C1507
C147
2 2
50mA
AA48 +VCC_AXF
2 2 2 +1.05V_M_PEGPLL VCCA_PEG_PLL +1.05V_VCCP
/x
R122
+VCC_AXF 1 2 0_0603_5%
10U_0805_4VAM~D
1U_0603_10V6K~D
+1.05V_VCCP 1 1
+1.05V_A_SM
C149
747mA
POWER
C148
R123 AR20 VCCA_SM_1
2 1 AP20 @ DDR3 connect to 1.5V
su
VCCA_SM_2 2 2
100U_D2E_6.3VM_R18M~D
0_0603_5% AN20 VCCA_SM_3
+1.05V_M_DPLLB
22U_0805_6.3V6M~D
4.7U_0603_6.3V6M~D
1U_0603_10V6K~D
C +1.05V_VCCP C
1 AR17 VCCA_SM_4 321.35mA
A SM
L1503 1 1 1 AP17 +1.5VS
VCCA_SM_5
C150
C152
+
64.8mA Max. 2 1 AN17 B22 R124
C153
C151
VCCA_SM_6 VCC_AXF_1
AXF
0.1U_0402_10V7K~D
10UH_LB2012T100MR_20%_0805~D AT16 B21 2 1

VCCA_SM_7 VCC_AXF_2
220U_D2_4VY_R15M~D
0.1U_0402_10V7K~D
1 AR16 VCCA_SM_8 VCC_AXF_3 A21 0_0805_5%
p.
2 2 2 2 AP16
1 VCCA_SM_9
1
+ +1.5V_SM_CK
1
1_0402_5%
C1510
C1509
R125
C154
2 2
149mA
BF21
VCC_SM_CK_1
om
2
SM CK
BH20
2
+1.05V_VCCP +1.05V_A_SM_CK VCC_SM_CK_2
37.95mA VCC_SM_CK_3
BG20 C155
BF20 1 2
R126 2 VCC_SM_CK_4
Place close to U4H.L48 1 0_0603_5% AP28
VCCA_SM_CK_1 10U_0805_4VAM~D
AN28
22U_0805_6.3V6M~D
0.1U_0402_10V7K~D
VCCA_SM_CK_2
AP25
VCCA_SM_CK_3 CRB schematic
1 1 AN25 118.8mA
AN24
VCCA_SM_CK_4
K47 HPB & Avia no draw.
C156
C157
VCCA_SM_CK_5 VCC_TX_LVDS +VCC_TX_LVDS
A CK
yc
AM28
VCCA_SM_CK_NCTF_1 +3VS
AM26 D1
2 2 VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3 105.3mA R127 @
AL25 C35 1 2 1 2@ +1.05V_VCCP
VCCA_SM_CK_NCTF_4 VCC_HV_1
AM24 B35 1 10_0402_5%
HV
AL24 A35 CH751H-40PT_SOD323-2~D
m
AM23 C158
VCCA_SM_CK_NCTF_7 0.1U_0402_10V7K~D
AL23
VCCA_SM_CK_NCTF_8 2
1782mA
TVA_DAC 24.15mA V48 +1.05V_VCCP
+1.5VS +1.5VS_QDAC VCC_PEG_1 +VCC_PEG R02 modify
TVB_DAC 39.48mA U48
VCC_PEG_2
//
PEG
V47
L3 TVC_DAC 24.15mA VCC_PEG_3
U47 1 2
VCC_PEG_4 @ JP2
1 2 +3VS_TVDAC B24 U46
B VCCA_TV_DAC_1 VCC_PEG_5 B
BLM18PG181SN1_0603~D A24
VCCA_TV_DAC_2
0.01U_0402_25V7K~D
4.7U_0603_6.3V6M~D
22U_0805_6.3V6M~D
C164
220U_D2_4VY_R15M~D
C162
TV
0.1U_0402_10V7K~D
1
+1.5VS +VCC_DMI +VCC_PEG
1 1 1 1
C163
456mA +
p: C160
C161
50mA A32 AH48 R129 1 2 0_0603_5%

VCC_HDA VCC_DMI_1
HDA
2 AF48 1
2 2 VCC_DMI_2 2 2 2
DMI
Place close to U4H.M25 VCC_DMI_3
AH47
C159 AG47 C165
+1.5VS +1.5VS_TVDAC 0.1U_0402_10V7K~D VCC_DMI_4 0.1U_0402_10V7K~D
35mA
tt
1 M25 2
+1.5VS_TVDAC VCCD_TVDAC
D TV/CRT
R1539
2 1 R130 2 1 0_0402_5% 1mA L28
+1.05V_VCCP VCCD_QDAC
0.01U_0402_25V7K~D
0.1U_0402_10V7K~D
0_0603_5%
h
1 1
157.2mA AF1
C1526
C1525
1 VCCD_HPLL
A8 GMCH_VTTLF1
C166 VTTLF1 GMCH_VTTLF2
2 2
50mA AA47
VCCD_PEG_PLL VTTLF2
L1
0.1U_0402_10V7K~D AB2 GMCH_VTTLF3
VTTLF
0103 modify it.
2 VTTLF3
.47U_0402_6.3V6-K~D
C167
.47U_0402_6.3V6-K~D
C168
.47U_0402_6.3V6-K~D
C169
+1.8VS 60.31mA M38 VCCD_LVDS_1
LVDS
L37 1 1 1
VCCD_LVDS_2
1U_0603_10V6K~D
+1.05V_VCCP L4 +1.05V_M_PEGPLL
BLM18PG181SN1_0603~D CANTIGA ES_FCBGA1329 2 2 2
1
1 2
C170
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C171
2
Place close to U4H.B24 and A24 10U_0805_4VAM~D
R131 1 1
2 1
+3VS +3VS_TVDAC
C172
C173
1_0402_5%
L1502
A BLM18PG181SN1_0603~D 2 2 A
1 2
0.01U_0402_25V7K~D
0.1U_0402_10V7K~D
1 1 DELL CONFIDENTIAL/PROPRIETARY
C1524
C1523
0103 modify it.

2 2 Compal Electronics, Inc.
LA-5152P
5 4 3 2 1
5 4 3 2 1
U4I U4J
AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 AE36 L12 Y8
VSS_2 VSS_101 VSS_200 VSS_298
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 AA35 AB21 AJ7
AB47 Y35 R21 AE7
D VSS_10 VSS_109 VSS_208 VSS_306 D
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 T35 J21 N7
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 AJ34 BA20 BD6
BD46 AF34 AW20 AV6
BA46 AE34 AT20 AT6
AY46 W34 AJ20 AM6
AV46 B34 AG20 M6
AR46 A34 Y20 C6
AM46 BG33 N20 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
/
U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
/x
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 H29 N16 AP2
su
C
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2 C
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
p.
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 AJ28 AA14 K2
AU41 AG28 C14 AM1
AM41 AE28 BG13 AA1
om
AH41 AB28 BC13 P1
AD41 Y28 BA13 H1
AA41 P28
VSS_55 VSS_154
Y41 K28 U24
VSS_56 VSS_155 VSS_351
U41 H28 AN13 U28
T41 F28 AJ13 U25
M41 C28 AE13 U29
G41 BF26 N13
yc
B41 AH26 L13 AF32
VSS_61 VSS_160 VSS_259 VSS_NCTF_1
BG40 AF26 G13 AB32
BB40 AB26 E13 V32
AV40 AA26 BF12 AJ30
AN40 C26 AV12 AM29
H40 B26 AT12 AF29
m
E40 BH25 AM12 AB29
AT39 BD25 AA12 U26
VSS NCTF
AM39 BB25 J12 U23
AJ39 AV25 A12 AL20
AE39 AR25 BD11 V20
N39
L39
VSS_72
VSS_73
// VSS_171
VSS_172
AJ25
AC25
BB11
AY11
VSS_270
VSS_271
VSS_NCTF_12
VSS_NCTF_13
AC19
AL17
B39 Y25 AN11 AJ17
B VSS_74 VSS_173 VSS_272 VSS_NCTF_14 B
BH38 N25 AH11 AA17
BC38 L25 U17
VSS_76 VSS_175 VSS_NCTF_16
BA38 J25 Y11
AU38 G25 N11
p:

AH38 E25 G11 BH48
VSS_79 VSS_178 VSS_277 VSS_SCB_1
AD38 BF24 C11 BH1
AA38 AD12 BG10 A48
Y38 AY24 AV10 C1
VSS SCB
U38 AT24 AT10 A3
tt

T38 AJ24 AJ10
J38 AH24 AE10
F38 AF24 AA10
C38 AB24 M10
h
BF37 R24 BF9 E1

VSS_88 VSS_187 VSS_286 NC_26
BB37 L24 BC9 D2
VSS_89 VSS_188 VSS_287 NC_27
AW37 K24 AN9 C3
VSS_90 VSS_189 VSS_288 NC_28
AT37 J24 AM9 B4
VSS_91 VSS_190 VSS_289 NC_29
AN37 G24 AD9 A5
VSS_92 VSS_191 VSS_290 NC_30
AJ37 F24 G9 A6
VSS_93 VSS_192 VSS_291 NC_31
H37 E24 B9 A43
VSS_94 VSS_193 VSS_292 NC_32
C37 BH23 BH8 A44
VSS_95 VSS_194 VSS_293 NC_33
BG36 AG23 BB8 B45
VSS_96 VSS_195 VSS_294 NC_34
BD36 Y23 AV8 C46
NC
VSS_97 VSS_196 VSS_295 NC_35
AK15 B23 AT8 D47
VSS_98 VSS_197 VSS_296 NC_36
AU36 A23 B47
VSS_99 VSS_198 NC_37
AJ6 A46
VSS_199 NC_38
F48
CANTIGA ES_FCBGA1329 NC_39
E48
NC_40
C48
NC_41
B48
NC_42
A CANTIGA ES_FCBGA1329 A
LA-5152P
5 4 3 2 1
5 4 3 2 1
+1.5V
+1.5V +1.5V
+V_DDR_MCH_REF
JDIMM1 Note :
1
+V_DDR_MCH_REF 1 2
VREF_DQ VSS1 DDR3 command & contorl signals need no termination.
2.2U_0603_6.3V6K~D
0.1U_0402_10V7K~D
3 4 DDR_A_D4
R132 DDR_A_D0 VSS2 DQ4 DDR_A_D5
1K_0402_1% +V_DDR_MCH_REF DDR_A_D1
5 DQ0 DQ5 6 DDR2 command & command signals 56 ohm pull up to VccSus0_9
7 DQ1 VSS3 8
1 1 9 10 DDR_A_DQS#0
2
VSS4 DQS#0
C175
C174
DDR_A_DM0 11 12 DDR_A_DQS0
+V_DDR_MCH_REF DM0 DQS0
13 14
DDR_A_D2 VSS5 VSS6 DDR_A_D6
15 16
D 2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7 D
17 DQ3 DQ7 18
1
19 20
21 DQ8 DQ12 22
R133 DDR_A_D9 23 24 DDR_A_D13
1K_0402_1% DQ9 DQ13
25 26
DDR_A_DQS#1 VSS9 VSS10 DDR_A_DM1
27 28
2
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#

29 30 DDR3_DRAMRST# <11,18>
DQS1 RESET#
31 32
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 38
39 DQ16 DQ20 40
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21 <13> DDR_A_D[0..63]
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48 <13> DDR_A_DQS[0..7]
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28 <13> DDR_A_DQS#[0..7]
55 VSS20 DQ28 56
DQ24 DQ29
/
DDR_A_D25 59 60
DQ25 VSS21 DDR_A_DQS#3 <13> DDR_A_DM[0..7]
61 VSS22 DQS#3 62
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3
/x
65 VSS23 VSS24 66 <13> DDR_A_MA[0..14]
69 DQ27 DQ31 70
71 VSS25 VSS26 72
su
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
C <11> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <11> C
75 VDD1 VDD2 76
+1.5V
Place close to SO-DIMM
77 NC1 A15 78 T55
DDR_A_BS2 79 80 DDR_A_MA14
<13> DDR_A_BS2 BA2 A14
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
A12/BC# A11
p.
330U_D2_2.5VY_R15M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
A9 A7
87 VDD5 VDD6 88 1
DDR_A_MA8 89 90 DDR_A_MA6 1 1 1 1 1 1
DDR_A_MA5 A8 A6 DDR_A_MA4 +
C176
C177
C178
C179
C180
C181
91 92
C182
A5 A4
93 94
VDD7 VDD8
om
DDR_A_MA1 A3 A2 DDR_A_MA0 2 2 2 2 2 2 2
97 98
A1 A0
99 100
M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1
<11> M_CLK_DDR0 101 102 M_CLK_DDR1 <11>
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
<11> M_CLK_DDR#0 103 104 M_CLK_DDR#1 <11>
CK0# CK1#
105 106
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS1 <13>
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<13> DDR_A_BS0 109 110 DDR_A_RAS# <13>
BA0 RAS#
yc
111 112
DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
<13> DDR_A_WE# 113 114 DDR_CS0_DIMMA# <11>
WE# S0#
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
DDR_A_CAS# 115 116 M_ODT0_DIMMA
<13> DDR_A_CAS# CAS# ODT0 M_ODT0_DIMMA <11>
117 118 1 1 1 1
DDR_A_MA13 VDD15 VDD16 M_ODT1_DIMMA
119 120 M_ODT1_DIMMA <11>
A13 ODT1
C183
C184
C185
C186
DDR_CS1_DIMMA# 121 122
<11> DDR_CS1_DIMMA# S1# NC2
m
123 124
VDD17 VDD18 +V_DDR_MCH_REF 2 2 2 2
T56 125 126 +V_DDR_MCH_REF
NCTEST VREF_CA
127 128
0.1U_0402_10V7K~D
2.2U_0603_6.3V6K~D
129 130
131 132
DQ33 DQ37
DDR_A_DQS#4
133
VSS29
//
VSS30
134
DDR_A_DM4
1 1
C188
135 136
C187
137 138
B DQS4 VSS31 DDR_A_D38 B
139 140
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_A_D44
145 146
p:

147 148
DDR_A_D41 DQ40 DQ45 +0.75VS
149 150
DQ41 VSS35 DDR_A_DQS#5
151 152
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
DM5 DQS5
155 156
tt
VSS37 VSS38
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_D42 157 158 DDR_A_D46
159 160
DQ43 DQ47
161 162 2 2 2 2
VSS39 VSS40
C190
C189
C191
DDR_A_D48 DDR_A_D52
C192
163 164
DQ48 DQ52
h
DDR_A_D49 165 166 DDR_A_D53

DQ49 DQ53
167 168
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6 1 1 1 1
169 170
171 172
DQS6 VSS43 DDR_A_D54
173 174
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_A_D60
179 180
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_A_DQS#7
DDR_A_DM7
185
VSS48 DQS#7
186
DDR_A_DQS7
Place close to JDIMM pin 203 and 204
187 188
DM7 DQS7
189 190
191 192
193 194
+3VS DQ59 DQ63 @
195 196
VSS51 VSS52 R134 1
197 198 PM_EXTTS#0_R 2 0_0402_5%
SA0 EVENT# ICH_SM_DA PM_EXTTS#0 <11>
199 200 ICH_SM_DA <6,18,20,21>
VDDSPD SDA ICH_SM_CLK
2.2U_0603_6.3V6K~D
201 202
0.1U_0402_10V7K~D
A SA1 SCL ICH_SM_CLK <6,18,20,21> A

+0.75VS 203 VTT1 VTT2 204 +0.75VS
10K_0402_5%
10K_0402_5%
1
205 206
1 1 G1 G2 DELL CONFIDENTIAL/PROPRIETARY
C194
C193
R135
R136
FOX_AS0A626-U4RN-7F
CONN@
2 2
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Compal Electronics, Inc.
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Title
DDR3 SO-DIMM/Standard Type BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD DDRIII SO-DIMM A SLOT
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
A00
LA-5152P
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
LINK OK
+V_DDR_MCH_REF
JDIMM2
+V_DDR_MCH_REF 1 2
VREF_DQ VSS1 DDR_B_D4
3 4
2.2U_0603_6.3V6K~D
0.1U_0402_10V7K~D
DDR_B_D0 VSS2 DQ4 DDR_B_D5
5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
1 1 9 VSS4 DQS#0 10
DDR_B_DM0 DDR_B_DQS0
C196
11 12
C195
DM0 DQS0
13 14
DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 16
D 2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7 D
17 DQ3 DQ7 18
19 20
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13 <13> DDR_B_D[0..63]
25 26
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1
27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 30 DDR3_DRAMRST# <11,17> <13> DDR_B_DQS[0..7]
DQS1 RESET#
31 32
33 34
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36 <13> DDR_B_DQS#[0..7]
DQ11 DQ15
37 38
39 DQ16 DQ20 40
DQ17 DQ21 <13> DDR_B_DM[0..7]
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48 <13> DDR_B_MA[0..14]
49 50 DDR_B_D22
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DQ24 DQ29
/
DDR_B_D25 59 60
61 VSS22 DQS#3 62
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
/x
65 VSS23 VSS24 66
69 DQ27 DQ31 70 Place close to SO-DIMM
71 VSS25 VSS26 72
+1.5V
su
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
C <11> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <11> C
75 VDD1 VDD2 76
330U_D2_2.5VY_R15M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
77 NC1 A15 78 T57
DDR_B_BS2 79 80 DDR_B_MA14 1
<13> DDR_B_BS2 BA2 A14
81 VDD3 VDD4 82 1 1 1 1 1 1
DDR_B_MA12 83 84 DDR_B_MA11 +
C197
C198
C199
C201
C202
C203
C200
A12/BC# A11
p.
DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6 2 2 2 2 2 2 2
DDR_B_MA5 A8 A6 DDR_B_MA4
91 92
A5 A4
93 94
VDD7 VDD8
om
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
<11> M_CLK_DDR2 101 102 M_CLK_DDR3 <11>
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
<11> M_CLK_DDR#2 103 104 M_CLK_DDR#3 <11>
CK0# CK1#
105 106
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 <13>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<13> DDR_B_BS0 109 110 DDR_B_RAS# <13> 1 1 1 1
BA0 RAS#
yc
111 112
VDD13 VDD14
C204
C205
C206
C207
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
<13> DDR_B_WE# DDR_B_CAS# WE# S0# M_ODT2_DIMMB DDR_CS2_DIMMB# <11>
<13> DDR_B_CAS# 115 116 M_ODT2_DIMMB <11>
CAS# ODT0 2 2 2 2
117 118
DDR_B_MA13 VDD15 VDD16 M_ODT3_DIMMB
119 120 M_ODT3_DIMMB <11>
DDR_CS3_DIMMB# A13 ODT1
<11> DDR_CS3_DIMMB# 121 122
S1# NC2
m
123 124
VDD17 VDD18 +V_DDR_MCH_REF
T58 125 126 +V_DDR_MCH_REF
NCTEST VREF_CA
2.2U_0603_6.3V6K~D
0.1U_0402_10V7K~D
127 128
129 130
131 132
DQ33 DQ37
DDR_B_DQS#4
133
135
VSS29
//VSS30
134
136 DDR_B_DM4
1 1
C209
C208
137 138
B DQS4 VSS31 DDR_B_D38 B
139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2 +0.75VS
141 142
DDR_B_D35 DQ34 DQ39
143 144
145 146
p:

147 148
DQ40 DQ45
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_B_D41 149 150
151 152
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 154 2 2 2 2
DM5 DQS5
155 156
C210
C211
C212
C213
tt

157 158
159 160
DQ43 DQ47 1 1 1 1
161 162
163 164
DQ48 DQ52
h
DDR_B_D49 165 166 DDR_B_D53

DQ49 DQ53
167 168
DDR_B_DQS#6 VSS41 VSS42 DDR_B_DM6
169 170
171 172
DQS6 VSS43 DDR_B_D54
DDR_B_D50
173
VSS44 DQ54
174
DDR_B_D55
Place close to JDIMM pin 203 and 204
175 176
DDR_B_D51 DQ50 DQ55
177 178
179 180
181 182
DDR_B_D57 DQ56 DQ61
183 184
185 186
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 188
DM7 DQS7
189 190
191 192
193 194
+3VS DQ59 DQ63 @ R137
195 196
VSS51 VSS52
197 198 PM_EXTTS#1_R 1 2 0_0402_5%
R138 SA0 EVENT# ICH_SM_DA PM_EXTTS#1 <11>
199 200 ICH_SM_DA <6,17,20,21>
VDDSPD SDA ICH_SM_CLK
+3VS 1 2 201 SA1 SCL 202 ICH_SM_CLK <6,17,20,21>
A A
2.2U_0603_6.3V6K~D
0.1U_0402_10V7K~D
10K_0402_5% +0.75VS 203 VTT1 VTT2 204 +0.75VS

10K_0402_5%
1
1 1 205 G1 G2 206
R139
C214
C215
FOX_AS0A626-U8RN-7F
2 2
CONN@ DELL CONFIDENTIAL/PROPRIETARY
2

DDR3 SO-DIMM/Standard Type PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII SO-DIMM B SLOT
LA-5152P
5 4 3 2 1
5 4 3 2 1
C864 15P_0402_50V8J ICH_RTCX1

Y2
D CMOS_CLR1 CMOS setting 2 NC IN 1 D
1
Shunt Clear CMOS 3 4 R140
NC OUT 10M_0402_5%
32.768KHZ_12.5PF_1TJS125BJ4A421P U6A LPC_AD[0..3] <27,31> +3VS
Open Keep CMOS LPC_AD0
R141 C23 K5
2
C217 15P_0402_50V8J ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1
1 2 C24 RTCX2 FWH1/LAD1 K4
0_0402_5% L6 LPC_AD2 GATEA20 R142 2 110K_0402_5%
R143 1 FWH2/LAD2
+RTCVCC 2 20K_0402_5% ICH_RTCRST# A25 RTCRST# FWH3/LAD3 K2 LPC_AD3
R144 1 2 20K_0402_5% SRTCRST# F20 KB_RST# R145 2 1 10K_0402_5%
RTC
LPC
R146 1 SRTCRST#
2 1K_0402_5% INTRUDER# C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME#
LPC_FRAME# <27,31>
R157
+RTCVCC 1 2 ICH_INTVRMEN B22 INTVRMEN LDRQ0# J3 T59
1U_0603_10V6K~D
ME_CLR1 TPM setting 332K_0402_1% A22 J1
1U_0603_10V6K~D
LAN100_SLP LDRQ1#/GPIO23 T60
2 2 +1.05V_VCCP
1
CMOS1
@ GATEA20
Shunt Clear ME RTC Registers E25 N7
C218
C219
GLAN_CLK A20GATE GATEA20 <31> R147 2 1 49.9_0402_1%
ME1
AJ27 H_A20M# H_FERR#
A20M# H_A20M# <7>
Open Keep ME RTC Registers C13
2
1 1 LAN_RSTSYNC
@
AJ25 H_DPRSTP#
DPRSTP# H_DPRSTP# <8,11,43>
H_DPSLP#
/
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# <8>
LAN / GLAN
G13 LAN_RXD1 R148 dual core 56_5%
D14 LAN_RXD2 FERR# AJ26 2 1 H_FERR# <7> quad core 50_5%
/x
56_0402_5%
D13 AD22 H_PW RGOOD
LAN_TXD0 CPUPWRGD H_PW RGOOD <8>
D12 LAN_TXD1
R02 RF reserve part. E13 AF25 H_IGNNE#
LAN_TXD2 IGNNE# H_IGNNE# <7>
CPU
@ C1532 R149 B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# <7>
su
2 1 24.9_0402_1% AG25 H_INTR +1.05V_VCCP
INTR H_INTR <7>
C
+1.5VS 1 2 B28 L3 KB_RST# C
GLAN_COMPI RCIN# KB_RST# <31>
Delete when UMA net in 10P_0402_50V8J~D B27 GLAN_COMPO
1
AF23 H_NMI dual core 56_5%
R150 1 NMI H_NMI <7>
<25> HDA_BITCLK_AUDIO 2 33_0402_5% HDA_BITCLK_ICH AF6 HDA_BIT_CLK SMI# AF24 H_SMI#
H_SMI# <7>
R151
1 2 HDA_BITCLK_ICH R152 1 2 33_0402_5% HDA_SYNC_ICH AH4 49.9_0402_1% quad core 50_5%
p.
<11> HDA_BITCLK_NB R874 <25> HDA_SYNC_AUDIO HDA_SYNC
33_0402_5% AH27 H_STPCLK#
STPCLK# H_STPCLK# <7>
1 2 HDA_SYNC_ICH
<25> HDA_RST_AUDIO#
R153 1 2 33_0402_5% HDA_RST_ICH# AE7
2
<11> HDA_SYNC_NB 33_0402_5% HDA_RST# THERMTRIP_ICH# R154
R875
THRMTRIP# AG26 1 2 54.9_0402_1% H_THERMTRIP# <7,11>
1 2 HDA_RST_ICH# HDA_SDIN0 AF4
<11> HDA_RST_NB# <25> HDA_SDIN0 HDA_SDIN0
om
R876 33_0402_5%
<11> HDA_SDIN1
HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27 ICH_TP12 T61 placed within 2" from
1 2 HDA_SDOUT_ICH AH3 ICH9M
IHDA
<11> HDA_SDOUT_NB R877 33_0402_5% HDA_SDIN2
AE5 HDA_SDIN3
SATA4RXN AH11 SATA_IRX_DTX_N4 <30>
R155 1 2 33_0402_5% HDA_SDOUT_ICH AG5 AJ11
<25> HDA_SDOUT_AUDIO HDA_SDOUT SATA4RXP SATA_IRX_DTX_P4 <30>
AG12 SATA_ITX_DRX_N4 C220 2 1 0.01U_0402_16V7K~D To ESATA
SATA4TXN SATA_ITX_C_DRX_N4 <30>
AG7 AF12 SATA_ITX_DRX_P4 C221 2 1 0.01U_0402_16V7K~D
HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_ITX_C_DRX_P4 <30>
T62 PAD~D AE8
yc
T63 PAD~D HDA_DOCK_RST#/GPIO34
SATA5RXN AH9 SATA_IRX_DTX_N5 <29>
SATA_ACT#_R AG8 AJ9
T84 PAD~D SATALED# SATA5RXP SATA_ITX_DRX_N5 C222 2 SATA_IRX_DTX_P5 <29>
SATA5TXN AE10 1 0.01U_0402_16V7K~D SATA_ITX_C_DRX_N5 <29> To ODD
AJ16 AF10 SATA_ITX_DRX_P5 C223 2 1 0.01U_0402_16V7K~D
<29> SATA_IRX_DTX_N0 SATA0RXN SATA5TXP SATA_ITX_C_DRX_P5 <29>
To JSATA1 AH16
m
<29> SATA_IRX_DTX_P0 C224 2 SATA0RXP
1 0.01U_0402_16V7K~D SATA_ITX_DRX_N0 CLK_PCIE_SATA#
SATA
<29> SATA_ITX_C_DRX_N0 AF17 SATA0TXN SATA_CLKN AH18 CLK_PCIE_SATA# <6>
C225 2 1 0.01U_0402_16V7K~D SATA_ITX_DRX_P0 AG17 AJ18 CLK_PCIE_SATA
<29> SATA_ITX_C_DRX_P0 SATA0TXP SATA_CLKP CLK_PCIE_SATA <6>
<29> SATA_IRX_DTX_N1 AH13 SATA1RXN SATARBIAS# AJ7
To JSATA2
<29>
<29>
SATA_IRX_DTX_P1
SATA_ITX_C_DRX_N1
C226 2 1 0.01U_0402_16V7K~D
// SATA_ITX_DRX_N1
AJ13
AG14
SATA1RXP
SATA1TXN
SATARBIAS AH7 2
R156
1
24.9_0402_1%
C227 2 1 0.01U_0402_16V7K~D SATA_ITX_DRX_P1 AF14
B <29> SATA_ITX_C_DRX_P1 SATA1TXP B
ICH9M_FCBGA676~D
Within 500 mils
p:
P/N : SA00002G12L (S IC AF82801IEM SLB8P A3 PBGA676P ICH9ME )

tt
+3VS
h
1
XOR Chain Entrance Strap
@ R158
1K_0402_5%
ICH TP3 HDA SDOUT Description
2
0 0 RSVD HDA_SDOUT_ICH
ICH_TP3 <21>
1
0 1 Enter XOR Chain
@ R160
1K_0402_5%
1 0 Normal Operation (Default)
2
1 1 Set PCIE port config bit 1

A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH9-M(1/5)
LA-5152P
5 4 3 2 1
5 4 3 2 1
Boot BIOS Strap

+3VS
PCI_GNT0# SPI_CS#1 Boot BIOS Location

R161 1 2 8.2K_0402_5% PCI_REQ0#
R162 1 2 8.2K_0402_5% PCI_REQ1#

0 1 SPI
D R163 1 2 8.2K_0402_5% PCI_REQ2# D
R164 1 2 8.2K_0402_5% PCI_REQ3#

U6B 1 0 PCI
PCI_REQ0# F1 D11
R165 1 REQ0# AD0
2 8.2K_0402_5% PCI_IRDY# PCI_GNT0# G4 GNT0# PCI AD1 C8
PCI_REQ1#
R166 1 2 8.2K_0402_5% PCI_DEVSEL#
B6
A7
REQ1#/GPIO50
GNT1#/GPIO51
AD2
AD3
D9
E12 1 1 LPC *
PCI_REQ2# F13 E9
R167 1 REQ2#/GPIO52 AD4
2 8.2K_0402_5% PCI_PERR# F12 GNT2#/GPIO53 AD5 C9
PCI_REQ3# E6 E10 +3VALW
R168 1 REQ3#/GPIO54 AD6
2 8.2K_0402_5% PCI_PLOCK# PCI_GNT3# F6 GNT3#/GPIO55 AD7 B7
C7 SPI_CS1#R @ R172 1 2 1K_0402_5%
AD8 <22> SPI_CS1#R
R169 1 2 8.2K_0402_5% PCI_SERR# D8 C5
C/BE0# AD9
B4 C/BE1# AD10 G11
R170 1 2 8.2K_0402_5% PCI_STOP# D6 F8 PCI_GNT0# @ R175 1 2 1K_0402_5%
C/BE2# AD11
A5 C/BE3# AD12 F11
R171 1 2 8.2K_0402_5% PCI_TRDY# E7
PCI_IRDY# AD13
D3 IRDY# AD14 A3
R173 1 2 8.2K_0402_5% PCI_FRAME#
/
E3 PAR AD15 D2
PCI_PCIRST# R1 F10 GNT0 & SPI_CS#1 have a weak internal pull up
R174 1 PCIRST# AD16
2 8.2K_0402_5% PCI_PME# PCI_DEVSEL# C6 DEVSEL# AD17 D5
/x
PCI_PERR# E4 D10
PCI_PLOCK# PERR# AD18
C2 PLOCK# AD19 B3
PCI_SERR# J4 F7
R176 1 SERR# AD20
2 8.2K_0402_5% PCI_PIRQA# PCI_STOP# A4 STOP# AD21 C3
PCI_TRDY# F5 F3
R177 1 TRDY# AD22 +3VALW
2 8.2K_0402_5% PCI_PIRQB# PCI_FRAME# D7 FRAME# AD23 F4
su
AD24 C1
C R178 1 2 8.2K_0402_5% PCI_PIRQC# PCI_PLTRST# C14 G7 1 C
PCI_CLK PLTRST# AD25
<6> PCI_CLK D4 PCICLK AD26 H7
R179 1 @ C954
2 8.2K_0402_5% PCI_PIRQD# PCI_PME# R2 PME# AD27 D1
G5 0.1U_0402_10V7K~D
R180 1 AD28 2
2 8.2K_0402_5% PCI_PIRQH# H6
p.
AD29 @ U7
5
AD30 G1
R181 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PCIRST# MC74VHC1G08DFT2G SC70 5P
R03 Modify H3 2
P
AD31 B
Y 4 PCI_RST# <24,27,28>
R182 1 2 8.2K_0402_5% PCI_PIRQG#
Interrupt I/F 1 A
G
om
ACCEL_INT# H4 J5 PCI_PIRQA#
R183 2 PIRQE#/GPIO2 PIRQA#
1 8.2K_0402_5% ACCEL_INT# PCI_PIRQF# K6 E1 PCI_PIRQB#
3
PCI_PIRQG# PIRQF#/GPIO3 PIRQB# PCI_PIRQC#
F2 PIRQG#/GPIO4 PIRQC# J6
PCI_PIRQH# G2 C4 PCI_PIRQD#
PIRQH#/GPIO5 PIRQD#
ICH9M_FCBGA676~D R184 2 1 0_0402_5%
C228 @ R185
@ 2 1 1 2 PCI_CLK
yc
22P_0402_50V8J 33_0402_5% +3VALW
+3VS
1
m
Free Fall Sensor @ C955
0.1U_0402_10V7K~D
2 @ U8
5
MC74VHC1G08DFT2G SC70 5P
// 2 1 PCI_PLTRST# 2
P
B PLT_RST#
Y 4 PLT_RST# <11,27,30,31>
B C961 C962 B
1 A
G
0.1U_0402_16V4Z~D 10U_0805_10V4Z~D
+3VS +3VS_ACL_IO 1 2
3
p:
@
1 2
R1004 0_0603_5%
R187 2 0_0402_5%
1
tt
U43 +3VS
DE351DLTR
h
+3VS_ACL_IO 1 VDD_IO
+3VS 6 VDD GND 2
ACCEL_INT# GND 4 A16 swap override Strap

8 INT 1 GND 5
9 INT 2 GND 10
Low= A16 swap override Enble
<6,17,18,21> ICH_SM_DA
12
13
SDO PCI_GNT3# High= Default *
SDA / SDI / SDO
<6,17,18,21> ICH_SM_CLK 14 SCL / SPC
3
RSVD
+3VS 1 2 7 CS 11
RSVD
R1005 10K_0402_5%
DE351DLTR_LGA14_3X5 PCI_GNT3# @ R186 1 2 1K_0402_5%
A Must be placed in the center of the system. A
P/N : SA000039C00 (S IC DE351DLTR LGA 14P MOTION SENSOR)

Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
ICH9-M(2/5)
A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-5152P
5 4 3 2 1
5 4 3 2 1
+3VS
Change PN: SB00000AR00 (S TR 2N7002DW T/R7 2N SOT-363-6) to
SB57002528L (S TR 2N7002DW-7-F 2N SOT-363)
1
R188 R189
Place closely pin AF3 Place closely pin H1
2.2K_0402_5% 2.2K_0402_5%
R03 memo modify CLK_48M_ICH CLK_14M_ICH
+3VALW
2
<6,17,18,20> ICH_SM_DA 1 6 ICH_SMBDATA
1
Q2A @ @
2N7002DW -7-F_SOT363-6~D If not used, pull-up to R190 R191
1
D 10_0402_5% 10_0402_5% D
Vcc3_3 or pull-down to GND
2
R192 R193
4 3ICH_SMBCLK 2.2K_0402_5% 2.2K_0402_5%
2
<6,17,18,20> ICH_SM_CLK Q2B
2N7002DW -7-F_SOT363-6~D U6C R996 1 @ 1 @
2
ICH_SMBCLK G16 SMBCLK AH23 GPIO21 1 2 C230
5
ICH_SMBDATA SATA0GP/GPIO21 GPIO19 C229
+3VS A13 SMBDATA SATA1GP/GPIO19 AF19 10K_0402_5% 4.7P_0402_50V8C~D
LINKALERT# E17 LINKALERT#/GPIO60/CLGPIO4 AE21 GPIO36 4.7P_0402_50V8C~D
SATA4GP/GPIO36 2 2
SATA
GPIO
ICH_SMLINK0 C17 SMLINK0 AD20 GPIO37
SMB
ICH_SMLINK1 SATA5GP/GPIO37
B18 SMLINK1
H1 CLK_14M_ICH
CLK14 CLK_14M_ICH <6>
ICH_RI# F19 AF3 CLK_48M_ICH
RI# CLK48 CLK_48M_ICH <6>
Clocks
+3VS
T64 SUS_STAT# R4 P1 ICH_SUSCLK T65 PAD
XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK
<7> XDP_DBRESET# G19 SYS_RESET#
C16 SLP_S3# ICH_PW ROK R195 1 2 100_0402_5%
SLP_S3# SLP_S3# <31> M_PW ROK <11>
R194 1 2 10K_0402_5% SERIRQ
<11> PM_SYNC#
PM_SYNC# M6 PMSYNC#/GPIO0 SLP_S4# E16 SLP_S4#
SLP_S4# <11,31>
1
G17 SLP_S5#
10K_0402_5%
R198 1 SLP_S5# SLP_S5# <31>
2 8.2K_0402_5% EC_THERM#
<31> EC_LID_OUT#
EC_LID_OUT# A17 SMBALERT#/GPIO11
R197
/
S4_STATE#/GPIO26 C10 T66 PAD
R199 1 2 10K_0402_5% LAN_CABDT H_STP_PCI# A14
<6> H_STP_PCI# H_STP_CPU# STP_PCI# ICH_PW ROK
E19 G20 ICH_PW ROK <11,31>
SYS GPIO
2
R200 1 <6> H_STP_CPU# STP_CPU# PWROK
2 10K_0402_5%
/x
OCP#
L4 CLKRUN# DPRSLPVR/GPIO16 M2 DPRSLPVR <11,43>
@ R201 1 2 8.2K_0402_5% EC_SCI# R207
ICH_PCIE_W AKE# E20 B13 ICH_LOW _BAT# ICH_LOW _BAT# 2 1 +3VALW
<24,27,28,31> ICH_PCIE_W AKE# WAKE# BATLOW#
Power MGT
SERIRQ M5 8.2K_0402_5%
<31> SERIRQ SERIRQ
EC_THERM# AJ23 R3 PBTN_OUT#
<31> EC_THERM# THRM# PWRBTN# PBTN_OUT# <31>
su
+3VALW
C 1 R203 2 VRMPW RGD D21 D20 C
R206 1 <11,31,43> VGATE VRMPWRGD LAN_RST#
2 10K_0402_5% LINKALERT#
R211 1
1 2
0_0402_5%
T67 A20 TP11 RSMRST# D22 R_EC_RSMRST# 1
R205
2 RSMRST circuit
2 10K_0402_5% ICH_SMLINK0 R204 100K_0402_5% PAD 10K_0402_5%
OCP# AG19 R5 CK_PW RGD
p.
R213 1 <7> OCP# GPIO1 CK_PWRGD CK_PW RGD <6>
2 10K_0402_5% ICH_SMLINK1
<24> LAN_LOPW EN
LAN_LOPW EN AH21 GPIO6 @ R219 R220
AG21 R6 M_PW ROK 2 1 2 1
R209 1 GPIO7 CLPWROK M_PW ROK <11> <40> POK EC_RSMRST# <31>
2 10K_0402_5% ICH_RI#
<31> EC_SMI#
EC_SMI# A21 GPIO8 0_0402_5% 0_0402_5%
EC_SCI# C12 B16 T68 PAD
<31> EC_SCI# GPIO12 SLP_M#
om
R210 1 2 10K_0402_5% XDP_DBRESET# PAD T69 C21 R_EC_RSMRST#
GPIO13 CL_CLK0
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 <11>
R214 1 2 10K_0402_5% EC_LID_OUT# K1 GPIO18 CL_CLK1 B19
R02 add PAD T81 AF8
R208 1 GPIO20
2 1K_0402_5% ICH_PCIE_W AKE# AJ22 SCLOCK/GPIO22 CL_DATA0 F22 CL_DATA0
CL_DATA0 <11>
PAD T70 A9 GPIO27 CL_DATA1 C19
GPIO
Controller Link
PAD T71 D19 GPIO28
CLKSATAREQ# L1 C25 CL_VREF0_ICH R212 1 2 3.24K_0402_1% +3VS
yc
R216 1 <6> CLKSATAREQ# SATACLKREQ#/GPIO35 CL_VREF0
2 8.2K_0402_5% EC_SMI# AE19 SLOAD/GPIO38 CL_VREF1 A19
1
453_0402_1%
AG22 SDATAOUT0/GPIO39 1
AF21 F21 CL_RST#
SDATAOUT1/GPIO48 CL_RST0# CL_RST# <11> C231
R215
GPIO49 has a weak internal pull-up AH24 GPIO49 CL_RST1# D18
A8 0.1U_0402_10V7K~D
m
GPIO57/CLGPIO5 2
@ A16
2
R218 1 MEM_LED/GPIO24
+3VS 2 10K_0402_5% SB_SPKR
<25> SB_SPKR
SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18
MCH_ICH_SYNC# AJ24 C11
<11> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT ACIN <25,31,38,39>
ICH_TP3 B21 C20 1 2
<19> ICH_TP3 TP3 WOL_EN/GPIO9 LAN_CABDT <24>
low --> default R217 0_0402_5%
PAD T72
// AH20 @
MISC
TP8
PAD T73 AJ20 TP9
High -->No reboot PAD T74 AJ21 TP10
B B
ICH9M_FCBGA676~D Maybach CL_CLK1/DATA1 connect to WLAN card
to support iAMT
p:
tt
h
A A
LA-5152P
5 4 3 2 1
5 4 3 2 1
D D
U6D
PCIE_IRX_W ANTX_N1 N29 V27 DMI_MTX_IRX_N0
<27> PCIE_IRX_W ANTX_N1 PERN1 DMI0RXN DMI_MTX_IRX_N0 <11>
PCIE_IRX_W ANTX_P1 N28 V26 DMI_MTX_IRX_P0
<27> PCIE_IRX_W ANTX_P1 C232 1 0.1U_0402_10V7K~D PERP1 DMI0RXP DMI_MTX_IRX_P0 <11>
MiniWWAN (Mini Card 1)---> 2 PCIE_ITX_W ANRX_N1 P27 U29 DMI_MRX_ITX_N0
Direct Media Interface

<27> PCIE_ITX_C_W ANRX_N1 C233 1 0.1U_0402_10V7K~D PCIE_ITX_W ANRX_P1 PETN1 DMI0TXN DMI_MRX_ITX_P0 DMI_MRX_ITX_N0 <11>
<27> PCIE_ITX_C_W ANRX_P1 2 P26 PETP1 DMI0TXP U28 DMI_MRX_ITX_P0 <11>
PCIE_IRX_W LANTX_N2 L29 Y27 DMI_MTX_IRX_N1
<27> PCIE_IRX_W LANTX_N2 PERN2 DMI1RXN DMI_MTX_IRX_N1 <11>
PCIE_IRX_W LANTX_P2 L28 Y26 DMI_MTX_IRX_P1
<27> PCIE_IRX_W LANTX_P2 C234 PERP2 DMI1RXP DMI_MTX_IRX_P1 <11>
MiniWLAN (Mini Card 2)---> <27> PCIE_ITX_C_W LANRX_N2 1 2 0.1U_0402_10V7K~D PCIE_ITX_W LANRX_N2 M27 PETN2 DMI1TXN W29 DMI_MRX_ITX_N1
DMI_MRX_ITX_N1 <11>
C235 1 2 0.1U_0402_10V7K~D PCIE_ITX_W LANRX_P2 M26 W28 DMI_MRX_ITX_P1
<27> PCIE_ITX_C_W LANRX_P2 PETP2 DMI1TXP DMI_MRX_ITX_P1 <11>
/
PCIE_IRX_W PANTX_N3 J29 AB27 DMI_MTX_IRX_N2
<28> PCIE_IRX_W PANTX_N3 PERN3 DMI2RXN DMI_MTX_IRX_N2 <11>
PCIE_IRX_W PANTX_P3 J28 AB26 DMI_MTX_IRX_P2
<28> PCIE_IRX_W PANTX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2 <11>
/x
MiniWPAN (Mini Card 3)---> C236 1 2 0.1U_0402_10V7K~D PCIE_ITX_W PANRX_N3 K27 AA29 DMI_MRX_ITX_N2
PCI-Express
<28> PCIE_ITX_C_W PANRX_N3 C237 1 PETN3 DMI2TXN DMI_MRX_ITX_N2 <11>
<28> PCIE_ITX_C_W PANRX_P3 2 0.1U_0402_10V7K~D PCIE_ITX_W PANRX_P3 K26 PETP3 DMI2TXP AA28 DMI_MRX_ITX_P2
DMI_MRX_ITX_P2 <11>
PCIE_IRX_CBPTX_N4 G29 AD27 DMI_MTX_IRX_N3
<30> PCIE_IRX_CBTX_N4 PERN4 DMI3RXN DMI_MTX_IRX_N3 <11>
PCIE_IRX_CBPTX_P4 G28 AD26 DMI_MTX_IRX_P3
<30> PCIE_IRX_CBTX_P4 PERP4 DMI3RXP DMI_MTX_IRX_P3 <11>
Cardbus---> <30> PCIE_ITX_C_CBRX_N4
C238 1 2 0.1U_0402_10V7K~D PCIE_ITX_CBPRX_N4 H27 PETN4 DMI3TXN AC29 DMI_MRX_ITX_N3
DMI_MRX_ITX_N3 <11>
su
C239 1 2 0.1U_0402_10V7K~D PCIE_ITX_CBPRX_P4 H26 AC28 DMI_MRX_ITX_P3
C <30> PCIE_ITX_C_CBRX_P4 PETP4 DMI3TXP DMI_MRX_ITX_P3 <11> C
PCIE_IRX_EXPTX_N5 E29 T26 CLK_DMI_ICH#
<28> PCIE_IRX_EXPTX_N5 PERN5 DMI_CLKN CLK_DMI_ICH# <6>
PCIE_IRX_EXPTX_P5 E28 T25 CLK_DMI_ICH Within 500 mils
<28> PCIE_IRX_EXPTX_P5 PERP5 DMI_CLKP CLK_DMI_ICH <6>
Express card---> <28> PCIE_ITX_C_EXPRX_N5
C240 1 2 0.1U_0402_10V7K~D PCIE_ITX_EXPRX_N5 F27 PETN5
C241 1 2 0.1U_0402_10V7K~D PCIE_ITX_EXPRX_P5 F26 AF29
p.
<28> PCIE_ITX_C_EXPRX_P5 PETP5 DMI_ZCOMP DMI_IRCOMP R221 1
DMI_IRCOMP AF28 2 24.9_0402_1% +1.5VS
PCIE_IRX_GLANTX_N6 C29
<24> PCIE_IRX_GLANTX_N6 PERN6/GLAN_RXN
PCIE_IRX_GLANTX_P6 C28 AC5 USBP0-
<24> PCIE_IRX_GLANTX_P6 PERP6/GLAN_RXP USBP0N USBP0- <30>
C242 1 2 0.1U_0402_10V7K~D PCIE_ITX_GLANRX_N6 D27 AC4 USBP0+
<24> PCIE_ITX_C_GLANRX_N6 PETN6/GLAN_TXN USBP0P USBP0+ <30>
om
10/100/1G LAN ---> <24> PCIE_ITX_C_GLANRX_P6
C243 1 2 0.1U_0402_10V7K~D PCIE_ITX_GLANRX_P6 D26 PETP6/GLAN_TXP USBP1N AD3 USBP1-
USBP1- <30>
USBP1+ USB Port
D23
USBP1P AD2
AC1 USBP2-
USBP1+ <30> Device
SPI_CLK USBP2N USBP2- <30>
USBP2+ 0
SPI_CS1#R
D24
F23
SPI_CS0# USBP2P AC2
AA5
USBP2+ <30> USB&ESATA
<20> SPI_CS1#R SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P AA4
USBP4-
1 Reader board
D25 SPI_MOSI USBP4N AB2 USBP4- <27>
USBP4+ 2
E23 AB3 USB board
yc
SPI
+3VALW SPI_MISO USBP4P USBP4+ <27>
AA1 USBP5-
USBP5N USBP5- <27>
ESATA_USB_OC# USBP5+ 3
<30> ESATA_USB_OC#
USB_OC1#
N4
N5
OC0#/GPIO59 USBP5P AA2
W5 USBP6-
USBP5+ <27> NC
R222 10K_0402_5% <30> USB_OC1# OC1#/GPIO40 USBP6N USBP6- <28>
ESATA_USB_OC# USB_OC2# USBP6+
R223
1
1
2
2 10K_0402_5% USB_OC1#
<30> USB_OC2#
USB_OC3#
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3 USBP7-
USBP6+ <28> 4 WLAN
USBP7- <28>
m
R882 10K_0402_5% USB_OC2# USB_OC4# OC3#/GPIO42 USBP7N USBP7+
R224
1 2
10K_0402_5% USB_OC3# USB_OC5#
M1 OC4#/GPIO43 USBP7P Y2 USBP7+ <28> 5 WWAN
1 2 N2 OC5#/GPIO29 USBP8N W1
R225 USB_OC4# USB_OC6#
R226
1 2 10K_0402_5%
10K_0402_5% USB_OC5# USB_OC7#
M4 OC6#/GPIO30 USBP8P W2
USBP9-
6 WPAN
1 2 M3 OC7#/GPIO31 USBP9N V2 USBP9- <32>
R227 10K_0402_5% USB_OC6# USB_OC8# USBP9+
R228
1
1
2
2 10K_0402_5% USB_OC7#
// USB_OC9#
N3
N1
OC8#/GPIO44
OC9#/GPIO45
USBP9P
USBP10N
V3
U5 USBP10-
USBP9+ <32>
USBP10- <30>
7 Express
R229 10K_0402_5% USB_OC8# USB_OC10# USBP10+
B
1 2
10K_0402_5% USB_OC9# USB_OC11#
P5 OC10#/GPIO46 USBP10P U4
USBP11-
USBP10+ <30> 8 NC B
R230 1 2 P3 U1 USBP11- <30>
R231 10K_0402_5% USB_OC10# OC11#/GPIO47 USBP11N USBP11+
R883
1 2
10K_0402_5% USB_OC11# USBRBIAS USBP11P U2 USBP11+ <30> 9 Touch screen
1 2 2 1 AG2 USBRBIAS
p:
R232 10
22.6_0402_1%
AG1 USBRBIAS# Bluetooth
Within 500 mils ICH9M_FCBGA676~D 11 Camera
tt
h
A A
LA-5152P
5 4 3 2 1
5 4 3 2 1
U6E
+RTCVCC +1.05V_VCCP AA26 H5
VSS[1] VSS[107]
20 mils U6F AA27
VSS[2] VSS[108]
J23
+5VS +3VS A23 A15 1634mA AA3 J26
VCCRTC VCC1_05[1] VSS[3] VSS[109]
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
B15 AA6 J27
+ICH_V5REF_RUN VCC1_05[2] VSS[4] VSS[110]
2mA A6 V5REF VCC1_05[3] C15 AB1 VSS[5] VSS[111] AC22
2
D15 1 1 AA23 K28
+ICH_V5REF_SUS VCC1_05[4] VSS[6] VSS[112]
R233 1 1 2mA AE1 V5REF_SUS VCC1_05[5] E15 AB28 VSS[7] VSS[113] K29
C249
C245
D2 F15 AB29 L13
C244
100_0402_5%
C248
SDMK0340L-7-F_SOD323-2~D VCC1_05[6] VSS[8] VSS[114]
646mA AA24 VCC1_5_B[1] VCC1_05[7] L11
2 2
AB4 VSS[9] VSS[115] L15
AA25 L12 AB5 L2
2
1
2 2 VCC1_5_B[2] VCC1_05[8] VSS[10] VSS[116]
AB24 VCC1_5_B[3] VCC1_05[9] L14 AC17 VSS[11] VSS[117] L26
+ICH_V5REF_RUN AB25 L16 AC26 L27
VCC1_5_B[4] VCC1_05[10] VSS[12] VSS[118]
1 20 mils AC24
VCC1_5_B[5] VCC1_05[11]
L17 AC27
VSS[13] VSS[119]
L5
AC25 L18 L6 AC3 L7
D C246 VCC1_5_B[6] VCC1_05[12] VSS[14] VSS[120] D
1U_0402_6.3V6K~D AD24 VCC1_5_B[7] VCC1_05[13] M11 1 2 +1.5VS AD1 VSS[15] VSS[121] M12
0.01U_0402_16V7K~D
AD25 M18 1UH_GLF2012T1R0M_20%_0805~D AD10 M13
2 VCC1_5_B[8] VCC1_05[14] VSS[16] VSS[122]
AE25 VCC1_5_B[9] VCC1_05[15] P11 1 1 AD12 VSS[17] VSS[123] M14
AE26 P18 C250 AD13 M15
C247
VCC1_5_B[10] VCC1_05[16] 10U_0805_10V4Z~D VSS[18] VSS[124]
AE27 T11 AD14 M16
VCC1_5_B[11] VCC1_05[17] VSS[19] VSS[125]
AE28 T18 AD17 M17
+5VALW +3VALW VCC1_5_B[12] VCC1_05[18] 2 2 VSS[20] VSS[126]
AE29 U11 AD18 M23
VCC1_5_B[13] VCC1_05[19] VSS[21] VSS[127]
CORE
F25 U18 AD21 M28
VCC1_5_B[14] VCC1_05[20] VSS[22] VSS[128]
G25 V11 AD28 M29
VCC1_5_B[15] VCC1_05[21] VSS[23] VSS[129]
1
H24 V12 L5 AD29 N11

D3 VCC1_5_B[16] VCC1_05[22] VSS[24] VSS[130]
H25 V14 1 2 +1.05V_VCCP AD4 N12
R234 SDMK0340L-7-F_SOD323-2~D VCC1_5_B[17] VCC1_05[23] VSS[25] VSS[131]
J24 VCC1_5_B[18] VCC1_05[24] V16 BLM18PG600SN1_0603~D AD5 VSS[26] VSS[132] N13
100_0402_5% J25 V17 AD6 N14
VCC1_5_B[19] VCC1_05[25] 1 VSS[27] VSS[133]
K24 V18 AD7 N15
2
+ICH_V5REF_SUS VCC1_5_B[20] VCC1_05[26] C251 VSS[28] VSS[134]

K25 VCC1_5_B[21] AD9 VSS[29] VSS[135] N16
20 mils L23 VCC1_5_B[22] VCCDMIPLL R29 +VCCDMIPLL 4.7U_0603_6.3V6M~D AE12 VSS[30] VSS[136] N17
2
1 L24 VCC1_5_B[23] 23mA AE13 VSS[31] VSS[137] N18
C252 L25 VCC1_5_B[24] VCC_DMI[1] W23 +VCC_DMI_ICH AE14 VSS[32] VSS[138] N26
M24 Y23 48mA +1.05V_VCCP AE16 N27
1U_0402_6.3V6K~D VCC1_5_B[25] VCC_DMI[2] VSS[33] VSS[139]
M25 VCC1_5_B[26] AE17 VSS[34] VSS[140] P12
2
N23 VCC1_5_B[27] V_CPU_IO[1] AB23 AE2 VSS[35] VSS[141] P13
/
4.7U_0603_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
N24 VCC1_5_B[28] V_CPU_IO[2] AC23 2mA AE20 VSS[36] VSS[142] P14
N25 VCC1_5_B[29] AE24 VSS[37] VSS[143] P15
+1.5VS +1.5VS_PCIE_ICH P24 AG29 AE3 P16
VCC1_5_B[30] VCC3_3[1] +3VS 1 1 1 VSS[38] VSS[144]
L7 40 mils
/x
P25 AE4 P17
0805
0.1U_0402_10V7K~D
VCC1_5_B[31] VSS[39] VSS[145]
VCCA3GP
C253
C254
C255
1 2 R24 VCC1_5_B[32] VCC3_3[2] AJ6 +3VS 1 AE6 VSS[40] VSS[146] P2
BLM21PG331SN1D_2P~D R25 AE9 P23
C259
1
0.1U_0402_10V7K~D
VCC1_5_B[33] 2 2 2 VSS[41] VSS[147]
220U_D2_4VY_R15M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
2.2U_0603_6.3V6K~D
1 1 1 1 R26 AC10 +3VS AF13 P28
C262
VCC1_5_B[34] VCC3_3[7] VSS[42] VSS[148]
C258
R27 AF16 P29

C260
C257
VCC1_5_B[35] 1 2 VSS[43] VSS[149]

+
C256
T24 VCC1_5_B[36] VCC3_3[3] AD19 AF18 VSS[44] VSS[150] P4

C261 2
T27 AF20 AF22 P7
su
2 2 2 VCC1_5_B[37] VCC3_3[4] 0.1U_0402_10V7K~D VSS[45] VSS[151]
VCCP_CORE
T28 VCC1_5_B[38] VCC3_3[5] AG24 AH26 VSS[46] VSS[152] R11
C 2 T29 AC20 2 AF26 R12 C
VCC1_5_B[39] VCC3_3[6] VSS[47] VSS[153]
U24 VCC1_5_B[40] 308mA AF27 VSS[48] VSS[154] R13
U25 VCC1_5_B[41] VCC3_3[8] B9 +3VS AF5 VSS[49] VSS[155] R14
V24 VCC1_5_B[42] VCC3_3[9] F9 1 AF7 VSS[50] VSS[156] R15
V25 VCC1_5_B[43] VCC3_3[10] G3 C263 AF9 VSS[51] VSS[157] R16
p.
U23 VCC1_5_B[44] VCC3_3[11] G6 0.1U_0402_10V7K~D AG13 VSS[52] VSS[158] R17
W24 VCC1_5_B[45] VCC3_3[12] J2 AG16 VSS[53] VSS[159] R18
W25 J7 2 AG18 R28
PCI
VCC1_5_B[46] VCC3_3[13] VSS[54] VSS[160]
K23 K7 AG20 T12
VCC1_5_B[47] VCC3_3[14] VSS[55] VSS[161]
Y24 AG23 T13
VCC1_5_B[48] VSS[56] VSS[162]
om
+1.5VS Y25 AJ4 11mA R879 1 2 0_0402_5% AG3 T14
VCC1_5_B[49] VCCHDA +1.5VS VSS[57] VSS[163]
L8 R881 1 AG6 T15
+VCCSATAPLL VSS[58] VSS[164]
1 2 47mA AJ19
VCCSATAPLL VCCSUSHDA
AJ3 11mA 1 2 +1.5V C264
AG9
VSS[59] VSS[165]
T16
10UH_LB2012T100MR_20%_0805~D 1 0_0402_5% AH12 T17
0.1U_0402_10V7K~D VSS[60] VSS[166]
10U_0805_10V4Z~D
1U_0603_10V6K~D
+1.5VS AC16 AC8 AH14 T23

VCC1_5_A[1] VCCSUS1_05[1] T75 2 VSS[61] VSS[167]
1 1 AD15 F17 C265 AH17 B26
VCC1_5_A[2] VCCSUS1_05[2] T76 VSS[62] VSS[168]
C266
C268
1 AD16 AH19 U12

VCC1_5_A[3] 2 0.1U_0402_10V7K~D VSS[63] VSS[169]
ARX
AE15 AD8 +VCCSUS1_5_ICH_1 AH2 U13
VCC1_5_A[4] VCCSUS1_5[1] T77 VSS[64] VSS[170]
yc
C267 AF15 AH22 U14
2 2 1U_0603_10V6K~D VCC1_5_A[5] +VCCSUS1_5_ICH_2 VSS[65] VSS[171]
AG15 F18 1 2 AH25 U15
2 VCC1_5_A[6] VCCSUS1_5[2] C269 0.1U_0402_10V7K~D VSS[66] VSS[172]
AH15 AH28 U16
VCC1_5_A[7] VSS[67] VSS[173]
AJ15 R974 AH5 U17
VCC1_5_A[8] VSS[68] VSS[174]
A18 +3VALW_ICH 1 2 +3VALW_S5_ICH AH8 AD23
VCCSUS3_3[1] VSS[69] VSS[175]
VCCPSUS
+1.5VS 1342mA AC11

VCC1_5_A[9] VCCSUS3_3[2]
D16 0_0603_5% AJ12
VSS[70] VSS[176]
U26
m
1 AD11 D17 AJ14 U27
VCC1_5_A[10] VCCSUS3_3[3] VSS[71] VSS[177]
AE11 E22 AJ17 U3
C270 VCC1_5_A[11] VCCSUS3_3[4] VSS[72] VSS[178]
ATX
AF11 AJ8 V1
1U_0603_10V6K~D VCC1_5_A[12] VSS[73] VSS[179]
2
AG10
VCC1_5_A[13] 212mA R975 B11
VSS[74] VSS[180]
V13
AG11 AF1 +3VALW_USB_ICH 1 2 +3VALW_S5_ICH B14 V15
AH10
VCC1_5_A[15]
// 0_0603_5% B17
VSS[76] VSS[182]
V23
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
AJ10 T1 B2 V28
0.1U_0402_10V7K~D
T2 B20 V29
B VCCSUS3_3[7] VSS[78] VSS[184] B
AC9 T3 1 1 1 B23 V4
C271
C272
T4 B5 V5
C273
VCCSUS3_3[9] VSS[80] VSS[186]
AC18
VCC1_5_A[18] VCCSUS3_3[10]
T5 R03 Modify B8
VSS[81] VSS[187]
W26
AC19 T6 C26 W27
p:
VCC1_5_A[19] VCCSUS3_3[11] 2 2 2 VSS[82] VSS[188]

+1.5VS VCCSUS3_3[12]
U6 Reduce ICH power consumptionat S5 mode. C27
VSS[83] VSS[189]
W3
VCCPUSB
AC21 U7 E11 Y1
VCC1_5_A[20] VCCSUS3_3[13] +3VALW +3VALW_S5_ICH VSS[84] VSS[190]
1 V6 E14 Y28
VCCSUS3_3[14] @ VSS[85] VSS[191]
G10 V7 E18 Y29
C274 VCC1_5_A[21] VCCSUS3_3[15] VSS[86] VSS[192]
G9 W6 1 2 E2 Y4
tt
0.1U_0402_10V7K~D VCC1_5_A[22] VCCSUS3_3[16] R1022 0_0805_5% VSS[87] VSS[193]

W7 E21 Y5
2 VCCSUS3_3[17] Q47 VSS[88] VSS[194]
AC12 Y6 E24 AG28
D
1U_0603_10V6K~D
AC13 Y7 B+_BIAS 6 20mil E5 AH6
S
+1.5VS AC14 T7 1 5 4 E8 AF2
300K_0402_5%
R972
C966
h
1 2 SI3456BDV-T1-E3_TSOP6~D F16 B25

VSS[92] VSS[198]
2
11mA AJ5 C275 1
G22 +VCCCL1_05_ICH 2 0.1U_0402_10V7K~D 1 F28
C276 VCCUSBPLL VCCCL1_05 VSS[93]
F29 A1
G
0.1U_0402_10V7K~D +VCCCL1_5_ICH 2 VSS[94] VSS_NCTF[1]
11mA AA7 G23 G12 A2
3
2 VCC1_5_A[26] VCCCL1_5 VSS[95] VSS_NCTF[2]
USB CORE
19/73/73mA
0.1U_0402_10V7K~D
AB6 G14 A28
1U_0603_10V6K~D
VCC1_5_A[27] @ 1 VSS[96] VSS_NCTF[3]

AB7 A24 +3VS 1 @ G18 A29
1
VCC1_5_A[28] VCCCL3_3[1] VSS[97] VSS_NCTF[4]
AC6 B24 G21 AH1
C277
C278
VCC1_5_A[29] VCCCL3_3[2] VSS[98] VSS_NCTF[5]
AC7 G24 AH29
VCC1_5_A[30] VSS[99] VSS_NCTF[6]
G26 AJ1
VSS[100] VSS_NCTF[7]
2
C279 1 2 2 D
2 0.1U_0402_10V7K~D +VCCLAN1_05_INT_ICH A10 G27 AJ2
VCCLAN1_05[1] Q46 R973 VSS[101] VSS_NCTF[8]
A11 <33> SYSON# 2 G8 AJ28
VCCLAN1_05[2] G SSM3K7002FU_SC70-3~D 2M_0402_5% VSS[102] VSS_NCTF[9]
H2 AJ29
VSS[103] VSS_NCTF[10]
+3VS A12 S H23 B1
3
VCCLAN3_3[1] VSS[104] VSS_NCTF[11]
0.1U_0402_10V7K~D
1 B12 H28 B29
1
VCCLAN3_3[2] VSS[105] VSS_NCTF[12]
H29
C280
VSS[106]
23mA A27 VCCGLANPLL ICH9M_FCBGA676~D
2 +1.5VS_PCIE_ICH
GLAN POWER
80mA D28 VCCGLAN1_5[1]

D29 VCCGLAN1_5[2]
A A
E26 VCCGLAN1_5[3]
E27 VCCGLAN1_5[4]
4.7U_0603_6.3V6M~D
L9 1
1 2 +VCCGLANPLL A26
+1.5VS +3VS
C281
VCCGLAN3_3
2.2U_0603_6.3V6K~D
1mA
10U_0805_10V4Z~D
1UH_GLF2012T1R0M_20%_0805~D
ICH9M_FCBGA676~D
2
1 1 Compal Electronics, Inc.
C282
C283
2 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH9M (5/5)
LA-5152P
5 4 3 2 1
A B C D E
Q3
+3VALW SI3456BDV-T1-E3_TSOP6~D
W=60mils FBMA-L11-322513-201LMA40T_1210 +LAN_IO
D
6 L10 W=60mils
S
1 5 4 1 2
C284 2
1
22U_1206_6.3V6M~D
0.1U_0402_10V7K~D
1U_0603_10V6K~D
22U_1206_6.3V6M~D
1 1 1
G
2
C285
C286
3
C287
W=60mils +LAN_VDD
R236 EN_WOL 2 @ 2 2 L11
B+_BIAS 2 1
300K_0402_5% 1 2
2200P_0402_50V7K~D
22U_1206_6.3V6M~D
1 1
0.1U_0402_10V7K~D
4.7UH_1008HC-472EJFS-A_5%_1008
1
2M_0402_5%
1 1 1
1
D
R1540
C306
C307
C958
2 Q4
<31> EN_WOL#
G
SSM3K7002FU_SC70-3~D S 2 2 2
2
+LAN_IO
These caps close to U9: Pin 4
1
+LAN_DVDD12
These components close to U9: Pin 48
R947
3.6K_0402_5% ( Should be place within 200 mils )
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
U9 1 2
C303
C302
C304 2 1 0.1U_0402_10V7K~D PCIE_IRX_C_GLANTX_P6 20 33 LAN_LED3 W=30mils W=30mils
<22> PCIE_IRX_GLANTX_P6 HSOP LED3/EEDO LAN_LED2 @R884
@ R884
LED2/EEDI/AUX 34
C305 2 1 0.1U_0402_10V7K~D PCIE_IRX_C_GLANTX_N6 21 35 LAN_LED1 2 1 2 1
<22> PCIE_IRX_GLANTX_N6 HSON LED1/EESK +LAN_VDD
32 0_0603_5%
PCIE_ITX_C_GLANRX_P6 EECS
<22> PCIE_ITX_C_GLANRX_P6 15 HSIP
1 2
38 LAN_LED0 C310 1U_0603_16V6K~D
LED0
/
PCIE_ITX_C_GLANRX_N6 16 1 2
<22> PCIE_ITX_C_GLANRX_N6 HSIN LAN_MDIP0
RTL8111DL MDIP0 2 C311 1U_0603_16V6K~D
17 3 LAN_MDIN0
<6> CLK_PCIE_GLAN REFCLK_P MDIN0 LAN_MDIP1
/x
<6> CLK_PCIE_GLAN# 18 REFCLK_N MDIP1 5
6 LAN_MDIN1 These caps close to U9: Pin 19
MDIN1 LAN_MDIP2
25 CLKREQB MDIP2 8
<6> GLAN_CLKREQ# LAN_MDIN2
MDIN2 9
LAN_MDIP3
LINK OK
<20,27,28> PCI_RST# 27 PERSTB MDIP3 11
12 LAN_MDIN3 +LAN_DVDD12@ R246 JRJ45
MDIN3 LAN_LED0 LAN_ACTIVITY#
R235 1 2 13
su
R239 +LAN_DVDD12 Yellow LED-
1 2 46 RSET FB12 4 +LAN_DVDD12 2 1 +LAN_VDD 220_0402_5%
2 2.49K_0402_1% 2
0_0603_5% +LAN_IO 12 Yellow LED+
<21,27,28,31> ICH_PCIE_WAKE#
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
ISOLATEB
26 LANWAKEB SROUT12 48 W=60mils RJ45_TX3-
+3VS R240 1 2 1K_0402_5% 28 1 1 1 1 1 8
ISOLATEB PR4-
0.1U_0402_10V7K~D
EVDD12 19
C293
C296
C295
C294
C292
R241 1 2 0_0402_5% LAN_CKTAL1 41 30 RJ45_TX3+ 7
<21> LAN_LOPWEN CKTAL1 DVDD12 PR4+
2
p.
LAN_CKTAL2 42 36
R242 CKTAL2 DVDD12 2 2 2 2 2 RJ45_RX1-
@ DVDD12 13 6 PR2-
15K_0402_5% 10
AVDD12 RJ45_TX2- 5
PR3-
39
1
AVDD12
om
W=40mils RJ45_TX2+ 4
PR3+
<21> LAN_CABDT 23 44
GPO VDDSR RJ45_RX1+
24 45 3
NC VDDSR PR2+
These caps close to U9: Pin 10, 13, 30, 36, 39 RJ45_TX0-
7 29 2
GND VDD33 PR1-
14 37 14
GND VDD33 RJ45_TX0+ GND
31 1
GND PR1+
47 1 R244 15
GND AVDD33 GND
yc
40 These caps close to U9: Pin 44.45 LED1_LED3 1 2 LINK_100_1000# 11
AVDD33 Orange LED-
22 43 +LAN_IO 220_0402_5%
LAN_CKTAL1 EGND ENSR
( Should be place within 200 mils ) +LAN_IO 10
Yellow LED+
R02 Modify LAN_CKTAL2
2 1 +LAN_IO
LED2_LED3 1
R245
LINK_10_1000#
RTL8111DL-GR_LQFP48_7X7 R942 @ 0_0805_5% 2 9
Y3 Green LED-
22U_1206_6.3V6M~D
C308
0.1U_0402_10V7K~D
1 1 220_0402_5%
m
1 2 FOX_JM3611A-R4953B-7F
C309
1 2 CONN@
25MHZ_20P_1BX25000CK1A
C318 C319 2 2
33P_0402_50V8J~D 27P_0402_50V8J~D
2 1
//
3
12/11 reserve for EMI as Dell Tony request. 3
These caps close to U9: Pin 1.29, 37, 40 LAN_MDIN3 C873 1 2 6.8P_0402_50V8C~D
p:
+LAN_IO
TS1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
RP1 1 1 1 1 LAN_MDIP3 C874 1 2 6.8P_0402_50V8C~D
C320 1 2 0.01U_0402_16V7K~D V_DAC 1 24 5 4
TCT1 MCT1
C288
C289
C290
C291
LAN_MDIN3 2 23 RJ45_TX3- 6 3 LAN_MDIN1 C875 1 2 6.8P_0402_50V8C~D
LAN_MDIP3 TD1+ MX1+ RJ45_TX3+
3 22 7 2
tt
TD1- MX1- 2 2 2 2 LAN_MDIN2 C876 1

8 1 2 6.8P_0402_50V8C~D
C321 1 2 0.01U_0402_16V7K~D V_DAC 4
TCT2 MCT2
21
LAN_MDIN2 5 20 RJ45_TX2- 75_1206_8P4R_5% LAN_MDIP2 C877 1 2 6.8P_0402_50V8C~D
6 19 2
TD2- MX2-
h
C323 LAN_MDIP1 C878 1 2 6.8P_0402_50V8C~D

C322 1 2 0.01U_0402_16V7K~D V_DAC 7
TCT3 MCT3
18 1000P_1206_2KV7~D
LAN_MDIN1 8 17 RJ45_RX1- LAN_MDIN0 C879 1 2 6.8P_0402_50V8C~D
LAN_MDIP1 TD3+ MX3+ RJ45_RX1+ 1 D4 D6
9 16
TD3- MX3- LAN_LED2 1 LED2_LED3 LAN_LED1 1 LED1_LED3 LAN_MDIP0 C880 1
2 2 2 6.8P_0402_50V8C~D
C324 1 2 0.01U_0402_16V7K~D V_DAC 10 15
LAN_MDIN0 TCT4 MCT4 RJ45_TX0- SDMK0340L-7-F_SOD323-2~D SDMK0340L-7-F_SOD323-2~D
11 14
12 13
TD4- MX4- D5 D7
LAN_LED3 1 2 LAN_LED3 1 2
BOTH_GST5009-LF SDMK0340L-7-F_SOD323-2~D SDMK0340L-7-F_SOD323-2~D
4 4
LEDS1-0 00 01 10 11
LED0 Tx / Rx Tx / Rx Tx LINK10 / ACT

LED1 LINK100 LINK10 /100 / 1000 LINK LINK100 / ACT
LED2 LINK10 LINK10 / 100 Rx FULL PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Gigabit LAN_RTL8111DL
LED3 LINK1000 LINK1000 FULL LINK1000 / ACT NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1A
LA-5152P
A B C D E
A B C D E F G H
+3VS
+3VS
C968
1 2 2
@ +DVDD_AUDIO +3VS +AVDD_AUDIO @ +5VS
C325
+3VS R1549 1 2 20K_0402_5% 0.1U_0402_16V4Z~D +1.5VS R250 R248
5
U46 2 1 +AVDD_AUDIO 2 1 1U_0603_10V6K~D
EAPD# 1 1
0_0603_5% 0_0603_5%
P
IN1
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
4 EA_EC_SPK_MUTE#
0.1U_0402_10V7K~D
19
10
1U_0402_6.3V6K~D
O
0.1U_0402_10V7K~D
10U_0603_6.3V6M~D
EC_SPK_HP_MUTE# 2 +3VS U10
<31> EC_SPK_HP_MUTE# IN2 1 1 1 1 1
G
C952
C333
C327
1 1 1 1
C334
PVDD
SVDD
C335
C328
C332
1 2 74AHC1G08GW_SOT353-5~D R02 Modify 1 2 14 11 HP1_AMP_R
C326
C331
C330
+3VS
3
R1550 10K_0402_5% SHDNR# OUTR
0.1U_0402_10V7K~D 2 2 2 2 2 HP_AMP_MUTE# HP1_AMP_L
+3VS 2 2 2 2 R02 Modify 18
SHDNL# OUTL
9
1 C969 1
5
1 2 U108 C1527 270P_0402_50V7K~D 21
HP1_JD PAD
1 R1545 1 2
P
INB
5
0.1U_0402_16V4Z~D 4 HP_JD 75mA 2.2U_0805_10V7K~D 2K_0402_1% 4
EAPD# HP2_JD Y HP1_CD_R NC-4
1 2 132mA C336 1 2 HP1_CD_R1 1 2 HP1_CD_R2 15
25
38
P
IN1 INA INR
9
1
4 EA_EC_SUB_MUTE# U11 6
EC_SUB_MUTE# O TC7SZ02FU_SSOP5 HP1_CD_L HP1_CD_L1 1 HP1_CD_L2 NC-6
2 1 2 2 13
DVDD_IO
AVDD1
AVDD2
DVDD_CORE
DVDD_CORE
<31> EC_SUB_MUTE#
3
IN2 C1528 270P_0402_50V7K~D INL
G
U47 C337 R1546 8
74AHC1G08GW_SOT353-5~D 2.2U_0805_10V7K~D NC-8
+3VS 1 2 2K_0402_1% 1 2
3
R1551 10K_0402_5% 12
HP1_CD_L NC-12
39
PORTA_L HP1_CD_R C338 1
PORTA_R 41 2 1U_0603_10V6K~D1 C1P NC-16 16
<19> HDA_BITCLK_AUDIO 6 BITCLK VREFOUT-A 37
PGND
SGND
3 20
PVss
SVss
+3VS R249 C1N NC-20
<19> HDA_SDIN0 1 2 HDA_SDIN0_R 8 SDI_CODEC PORTB_L 21
C949 33_0402_5% 22
PORTB_R MAX4411ETP+T_TQFN20_4X4
1 2 5 28
17
<19> HDA_SDOUT_AUDIO SDO VREFOUT-B
0.1U_0402_10V7K~D C339
<19> HDA_SYNC_AUDIO
10 SYNC PORTC_L 23 Int. Speaker and
5
U42 24 2 1
EA_EC_SPK_MUTE# 1 11
PORTC_R
29
Sub woofer
P
IN1 <19> HDA_RST_AUDIO# RESET# VREFOUT-C
/
4 SPK_AMP_MUTE# 1U_0603_10V6K~D
O SPK_AMP_MUTE# <26>
HP_JD 2 35 SPK_CD_L
IN2 PORTD_L SPK_CD_L <26>
G
2 36 SPK_CD_R
<30> DMIC_CLK VOL_UP/DMIC_CLK/GPIO1 PORTD_R SPK_CD_R <26>
74AHC1G08GW_SOT353-5~D
/x
3
4 14 MIC_CD_L Front R251 L14 JHP1

<30> DMIC0 VOL_DN/DMIC_0/GPIO2 PORTE_L MIC_CD_R 68_0603_1% BLM18BD601SN1D_0603~D
100P_0402_50V8J~D
15 1
100P_0402_50V8J~D
PORTE_R HP1_AMP_L HP1_AMP_L1 1 HP1_AMP_L1_JK
1 1 30 DMIC1/GPIO5 VREFOUT-E 31 +MIC1_VREFO 1 2 2 2
+3VS @ @ 6
C341
C342
C950 SENSE_A 13 16 HP2_CD_L HP1_AMP_R 1 2 HP1_AMP_R1 1 2 HP1_AMP_R1_JK 3
SENSE_B SENSE_A PORTF_L HP2_CD_R L15
1 2 34 17 SHLD1 7
su
2 2 SENSE_B PORTF_R R252 BLM18BD601SN1D_0603~D HP1_JD
32 SENSE_C 4 SHLD2 8
2 0.1U_0402_10V7K~D 68_0603_1% 2
PORTG_L 43 NPTH1 9
5
U48 44 5 10
1000P_0402_50V7K~D
1000P_0402_50V7K~D
PORTG_R NPTH2
EA_EC_SUB_MUTE# 1 PC_BEEP 12 Place close to Jack 1 1
P
IN1 SUB_AMP_MUTE# SUB_AMP_MUTE# <26> PCBEEP FOX_JA6333L-B5S4-7F

4 45 R02 Modify
C343
C344
HP_JD O EAPD# PORTH_L CONN@
2 IN2 47 EAPD/SPDIF IN/GPIO0 PORTH_R 46 D31
G
p.
Int. 60k pull down.
74AHC1G08GW_SOT353-5~D 3 HP1_AMP_L1_JK 2 2
3
18 1
+3VS PORTI_L @ HP1_AMP_R1_JK
19 2
C948 PORTI_C R1006
20 48
PORTI_R SPDIF OUT0
om
1 2 40 ACIN_R 1 2 @ PACDN042Y3R_SOT23-3~D
SPDIF OUT1/GPIO3 ACIN
0_0402_5%
0.1U_0402_10V7K~D <21,31,38,39>
5
U41
EA_EC_SPK_MUTE# 1 7
P
IN1 HP_AMP_MUTE# DVSS

4 26 27 +MIC1_VREFO 1 2
HP_JD# O AVSS1 VREFFILT C345 1000P_0402_50V7K~D
1U_0402_6.3V6K~D
2 42 33
10U_0603_6.3V6M~D
IN2 AVSS2 CAP2
G
+3VS
+MIC1_VREFO W=10 mil
1
yc
74AHC1G08GW_SOT353-5~D 1 1
3
R256 R257
C348
C347
1
92HD73C1X5PRGXC1X8_QFP48_7X7 Rear or MIC 4.7K_0402_5% 4.7K_0402_5%

R1552
10K_0402_5% 2 2 C349 L16 JMIC1
2
2.2U_0603_10V6K~D BLM18BD601SN1D_0603~D 1
m
MIC_CD_L 1 2 MIC_CD_L1 1 2 MIC_CD_L1_JK 2
2
6
MIC_CD_R 1 2 MIC_CD_R1 1 2 MIC_CD_R1_JK 3
1
D +3VS L17 SHLD1 7

HP_JD 2 Q48 C350 BLM18BD601SN1D_0603~D MIC_JD 4 8
SHLD2
G
S
SSM3K7002FU_SC70-3~D Reserved for TEST
// 2
2.2U_0603_10V6K~D
Place close to Jack 5
NPTH1
NPTH2
9
10
3
100P_0402_50V8J~D
100P_0402_50V8J~D
C351
3 R268 1 2 0_0805_5% FOX_JA6333L-B5S4-7F 3
1U_0603_10V6K~D 1 1
@ R269 1 2 0_0805_5% CONN@
C353
D32
C352
@ R270 1 2 0_0805_5% 1
3 MIC_CD_L1_JK
19
10
p:
+AVDD_AUDIO U12 2 2
1
MIC_CD_R1_JK
GND AGND 2
PVDD
SVDD
14 11 HP2_AMP_R
R545 SHDNR# OUTR
SENSE_B 1 2 @ PACDN042Y3R_SOT23-3~D
1000P_0402_50V7K~D
2 HP_AMP_MUTE# 18 9 HP2_AMP_L
5.1K_0402_1%
tt
SHDNL# OUTL
1
1
20K_0402_1%
C866
39.2K_0402_1%
R02 Modify
+3VS C1529 270P_0402_50V7K~D
R547
R546
21
1 PAD
+3VS R1548 1 2 Center R261
h
2.2U_0805_10V7K~D 2K_0402_1% 4 L19 JHP2

NC-4
1
100K_0402_5%
100K_0402_5%
HP2_CD_R C354 1 2 HP2_CD_R1 1 2 HP2_CD_R2 15 68_0603_1% BLM18BD601SN1D_0603~D 1

2
INR
R979
1
6 HP2_AMP_L 1 2 HP2_AMP_L1 1 2 HP2_AMP_L1_JK 2

NC-6
R978
HP2_CD_L C355 1 2 HP2_CD_L1 1 2 HP2_CD_L2 13 6

INL
6
R1547 C1530 270P_0402_50V7K~D 8 HP2_AMP_R 1 2 HP2_AMP_R1 1 2 HP2_AMP_R1_JK 3

2.2U_0805_10V7K~D NC-8 L18
2K_0402_1% 1 2 R262 SHLD1 7
2
Q42A Q42B 12 68_0603_1% BLM18BD601SN1D_0603~D HP2_JD 4 SHLD2 8

2
MIC_JD HP2_JD NC-12

2 5 NPTH1 9
2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D C358 1 2 1U_0603_10V6K~D 1 16 5 NPTH2 10
1000P_0402_50V7K~D
C1P NC-16
1000P_0402_50V7K~D
Place close to Jack 1 1
1
PGND
SGND
3 20 FOX_JA6333L-B5S4-7F
PVss
SVss
C356
C357
C1N NC-20 CONN@
+AVDD_AUDIO MAX4411ETP+T_TQFN20_4X4 2 2
D33
5
17
R543 3 HP2_AMP_L1_JK
SENSE_A 1 2 1
1000P_0402_50V7K~D
1 5.1K_0402_1% 2 HP2_AMP_R1_JK
1U_0603_10V6K~D
EC Beep 1
1
C865
4 4
39.2K_0402_1%
+3VS @ PACDN042Y3R_SOT23-3~D
C360
R544
2 C945 R264
100K_0402_5%
1
0.1U_0402_10V7K~D 499K_0402_1% 2
R971
1 2 BEEP_C# 1 2 PC_BEEP
<31> BEEP# PC_BEEP <26>
2
SB_SPKR_C 1
<21> SB_SPKR 1 2 2 Compal Electronics, Inc.
2
D R267
HP1_JD 2 Q43 C946 R266 10K_0402_5% PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
G SSM3K7002FU_SC70-3~D 0.1U_0402_10V7K~D 499K_0402_1% @
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Codec IDT 92HD73C
S
ICH Beep
3
LA-5152P
A B C D E F G H
5 4 3 2 1
High-Pass Filiter,fc=500Hz, Av=1.45V/V

19V U13
B+
27 PVDD1 OUTL-1 1 AMP_SPKL- 1
L67
2 AMP_SPK_JK_L- Speaker amp impedance of JBL is 4 ohm.
1A/40mil 30 2 BLM18PG181SN1_0603~D 1
PVDD2 OUTL-2
2 2 2 1 1
C906
C901 C902 C903 C904 C905 330P_0402_50V7K~D
22U_1210_25V6K~D 22U_1210_25V6K~D 22U_1210_25V6K~D 0.1U_0603_50V4Z~D 0.1U_0603_50V4Z~D 2
1 1 1 2 2 28 PGND2
29 PGND1
D D
L68 L1508
31 AMP_SPKL+ 1 2 AMP_SPKL+_L 1 2 AMP_SPK_JK_L+
R900 OUTL+1
SPK_CD_L2 1 2 SPKER_CD_L2_FBL 32 BLM18PG181SN1_0603~D 1 22UH_LQH55PN220MR0L_0.85A_20%~D
OUTL+2
11K_0402_1%
C907
A00 Modify 1
R902
2 5 330P_0402_50V7K~D
FB_L 2
C909 182K_0402_1%
R903 2200P_0402_25V7K~D C910
SPK_CD_L 1 2 SPK_CD_L1 1 2 1 2 SPK_CD_L3 1 2 SPK_CD_L4 6
<25> SPK_CD_L IN_L
C911 1U_0603_10V6K~D 16.5K_0402_1% 7
0.022U_0402_25V7K~D NC1
1 2 NC2
8
R901 R904 17.8K_0402_1% 17
PC_BEEP PC_BEEP_1 NC3
<25> PC_BEEP 1 2 1 2
C908 0.1U_0402_10V7K~D 182K_0402_1% R905
SPK_CD_R2 1 2 SPK_CD_R2_FBL
11K_0402_1% R907
1 2 19 FB_R
C913 182K_0402_1%
2200P_0402_25V7K~D C914 L69 L1509
R908
<25> SPK_CD_R SPK_CD_R 1 2 SPK_CD_R1 1 2 1 2 SPK_CD_R3 1 2 SPK_CD_R4 18 25 AMP_SPKR+ 1 2 AMP_SPKR+_L 1 2 AMP_SPK_JK_R+
C915 IN_R OUTR+1 22UH_LQH55PN220MR0L_0.85A_20%~D
1U_0603_10V6K~D 16.5K_0402_1% 26 BLM18PG181SN1_0603~D 1
OUTR+2
/
1 2 0.022U_0402_25V7K~D
R909 17.8K_0402_1% C917
PC_BEEP 1 2 PC_BEEP_2 1
R906
2 SPK_AMP_MUTE# 10 330P_0402_50V7K~D
Speaker Connector
<25> PC_BEEP SHDN# 2
C912 0.1U_0402_10V7K~D
/x
182K_0402_1% 11 REGEN
SPK_AMP_MUTE_R# 9 15 mils trace JSPK1
MUTE# AMP_SPK_JK_L- 1 1
+3VS AMP_SPK_JK_L+ 2
For filterless modualation/spread-spectrum mode AMP_SPK_JK_R- 2
3 3 G5 5
R910 1 2 0_0402_5% 20 L70 AMP_SPK_JK_R+ 4 6
MODE AMP_SPKR- 1 AMP_SPK_JK_R- 4 G6
23 2
su
Mono Select. Set MONO high for mono mode. OUTR-1 MOLEX_53261-0471
4 24 BLM18PG181SN1_0603~D 1
C MONO OUTR-2 CONN@ C
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
16 C921
VS
2
C922 330P_0402_50V7K~D
D1507 Internal Regulator Output. 2
15 REG BOOT 3 2 1
D20
D21
1 2 Internal 2V Bias. 12 COM
p.
1U_0805_50V4Z~D
<25> SPK_AMP_MUTE# SDMK0340L-7-F_SOD323-2~D 21 33
C1N EP
R1558 1
1
1U_0603_25V6-K~D
1U_0603_25V6-K~D
1U_0603_25V6-K~D
1 2 SPK_AMP_MUTE_R# 1 1 1 C924
0.1U_0603_50V4Z~D
C925
1
C923
C926
330K_0402_5%
om
R10 Modify
C1547 2
22
2.2U_0603_10V6K~D 2 2 2 C1P
2 13
AGND
14
AGND R03 Modify
MAX9736AETJ+T_TQFN32_7X7
yc
U14
B+ L65
27 1 AMP_SW- 1 2 AMP_SW_JK-
1A/40mil PVDD1 OUTL-1
30 2 BLM18PG181SN1_0603~D 1
PVDD2 OUTL-2
2 2 2 1 1
C892 X01 modify
m
C977 C918 C916 C967 C980 330P_0402_50V7K~D JWFER1
22U_1210_25V6K~D 22U_1210_25V6K~D 22U_1210_25V6K~D 0.1U_0603_50V4Z~D 0.1U_0603_50V4Z~D 2 1
1 1 1 2 2 1
28 2
PGND2 2
29 3
PGND1 G1
4
G2
R999
// L66 MOLEX_53398-0271~D
SUB_FB_L2 1 2 SUB_FB_L4 31 AMP_SW+ 1 2 AMP_SW_JK+
B OUTL+1 B
11.5K_0402_1% 32 BLM18PG181SN1_0603~D 1
OUTL+2
C979 R993 C988 C989 R1000 C894
SUB_FB_L 1 2 SUB_FB_L1 1 2 1 2 SUB_FB_L3 1 2 1 2 5 330P_0402_50V7K~D
p:
FB_L 2
10K_0402_1% 100K_0402_1%
2
1U_0603_10V6K~D 0.047U_0402_16V7K~D 0.047U_0402_16V7K~D

R998 SUB_IN_L 6
20K_0402_1% IN_L
7
R02 memo modify NC1
8
tt
NC2
17
1
NC3
1 2 SUB_FB_L
R989 6.49K_0402_1%
h
R943 R987
SPK_CD_R 1 2 SUB_CD_R 1 2 SUB_CD_R1 1 2 SUB_CD_R2 1 2 19
<25> SPK_CD_R FB_R
C973 0.47U_0603_10V7K~D 9.09K_0402_1% 2 15.8K_0402_1% C976 0.01U_0402_16V7K~D
SPK_CD_L SUB_CD_L R986 SUB_IN_R AMP_SW+

<25> SPK_CD_L 1 2 1 2 C981 18 25
C970 0.47U_0603_10V7K~D 9.09K_0402_1% .1U_0402_16V7K~D IN_R OUTR+1
26
1 OUTR+2
SUB_AMP_MUTE#
R02 memo modify
<25> SUB_AMP_MUTE# 10
11
SHDN#
REGEN
SUB WOOFER amp impedance of JBL is 4 ohm.
9
MUTE#
+3VS
For filterless modualation/spread-spectrum mode
R988 1 2 0_0402_5% 20 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
MODE AMP_SW- TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Band-Pass Filiter,fc=100 Hz, 500Hz, Av=1.45V/V 4
OUTR-1
23
24 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MONO OUTR-2 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
16 PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A VS C953 A
Internal Regulator Output. 15 3 2 1
Internal 2V Bias. REG BOOT
12 COM 1U_0805_50V4Z~D
21 C1N EP 33 DELL CONFIDENTIAL/PROPRIETARY
1
1U_0603_25V6-K~D
1U_0603_25V6-K~D
1U_0603_25V6-K~D
1 1 1 C971
0.1U_0603_50V4Z~D
C965
C975
C983
2 Title
22 C1P
2 2 2
13
Speaker
AGND Size Document Number Rev
14 AGND A00
MAX9736AETJ+T_TQFN32_7X7 LA-5152P
5 4 3 2 1
A B C D E
R02 RF reserve part. +3VS R02 RF reserve part. +1.5VS
WWAN 1
47P_0402_50V8J~D
0.01U_0402_16V7K~D
C403
.1U_0402_16V7K~D
C404
4.7U_0805_10V4Z~D
C405
330U_D2E_6.3VM_R25~D
C956
47P_0402_50V8J~D
0.01U_0402_16V7K~D
C407
.1U_0402_16V7K~D
C408
4.7U_0805_10V4Z~D
C409
1 1 1 1 1 1 1 1
U109
C1535
C1536
+
2 2 2 2 2 2 2 2 2
1 6
@ @
1 2 5 1
3 4
+UIM_PW R +3VS
+3VS +1.5VS +3VS Don't forget to remove R287 or SRV05-4.TCT_SOT23-6~D
D10 @
JW W AN1 disble debug port when doing JSIM1 3
<21,24,28,31> ICH_PCIE_W AKE#
ICH_PCIE_W AKE# 1
3
1 2 2
4
SIM Pre-test and before RTS. UIM_VPP
5
6
GND VCC 1
2 UIM_RST
1
2
3 4 UIM_DATA VPP RST UIM_CLK
5 5 6 6 7 I/O CLK 3
W W AN_CLKREQ# 7 8 +UIM_PW R 8 4 DAN217_SC59-3
<6> W W AN_CLKREQ# 7 8 UIM_DATA NC NC
9 9 10 10 9 GND
CLK_PCIE_W AN# 11 12 UIM_CLK 10
<6> CLK_PCIE_W AN# 11 12 C410 GND
CLK_PCIE_W AN 13 14 UIM_RST C411
<6> CLK_PCIE_W AN 13 14 33P_0402_50V8J~D MOLEX_475531001
15 16 @ R285 1 2 0_0402_5% UIM_VPP 33P_0402_50V8J~D 1 1
15 16 CONN@
17 17 18 18
W W AN_RADIO_OFF# Link ok C412 C413
/
19 19 20 20 W W AN_RADIO_OFF# <31>
21 22 PCI_RST# 4.7U_0805_10V4Z~D .1U_0402_16V7K~D
21 22 PCI_RST# <20,24,28> 2 2
PCIE_IRX_W ANTX_N1 23 24
<22> PCIE_IRX_W ANTX_N1 23 24
/x
PCIE_IRX_W ANTX_P1 25 26
<22> PCIE_IRX_W ANTX_P1 25 26
27 27 28 28
29 29 30 30 R911 1 2 0_0402_5% EC_SMB_CK2 <7,28,31> Place as close as JSIM1
PCIE_ITX_C_W ANRX_N1 31 32 R912 1 2 0_0402_5%
<22> PCIE_ITX_C_W ANRX_N1 31 32 EC_SMB_DA2 <7,28,31>
PCIE_ITX_C_W ANRX_P1 33 34
<22> PCIE_ITX_C_W ANRX_P1 33 34
35 36 USBP5_D-
35 36
su
USBP5_D+
2
37
39
37 38 38
40
Wireless Radios (on/off) use Fn Key controll ? 2
39 40
41 42 L71 @
41 42
43 43 44 44 DLW 21SN121SQ2L_4P~D
45 46 USBP5_D+ 2 2
45 46 1 1 USBP5+ <22>
47 48
p.
R1010 0_0402_5% 47 48
<31> EC_TX_P80_DATA 1 2 49 49 50 50
R1011 1 2 0_0402_5% 51 52 USBP5_D- 3 3 4
<31> EC_RX_P80_CLK 51 52 4 USBP5- <22>
53 54 @ R913 1 2 0_0402_5%
GND1 GND2
om
@ R914 1 2 0_0402_5%
TYCO_1775838-1~D
yc
WLAN +3V_W LAN
+1.5VS +3V_W LAN
m
+3V_W LAN R02 modify
ICH_PCIE_W AKE# JW LAN1
<21,24,28,31> ICH_PCIE_W AKE#
1 1 2 2 1 2 +3VS
@ R291 1 2 0_0402_5% 3 4 @ JP1
<28,30> COEX2_W LAN_ACTIVE COEX1_W LAN_ACTIVE 3 4
5 5
// 6 6
0.01U_0402_16V7K~D
.1U_0402_16V7K~D
4.7U_0805_10V4Z~D
W LAN_CLKREQ# 7 8 R919@ 1 2 0_0402_5%
<6> W LAN_CLKREQ# 7 8 LPC_FRAME# <19,31>
47P_0402_50V8J~D
9 10 R920@ 1 2 0_0402_5% LPC_AD3 1 1 1 1
3 9 10 3
C1537
CLK_PCIE_W LAN# 11 12 R915@ 1 2 0_0402_5% LPC_AD2
C414
C415
C416
<6> CLK_PCIE_W LAN# 11 12
CLK_PCIE_W LAN 13 14 R916@ 1 2 0_0402_5% LPC_AD1
<6> CLK_PCIE_W LAN 13 14
15 16 R917@ 1 2 0_0402_5% LPC_AD0
15 16 2 2 2 2
p:
@ R918 1 2 0_0402_5% 17 18
<11,20,30,31> PLT_RST# 17 18 LPC_AD[0..3] <19,31>
@ R921 1 2 0_0402_5% 19 20 W LAN_RADIO_OFF# @
<6> CLK_DEBUG_PORT 19 20 W LAN_RADIO_OFF# <31>
21 21 22 22 PCI_RST# <20,24,28>
PCIE_IRX_W LANTX_N2 23 24
<22> PCIE_IRX_W LANTX_N2 PCIE_IRX_W LANTX_P2 23 24
<22> PCIE_IRX_W LANTX_P2 25 25 26 26
tt
27 27 28 28
29 30 @ R922 1 2 0_0402_5%
29 30 EC_SMB_CK2 <7,28,31>
PCIE_ITX_C_W LANRX_N2 31 32 @ R923 1 2 0_0402_5%
<22> PCIE_ITX_C_W LANRX_N2 31 32 EC_SMB_DA2 <7,28,31> R02 RF reserve part.
PCIE_ITX_C_W LANRX_P2 33 34
h
<22> PCIE_ITX_C_W LANRX_P2 33 34

35 36 USBP4_D-
35 36 USBP4_D+ +1.5VS
37 37 38 38
39 39 40 40
41 42 R02 RF reserve part.
41 42
0.01U_0402_16V7K~D
43 44
0.01U_0402_16V7K~D
43 44
47P_0402_50V8J~D
45 46 L72 @ 1 1 1
45 46
C1538
D40 47 48 DLW 21SN121SQ2L_4P~D
C417
47 48
C418
W PAN_ACTIVE 2 49 50 USBP4_D+ 2 2 1
<28> W PAN_ACTIVE 49 50 1 USBP4+ <22>
51 51 52 52
COEX1_W LAN_ACTIVE 2 2 2
1
53 54 USBP4_D- 3 4 @
GND1 GND2 3 4 USBP4- <22>
BT_ACTIVE 3
<30> BT_ACTIVE
1
@ R924 1 2 0_0402_5%
BAT54C-7-F_SOT23-3~D R997 TYCO_1775838-1~D
10K_0402_5% @ R925 1 2 0_0402_5%
2
4 4
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card_WLAN/WWAN
LA-5152P
A B C D E
5 4 3 2 1
+1.5VS +3VS
WPAN Card
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
4.7U_0603_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 1 1 1 1 1 1
D +3VS D
C420
C419
C421
C422
+3VS +1.5VS
C423
C424
C425
ICH_PCIE_WAKE#
<21,24,27,31> ICH_PCIE_WAKE# JWPAN1 2 2 2 2 2 2 2
1 2
@ R292 1 2
<27,30> COEX2_WLAN_ACTIVE 1 2 0_0402_5% 3
3 4
4
@ R293 1 2 0_0402_5% WPAN_ACTIVE_R 5 6
<27> WPAN_ACTIVE WPAN_CLKREQ# 5 6
7 8
<6> WPAN_CLKREQ# 7 8
9 10
CLK_PCIE_WPAN# 9 10
<6> CLK_PCIE_WPAN# 11 12
CLK_PCIE_WPAN 11 12
<6> CLK_PCIE_WPAN 13 14
13 14
15 15 16 16
17 17 18 18
19 20 WPAN_RADIO_OFF#
19 20 PCI_RST# WPAN_RADIO_OFF# <31>
21 21 22 22 PCI_RST# <20,24,27>
PCIE_IRX_WPANTX_N3 23 24
<22> PCIE_IRX_WPANTX_N3 PCIE_IRX_WPANTX_P3 23 24
25 25 26 26
<22> PCIE_IRX_WPANTX_P3
27 27 28 28
29 30 @ R294 1 2 0_0402_5%
PCIE_ITX_C_WPANRX_N3 29 30 EC_SMB_CK2 <7,27,31>
31 32 @ R298 1 2 0_0402_5%
<22> PCIE_ITX_C_WPANRX_N3 31 32 EC_SMB_DA2 <7,27,31>
PCIE_ITX_C_WPANRX_P3 33 34
<22> PCIE_ITX_C_WPANRX_P3 33 34
/
35 36 USBP6_D-
35 36 USBP6_D+
37 37 38 38
39 40 L26 @
39 40 DLW21SN121SQ2L_4P~D
/x
41 41 42 42
43 44 USBP6_D- 2 2
43 44 1 1 USBP6- <22>
45 45 46 46
47 47 48 48
49 50 USBP6_D+ 3 4
49 50 3 4 USBP6+ <22>
51 51 52 52
@ R295 2 1 0_0402_5%
su
53 GND1 GND2 54
C @ R296 2 C
1 0_0402_5%
TYCO_1775838-1~D
p.
om
yc
Express Card Power
Switch
m
(1A) +3VS_CARD
Express Card
0.1U_0402_10V7K~D
JEXP1
4.7U_0805_10V4Z~D
1
+3VALW GND
+1.5VS +3VS
// 1 1 <22> USBP7-
USBP7-
USBP7+
2
3
USB-
C430
<22> USBP7+
C429 EXPR_CPUSB# USB+
4
B CPUSB# B
5
2 2 REV
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
6
EC_SMB_CK2 REV
1 1 1 <7,27,31> EC_SMB_CK2 7
EC_SMB_DA2 SMBCLK
8
p:
<7,27,31> EC_SMB_DA2 SMBDATE

C431
C433
C432
+1.5VS_CARD 9
+1.5V
10
2 2 2 +1.5V
11
+3VS_CARD_AUX <21,24,27,31> ICH_PCIE_WAKE# WAKE#
+3VS_CARD_AUX 12
U16 PERST# +3.3VAUX
13
tt
PERST#
2 3 +3VS_CARD 14
3.3Vin 3.3Vout +3.3V
17 15 15
3.3Vin 3.3Vout EXP_CLKREQ# +3.3V
4.7U_0805_10V4Z~D
16
0.1U_0402_10V7K~D
<6> EXP_CLKREQ# CPPE# CLKREQ#

12 11 17
AUX_IN AUX_OUT CPPE#
h
1 1 CLK_PCIE_EXPR# 18
<6> CLK_PCIE_EXPR# REFCLK-
PCI_RST# 6 19 CLK_PCIE_EXPR 19
C435
<20,24,27> PCI_RST# SYSRST# OCZ <6> CLK_PCIE_EXPR REFCLK+

C434
20
PERST# PCIE_IRX_EXPTX_N5 GND
<31,33,42> SYSON 20 8 21
SHDNZ PERSTZ 2 2 <22> PCIE_IRX_EXPTX_N5 PCIE_IRX_EXPTX_P5 PERn0
22
<22> PCIE_IRX_EXPTX_P5 PERp0
<31,33,41,42> SUSP# 1 4 23
STBYZ NC PCIE_ITX_C_EXPRX_N5 GND
5 <22> PCIE_ITX_C_EXPRX_N5 24
CPPE# NC PCIE_ITX_C_EXPRX_P5 PETn0
10 13 <22> PCIE_ITX_C_EXPRX_P5 25
CPPE# NC PETp0
14 26
EXPR_CPUSB# NC GND
9 16
CPUSB# NC +1.5VS_CARD 27
G1
18 7 28
RCLKEN GND G2
(0.5A) 29
G3
30
P2231NL E2_QFN20_4X4 G4
0.1U_0402_10V7K~D
4.7U_0805_10V4Z~D
TAITW_PXPXAE-000LBS2ZZ4N0_NR
1 1
+1.5V_CARD Max. 650mA , Average 500mA
C428
C427
A +3V_CARD Max. 1300mA, Average 1000mA A

2 2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, WPAN / Express Card
LA-5152P
5 4 3 2 1
A B C D E
SATA ODD CONN

JODD1
+5VS
1 GND
SATA_ITX_C_DRX_P5 2
<19> SATA_ITX_C_DRX_P5 A+
1 SATA_ITX_C_DRX_N5 3 1
<19> SATA_ITX_C_DRX_N5 A-
1000P_0402_50V7K~D
4 GND
10U_0805_10V4Z~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
C437 1 2 0.01U_0402_16V7K~DSATA_IRX_C_DTX_N5 5
<19> SATA_IRX_DTX_N5 C436 B-
<19> SATA_IRX_DTX_P5 1 2 0.01U_0402_16V7K~DSATA_IRX_C_DTX_P5 6 B+ 1 1 1 1
C438
C439
7 GND
C440
C441
2 2 2 2
8 DP
+5VS 9 V5
10 V5
11 MD G1 14
12 GND G2 15
13 GND G3 16
MOLEX_47639-3000_13P Close to ODD Conn
R02 Follow ME request.
/
SATA HDD (On board)
/x
JSATA1
1 GND
SATA_ITX_C_DRX_P1 2
<19> SATA_ITX_C_DRX_P1 A+
SATA_ITX_C_DRX_N1 3
<19> SATA_ITX_C_DRX_N1 A-
4 GND
su
C449 2 1 0.01U_0402_25V7K~D SATA_IRX_C_DTX_N1 5
<19> SATA_IRX_DTX_N1 C450 B- +5VS
2
<19> SATA_IRX_DTX_P1 2 1 0.01U_0402_25V7K~D SATA_IRX_C_DTX_P1 6 B+ Close to JSATA1. 2
7 GND
10U_0805_10V4Z~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1000P_0402_50V7K~D
8
p.
V33
R02 modify. JSATA1 with JSATA2 swap 9 V33
10 V33 1 1 1 1
C445
11 GND
C446
C447
C448
12 GND
om
13 GND 2 2 2 2
+5VS 14 V5
15 V5
16 V5
17 GND
18 Reserved
19 GND
20 23
yc
V12 GND
21 V12 GND 24
22 V12 GND 25
MOLEX_47662-2000
m
CONN@
SATA HDD
//
JSATA2
3 3
1 GND
SATA_ITX_C_DRX_P0 2
<19> SATA_ITX_C_DRX_P0 RX+ +5VS
SATA_ITX_C_DRX_N0 3 Close to JSATA2.
<19> SATA_ITX_C_DRX_N0 RX-
p:
4 GND
C442 2 1 0.01U_0402_25V7K~D SATA_IRX_C_DTX_N0 5
<19> SATA_IRX_DTX_N0 C443 TX-
<19> SATA_IRX_DTX_P0 2 1 0.01U_0402_25V7K~D SATA_IRX_C_DTX_P0 6 TX+
10U_0805_10V4Z~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1000P_0402_50V7K~D
7 GND
tt
1 1 1 1
C452
C453
C454
C455
8
h
3.3V 2 2 2 2
9 3.3V
10 3.3V
11 GND
12 GND
13 GND
+5VS 14 5V
15 5V
16 5V
17 GND
18 Reserved
19 GND
20 12V
21 12V GND1 23
22 12V GND2 24
TYCO_1770615-3~D
4
CONN@ 4
R02 Modify DELL CONFIDENTIAL/PROPRIETARY
由由Kink pin尺尺尺由kink hole，將將將將將將將，也也也也也pin腳腳腳。 Compal Electronics, Inc.

因因將原HDD Conn.(REV.) –FOXCONN–SP01000LC0L layout 改改Tyco–SP01000E70L layout PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
即即即即即改pin腳腳腳腳腳腳
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ODD / SATA CONN
LA-5152P
A B C D E
+5VALW +5V_CHGUSB
U17
1 8 ESATA_USB_OC# ESATA_USB_OC# <22>
GND OC1#
2 IN OUT1 7
3 EN1# OUT2 6
<31> PWRSHARE_EN# 4 EN2# OC2# 5
+1.8VS
0.1U_0402_10V7K~D
10U_0805_10V4Z~D
TPS2062ADR_SO8~D
10U_0805_10V4Z~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
Output Swing Control Output De-emphasis Adjustment 1 1
C462
C463
SEL2_ [A:B] Swing SEL3_ [A:B] De-emphasis 1 1 1 1 1 1
C935
C936
C937
C938
C939
C940
2 2
* 0 1x * 0 0dB R03 modify
2 2 2 2 2 2 +5V_CHGUSB
1 1.2x 1 -3.5dB
U40 C941 C466

SATA_ITX_C_DRX_P4 2 1 4700P_0402_25V7K~D 0.1U_0402_10V7K~D
<19> SATA_ITX_C_DRX_P4 AI+ VDD
2
SATA_ITX_C_DRX_N4 3 6 2 1 ESATA_ITX_C_DRX_P4 U18 1 2
<19> SATA_ITX_C_DRX_N4 AI- VDD
2
1 2SATA_IRX_C_DTX_P4 VDD 10
<19> SATA_IRX_DTX_P4
1
C942 0.01U_0402_16V7K~D 7 23 R301 R302 1 10 +3VALW
BO+ VDD <22> USBP0+ 1D+ VCC
1 2SATA_IRX_C_DTX_N4 8 BO- VDD 28 R953 43.2K_0402_1% 75K_0402_1%
<19> SATA_IRX_DTX_N4 C943 0.01U_0402_16V7K~D 390_0402_5% PWRSHARE_OE#
5 <22> USBP0- 2 9 PWRSHARE_OE# <31>
1
R954 AVDD 1D- S
1 2 0_0402_5% 34 C944
1
SEL0_A
1
R955 1 2 0_0402_5% 13 27 ESATA_ITX_DRX_P4 4700P_0402_25V7K~D USB_CHARGE_D+ 3 8 USBP0_D+
2
SEL0_B AO+ ESATA_ITX_DRX_N4 2D+ D+
26 2 1 ESATA_ITX_C_DRX_N4 R303
@ R956 AO- USB_CHARGE_D- USBP0_D-
1 2 0_0402_5% 33 SEL1_A 4 2D- D- 7 100K_0402_5%
@ R957 1 2 0_0402_5% 14 21 ESATA_IRX_DTX_N4
SEL1_B BI- ESATA_IRX_DTX_P4
22 5 6
2
BI+ GND OE#
/
@ R958 1 2 0_0402_5% 32 SEL2_A
2
@ R959 1 2 0_0402_5% 15 SEL2_B @ R960 1
@R960
OUT+ 17 2 0_0402_5% R304 R305
R961 2 0_0402_5% @R962
@ R962 1 2 0_0402_5% 49.9K_0402_1% 49.9K_0402_1% TS3USB221RSER_QFN10_2x1P5~D
/x
1 31 18 S OE# Function
+1.8VS R963 1 SEL3_A OUT-
2 0_0402_5% 16 SEL3_B
36 @ R964 1
@R964 2 0_0402_5% H
X Disconnect
1
R965 SD_A
1 2 10K_0402_1% 30 EN_A SD_B 35 @R966
@ R966 1 2 0_0402_5% S Logic"1" Work from BKT
R967 1 2 10K_0402_1% 29 EN_B L L D=1D
USB_DETECT
19 25 H L D=2D
su
IREF GND
GND 20
@ R968 1 2 470_0402_5% 9
GND
GND 4
+1.8VS 24 +5V_CHGUSB
@ R969
@R969 AGND
1 2 0_0402_5% 11 ESATA
@R970
@ R970 CLKIN+
1 2 0_0402_5% 12 CLKIN- PAD 37
p.
1 1
PI2EQX3201BZFEX_TQFN36_6X5
+ C460 C461 JESA1
150U_D _10VM_R40M~D 0.1U_0402_10V7K~D
A00 change to SA00002YQ0L (S IC PI2EQX3201BLZFEX TQFN 36P) 2 USB
1
2 VBUS
om
R03 modify USBP0_D- 2
USBP0_D+ D-
3
R10 Delete USB_DETECT Equalizer Selection 4
D+
GND
*SEL0_ [A:B] SEL1_ [A:B] Compliance Channel
1
D @ D34 5
USB_DETECT# Q11 USBP0_D- ESATA_ITX_C_DRX_P4 GND
2 0 0 no equalization 1
CH1 CH4
4
ESATA_ITX_C_DRX_N4
6
A+ ESATA
G SSM3K7002FU_SC70-3~D 7
A-
S 0 1 [0:2.5dB] @ 1.6 GHz 8 14
3
ESATA_IRX_DTX_N4 2 GND GND

1ESATA_IRX_C_DTX_N4
yc
9 15
C464 4700P_0402_25V7K~D B- GND
1 0 [2.5:4.5dB] @ 1.6 GHz 2
Vn Vp
5 +5V_CHGUSB
ESATA_IRX_DTX_P4 2
10
B+ GND
16
1ESATA_IRX_C_DTX_P4 11 17
C465 4700P_0402_25V7K~D GND GND
1 1 [4.5:6.5dB] @ 1.6 GHz USB_DETECT# 12
USBP0_D+ <32> USB_DETECT# DET1
3 6 13
CH2 CH3 DET2
m
@ CM1293-04SO_SOT23-6
FOX_3Q3813C-RB1C3B-7F
CONN@
// Place close JESA1
Camera Conn
@ L27 WCM2012F2S-900T04_0805
1 1
Cardreader Connector
2 2 JCARD1
<31> USB_EN# 30 34
30 G4
4 3
Bluetooth 29 33
p:
4 3 <22> USB_OC1# 29 G3
28 32
28 G2
<22> USBP1+ 27
26
27 G1
31
to Single USB board
<22> USBP1- 26
JBT1 25
BT_DET# 25
JCAM1
<31> BT_DET# 1 2 BT_ACTIVE +5VALW 24
tt
USBP11+ R297 2 USBP_P11 COEX2_WLAN_ACTIVE3 1 2 BT_ACTIVE <27> 24

<22> USBP11+ 10_0402_5% 1
1 <27,28> COEX2_WLAN_ACTIVE 3 4
4 +3VS 23
23
USBP11- R299 2 10_0402_5% USBP_N11 2 BT_OFF# 5 6 USBP10+ 22 +5VALW
<22> USBP11- 2 <31> BT_OFF# BT_RADIO_OFF# 5 6 USBP10+ <22> 22 JSUSB1
+3VS L28 2 1BLM18BB221SN1D 0603 3 7 8 USBP10- USBP10- <22> 21
DMIC_CLK 3 <31> BT_RADIO_OFF# 7 8 21
<25> DMIC_CLK 4 9 10 20 1
4 9 10 20 1
h
5 11 12 19 2
DMIC0 5 11 12 19 2
<25> DMIC0 6 13 14 18 3
6 13 14 18 3
7 +3VS 17 <22> USBP2- 4
7 17 4
15 16 16 <22> USBP2+ 5
GNDGND 16 5
8 15 6
GND 15 6
100P_0402_50V8J~D
100P_0402_50V8J~D
Layout note: Pin5 thru 9

GND
14
14 <31> USB_EN# 7
7
13 8
individual via to GND layer 1 1 MOLEX_48227-0701 HRS_CL537-0918-4-86 12
13 <22> USB_OC2#
<31> BATT_CHG_LED# 9
8
12 9
C458
C459
@ @ CONN@ PCIE_ITX_C_CBRX_P4 11 10
<22> PCIE_ITX_C_CBRX_P4 PCIE_ITX_C_CBRX_N4 11 <31> BATT_LOW_LED# 10
<22> PCIE_ITX_C_CBRX_N4 10
10
9
2 2 USBP10- PCIE_IRX_CBTX_P4 9
8 11
USBP10+ <22> PCIE_IRX_CBTX_P4 PCIE_IRX_CBTX_N4 8 G1
7 12
<22> PCIE_IRX_CBTX_N4 7 G2
47P 50V J NPO 0402
47P 50V J NPO 0402
6
AS CLOSE AS JCA1 CLK_PCIE_CB 6 FCI_10089709-010010-LF
<6> CLK_PCIE_CB 5
@ R995 CLK_PCIE_CB# 5 CONN@
1 1 <6> CLK_PCIE_CB# 4
10K_0402_5% C456 C457 4
3
BT_ACTIVE CB_CLKREQ# 3
1 2 @ @ 2
D35 <6> CB_CLKREQ# PLT_RST# 2
<11,20,27,31> PLT_RST# 1 1
USBP_P11 1 4 DMIC_CLK 2 2
CH1 CH4 FOX_GS12301-1011A-9F~D
CONN@
2 Vn Vp 5 +3VS DELL CONFIDENTIAL/PROPRIETARY

USBP_N11 3 6 DMIC0 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
CH2 CH3 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
@ CM1293-04SO_SOT23-6 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB / ESATA / BT / CAMARA
Place close JCAM1 LA-5152P
+3VALW L29
FBM-11-160808-601-T_0603
+EC_AVCC 2 1 +3VALW
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 1 1 1 1 1
1 2
C469
C467
C468
C470
C471
C472
C473 C474
+EC_AVCC +3VALW
2 2 2 2 2 2
1000P_0402_50V7K~D 0.1U_0402_10V7K~D
Board ID
ECAGND 2 1
2 1
L30
2
FBM-11-160808-601-T_0603
+3VALW R311
111
125
Ra
22
33
96
67
100K_0402_5%
9
U19
R324 1 2 10K_0402_5% MSEN#
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
1
AD_BID
R306 2 1 10K_0402_5% PCIE_PME# 1
1
GATEA20 1 21 EC_PWM R312 C477
<19> GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# EC_PWM <35> 0.1U_0402_10V7K~D
R307 1 2 47K_0402_5% EC_RST# <19> KB_RST# SERIRQ
2
3
KBRST#/GPIO01 BEEP#/PWM2/GPIO10
23
26 PWRSHARE_EN# BEEP# <25> Rb 33K_0402_5%
2
<21> SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF PWRSHARE_EN# <30>
4 27 ACOFF <39> ECAGND
2
<19,27> LPC_FRAME# LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 C522 1
<19,27> LPC_AD3 5
LAD3 2 0.01U_0402_16V7K~D
C475 2 10.1U_0402_10V7K~D LPC_AD2 2 0.01U_0402_16V7K~DECAGND
<19,27> LPC_AD2 7
LAD2 PWM Output C476 1
LPC_AD1 8 63 BATT_TEMP
KSO0 <19,27> LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP BATT_TEMP <44>
LAD0 LPC & MISC
R308 1 2 47K_0402_5% 10 64 VCC 3.3V+/-5% 0.6V~1.6V
<19,27> LPC_AD0 BATT_OVP/AD1/GPIO39 ADP_I BATT_OVP <44>
ADP_I/AD2/GPIO3A 65 ADP_I <39>
R309 1 2 47K_0402_5% KSO1 CLK_PCI_EC 12 AD Input 66 AD_BID Ra 100K
<6> CLK_PCI_EC PCICLK AD3/GPIO3B
PLT_RST# 13 75 MSEN# R03 add
R926 2 <11,20,27,30> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 MSEN# <35>
1 10K_0402_5% EN_KBL# EC_RST# 37 ECRST# SELIO2#/AD5/GPIO43 76 POW_MON <43> Board ID Rb
EC_SCI# 20
R314 2 EC_SMB_DA1 <21> EC_SCI# TOUCHKEY_TINT SCI#/GPIO0E
1 4.7K_0402_5% <32> TOUCHKEY_TINT 38 CLKRUN#/GPIO1D 0 0 +/- 5% 0V
68 EC_SUB_MUTE#
R315 2 EC_SMB_CK1 DAC_BRIG/DA0/GPIO3C EN_DFAN1 EC_SUB_MUTE# <25>
1 4.7K_0402_5% EN_DFAN1/DA1/GPIO3D 70 1 8.2K+/- 5% 0.250V
KSI[0..7] IREF EN_DFAN1 <7>
<32> KSI[0..7] DA Output IREF/DA2/GPIO3E 71 IREF <39>
KSI0 55 72 2 18K +/- 5% 0.503V
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <39>
/
+3VS KSI1 56
KSI2 KSI1/GPIO31
57 R10 add 3 33K +/- 5% 0.819V
R317 2 1 4.7K_0402_5% EC_SMB_DA2 KSI3
KSI4
58
KSI2/GPIO32
KSI3/GPIO33 PSCLK1/GPIO4A 83 LCD_TST
USB_EN# LCD_TST <35>
*
4 56K +/- 1% 1.185V
/x
59 KSI4/GPIO34 PSDAT1/GPIO4B 84 USB_EN# <30>
R318 2 1 4.7K_0402_5% EC_SMB_CK2 KSI5 60 85
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C KSO5
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
KSO5 <32> 5 100K +/- 1% 1.650V
@ R319 2 1 4.7K_0402_5% LCD_TST KSO[0..18] KSI7 62 87 TP_CLK
<32> KSO[0..18] KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK <32>
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <32>
KSO1 40
KSO2 KSO1/GPIO21
41
su
R320 2 BT_RADIO_OFF# KSO3 KSO2/GPIO22 WPAN_RADIO_OFF#
1 4.7K_0402_5%
KSO4
42
43
KSO3/GPIO23 SDICS#/GPXOA00 97
98 EN_WOL# WPAN_RADIO_OFF# <28> Follow the suggestion of EC team to
EC_FB_SCLK KSO6 KSO4/GPIO24 SDICLK/GPXOA01 BT_OFF# EN_WOL# <24>
KSO5/GPIO25 Int. K/B
R339 2 1 4.7K_0402_5%
KSO7
44
45
SDIDO/GPXOA02 99
109 VGATE BT_OFF# <30> follow JAT10 setting.
EC_FB_SDATA KSO8 KSO6/GPIO26 Matrix SDIDI/GPXID0 VGATE <11,21,43>
R342 2 1 4.7K_0402_5% 46 KSO7/GPIO27 SPI Device Interface
KSO9 47 KSO8/GPIO28
p.
KSO10 48 119 FRD#SPI_SO R333
KSO11 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI 15_0402_5%
49 KSO10/GPIO2A SPIDO/WR# 120
+5VS KSO12 50 SPI Flash ROM 126 SPI_CLK 2 1 SPI_CLK_R
KSO13 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS#
51 128 1
KSO14 KSO12/GPIO2C SPICS# @
52 R422
KSO13/GPIO2D
om
R325 2 1 4.7K_0402_5% TP_DATA KSO15 53 C1539 EC_ENBKL 1 2
KSO14/GPIO2E 22P_0402_50V8J~D GMCH_ENBKL <12>
KSO16 54 73 EC_SPK_HP_MUTE# 0_0402_5%
R326 2 TP_CLK KSO17 KSO15/GPIO2F CIR_RX/GPIO40 USB_DET_DELAY# EC_SPK_HP_MUTE# <25> 2
1 4.7K_0402_5% 81
KSO16/GPIO48 CIR_RLC_TX/GPIO41
74
USB_DET_DELAY# <32> R03 add
KSO18 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHG_LED# FSTCHG <39>
90
BATT_CHGI_LED#/GPIO52 BATT_CHG_LED# <30> R383
91 PWRSHARE_OE# <30>
EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_LOW_LED#
<44> EC_SMB_CK1
77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92
BATT_LOW_LED# <30>
100K_0402_5%
R948 1 2 200K_0402_5% KSO5 EC_SMB_DA1 78 93 BKLT_KB_DET#
<44> EC_SMB_DA1 EC_SMB_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON BKLT_KB_DET# <32>
yc
<7,27,28> EC_SMB_CK2
79
SCL2/GPIO46 SM Bus SYSON/GPIO56
95
SYSON <28,33,42>
EC_SMB_DA2 80 121 VR_ON
<7,27,28> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <7,43>
EC Adam_Yang request 127 ACIN
AC_IN/GPIO59 ACIN <21,25,38,39>
SLP_S3# 6 100 EC_RSMRST#

<21> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <21>
m
SLP_S3# SLP_S5# 14 101 EC_LID_OUT#
T78 <21> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <21>
T79 SLP_S5# EC_SMI# 15 102 EC_ON
SLP_S4# <21> EC_SMI# LID_SW# EC_SMI#/GPIO08 EC_ON/GPXO05 BT_RADIO_OFF# EC_ON <32>
T80 <32> LID_SW# 16 103
EC_FB_SCLK LID_SW#/GPIO0A EC_SWI#/GPXO06 ICH_PWROK BT_RADIO_OFF# <30>
17 104
<32> EC_FB_SCLK EC_FB_SDATA SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# ICH_PWROK <11,21>
<32> EC_FB_SDATA 18
PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
105
BKOFF# <35>
<21,24,27,28> ICH_PCIE_WAKE#
R977 1 2 0_0402_5%
<32> KB_BL_PWM#
PCIE_PME#
KB_BL_PWM#
19
25
EC_PME#/GPIO0D
EC_THERM#/GPIO11
GPIO
// WL_OFF#/GPXO09
GPXO10
106
107
WWAN_RADIO_OFF#
LCD_VCC_TEST_EN WWAN_RADIO_OFF# <27>
LCD_VCC_TEST_EN <35> R02 Delete
FAN_SPEED1 28 108 CP_SEL
<7> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 CP_SEL <39>
WLAN_RADIO_OFF# 29
<27> WLAN_RADIO_OFF# EC_TX_P80_DATA 30 FANFB2/GPIO15
<27> EC_TX_P80_DATA EC_RX_P80_CLK EC_TX/GPIO16 SLP_S4#
<27> EC_RX_P80_CLK 31 110 SLP_S4# <11,21>
ON_OFF EC_RX/GPIO17 PM_SLP_S4#/GPXID1 EC_ENBKL
32 112
p:
<32> ON_OFF ON_OFF/GPIO18 ENBKL/GPXID2

PWR_BTN_LED# 34 114 BT_DET# @ R330 C483 @
<32> PWR_BTN_LED# EN_KBL# PWR_LED#/GPIO19 GPXID3 EC_THERM# BT_DET# <30> SPI_CLK_R 2
<32> EN_KBL#
36
NUMLED#/GPIO1A GPI GPXID4
115
EC_THERM# <21>
1 2 1
116 SUSP# 0_0402_5% 0.1U_0402_10V7K~D
GPXID5 PBTN_OUT# SUSP# <28,33,41,42>
117
GPXID6 PS_ID PBTN_OUT# <21>
118 PS_ID <38>
tt
XCLKI GPXID7
122
CLK_PCI_EC XCLKO XCLK1 C480 1
123
XCLK0 V18R
124 2 1U_0603_10V6K~D
@
1
AGND
1 R328 2 XCLKI
GND
GND
GND
GND
GND
h
XCLKO 20M_0603_5% 2 1 C482

@ R327 0.1U_0402_10V7K~D
10_0402_5% Y4 KB926QFD3_LQFP128
SPI Flash (16Mb*1) +3VALW
11
24
35
94
113
69
1 4 R329
2
1 2 1
22P_0402_50V8J~D
2 G G 3 1 ECAGND 20mils 10K_0402_5% 2

@ C478
22P_0402_50V8J~D
C481
15P_0402_50V8J 1 32.768KHZ_12.5PF_QTFM28-32768K1 +SPI_R C484

2 R331 0.1U_0402_10V7K~D
2 1
C479
15_0402_5% U20
2
D3 Version : P/N : SA00001J580 FSEL#SPICS# 2 1 SPI_CS# 1
CS# VCC
8
FRD#SPI_SO 1 2 SPI_SO 2 7
SO HOLD# SPI_CLK_R
3 6
R332 WP# SCLK SPI_SI FWR#SPI_SI
4 5 1 2
15_0402_5% GND SI
MX25L1605AM2C-12G_SO8~D R334
15_0402_5%
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, BIOS & EC I/O Port
LA-5152P
A B C D E
+3VALW INT_KB_Conn.1
Power Button Circuit
2
100K_0402_5%
JKB1
30 32
To power board 30 GND
R335
KSI7 29 31
KSI6 29 GND
28 28
KSI4 27
1
D11 KSI2 27 KSI0 @ C485 100P_0402_50V8J~D KSO6 @ C486 100P_0402_50V8J~D
26 26
R896 2 KSI[0..7] KSI5 25
200_0402_5% JPBTN1 ON_OFF <31> <31> KSI[0..7] KSI1 25 KSI1 @ C487 100P_0402_50V8J~D KSO7 @ C488 100P_0402_50V8J~D
24 24
1 2 PWR_LED+ 1 PWR_ON-OFF_BTN# 1 KSO[0..18] KSI3 23
+5VALW 1 <31> KSO[0..18] 23
PWR_BTN_LED# 2 KSI0 22 KSI2 @ C489 100P_0402_50V8J~D KSO8 @ C490 100P_0402_50V8J~D
1 <31> PWR_BTN_LED# 2 22 1
PWR_ON-OFF_BTN# 3 5 3 51ON# KSO5 21
3 G5 51ON# <38> KSO4 21 KSI3 @ C491 100P_0402_50V8J~D KSO9 @ C492 100P_0402_50V8J~D
4 6 20
4 G6 BAT54C-7-F_SOT23-3~D KSO7 20
19 19
MOLEX_53261-0471 KSO6 18 KSI4 @ C493 100P_0402_50V8J~D KSO10 @ C494 100P_0402_50V8J~D
CONN@ KSO8 18
17
17
1
D KSO3 KSI5 @ C495 100P_0402_50V8J~D KSO11 @ C496 100P_0402_50V8J~D
D30 R336 16
EC_ON Q6 KSO1 16
<31> EC_ON 1 2 2 15
15
3 PWR_ON-OFF_BTN# 0_0402_5% G SSM3K7002FU_SC70-3~D KSO2 14
14
KSI6 @ C497 100P_0402_50V8J~D KSO12 @ C498 100P_0402_50V8J~D
1 S KSO0 13
3
13
1
2 KSO12 12 KSI7 @ C499 100P_0402_50V8J~D KSO13 @ C500 100P_0402_50V8J~D
KSO16 12
R337 11
PESD24VS2UT_SOT23-3~D KSO15 11 KSO0 @ C501 100P_0402_50V8J~D KSO14 @ C502 100P_0402_50V8J~D
10K_0402_5% 10 10
KSO13 9
KSO14 9 KSO1 @ C503 100P_0402_50V8J~D KSO15 @ C504 100P_0402_50V8J~D
8
2
KSO9 8
7
Place close JPBTN1 KSO11
KSO10
6
5
7
6
KSO2 @ C505 100P_0402_50V8J~D KSO16 @ C506 100P_0402_50V8J~D
KSO17 5 KSO3 @ C507 100P_0402_50V8J~D KSO17 @ C508 100P_0402_50V8J~D

4 4
KSO18 3 3 KSO4 @ C509 100P_0402_50V8J~D KSO18 @ C510 100P_0402_50V8J~D
2 2
1 1
/
KSO5 @ C511 100P_0402_50V8J~D
JAE_FL4S030HB3R3000
CONN@ For EMI
R02 add R02 modify
/x
RTCVREF RTCVREF RTCVREF RTCVREF
SDMK0340L-7-F_SOD323-2~D
CLOSE TO U44
0.1U_0402_16V4Z~D
@
1
Touch Screen Connector
su
1
1
10K_0402_1%
R1007
220K_0402_1%
R1008
R03 modify JTCH1

D46
C963
2 2
10
51ON# D36 +3VS
2 51ON# <38> USBP9-
1 4 1
G2
CH1 CH4 +3VS 1
2
2
2
5 1 2 VBUS 3 3 1
p.
R935 0_0402_5% 4
C964 4
1
D USBP9- C927
1 2 5 5
P
NC Vn Vp +3VS <22> USBP9- 5

USB_DETECT# 2 1 2 4 2 Q44 USBP9+ 6 0.1U_0402_10V7K~D
<30> USB_DETECT# A Y <22> USBP9+ 6 2
G 2N7002_SOT23-3~D 7
G
2.2U_0603_10V6K~D 7
8
G1
S
3
8
om
U44 3 6 USBP9+
3
CH2 CH3
1
100K_0402_5%
9
TC7SZ14FU_SSOP5~D @ CM1293-04SO_SOT23-6
R1009
JST_SM08B-SURS-TF(LF)(SN)~D
Place close JTCH1 CONN@
2
JTP1
yc
D47 1
USB_DET_DELAY# TP_CLK 1
2 1 2
SDMK0340L-7-F_SOD323-2~D
USB_DET_DELAY# <31>
Touch PAD/B Conn. +5VS
<31>
<31>
TP_CLK
LID_SW#
LID_SW#
TP_DATA
3
4
2
3
<31> TP_DATA +HALL_VCC 4
5 7
+HALL_VCC 5 G1
1 2 6 8
Power share +3VALW 6 G2
m
R933 0_0402_5% 1
1 2 LID_SW# TYCO_2041084-6
PESD5V2S2UT_SOT23-3~D
100P_0402_50V8J~D
C513
100P_0402_50V8J~D
C514
R934 10K_0402_5% C512 1 1 CONN@
2
1 0.1U_0402_10V7K~D
2
D1505
// C521
0.1U_0402_10V7K~D 2 2
2
3 3
1
R10:change to DELL AVL part.
Keyboard back light +3VS
p: 1
R927
10K_0402_5%
tt
+5VS
Q38 +5VS_KBL +5VS +3VS
2
SI3456BDV-T1-E3_TSOP6~D @
F1 BKLT_KB_DET#
BKLT_KB_DET# <31>
Cap Sensor R10:change to DELL AVL part. JCAP1
D
1U_0603_10V6K~D
B+_BIAS 6 0.75A_24V_1812L075-24DR 6 8
S
6 G2
1 5 4 2 1 5
5 G1
7
1
300K_0402_5%
R928
C928
2 20mil D L77 1 2 BLM18AG601SN1D_0603~D FB_SDATA 4

<31> EC_FB_SDATA 4
2
1 1 2 BKLT_KB_DET 2 Q39 L78 1 2 BLM18AG601SN1D_0603~D FB_SCLK 3

G <31> EC_FB_SCLK 3
R929 0_0805_5% 20mil MMBF170LT1G_SOT23-3~D 2
G
2
1
2
2 S C959 1
3
R930 33P_0402_50V8J~D 1
100K_0402_5% 1 2 FB_SDATA D1504 TYCO_2041084-6
1
EN_KBL PESD5V2S2UT_SOT23-3~D CONN@

2
1
1
D FB_SCLK
1 2
2 Q40 R931
<31> EN_KBL#
G SSM3K7002FU_SC70-3~D 2M_0402_5% C960
S +5VS_KBL 33P_0402_50V8J~D
3
JKBL1 R1003
1 TOUCHKEY_TINT 1 2
BKLT_KB_DET 1 <31> TOUCHKEY_TINT 0_0402_5%
2 2
4 4
3 3 GND 5
KB_BL_PWM 4 6
4 GND
TYCO_2041084-4
20mil CONN@ DELL CONFIDENTIAL/PROPRIETARY
1
D
2 Q41
<31> KB_BL_PWM# G
S
MMBF170LT1G_SOT23-3~D
3
20mil TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PWROK/BTN/KB/Touch Pad
LA-5152P
A B C D E
A B C D E
+3VALW to +3VS Transfer +5VALW to +5VS Transfer +1.5V to +1.5VS Transfer

+3VALW +3VS
B+_BIAS Q50
SI4392DY-T1-E3_SO8~D +5VALW 4.4A +5VS
8 3 B+_BIAS Q5 B+_BIAS +1.5V Q45 +1.5VS
0.1U_0402_10V7K~D
10U_0805_10V4Z~D
1 7 2 SI4800BDY-T1-E3_SO8~D SI4392DY-T1-E3_SO8~D
6 1 8 1 8 3
10U_0805_10V4Z~D
20K_0402_5%
R338 C515 5 1 1 7 2 7 2
1
0.1U_0402_10V7K~D
C519
10U_0805_10V4Z~D
C520
300K_0402_5% 1 6 3 R344 6 1 1
R345
2 10U_0805_10V4Z~D
C516
C517
C531
R343 C518 5 1 1 470K_0402_5% 5
4
1 300K_0402_5% 1
2 2
4
3VS_GATE 2 10U_0805_10V4Z~D 2
2
2 2
1
SSM3K7002FU_SC70-3~D
5VS_GATE
1
D C532
1 D 1
SUSP 2 R346 470P_0402_50V7K~D
2
Q7
Q10
SUSP 2 R340 C524 1 G 2M_0402_5%
1
G 2M_0402_5% 0.01U_0402_25V7K~D D C525 S
3
2
Q8
S SUSP 2
3
2
G 0.01U_0402_25V7K~D
S 2
3
R03 Modify
/
+3VALW
/x
1
R354
100K_0402_5%
su
2
2 SYSON# 2
<23> SYSON#
Discharge Circuit
1
D +1.05V_VCCP +0.75VS +5VS +3VS

SYSON 2 Q16
<28,31,42> SYSON
G SSM3K7002FU_SC70-3~D
1
p.
S +1.5V
3
2
R356
R352 R358 R359
R355 470_0402_5% 470_0402_5%
1
470_0402_5% 470_0402_5%
10K_0402_5%
2
om
R353
1
470_0402_5%
1
D D D D
2
SUSP 2 Q12 SUSP 2 Q19 SUSP 2 Q20 SUSP 2 Q17
SUSP
G SSM3K7002FU_SC70-3~D G SSM3K7002FU_SC70-3~D G SSM3K7002FU_SC70-3~D G SSM3K7002FU_SC70-3~D
1
D
S S S S
3
SYSON# 2 Q15
+5VALW
yc
S
3
1
R360
m
100K_0402_5%
R03 Delete +3V_WLAN discharge circuit.
2
SUSP
1
D //
SUSP# 2 Q21
<28,31,41,42> SUSP#
2
S
3
3 3
R361
10K_0402_5%
p:
1
tt
h
4 4
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DC/DC Circuits
LA-5152P
A B C D E
5 4 3 2 1
FD1 FD2 FD3 FD4

FIDUCAL FIDUCAL FIDUCAL FIDUCAL
@ @ @ @
D D
1
H2
/
@ HOLEA
H_1P6N
/x
1
su
H6
C @ HOLEA C
H_2P6
1
p.
H7 H8 H9 H10 H11 H12 H14 H15 H16
@ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA
om
H_3P0
1
1
H17 H18 H19 H5 H21 H23 H24 H35 H36
@ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA
yc
1
1
m
H3 H4 H22
@ HOLEA @ HOLEA @ HOLEA
H_3P2
//
1
B B
p:
H25 H26 H27 H28

@ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_4P0
1
tt
h
H29
@ HOLEA
H_3P0X4P0
1
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Screw
LA-5152P
5 4 3 2 1
5 4 3 2 1
@ D14
@D14 @ D15 @ D16
CRT DAN217_SC59-3 DAN217_SC59-3 DAN217_SC59-3
+5VS
R02 Modify +CRT_VCC
1
W=40mils D17 W=40mils
2 1 R02 memo modify
3 NC 1
+3VS C535
RB491D_SC59-3~D 1U_0603_10V6K~D
3
2
L31 BLM18BB050SN1D_0603~D JCRT1

VGA_CRT_R 1 2 1 2 CRT_R_L 6
D <12> VGA_CRT_R D
R893 0_0603_5% MSEN# 11
<31> MSEN# CRT_R_L
L32 BLM18BB050SN1D_0603~D 1
VGA_CRT_G 1 2 1 2 CRT_G_L 7
<12> VGA_CRT_G CRT_DDC_DATA_C
R894 0_0603_5% 12
L33 BLM18BB050SN1D_0603~D CRT_G_L 2
VGA_CRT_B 1 2 1 2 CRT_B_L 8
<12> VGA_CRT_B HSYNC_L
R895 0_0603_5% 13
150_0402_1%
R366
150_0402_1%
R367
150_0402_1%
R368
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
4.7P_0402_50V8C~D
C540
4.7P_0402_50V8C~D
C541
4.7P_0402_50V8C~D
C542
1 @ 1 @ 1 @ CRT_B_L 3
C537
C538
C539
1 1 1 9
1
For EMI VSYNC_L 14 G 16
4 G 17
2 2 2 10
2 2 2 CRT_DDC_CLK_C 15
2
1 1 5
100P_0402_50V8J~D
C543
100P_0402_50V8J~D
C544
TYCO_1775763-2
CONN@
2 2
+CRT_VCC
C545
/
+3VS +3VS +3VS +CRT_VCC +CRT_VCC
1 2
2
5
1
0.1U_0402_10V7K~D
/x
2.2K_0402_5%
R369
2.2K_0402_5%
R370
2K_0402_5%
R371
2K_0402_5%
R372
OE#
P
CRT_HSYNC_R 2 4 D_CRT_HSYNC 1 2 R1543 HSYNC_L
<12> CRT_HSYNC_R A Y 0_0603_5%
G
U26
1
1
74AHCT1G125GW_SOT353-5
3
D_CRT_VSYNC 1 2 R1544 VSYNC_L
su
2
G
0_0603_5%
C Q22 C
+CRT_VCC 1 1
15P_0402_50V8J
C547
15P_0402_50V8J
C548
3 1 CRT_DDC_DATA_C
<12> CRT_DDC_DATA C546
S
R373
1 2 1 2
SSM3K7002FU_SC70-3~D 2 2
10K_0402_5%
2
p.
0.1U_0402_10V7K~D
G
5
1
3 1 CRT_DDC_CLK_C
OE#
P
<12> CRT_DDC_CLK CRT_VSYNC_R
Q23
S
<12> CRT_VSYNC_R 2 4
SSM3K7002FU_SC70-3~D A Y
om
U27
74AHCT1G125GW_SOT353-5
3
yc
JAE_FI-G40SB-VF25-DT
40
+LCDVDD +5VALW 40 G11 51
39
+LCDVDD 39 G10 50
W=60mils 38
38 G9 49
37
+3VS 37 G8 48
2
m
LCD_TST 36
R376 R377 +3VS @ <31> LCD_TST R374 0_0402_5% EDID_CLK_LCD 36 G7 47
2 1 35
100_0603_5% 47K_0402_5%
<12> LVDS_DDC_CLK
R375 EDID_DATA_LCD 35 G6 46
R03: Add 2 1 0_0402_5% 34
G5 45
LCD 1
R384
2
0_0805_5%
<12> LVDS_DDC_DATA
<12> LVDS_A0-
<12> LVDS_A0+
LVDS_A0-
LVDS_A0+
33
32
34
33 G4 44
G3 43
1 1
32
// W=40mils Q202
31
31 G2 42
3
D S
LVDS_A1- 30
Q24
R378 G
Q25 B+ SI3457BDV-T1-E3_TSOP6~D <12> LVDS_A1- LVDS_A1+ 30 G1 41
2 2 1 2 <12> LVDS_A1+ 29
B SSM3K7002FU_SC70-3~D G SI2301BDS-T1-E3_SOT23-3~D 29 B
56K_0402_5% +INV_PWR_SRC 28
D
LVDS_A2- 28
S D 6 27
S
<12> LVDS_A2-
3
12.30 modify it +LCDVDD @ LVDS_A2+ 27

1 W=60mils 4 5 W=60mils <12> LVDS_A2+ 26
26
0.1U_0402_16V4Z~D
C549
D37 2 C1541 2 1 5P_0402_50V8C 25

p:
GM_ENVDD +LCDVDD LVDS_ACLK- 25

<12> GM_ENVDD 2 1 <12> LVDS_ACLK- 24
24
1
1
D
100K_0402_5%
G
1 LVDS_ACLK+ 23
2 <12> LVDS_ACLK+ 23
1000P_0402_50V7K~D
R1555
1 2 Q26 1 1 C1542 2 1 5P_0402_50V8C 22
3
22
C1546
G BSS138_SOT23~D @ 1 LVDS_B0- 21
<12> LVDS_B0- 21
1
LCD_VCC_TEST_EN 3 S C550 C551 @ LVDS_B0+ 20

<31> LCD_VCC_TEST_EN <12> LVDS_B0+
3
tt
R380 4.7U_0805_10V4Z~D 0.1U_0402_10V7K~D 2 C1545 20

19
2
BAT54C-7-F_SOT23-3~D 10K_0402_5% 2 2 0.1U_0603_50V4Z~D LVDS_B1- 19
2 R03: Reserve for EMI <12> LVDS_B1-
LVDS_B1+
18
18
<12> LVDS_B1+ 17
Place close to JLVDS1 16
17
2
16
h
LVDS_B2- 15
<12> LVDS_B2- 15
PWR_SRC_ON @ LVDS_B2+ 14
<12> LVDS_B2+ 14
C1544 2 1 5P_0402_50V8C 13
13
1
100K_0402_5%
LVDS_BCLK- 12
<12> LVDS_BCLK- 12
R1556
LVDS_BCLK+ 11
<12> LVDS_BCLK+ 11
C1543 2 1 5P_0402_50V8C 10
+3VS +3VS +3VS 10
9
@ 9
8
2
8
7
7
1
+LCDVDD INVT_PWM 6
6
1
R382 D DISPOFF# 5
@ R394 Q203 5
2 4
4
5
4.7K_0402_5% U45 10K_0402_5% G 2N7002W-7-F_SOT323-3~D +INV_PWR_SRC 3

D19 3
1 S 2
P
<12> VGA_PWM
2
BKOFF# DISPOFF# INA INVT_PWM 2

<31> BKOFF# 1 2 4 1
O 1
<31> EC_PWM 2
INB W=60mils
G
SDMK0340L-7-F_SOD323-2~D JLVDS1
CONN@
3
A 74AHC1G32GW_SOT353-5~D A
@ R944
0_0402_5%
@ R945
0_0402_5%
2 1
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CRT / LVDS CONN
LA-5152P
5 4 3 2 1
5 4 3 2 1
Recommended Equalization: [PC1,PC0]=01, 4dB

ST Parade
D +3VS R1523 X V +3VS D
R1524 V X
R1503 4.3K 499
1
0_0402_5%
R1525 V X
X76@
R1523
R1526 V X X76@ +5VS
R1527 V X R1528 1225 modify it.
R1528 V X 20K_0402_1% R1504 1 2 2.2K_0402_5% HDMI_SCL_SINK
X76@ R1529 V X
Vendor's suggestion for power saving.
2
R1524 @ U100 V V R1505 1 2 2.2K_0402_5% HDMI_SDA_SINK
2 1 R1500 1 2 4.7K_0402_1% HDMI_PC1 R1500 V X HDC_HPD#
R1516 V X
0_0402_5% R1511 V X
1
R1501 1 2 4.7K_0402_1% HDMI_PC0 R1512 V X X76@
R1513 V X R1529 +3VS +3VS
C1513 V X 7.5K_0402_1%
C1514 V X R1506 1 2 2.2K_0402_5% HDMI_C_DATA
C1515 V X
1
C1516 V X R1520 1 2 2.2K_0402_5% HDMI_C_CLK
R1519
10K_0402_1%
2
+3VS HDMI_OE#
U100 Q200
/x
1
D SSM3K7002FU_SC70-3~D
0.1U_0402_10V7K~D
0.01U_0402_16V7K~D
R1517 @ 0_0402_5% 2 HDMI_HPD_SINK
HDMI_OE# 25 1 1 1 2 G
OE#
S
3
C1511
C1512
2 L1504
HDMI_SCL_SINK VCC HDMI_OUT_D2+ HDMI_OUT_D2+_CONN
28 11 1 2
su
SCL_SINK VCC 2 2 1 2
VCC 15
C HDMI_SDA_SINK C
29 SDA_SINK VCC 21
26 HDMI_OUT_D2- 4 3 HDMI_OUT_D2-_CONN
VCC 4 3
VCC 33
+3VS HDMI_HPD_SINK 30 40 DLW21SN900HQ2L_0805_4P~D
HPD_SINK VCC
VCC 46 1 2
p.
R1502 1 2 4.7K_0402_1% 32 R1515 @ 0_0402_5%
DDC_EN
2 1 34 4 HDMI_PC1 +5VS
R1526 0_0402_5% CFG0 PC1 HDMI_PC0
X76@ 35 3
CFG1 PC0
om
X76@ R1514 1 @ 2 0_0402_5%
2 1 6 R1503 1 2 499_0402_1%
R1527 0_0402_5% REXT L1505
X76@
2
7 HDC_HPD# HDMI_OUT_D1+ 1 2 HDMI_OUT_D1+_CONN
HPD# HDC_HPD# <12> 1 2 @ R1518 F1500
8 0_1206_5% 1.5A_6V_1206L150PR~D
SDA HDMI_C_DATA <11>
HDMI_OUT_D1- 4 3 HDMI_OUT_D1-_CONN
4 3
yc
9 Co_Lay LINK OK
HDMI_C_CLK <11>
1
SCL X76@ DLW21SN900HQ2L_0805_4P~D
R1525 1 2 C1517 JHDMI1
10 2 1 R1507 @ 0_0402_5% 1U_0402_6.3V6K~D HDMI_HPD_SINK 19
RT_EN# +5VS_HDMI HP_DET
0_0402_5% 1 2 18
+5V
17
DDC/CEC_GND
m
48 13 HDMI_OUT_CLK+ HDMI_SDA_SINK 16
<12> HDC_CLK_P_C IN_D4+ OUT_D4+ HDMI_OUT_CLK- HDMI_SCL_SINK SDA
<12> HDC_CLK_N_C 47 14 15
IN_D4- OUT_D4- R1509 1 @ 0_0402_5% SCL
2 14
Reserved
45 16 HDMI_OUT_D2+ T9PAD 13
<12> HDC_DATA_P2_C IN_D3+ OUT_D3+ HDMI_OUT_D2- HDMI_OUT_CLK-_CONN CEC
44 17 L1507 12
<12> HDC_DATA_N2_C IN_D3- OUT_D3- CK-
<12> HDC_DATA_P1_C 42
IN_D2+ OUT_D2+
19
//
HDMI_OUT_D1+
HDMI_OUT_D0+ 1
1 2
2 HDMI_OUT_D0+_CONN
HDMI_OUT_CLK+_CONN
11
10
CK_shield
CK+
41 20 HDMI_OUT_D1- HDMI_OUT_D0-_CONN 9
B <12> HDC_DATA_N1_C IN_D2- OUT_D2- D0- B
HDMI_OUT_D0- 4 3 HDMI_OUT_D0-_CONN 8
HDMI_OUT_D0+ 4 3 HDMI_OUT_D0+_CONN D0_shield
<12> HDC_DATA_P0_C 39 22 7
IN_D1+ OUT_D1+ HDMI_OUT_D0- DLW21SN900HQ2L_0805_4P~D HDMI_OUT_D1-_CONN D0+
<12> HDC_DATA_N0_C 38 23 6
IN_D1- OUT_D1- D1-
1 2 5
p:
R1508 @ 0_0402_5% HDMI_OUT_D1+_CONN D1_shield

4 20
UMA use HDMI_OUT_D2-_CONN D1+ GND
3 21
D2- GND
1 2 22
GND HDMI_OUT_D2+_CONN D2_shield GND
5 1 23
GND R1522 1 D2+ GND
12 @ 2 0_0402_5%
tt
GND FOX_QJ5119L-NVBT-7F
18
GND L1506
24
GND HDMI_OUT_CLK+ HDMI_OUT_CLK+_CONN
27 1 2
GND 1 2
31
GND
h
36
GND HDMI_OUT_CLK- HDMI_OUT_CLK-_CONN
37 4 3
GND 4 3
43
GND DLW21SN900HQ2L_0805_4P~D
49
PAD
1 2
X76@ PS8101TQFN48G_QFN48_7X7 R1510 @ 0_0402_5%
HDMI_OUT_D2+ @ R1516 1 2 HDMI_OUT_D2+- @ C1514 1 2 HDMI_OUT_D2-

300_0402_1% 0.1U_0402_10V7K~D
300_0402_1% 0.1U_0402_10V7K~D
300_0402_1% 0.1U_0402_10V7K~D
HDMI_OUT_CLK+ @ R1512 1 2 HDMI_OUT_CLK+-@ C1515 1 2 HDMI_OUT_CLK-
300_0402_1% 0.1U_0402_10V7K~D
A A
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-5152P
5 4 3 2 1
5 4 3 2 1
Place close JDP1

D @ D150 D
DPB_LANE_P0_C 1 10 DPB_LANE_P0_C
+3VS
DPB_LANE_N0_C 2 9 DPB_LANE_N0_C
1
R1534
20K_0402_5% DPB_LANE_N1_C 5 6 DPB_LANE_N1_C
GCH:Level voltage 0.9V 3
2
+3VS
<12> DPB_HPD# Q201 8
1
D SSM3K7002FU_SC70-3~D
2 DPB_HPD RCLAMP0524P.TCT~D
1
1
R1535 S
3
7.5K_0402_5% R1530
100K_0402_5% @ D151
1.5A_6V_1206L150PR~D
2
2
2
F1501
DPB_LANE_N2_C 2 9 DPB_LANE_N2_C @
1
/
0_1206_5%
R1521
1
DPB_LANE_N3_C 5 DPB_LANE_N3_C
/x
6
CO_Lay
2
3
8
JDP1
RCLAMP0524P.TCT~D
su
C C
DPB_LANE_P0_C 1
<12> DPB_LANE_P0_C LANE0_P
2 GND
DPB_LANE_N0_C 3
<12> DPB_LANE_N0_C DPB_LANE_P1_C
LANE0_N
<12> DPB_LANE_P1_C 4 LANE1_P
p.
5 GND
DPB_LANE_N1_C 6
<12> DPB_LANE_N1_C LANE1_N
DPB_LANE_P2_C 7
8 GND
DPB_LANE_N2_C 9
<12> DPB_LANE_N2_C LANE2_N
om
DPB_LANE_P3_C 10
11 GND
DPB_LANE_N3_C 12
<12> DPB_LANE_N3_C DPB_CA_DET
LANE3_N
13
DISP_CEC 14 CONFIG1
CONFIG2
DPB_AUX_SW 15 AUXCH_P
16 GND
DPB_AUX#_SW 17 AUXCH_N
yc
DPB_HPD
DPB_CA_DET= 1 TMDS Signaling 18
SW for MB side DPB_CA_DET= 0 DP Signaling +3VS_DP2
19
20
RETURN
HPD
DP_PWR
21
22
C1518
R1531
R416
GROUND
+5VS 23
C573
C1521 0.1U_0402_10V7K~D
C572
24
0.1U_0402_10V7K~D U105 R03 modify it.
2 1
1
2 1 DPB_AUX_C 2 8 1 1
<12> DPB_AUX DPB_AUX#_C 1A VCC DPB_AUX_SW
5 3 R1553 1 2 100K_0402_5% FOX_3V102P1-RB2BT-8F
2A 1B
<12> DPB_AUX# 2 1 1
7
1OE# 2B
6
4
// DPB_AUX#_SW R1554 1 2 100K_0402_5% +3VS
0.1U_0402_10V7K~D
C1522 2OE# GND 2 2
2
1M_0402_5%
5.1M_0402_5%
22U_0805_6.3V6M~D
B 0.1U_0402_10V7K~D SN74CBTD3306CPWR_TSSOP8~D B
p:
+5VS C1519
0.1U_0402_10V7K~D
U106
1 2
HDMI_B_CLK 2 8
<11> HDMI_B_CLK HDMI_B_DATA 1A VCC
<11> HDMI_B_DATA 5 3
tt
2A 1B
1 6
1OE# 2B +3VS C1520
7 4
2OE# GND 0.1U_0402_10V7K~D
SN74CBTD3306CPWR_TSSOP8~D 2 1
+3VS
h
1
R1533
P
NC
1 2 HDMI_B_CLK DPB_CA_DET# 4 2 DPB_CA_DET

Y A
2.2K_0402_5%
G
R1532 U107
1 2 HDMI_B_DATA NC7SZ04P5X_NL_SC70-5~D
3
2.2K_0402_5%
1225 modify it.
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Display Port
LA-5152P
5 4 3 2 1
5 4 3 2 1
+5VALW +3VALW
ADPIN VIN
DA204U_SOT323~D
PL1
SMB3025500YA_2P
2
PD4
2.2K_0402_5%~D
@PR15
@ PR15 0_0402_5%~D
7 7 1 2 1 2
2
6 6
5 5 PQ2
PR16
D D
4 4 FDV301N_NL_SOT23-3~D PR17
3 3
1
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
33_0402_5%~D
2 2
1
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
DOCK_PSID
1 1
1 3 1 2
S
PS_ID <31>
1
PC3
PC5
PC7
MOLEX_87438-0743
PC2
PC4
PC6
@PJPDC1
@ PJPDC1
G
2
2
15K_0402_1%~D 100K_0402_1%~D
+5VALW
2
+5VALW
DA204U_SOT323~D
PR18
10K_0402_1%~D
1
2
PD6
1
2
PR19
C
PL2 2 PQ3
BLM18BD102SN1D_0603~D B MMST3904-7-F_SOT323~D @
2
PSID 2 1 DOCK_PSID E
2
PR20
1
@
1
PD5 PR21
SM24_SOT23 1 2
/
@ 10K_0402_1%~D
/x
su
C C
VIN
p.
2
PD2
PJP1
om
PD3 @ JUMP_43X118 RLS4148_LL34-2
1 1
2 1 1 1
BATT+ 2 2
1
PC193 @ PR204
@
RLS4148_LL34-2 PR10 PR208 2200P_0402_50V7K~D 56K_0402_5%~D
68_1206_5%~D 68_1206_5%~D VS
1 2 1 2
2
2
PQ1
yc
CHGRTCP 3 TP0610K-T1-E3_SOT23-3
1 PR202
0.22U_1206_25V7K
@ 1M_0402_1%~D
32.8 1 2
1
VIN
1
PR11 VS VIN
PC11
0.01U_0402_25V7K~D
100K_0402_5%~D PC12
m
0.1U_0603_25V7K~D
2
1
PR12 @ PR205 @ PR192
@PR192
2
1
PC192
22K_0402_5%~D @PR191
@PR191 10K_0402_5%~D 1K_0402_5%~D
1 2 82.5K_0402_1%~D 1 2 ACIN <21,25,31,39>
<32> 51ON#
2
// PR193 @
2
8
@ 22K_0402_1%~D @
N41 VinDe_IN3 3 PU17A
1 2
P
B + VinDe_Out B
1
O
19.6K_0402_1%~D
.1U_0402_16V7K~D
VinDe_Ref 2
-
G
1
1
1
1
PC194
PR206
LM393DR_SO8 @ PR203
p:
4
@ PC191 @ PD1 10K_0402_5%~D
1000P_0402_50V7K~D RLZ4.3B_LL34
2
@ @
2
tt
@ PR201
10K_0402_5%~D
2 1
RTCVREF
1
h
3.3V
8
PR13
5 @ PU17B
200_0805_5%
P
+
7
O
6
2
G
LM393DR_SO8
Vin Detector
4
RTCVREF
PU3
1 MAX1615_IN Max. typ. Min.
IN
3
OUT L-->H 18.234 17.841 17.449
MAX1615_#SHDN1
H-->L 17.597 17.210 16.813
4.7U_0805_6.3V6K~D
5 2
#SHDN
1
1
PC13
4 PR14 0_0402_5%~D
GND
5/3+ PC14
1U_0805_25V4Z~D
2
MAX1615EUK+_SOT23-5~D
2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DCIN/Precharge
LA-5152P
5 4 3 2 1
A B C D E
PR90 0_1206_5%~D
PVCC_CHG 2 1
B+
VIN PQ4 PQ5
FDS6675BZ_SO8 FDS6675BZ_SO8 PR22
8 1 1 8 0.015_2512_1%
0.01U_0402_25V7K~D
7 2 2 7 PJP17
6 3 3 6 1 4 2 1 CHG_B+
2 1
1
5 5
2
2200P_0402_50V7K~D
PC21
PC17
PC22
PC18
PC23
0.1U_0603_25V7K~D
2 3 @ JUMP_43X118 PR24
PC15
3.3_1210_5%~D
100K_0402_1%~D
4
1
2
PC189
PC188
0.022U_0603_50V7~D
1
2
100K_0402_1%~D
PR23
CHGEN#
2
1
1000P_0402_50V7K~D
1000P_0402_50V7K~D
4.7U_1206_25V6K~D
4.7U_1206_25V6K~D
4.7U_1206_25V6K~D
PC16 PC24 PC20
1
2
5
6
7
8
3
2
1
PC25
0.01U_0603_50V7K~D .1U_0402_16V7K~D PU4 0.1U_0603_25V7K~D
PR26
1 PQ7 1
1 2 1 28 1 2
1 2
PR28 CHGEN PVCC PQ6 FDS6675BZ_SO8
2
1
1
340K_0402_1%~D PR25 FDS8884_SO8 4
/BATDRV
2
PR27
3.3_1210_5%~D
PC26 PC27 2.2_0603_5%~D

0.1U_0603_25V7K~D 0.1U_0603_25V7K~D 27 1 2 4
2
BTST
@ PC100 0.022U_0603_50V7~D
2
2 1 ACN 2 26 DH_CHG
ACDRV_CHG# ACP ACN HIDRV
3
3
2
1
5
6
7
8
ACP
2
PR37 0_0603_5%~D
2 1 4 25 LX_CHG PL3 PR29
ACDRV PH
2.2U_0805_25V6K
ACDET 5 PD7 10UH_SIL1045RA-100PF_4.5A_30% 0.02_2512_1%~D BATT+

1
ACDET
2 1 1 2 1 2 1 4
PC19
CP setting
10U_1206_25V6M~D
10U_1206_25V6M~D
680P_0603_50V7K~D 4.7_1206_5%~D
ACSET
REGN
RLS4148_LL34-2 PC28 2 3
2
0.1U_0603_25V7K~D
5
6
7
8
1
PR32
PC31
PC32
PR31 PR89
10U_1206_25V6M~D
1
54.9K_0402_1% 97.6K_0402_1%~D 6
PC30
ACSET
2
SSM3K7002F_SC59-3
24 PQ8
2
REGN
1
0.01U_0402_25V7K~D
FDS6690AS_NL_SO8 @
11
1
D
60.4K_0402_1%
@ PC33
PR33 PC29
1
/
PQ25
CP_SEL 2 100K_0402_1%~D 1U_0603_10V6K~D 4
1 2
<31> CP_SEL
PR30
0.1U_0402_10V7K~D
G
2
2
2
1
PC190
PC35
/x
1 2 7 ACOP
1
PR34 PC34 23 DL_CHG
3
2
1
2
340K_0402_1%~D 0.47U_0603_16V7K~D LODRV
2
@ +3VALW @
1
PGND 22
OVPSET 8 OVPSET .1U_0402_16V7K~D
su
1 2
2 2
9 AGND LEARN 21 ACOFF <31>
2
1
PR35 PR88
54.9K_0402_1% VREF 0_0402_5%~D PC37 PC38
20 CELLS 1 2 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
2
CELLS
p.
1
10 VREF
PQ9
1
SI2301BDS-T1-E3_SOT23-3 PC39
1U_0603_10V6K~D PR86
om
PR36 @ 0_0402_5%~D 19 SRP
2
100K_0402_1%~D SRP
1 2GATE 2 11 18 SRN
2
VDAC SRN
1
+3VALW 1 2 BAT
17
PC40 PR87
1
0.1U_0603_25V7K~D 0_0402_5%~D VADJ 12
2
VADJ PC41
1
0.1U_0603_25V7K~D
yc
ACSET
2
29
TP
ACGOOD#
13
ACGOOD ICHG setting RTCVREF VREF
90W adapter PR38
16 SRSET 2 1
SRSET IREF <31>
2
/BATDRV
m
Icharge=(Vsrset/Vvdac)*(0.1/PR29)=3.3A REGN 14
BATDRV 51.1K_0402_1%~D
1
1
Iadapter=(Vacset/Vvdac)*(0.1/PR22)=4.16A PR40 PR41 PR42
1
15 1 2 100K_0402_1%~D @ PC42 47K_0402_1%~D 47K_0402_1%~D

PR43 IADAPT 0.01U_0402_25V7K~D
Input OVP : 22.3V
1
@ 0_0402_5%~D
// BQ24751ARHDR_QFN28_5X5 PR39
2
Input UVP : 16.98V PR44 10_0603_5%~D
210K_0402_1%~D ACIN <21,25,31,38>
2
1
3 VADJ D 3
Fsw : 300KHz <31> CHGVADJ 1 2
ACGOOD# 2 PQ11
<31> ADP_I
1
G SSM3K7002F_SC59-3
1
PR45 IREF Current S
p:
3
65W adapter(CP_SEL high) 499K_0402_1%~D PC43
100P_0402_50V8J~D
2
Iadapter=(Vacset/Vvdac)*(0.1/PR22)=3A 3.3V 3.3A
2
tt
+COINCELL
PR46
PQ12
B+ 1 2 3 TP0610K-T1-E3_SOT23-3
1 VREF
B+_BIAS
1
470K_0402_5%~D
100_0805_5%~D VREF
32.8 COIN RTC Battery
1
VREF
0.1U_0805_25V7M~N
GATE PR47
2
+5VALW PR49 1K_0402_5%~D

PR48
PC44 200K_0402_1%~D
1
2
RTCVREF
1
2
1
D +COINCELL PR51
PJPRTC
2
PR50 PQ13
Z4012
2 47K_0402_1%~D
1
1
220K_0402_5%
PD8 100K_0402_1%~D G SSM3K7002F_SC59-3 1

1
2
S 2
2
1
2
1
D
PR52
3
1SS355TE-17_SOD323-2 ACOFF 1 PQ14 G1
2 2 4 CHGEN#
G2
2
G SSM3K7002F_SC59-3
2
1
PC45 +RTCVCC D
S
1
MOLEX_53261-0271_2P
1
PQ15 D .1U_0402_16V7K~D PQ16

<31> FSTCHG 2
2 PR53 @ G SSM3K7002F_SC59-3
0.1U_0603_25V7K~D
G RHU002N06_SOT323-3 340K_0402_1%~D S
3
220K_0402_5%
S PD9
3
1
2
BAT54CW_SOT323~D
1
PC47
PR54
4
1 4
PC46
1U_0603_10V4Z~D
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC,MB A5152
LA-5152P
A B C D E
5 4 3 2 1
TPS51427_B+
TPS51427_B+
B+
PJP19 PR55
@ JUMP_43X118 0_0805_5%
1 1 2 2 1 2
D D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
4.7U_1206_25V6K~D
4.7U_1206_25V6K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
VL
4.7U_1206_25V6K~D
4.7U_1206_25V6K~D
1
5
6
7
8
<BOM Structure>
PC84
PC48
PC49
PC50
8
7
6
5
1
PC53
PC197
SI4686DY-T1-E3_SO8
2
PQ17
PC51
PC52
2
2
SI4686DY-T1-E3_SO8
1U_0603_10V6K~D
2
2
PQ18
4.7U_0805_6.3V6K~D
2
PC54 4
1
0.1U_0603_25V7K~D
PC55
4
1
+5VALWP
PC56
1
3
2
1
PL5
1
2
3
PL4 2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D
7
2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D PU5 PC59 2 1
1 2 1U_0603_10V6K~D
LDO
VIN
V5FILT
+3VALWP 33 19 1 2
4.7_1206_5%~D
TP V5DRV
5
6
7
8
1
/
1
8
7
6
5
DH3 26 15 DH5
680P_0603_50V7K~D 4.7_1206_5%~D
D
D
D
D
PQ19 PR59 DRVH2 DRVH1 PR60
PR56
PR58
FDS6670AS_NL_SO8
D
D
D
D
FDS6670AS_NL_SO8
/x
1 BST3A BST5A 2
0_0402_5%~D
2 24 17 1
0.1U_0402_10V7K~D
VBST2 VBST1
2
PQ20
1 0_0603_5%~D
0_0603_5%~D
2
2
2
PR57
61.9K_0402_1%~D
2
G
1
PC60 + PC57 PC61

PC79
680P_0603_50V7K~D
G
2
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
0.1U_0402_10V7K~D
1
1
1
S
S
S
330U_D_6.3VM_R18M~D LX3 LX5
PR61
25 16 1
330U_D_6.3VM_R18M~D
2
2 LL2 LL1
S
S
S
su
PC58
PC62
3
2
1
1
+
PC80
PC63
C C
1
2
3
DL3 23 18 DL5
1
DRVL2 DRVL1
2
2
10K_0402_1%~D
2
22
p.
PGND
2
FB3
PR62
30 VOUT2
PR63
10K_0402_1%~D
@ 10
VOUT1
VL 32
1
REFIN2
om
1
11 FB5
2VREF_TPS51427 FB1
1 2 1 VREF2
PC64 0.22U_0603_10V7K~D
9
yc
VSW
8 LDOREFIN @ PR64 0_0402_5%~D
SKIPSEL 29 2 1 VL
PR65 0_0402_5%~D
m
1 2
20 NC PGOOD2 28
PD10 PR66
VS RLZ5.1B_LL34 100K_0402_1%~D
EN_LDO POK <21>
1 2 1 2
// 4 EN_LDO PGOOD1 13 PR68
2
205K_0402_1%~D
200K_0402_5%~D
B PC65 TPS51427_EN1 ILM1 B

PR67
14 EN1 TRIP1 12 2 1
0.22U_0603_25V7-K
3.3VALWP
TONSE
VREF3
1
Thermal Design Current=8.21A

p:
TPS51427_EN2
27 EN2 31 ILIM2 2 1
GND
1
TRIP2
2
Peak Current=10.27A 2 PR69

@ PR70 TPS51427_QFN32_5X5 243K_0402_1%~D
0_0402_5%~D
OCP min=12.32A
21
VL 0_0402_5%~D
tt
PR71
806K_0603_1%
Fsw=300K
2
1
PR72
Output Ripple current=

2VREF_TPS51427 1
1U_0603_10V6K~D
h
@ PR74 1
PR73 47K_0402_5%~D
5VALWP
PC66
Rds(on) = 11.5m ohm(max)

1
2 1 1 2 @ PR75 Thermai Design Current=6.88A

2
<7,44> MAINPW ON 2VREF_TPS51427 2

Rds(on) = 9m ohm(typical) 0_0402_5%~D
0_0402_5%~D Peak Current=8.6A
0.047U_0603_16V7K~D
0.047U_0402_16V7K~N
OCP min=10.32A
1
PJP5
2
@ JUMP_43X118
PC67
Fsw=400K
PC68
+5VALW P 1 1 2 2
2
+5VALW
PQ21 @ Output Ripple current=
PJP7 TP0610K-T1-E3_SOT23-3
@ JUMP_43X118
Rds(on) = 11.5m ohm(max) ; Rds(on) = 9m ohm(typical)
1 1 2 2 1 3
A A
PD11
PJP11
@ JUMP_43X118
1 1 1SS355TE-17_SOD323-2
2 2
PJP9 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
@ JUMP_43X118 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1 1 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, +3VALWP/+5VALWP
+3VALW P 2 2 +3VALW NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
LA-5152P
5 4 3 2 1
A B C D
@ PJP20
VCCP_B++ 2 1 B+
+1.05V_VCCP
10U_1206_25V6M~D
2200P_0402_50V7K~D
PAD-OPEN 4x4m
Thermal Desig Current=15.81A
10U_1206_25V6M~D
0.1U_0603_25V7K~D
Peak Current=19.77A
PC70
1
1
PC85
PC86
OCP min=23A
PC69
Fsw=300KHz
2
1 <Vo=1.05V> VFB=0.75V 1
Vo=VFB*(1+PR430/PR433)=0.75*(1+8.66K/21.5K)=1.052V
PR76
267K_0402_1%~D
1 2
5
PR77
0_0402_5%~D PR78 PQ22
2 1 EN_VCCP BST_VCCP1 2 1 2 FDMS8692_POW ER56-8-5
<28,31,33,42> SUSP#
1
@ PC72 0_0603_5%~D PC71 0.1U_0603_25V7K~D
PR79 .1U_0402_16V7K~D 4
30.1K_0402_1%~D
2
+5VS
15
14
2
1
PU6
/ 3
2
1
PL6
EN_PSV
TP
VBST
1UH_FDUE1040D-1R0M-P3_21.3A_20% +1.05V_VCCPP
TON_VCCP 2 13 UG_VCCP 1 2
/x
TON DRVH
2
PR80 LX_VCCP
220U_D2_4VM
220U_D2_4VM
220U_D2_4VM
3 12
0.1U_0402_10V7K~D
4.7U_0805_6.3V6K~D
VOUT LL 1 1 1
5
300_0603_5%~D PR81 PR82 @ PR83
SI4634DY_SO8
SI4634DY_SO8
0_0603_5%~D + + +
PC73
PC83
PC99
+5VS 1 2 V5FILT_VCCP 4 11 TRIP_VCCP
1 2 4.7_1206_5%~D
V5FILT TRIP
1
PC74
PC81
7.87K_0402_1%~D
FB_VCCP 5 10 V5DRV_VCCP
su
2
2 1
VFB V5DRV
1
2 2 @ 2
PQ23
PQ24
2
2
PC76 6 9 LG_VCCP 4 4 @ PC75 2
PGOOD DRVL
PGND
1U_0603_10V6K~D 680P_0603_50V8J~D
GND
2
1
1
TPS51117RGYR_QFN14_3.5x3.5 PC77
p.
7
3
2
1
3
2
1
@ PC78 4.7U_0805_10V6K~D
2
47P_0402_50V8J~D
2 1
om
2 1
PR84
8.66K_0402_1%~D
1
PR85
21.5K_0402_1%~D
yc
2
m
//
@ PJP18
5
3
JUMP_43X118 PU13 RT9025 3
NC
+3VALW 1 1 2 2 3 VIN VOUT 6 +1.8VSP
p:
1K_0402_1%~D
10U_1206_25V6M~D
1
<28,31,33,42> SUSP# 1 2 2 EN ADJ 7
1
PR94
PC126
PC87
PR93 0_0402_5%~D 1000P_0402_50V7K~D PC88
4 1 10U_1206_25V6M~D
tt
+5VALW
2
VDD PGOOD
2
1
@ PC171 GND GND

0.1U_0402_16V7K~D
10U_1206_25V6M~D
8
h
2
PC172
1
806_0402_1%~D
1
2
PR95
PC170
1U_0402_6.3V6K~D
2
2
@ PJP4
JUMP_43X118
+1.05V_VCCPP 1 1 2 2 +1.05V_VCCP
@ PJP6
+1.8VSP
JUMP_43X118 Imax=0.67A
1 1 2 2
Vout=0.8*(PR94+PR95)/PR95=0.8*(1k+806)/806=1.79V
4 4
@ PJP27 DELL CONFIDENTIAL/PROPRIETARY

2 1 +1.8VS
+1.8VSP
PAD-OPEN 2x2m~D
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, +1.05V_VCCP/+1.8VSP
LA-5152P
A B C D
A B C D
@ PJP22
+1.5VSP_B++ 2 1 B+
1.5V
2200P_0402_50V7K~D
Thermal Design Current=10.56A PAD-OPEN 4x4m
Peak Current=13.2A
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0.1U_0603_25V7K~D
OCP min=15.84A
1
PC184
PC185
Fsw=298KHz
PC183
PC89
PC90
2
2
<Vo=1.5V> VFB=0.75V
1
Vo=VFB*(1+PR104/PR105)=0.75*(1+22.1K/22.1K)=1.5V 1
PR96
267K_0402_1%~D
1 2
5
PR97 PR98 PC91
0_0402_5%~D 0_0603_5%~D 0.1U_0603_25V7K~D PQ27
2 1 EN_1.5 BST_1.5 1 2 1 2
<28,31,33> SYSON
FDMS8692_POW ER56-8-5
1
PR99 4
30.1K_0402_1%~D @ PC92
2
.1U_0402_16V7K~D
+5VALW
15
14
2
1
PU8
3
2
1
PL8
/
EN_PSV
TP
VBST
1UH_FDUE1040D-1R0M-P3_21.3A_20%
TON_1.5 2 13 UG_1.5 1 2 +1.5VP
TON DRVH
/x
1
2
PR100 3 12 LX_1.6
0.1U_0402_10V7K~D
4.7U_0805_6.3V6K~D
VOUT LL 1 1
5
6
7
8
5
6
7
8
300_0603_5%~D PR101 PR102 @ PR103
220U_D2_4VM
220U_D2_4VM
1
0_0603_5%~D + +
PC82
1 2 V5FILT_1.5 4 11 TRIP_1.51 2 4.7_1206_5%~D
FDS6670AS_NL_SO8
FDS6670AS_NL_SO8
D
D
D
D
D
D
D
D
+5VALW V5FILT TRIP
PC177
PC93
PC94
6.49K_0402_1%~D
FB_1.5 5 10 V5DRV_1.5
2 1
2
VFB V5DRV
1
2 2
PQ28
PQ42
su
PC96 6 9 LG_1.5 4 4 @ PC95
<11> 1.5V_PGOOD PGOOD DRVL G G
PGND
2
1U_0603_10V6K~D 680P_0603_50V8J~D 2
GND
2
1
1
S
S
S
S
S
S
PR207 TPS51117RGYR_QFN14_3.5x3.5 PC97
3
2
1
3
2
1
@ PC98 100K_0402_1%~D 4.7U_0805_10V6K~D
p. 2
47P_0402_50V8J~D
1
2 1
+5VALW
om
2 1
PR104
22.1K_0402_1%~D
1
PR105
22.1K_0402_1%~D
yc
2
m
//
3
PU11 3
RT9026_MSOP10
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
@ PJP24
p:
1U_0603_10V6K~D
+1.5VP 1 1 2 2 1 VDDQSNS VIN 10 +3VALW
1
1
PC155
PC156
JUMP_43X118 2 VLDOIN
PC154
tt
2
2
@ 8
GND
VTTREF 6
+0.75VSP 3 VTT
10U_0805_10V6K~D
h
1
1
PR174
10U_0805_10V6K~D
5 VTTSNS S5 9
PC158
0_0402_5%~D PC159
PGND
PC157
7 2 1 0.1U_0402_16V7K~D
GND
SUSP# <28,31,33,41>
2
2
S3
+0.75VSP
1
4
11
@ PC160 Thermal Design Current:0.7A

0.1U_0402_16V7K~D
2
Peak current:1A
Vout=VDDQSNS/2=1.5V/2=0.75V
@ PJP15
JUMP_43X118
1 1 2 2 +1.5V
+1.5VP
4
@ PJP16 4
JUMP_43X118
1 1 2 2
+0.75VSP 2
@ PJP29
1
+0.75VS PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
PAD-OPEN 2x2m~D TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, +1.5VSP/+0.75VSP
LA-5152P
A B C D
5 4 3 2 1
+5VS
2
PR130
PC118 +CPU_B+
1_0603_5%~D
2 1 PL10
<8>
<8>
<8>
<8>
<8>
<8>
<8>
FBMA-L18-453215-900LMA90T_1812
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
1
@ 1 2
5600P_0402_25V7K
<7,31>
VR_ON
100U_25V_M~D
100U_25V_M~D
100U_25V_M~D
1U_0603_10V6K~D
10U_1206_25VAK~D
10U_1206_25VAK~D
10U_1206_25VAK~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
B+
1 1 1
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
1
1
PR131 499_0402_1%~D
PC120
PC121
@ PC175
PC173
PC174
1U_0603_10V6K~D
D D
1
+ + +
PC119
PC122
PC123
PC124
PC125
PC176
PC178
<11,21> DPRSLPVR 1 2
PR134 0_0402_5%~D
2
PR132 0_0402_5%~D
2
1
5
2 2 2
<8,11,19> H_DPRSTP# 1 2
PR135 0_0402_5%~D
PR142 0_0402_5%~D
PR136 0_0402_5%~D
PR137 0_0402_5%~D
PR138 0_0402_5%~D
PR139 0_0402_5%~D
PR140 0_0402_5%~D
SI7686DP-T1-E3_SO8
SI7686DP-T1-E3_SO8
1
1
PAD PT1
PQ39
PQ38
2
+3VS PR141 0_0402_5%~D 4 4
DPRSLPVR_CPU
1 2 @
DPRSTP#_CPU
CLK_EN#_CPU
VR_ON_CPU
2
+3VS PC128 PL11
1U_0603_10V6K~D
3V3_CPU
1.91K_0402_1%~D
3
2
1
3
2
1
1
PR144 0.22U_0603_10V7K~D 0.36UH_FDU1040D-R36M_26A_20%
PC127
1
VID6
VID5
VID4
VID3
VID2
VID1
VID0
BOOT_CPU1 1 2 1 2 4 1 +CPU_CORE
2
PR143
4.7_1206_5%~D
2
1
@ PR145 2.2_0603_5%~D 3 2
1
499_0402_1%~D
PR146
49
48
47
46
45
44
43
42
41
40
39
38
37
3.65K_1206_1%
10K_0402_1%~D
SI4634DY-T1-E3 1N SO8
PR149
PR148
2
1_0402_5%~D
PR147
3V3
CLK_EN#
DPRSTP#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
GND
DPRSLPVR
VR_ON
1
PQ35
PQ34
@ PR150
680P_0603_50V8J~D
1 2
<11,21,31> VGATE
/x
1 36 4 4 0_0402_5%~D
2
PGOOD BOOT1
PC129
<8> H_PSI# 1 2
2 35 UGATE_CPU1 PC130
<31> POW _MON 1U_0603_10V6K~D PC131 PR151 10K_0402_1%~D PSI# UGATE1
1 2
2
1 2 1 2 PMON_CPU3 34 PHASE_CPU1 VSUM VCC_PRM
3
2
1
3
2
1
PMON PHASE1 ISEN1
su
PR152 147K_0402_1%~D 4 33 0.22U_0603_16V7K~D
C RBIAS_CPU RBIAS PGND1 C
1 2
VR_TT# 5 32 LGATE_CPU1
VR_TT# LGATE1
5
@ PR153 4.22K_0402_1% @ PH1 100K_0603_1%_TH11-4H104FT
10U_1206_25VAK~D
10U_1206_25VAK~D
10U_1206_25VAK~D
+CPU_B+
1
NTC_CPU PVCC_CPU
PC179
PC133
PC134
PC135
1 2 1 2 6 31
SI7686DP-T1-E3_SO8
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
NTC PVCC
PC180
SI7686DP-T1-E3_SO8
p.
@ PC132 0.015U_0402_16V7K SOFT_CPU 7 30 LGATE_CPU2
2
SOFT LGATE2
PQ41
PQ40
1 2
OCSET_CPU 8 29 4 4
PC136 0.022U_0603_25V7K OCSET ISL6266ACRZ-T_QFN48_7X7 PGND2 @
om
1 2 VW _CPU 9 28 PHASE_CPU2
VW PHASE2
PR154 11.5K_0402_1%~D COMP_CPU 10 27 UGATE_CPU2 PL12
3
2
1
3
2
1
COMP UGATE2 PR155 PC137 0.36UH_FDU1040D-R36M_26A_20%
1 2
FB_CPU 11 26 BOOT_CPU2
1 2 1 2 4 1
PC138 1 FB BOOT2
2
1
DROOP
1000P_0402_50V7K~D 12 25 2.2_0603_5%~D
0.22U_0603_10V7K~D 3 2
FB2 NC
1
VDIFF
ISEN2
ISEN1
VSUM
FB2_CPU
VSEN
PR156 11.3K_0402_1%~D PR157
3.65K_1206_1%
yc
GND
VDD
RTN
DFB
1
VIN
4.7_1206_5%~D PR160
VO
PR158
1 2
10K_0402_1%~D
PR159
1 2 PU10 1_0402_5%~D
1 2
13
14
15
16
17
18
19
20
21
VDD_CPU22
23
24
PQ36
PQ37
2
PC139 1000P_0402_50V7K~D 4 4 @ PR161
2
m
29.1
ISEN1 PC140 0_0402_5%~D
DROOP_CPU
VDIFF_CPU
ISEN2 680P_0603_50V8J~D
VSEN_CPU
1 2
2
RTN_CPU
DFB_CPU
VIN_CPU
PR163 97.6K_0402_1%~D PC141 270P_0402_50V7K~D 1 2 +5VS

1
1 2 2 1 PC143
3
2
1
3
2
1
1
PR162 1_0603_5%~D VSUM

PC144 100P_0402_50V8J~D PR164
// PC142
1 2
1 2 1K_0402_1%~D 1U_0603_10V6K~D 0.22U_0603_16V7K~D

2
B B
2
2
VCC_PRM
100K_0402_1%~D
PR166 ISEN2
@ PR194
p:
PR165 PC145 2200P_0402_50V7K~D 10_0603_5%~D

1 2 1 2 1 2 +CPU_B+
1
100_0402_1%~D
1
1 2
PR167 1K_0402_1%~D PC146
2
tt
0.1U_0603_25V7K~D
PR168 PC147 330P_0402_50V7K~D
<8> VCCSENSE 1 2 1 2
VSUM
h
1
0_0402_5%~D
1
PC149 PC148
2.61K_0402_1%~D
330P_0402_50V7K~D 0.01U_0402_25V7K~D
PR169
2
1 2
11K_0402_1%~D
<8> VSSSENSE
PR170 0_0402_5%~D
Fsw=290KHz
2
1
PC150 180P_0402_50V8J~D
PR171
1 2
2
1 2 1 2
PH2
2
PR172 1K_0402_1%~D PR173 3.74K_0402_1%~D 10KB_0603_ERTJ1VR103J

PC151 0.1U_0603_50V4Z~D
1
VCC_PRM 1 2
PC153 0.22U_0603_10V7K~D
A
PC152 2 1 2 1 A
0.22U_0603_16V7K~D
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU_CORE
LA-5152P
5 4 3 2 1
5 4 3 2 1
Battery Connect/OTP
+3VALWP
DA204U_SOT323~D
DA204U_SOT323~D
DA204U_SOT323~D
DA204U_SOT323~D
D D
2
PD12
PD13
PD14
PD15
@ @ @ @
BATT+
BATT++ CPU
1
PH3 under CPU botten side :
BATT+
PL13
SMB3025500YA_2P CPU thermal protection at 90 +-3 degree C
1 2 BATT++
100P_0402_50V8J~D
Recovery at 50 +-3 degree C
1
1
100P_0402_50V8J~D
1
PC164
PC162
PC161
PC163 1000P_0402_50V7K~D
2
2
0.01U_0402_25V7K~D
2
PR175 Place clsoe to EC pin

1K_0402_5%~D VL VS
/
1 2 BATT_TEMP
BATT_TEMP <31>
BATT_SMD
BATT_SMC
PR176
2
BATT_B/I
1K_0402_5%~D
/x
2
PJPB1 battery connector @ PC165
1
11 .1U_0402_16V7K~D PC166
1
GND 0.1U_0603_25V7K~D
SMART 10
CPU
1
GND PR177
9 9
Battery: 8 8 PR182
7 1K_0402_5%~D 10.7K_0402_1%~D VL
su 2
7 PR184
6 6 2 1
C
1.BAT+ 5 5 1 2 +3VALWP 147K_0402_1%~D C
2
4 1 2
2.BAT+ 4
3 PR178 PR185
3 205K_0402_1%~D
3.ID 2 2 6.49K_0402_1%~D
1
4.B/I 1
p.
PR186
1
8
PJPB1 61.9K_0402_1%~D
5.TS SUYIN_200275MR009F50PZR~D
1 2 EC_SMB_DA1 <31>
OTP_IN OTP_IN+ PD16
1 2 3
P
6.SMD +
PR179 1 OTP_OUT
1 2 MAINPWON <7,40>
100_0402_5%~D OTP_IN- 0
7.SMC VL 1 2 2
-
G
om
1SS355TE-17_SOD323-2
8.GND PR188 PU12A
4
1
150K_0402_1%~D LM358ADR_SO8
9.GND 1 2 PH3
EC_SMB_CK1 <31>
1
100K_0603_1%_TH11-4H104FT
1
PR180
100_0402_5%~D PC168 PR190
2
1000P_0402_50V7K~D 150K_0402_1%~D
2
yc
2
PC169
1U_0603_10V6K~D
m
BATT+
1
PR181
453K_0402_1%~D
//
B VS B
2
1
0.01U_0402_25V7K~D
p:
PR183
499K_0402_1%~D
1
PC167
2
2
tt
8
LM358ADR_SO8
h
5 BATT_IN
P
BATT_OUT 7 +
1 2 0
<31> BATT_OVP
6
-
G
PR187
1
10K_0402_1%~D
4
PU12B
PR189
86.6K_0402_1%
2
LI-3S :13.5V----BATT_OVP=1.126V
A A
BATT_OVP=0.08338*BATT+
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, BATTERY CONN
LA-5152P
5 4 3 2 1
5 4 3 2 1
V ersion Change L ist ( P. I. R . L ist ) Page 1

R equest
Item Page# Title D ate Issue D escription Solution D escription R ev.
O w ner
1 06 Clock Generator 2009/03/03 Benson_Tung Error connection of clock gne I2C. Correct CLK_SMBDATA connect to U1.9 , CLK_SMBCLK connect to U1.10. Rev02 (X01)
D D
2 06 Clock Generator 2009/03/03 Benson_Tung Error connection of CLK_PCIE_WPAN & CLK_PCIE_WPAN# Correct WPAN CLK +/- signal of U1.
Rev02 (X01)
1. Change JCARD1 pin 1 location to prevent cable twist. 1. Modify JCARD1 symbol
3 30 JCARD1 2009/03/03 COMPAL 2. Connect contact current rating is only 0.3 Ampere max. 2. Add +5VALW pin count from 2 to 7 pins. Rev02 (X01)
4 32 Keyboard 2009/03/03 Benson_Tung Keyboard connector Pin 1 location is different with Keyboard module. Correct keyboard pin 1 location to fit keyboard module. Rev02 (X01)
5 32 Power share 2009/03/03 Benson_Tung Power share didn't work. Add power share schematic. Rev02 (X01)
6 12 Cantiga (3 of 7) 2009/03/03 Benson_Tung Error connection of LVDS CLK +/-. 1.Correct LVDS_ACLK+ connect to U4C.C40
2.Correct LVDS_ACLK- connect to U4C.C41
/
3.Correct LVDS_BCLK+ connect to U4C.A37 Rev02 (X01)
4.Correct LVDS_BCLK- connect to U4C.B37
/x
1. +3VALW to +3VS Ttransfer MOS change to U21 SI4800BDY-TI-E3 Rev02 (X01)
7 33 DC/DC Interface 2009/03/03 Benson_Tung Change DC to DC transfer of MOS parts 2. +5VALW to +5VS Ttransfer MOS change to U22 SI4800BDY-TI-E3
3. +1.5V to +1.5VS Ttransfer MOS change to Q45 SI4392DY-T1-E3
su
C C
8 20 FFS 2009/03/03 Compal Add FFS function Add FFS circuit in page 20
Rev02 (X01)
p.
9 4 Power Rail 2009/02/25 Bill_Huang Correct error item. Correct +3VS, +5VS Power consumption. Rev02 (X01)
1.Change Q200.3 net form GND SIGNAL to GND. Rev02 (X01)

10 36 HDMI 2009/03/03 Benson_Tung Error connection of Q200.3 and C1517.1 GND net name. 2.Change C1517.1 net form GND SIGNAL to GND.
om
11 19-23 ICH9M 2009/03/04 Bill_Huang Change ICH to consign P/N. Change U6 P/N: form SA00002G11L to SA00002G12L. Rev02 (X01)
12 35 CRT RGB EA 2009/03/10 Benson_Tung CRT RGB signals EA failed on Rising / Falling time. Change L31~L33 from SM01000AL00 (S SUPPRE_ CHENG-HANN MBK1608301YZF
yc
0603) to SM01000BP0L (BLM18BB050SN1D_0603~D) Rev02 (X01)
13 35 CRT Diode 2009/03/03 Benson_Tung CRT diode forward current is about 1Amp, need to change part to prevent Change D17 from SC1B411D010 ( S DIO RB411DT146 SOT23 ) to SCSB491DA0L
damage. (S SCH DIO RB491D SC59-3 ROHM) Rev02 (X01)
m
1. Update JDP1 symbol.
14 37 Display Port 2009/03/04 Jan_Chang Change JDP1,JLVDS1 and JWOOFER1 symbol. 2. Change JLVDS1 symbol to JAE_FI-G40SB-VF25-DT Rev02 (X01)
35 VGA / LVDS
// 3. Change JWOOFER1 symbol to MOLEX_53398-0271~D
B 26 Sub woofer / Speaker AMP B
15 31 EC_KB926/BIOS/Reed SW 2009/03/04 Benson_Tung Meet Xtal EA spec. 1.Change C479,C481 from 15P_0402_50V8J to 22P_0402_50V8J
Rev02 (X01)
p:
19 ICH9M(1/5)_LAN,HD,SATA,LPC 2.Change C217,C864 from 12P_0402_50V8J to 15P_0402_50V8J

24 Gigabit LAN_RTL8111DL 3.Change C318 from 27P_0402_50V8J to 33P_0402_50V8J
1. SPK_MUTE# change to controlled by HP1_JD or HP2_JD. 1. Add U108 OR gate.
16 25 HD Audio_IDT92HD73C 2009/03/04 Benson_Tung Rev02 (X01)
tt
2. Meet HP EA spec. 2. Change C336, C337, C349, C350 , C354, C355 from 1U_0603 to 2.2U_0805.
17 27 Mini Card_WLAN/WWAN 2009/03/06 Compal To supprot EC TX/RX debug card. Change EC_TX_P80_DATA & EC_RX_P80_CLK connect to JWWAN1 pin 49 & 51 Rev02 (X01)
h
22 30 USB/BlueTooth/Camera 2009/03/06 Compal To prevent antenna effect at E-SATA re-driver. Add R1012 & R1013 place close U40 Pin2 & Pin3
Add R1014 & R1015 place close U40 Pin 21 & Pin22 Rev02 (X01)
23 32 PWROK/BTN/KB/Touch Pad 2009/03/06 Compal Add powershare schematic. Add powershare schematic. Rev02 (X01)
24 33 DC/DC 2009/03/06 Compal 1. To fit power budget 1a. Change U21 & U22 from DMN3030LSS-13 to SI4800BDY Rev02 (X01)
1b. Change U25 SI4800BDY to Q45 SI4329DY
Market / Capacitor 2009/03/06 Compal Due to Janpan produce Y5V no more in the fucture. change C133,C138,C144,C152,C163,C251,C255,C281,C425 from SE000009W0L to Rev02 (X01)
25 SE107475M0L
A
26 23 ICH9M(5/5)_POWER&GND 2009/03/06 Compal ICH coneect to ALW power rail have power wastage at S5 mode Add MOSFET control circuit to reduce ICH power wastage at S5 mode. Rev02 (X01) A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, EE PIR-1
LA-5152P
5 4 3 2 1
5 4 3 2 1

R equest
O w ner
27 24 Gigabit LAN_RTL8111DL 2009/03/06 Compal 1. Prevent B+_BIAS damage Q3 1. Add R1006 (1.5M_0402)
D 2. Correct +LAN_DVDD12 power name 2. Correct C302 & C303 power source from +LAN_VDD12 to +LAN_DVDD12 Rev02 (X01) D
3. Meet LAN EMI test. 3. Pop C873 ~ C880 , SE07168AC0L(S CER CAP 6.8P 50V C NPO 0402)
1. LCD panel need to be turned backlight under this crisis recovery mode. add a gate to OR VGA_PWM and EC_PWM signals Rev02 (X01)
28 35 VGA / LVDS 2009/03/06 Compal 2. when FN+ D is pressed during POST, the LCD will perform the LCD
BIST test and boot to PSA directly
28 21 ICH9M(3/5)_PM,GPIO 2009/03/06 Compal Error net name PBTN_OUT# Correct U6C.R3 net to PBTN_OUT# Rev02 (X01)
29 4 Power Rail 2009/03/06 Compal Correct +1.5V to +1.5VS.DC/DC Interface chip name Form 4800BDY change to SI4392DY Rev02 (X01)
30 25 HD Audio_IDT92HD73C 2009/03/11 Compal Meet audio HP EA spec 1.C354,C355,C336,C337 change to 2.2uF 0805 size X7R Rev02 (X01)
2.Add a series 2k ohm resistor between these caps and the maxim amp U10,U12,.
3.At the pin of the maxim amp U10,U12 Pin 15 and U10,U12 Pin13 add a 220pF
/
cap 0603 NPO to ground.
/x
1. C913,C914,C910,C909 form 6800P_0402_16V7K~D change to
2200P_0402_25V7K~D
31 26 Speaker/Sub woofer AMP 2009/03/11 DELL Gain setting to 20.6dB 2. R907,R902 100K_0402_1% to 280K Rev02 (X01)
3. Delete C951,C952 0.015U_0402_16V7K part.
su
C 4.R900,R905 form 4.87K_0402 change to 43.2K_0402 C
5. U14 form MAX9736B change to MAX9736A
5.R901,R903,R906,R908 form 20K_0402 change to 25.5K_0402
p.
32 34 Screws/LED/Switch 2009/03/11 ME Modify MB drawing. 1. H2 change to NON-PTH 1.6mm. Rev02 (X01)
2,. Delete H13 part
om
1. D20,D21 (PACDN042Y3R_SOT23-3) change to POP.
26 Speaker/Sub woofer AMP 2009/03/11 EMC Follow EMC request. 2. R330 (0_0402), C483 (0.1U_0402) change to POP. Rev02 (X01)
33 31 EC_KB926/BIOS/Reed SW 3. Reserve ESD diode D1505 PJDLC05_SOT23-3 on touchpad
32 PWROK/BTN/KB/Touch Pad 4. Change D1504 part to PJDLC05_SOT23-3.
34 29 ODD/SATA HDD 2009/03/11 ME Follow ME request. JODD1 form MOLEX_47639-4000_NR change to MOLEX_47639-3000_13P Rev02 (X01)
yc
35 26 Speaker/Sub woofer AMP 2009/03/11 COMPAL Band-Pass Filiter,fc=100 Hz, 500Hz, Av=1.45V/V form MAX9737 change to MAX9736A. please see page 26 Rev02 (X01)
m
36 27 Display Port 2009/03/11 COMPAL Meet HDMI test 1. R1518 0_1206 change to non-pop. Rev02 (X01)
2. F1500 1.5A_6V_1206L150PR~D change to POP.
// RF reserve
37 6 Clock Generator CK505 2009/03/13 Compal RF Follow RF request. 1.C1531 part. CLK_14M_ICH need close U1
B B
19 ICH9M(1/5)_LAN,HD,SATA,LPC 2.C1532 part. HDA_BITCLK_AUDIO need close U6
27 Mini Card_WLAN/WWAN 3.C1533 part.PCI_CLK need close U1 Rev02 (X01)
4.c1534 part. CLK_PCI_EC need close U1
p:
31 EC_KB926/BIOS/Reed SW
5. C1535,C1536 part. Reserve 47 pF for +1.5V and +3V
6. C1537, C1538 part. Reserve 47 pF for +1.5V and +3V
7. Move R333 close to U19 and need reserve C1539 part.
tt
38 27 USB/BlueTooth/Camera 2009/03/13 COMPAL Delete E-SATA by-pass R. Delete R1012,R1013,R949,R950,R951,R952,R1014,R1015 part . Rev02 (X01)
h
39 25 HD Audio_IDT92HD73C 2009/03/13 COMPAL Modify Audio control circuit. please see page 25 about U46,U42,U108,U48,U47,U41,Q48 parts. Rev02 (X01)
40 33 DC/DC Interface 2009/03/13 COMPAL For reduce power consumption 1.R344 change to 470K. Rev02 (X01)
2.R346 change to 2M.
41 31 EC_KB926/BIOS/Reed SW 2009/03/14 COMPAL correct SPI_CLK_R non_pop parts. R330,C483 change to non_pop. Rev02 (X01)
42 36 HDMI 2009/03/16 COMPAL Meet HDMI chip spec. X7616831L04 ALT. GROUP R1500 change to pop part.. Rev02 (X01)
PARTS S-(SA00002C610) KAT00
43 11 Cantiga (2 of 7) 2009/04/27 COMPAL Correct HDMI CLK/DATA part B and C connect DDPC_CTRLCOK should be connecting HDMI_C_CLK. =>Port C Rev03 (X02)
A DDPC_CTRLDATA should be connecting HDMI_C_DATA. =>Port C A
SDVO_CTRLCLK should be connecting HDMI_B_CLK. =>Port B

SDVO_CTRLDATA should be connecting HDMI_B_DATA. =>Port B
LA-5152P
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D
44 36 HDMI Conn 2009/04/27 COMPAL Follow EMI request of HDMI L1504,L1505, L1506, L1507 parts change to DLW21SN900HQ2L Rev03 (X02) D
45 37 Display Port 2009/04/27 COMPAL Follow INTEL Design Guide DP AUX circuit. DPB_AUX_SW need connect R1553 (100kohm) to pull down. Rev03 (X02)
DPB_AUX#_SW need connect R1554 (100Kohm) to pull up +3VS.
46 33 DC/DC Interface 2009/04/28 COMPAL Delete +3V_WLAN discharge circuit. Delete +3V_WLAN discharge circuit. Rev03 (X02)
47 28 Mini Card_WPAN / Express 2009/04/28 COMPAL Chagne JEXP1 symbol. JEXP1 change to TAITW_PXPXAE-000LBS2ZZ4N0_NR part. Rev03 (X02)
48 34 Screws/LED/Switch 2009/04/29 COMPAL Original H1 is fan alignment pin , but now cancel this function. Delete H1 part. Rev03 (X02)
49 25 HD Audio_IDT92HD73C 2009/04/29 COMPAL Change EAPD# pull up to (+3VALW). Change R1549.1, U46.5 and U47.5 to +3VALW power Rev03 (X02)
50 23 ICH9M(5/5)_POWER&GND 2009/04/29 COMPAL Change +ICH_V5REF_RUN and SUS resistance R233,R234 form 10_0402_5% change to 100_0402_5% Rev03 (X02)
/
51 32 PWROK/BTN/KB/Touch Pad 2009/04/30 COMPAL follow EMC request. 1.Change L77 and L78 from 120 ohms to 600 ohms bead.
/x
2. Implement ESD diode on cap sensor D1504 PJDLC05_SOT23-3 Rev03 (X02)
3. Implement ESD diode on TP_CLK and TP_DATA for touchpad D1505
PJDLC05_SOT23-3
4. Reserve PES24VS2UT_SOT23-3 ESD diode for speaker connector of D20, D21
su
C C
52 23 ICH9M(5/5)_POWER&GND 2009/04/30 COMPAL Change to PSL parts

24 Gigabit LAN_RTL8111DL D2,D3,D4,D5,D6,D7,D19 form SC1H751H01L S DIO CH751H-40PT SOD-323 Change Rev03 (X02)
35 CRT / LVDS CONN to SCS0340L01L SDMK0340L-7-F_SOD323-2~D
p.
53 07 Penryn(1/3)-AGTL+/ITP-XDP 2009/04/30 COMPAL C19,C21,C463,C935 form S CER CAP 10U 16V Z F(Y5V) 1206 H1.15 change to
30 USB/BlueTooth/Camera SE053106Z8L S CER CAP 10U 10V Z Y5V0805 H1.25 Rev03 (X02)
om
53 07 Penryn(1/3)-AGTL+/ITP-XDP 2009/04/30 COMPAL Modify DC to DC circuit. Modify +3VALW to +3VS and +5VALW to +5VS circuit. Rev03 (X02)
30 USB/BlueTooth/Camera
yc
54 23 ICH9M (5/5) 2009/05/01 COMPAL Reduce ICH power consumption at S5 mode. Populate Q47 and non-populate R1022 Rev03 (X02)
55 30 USB/BlueTooth/Camera 2009/05/01 COMPAL Change E-SATA Output Swing Control TO 1.2x 1.Non-populate R958, R959 2. R953 change to 390 ohm. Rev03 (X02)
m
56 30 USB/BlueTooth/Camera 2009/05/01 COMPAL Solve USB Power Share fail issue. Swap GPIO for USB_DET_DELAY# and EC_SPK_HP_MUTE#. Rev03 (X02)
57 31 EC_KB926/BIOS/Reed SW 2009/05/04 COMPAL

//
Support S5 Power on when CRT insert Pull-up MSEN# from +3VS to +3VALW Rev03 (X02)
B B
58 31 EC_KB926/BIOS/Reed SW 2009/05/04 COMPAL FFS alert signal will change to other GPIO. FFS change int to PIRQ setting from PIRQH to PIRQE Rev03 (X02)
Because original PIRQH is by USB controller used.
p:
59 25 HD Audio_IDT92HD73C 2009/05/04 COMPAL Change package form 0603 to 0402. C1527, C1528, C1529, C1530 Change to 270P_0402_50V7K~D Rev03 (X02)
tt
60 35 VGA / LVDS 2009/05/05 COMPAL Add MOSFET circuit for LVDS converter power Rev03 (X02)
61 24 ICH9M(5/5)_POWER&GND 2009/05/06 COMPAL Modify +3VALW_S5_ICH circuit. R972 form 470Kohm change to 300Kohm. Rev03 (X02)
h
R973 form 1.5Mohm change to 2M ohm.
62 35 VGA / LVDS 2009/05/06 COMPAL Modify Keyboard back light circuit. R928 form 470Kohm change to 300Kohm.
R931 form 1.5Mohm change to 2M ohm. Rev03 (X02)
63 24 Gigabit LAN_RTL8111DL 2009/05/07 COMPAL Modify LAN_IO power circuit. R236 form 470Kohm change to 300Kohm.
R1540 form 1.5Mohm change to 2M ohm. Rev03 (X02)
64 26 Speaker/Sub woofer AMP 2009/06/04 COMPAL For Part source C901, C902, C903, C916, C918, C977 form SE00000NZ0L (S CER CAP 22U 25V
K X7R 1210 H2.5) change to SE00000GF8L (S CER CAP 22U 25V K X5R 1210 H2.5) Rev10 (A00)
A A
65 30 USB/BlueTooth/Camera 2009/06/04 COMPAL due to E-SATA connector doesn't sopport E-SATA detect function. De_pop SB00000960L (S TR SSM3K7002FU 1N SC70-3) Rev10 (A00)
Location: Q11
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66 32 PWROK/BTN/KB/Touch Pad 2009/06/04 Compal Change to DELL AVL Part Change PN: SCA00000A00 (S ZEN ROW PJDLC05 3P C/A SOT23) to
D SCA00000J0L (S ZEN ROW PESD5V2S2UT 3P C/A SOT23 ESD) Rev10 (A00) D
Location: D1504, D1505
67 25 HD Audio_IDT92HD73C 2009/06/04 Compal Solve S0 to S3 pop noise of HP. R1549 change to De_POP. Rev10 (A00)
68 12 CANTIGA((3/7)-VGA/LVDS/TV 2009/06/04 Compal CRT_HSYNC and CRT_VSYNC net name error 1. R116.1 net change to CRT_HSYNC_R Rev10 (A00)
2. R117.1 net change to CRT_VSYNC_R
69 36 HDMI 2009/06/04 Compal Cancel solder mask of by pass 0 ohm 1. Cancel solder mask R1517,R1515,R1514,R1507,R1509,R1508,R1522,R1510 parts. Rev10 (A00)
2. Cancel solder mask R1521 part.
3. Cancel solder mask L26,L71,L72,L27 parts.
70 31 EC_KB926/BIOS/Reed SW 2009/06/04 Compal Change Board ID R312 change to 33Kohm Rev10 (A00)
/
71 2009/06/04 Compal Short by-pass 0 ohm short parts of R2,R4,R3,R5,R6,R7,R8,R10,R12,R42,R43,R16,R17,R18,R19,R21,R23,
R26,R28,R31,R33,R35,R37,R40,R39,R14,R15,R44,R99,R94,R134,R1004,R884,R235, Rev10 (A00)
/x
R942,R248,R250,R285,R911,R912,R913,R914,R291,R918,R921,R919,R920,R915,R916,
R917,R922,R923,R924,R925,R292,293,R292,R293,R294,R298,R295,R296
72 26 Speaker/Sub woofer AMP 2009/06/08 Compal Main speaker AMP gain setting to 13dB 1. Change C908,C912 form 0.22uF to 0.1uF.
su
C 2. Change R903,R908 form 25.5Kohm to 16.5Kohm Rev10 (A00) C
3. Change R901,R906,R902,R907 form 280Kohm to 182Kohm

4. Change R904,R909 form 16.9ohm to 17.8Kohm
5. Change R900,R905 form 43.2K ohm to 11Kohm
p.
73 26 Speaker/Sub woofer AMP 2009/06/08 Compal Modify Main speaker AMP SHDN and mute # control circuit 1. Add D1507, R1558, C1547 diode and RC delay time of MUTE# pin. Rev10 (A00)
om
74 30 USB/BlueTooth/Camera 2009/06/08 Compal Solve E-SATA re-driver issue Chagne U40 from SA00002D80L (S IC PI2EQX3201BZFEX TQFN 36P) to Rev10 (A00)
SA00002YQ0L (S IC PI2EQX3201BLZFEX TQFN 36P)
75 25 HD Audio_IDT92HD73C 2009/06/08 Compal Support unboot pc-beep sound function Pop R1549 Rev10 (A00)
yc
76 27 Mini Card_WLAN/WWAN 2009/06/15 Compal delete short trace of jump Delete R1010,R1011,R911,R912 pin1 and pin2 connect trace. Rev10 (A00)
m
//
B B
p:
tt
h
A A
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Compal Change PR68 from P/N:SD03429438L (294K +-1% 0402) to
+3VALWP/+5VALWP 01/22 Setiing +5VALW OCP to 13.56A X01
D 01 40 Mike SD03433238L (332K +-1% 0402) D
Compal Change PR69 from P/N: SD03424938L (249K +-1% 0402) to

02 40 +3VALWP/+5VALWP 01/22 Setiing +3VALW OCP to 14.26A X01
Mike SD03434038L (340K +-1% 0402)
+1.05V_VCCP/ Compal Change PR81 from P/N: SD03480618L (8.06K +-1% 0402) to
03 41 01/22 X01
+1.8VSP Mike Setiing +1.05V_VCCP OCP to 23A SD03493118L (9.31K +-1% 0402)
04 42 +1.5VSP/+0.75VSP Compal Change PR101 from P/N: SD03413728L (13.7K +-1% 0402) to
01/22 X01
Mike Setiing +1.5VSP OCP to 15.84A SD03410528L (10.5K +-1% 0402)
/
Change PR10 from P/N: SD00103308L (33 +-5% 1206) to
05 38 Compal SD011680A8L (68 +-5% 1206)
DCIN/Precharger 01/22 Common circuit design modify X01
/x
Mike Add PR208 SD011680A8L (68 +-5% 1206) parallel with PR10
Compal HW need to use +1.5VSP PGOOD signal,so need Add PR207 SD03410038L (100K +-1% 0402) between PU8 pin6
06 42 +1.5VSP/0.75VSP 01/22 and PR97 pin 2. X01
Mike to add a pull high resister.
su
C C
Charger 02/09 Compal Populate PR88,take off PR37 and PQ10,change PR175 from X01
07 46 Take off Cells selector function. 47K to SD02810018L(1K +-5% 0402)
Mike
p.
Change PQ34,PQ35,PQ36,PQ37 from
08 43 CPU_CORE 02/24 Compal X01
om
Change CPU_CORE low-side MOSFET (SI4430BDY-T1-E3 1N SO-8) to
Mike SB00000DA00(SI4634DY-T1-E3 1N SO8)
09 43 CPU_CORE 02/24 Compal HW don't need to use VR_TT# signal,so Depopulate PR145 SD03449908L(499 +-1% 0402) X01
Mike depopulate pull high resister.
yc
10 43 CPU_CORE 02/24 Compal
Mike
Change input cap from X7R(85 ℃) to X6S(105℃) Change PC123,PC124,PC125,PC133,PC134,PC135
from (10U 25V M X5R1206 H1.6) to
X01
m
SE153106K8L(10U 25V K X6S 1206 H1.6)
Compal Change PC64 from P/N: SE080224K8L (.22U 10V K X7R 0603)
11 40 +3VALWP/+5VALWP 02/24 Take off Manufacturer:COMPOSTAR from PC64 X01
Mike
// to SE080224M8L (.22U 10V K X7R 0603)
B B
Change PQ45,PQ46 from P/N:

Compal SB000006800 (2N7002W T/R7 1N SOT-323)
12 44 BATTERY CONN 02/24 Take off non-PSL Manufacturer:Panjit
p:
Mike to SB00000B30L (PMF3800SN 1N SC70-3) X01

Change PR29 from P/N:
39 Charger 02/24 Compal X01
tt
13 Take off non-Lead Free material. SD021200D0L (S RES 1W .02 +-1% 2512)
Mike to SD000001F0L (S RES 1W .02 +-1% 2512 50PPM/C)
h
Compal Change PL6 from

14 41 +1.05V_VCCP 02/24 Change choke setting SH00000BQ0L (2.2UH +-20% MPLC1040L2R2 11A) X01
Mike
to SH000009U00 (1UH +-20% FDUE1040D-1R0M=P3 21.3A)
Compal Change PL4,PL5 from
15 40 02/24 Change choke reated current from 11A to 14.2A SH00000BQ0L (2.2UH +-20% MPLC1040L2R2 11A) X01
+3VALWP/+5VALWP Mike
to SH00000CG0L (2.2UH 20% FDVE1040-2R2M=P3 14.2A)
Compal Prevent diode breakdown from battery inrush Change PD3 from SCS00002G00 to SC11N414880
16 38 DCIN / Precharge 03/03 X01
Antony current
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PWR PIR-1
LA-5152P
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Item Page# Title D ate O w ner Issue D escription Solution D escription R ev.
Compal Change part number to L-end Change PD4 part number from X01
17 38 DCIN / Precharge 03/03 SC1A204U000 to SC1A204U00L
Antony
D D
18 40 +3VALWP/+5VALWP 03/03 Compal Change Rtrip resistance to meet OCP setting Change PR68 from 332K ohm to 205K ohm X01
Antony
19 40 +3VALWP/+5VALWP 03/03 Compal Change Rtrip resistance to meet OCP setting Change PR69 from 340K ohm to 243K ohm X01
Antony
20 41 +1.05V_VCCP/ 03/03 Compal Change Rtrip resistance to meet OCP setting Change PR81 from 9.31K ohm to 7.87K ohm
X01
+1.8VSP Antony
21 41 +1.05V_VCCP/ 03/03 Compal Add PC83 220uF Capand Reserve PC99 Cap space
/
Stabilize output voltage to output X01
+1.8VSP Antony
/x
Compal Change PR101 from 10.5K ohm to 6.49K ohm
22 42 +1.5VSP/+0.75VSP 03/03 Change Rtrip resistance to meet OCP setting X01
Antony
su
C
23 43 CPU_CORE 03/03
Compal
Antony
To avoid noise Add PC176 、PC179 0.1uF Cap to +CPU_B+ X01 C
p.
24 43 CPU_CORE 03/03
Compal
Antony
To avoid noise Add PC178 、PC180 2200pF Cap to +CPU_B+ X01
om
Compal Reserve PR194 space X01
25 43 CPU_CORE 03/03 Reserve space for load line shift control
Antony
yc
X01
26 Compal Change PC151 from 0.068uF to 0.1uF
43 CPU_CORE 03/16 To improve transient response
Antony
m
Compal Let difference of CPU Load Line and Change PR173 from 3.57K ohm to 3.74K ohm X01
27 43 CPU_CORE 03/16
Antony Spec smaller than 2mV
//
B
28 44 BATTERY CONN 03/16

Compal
Antony
Disable Hardware CPU OTP circuit Reserve PQ45 、PQ46、PR199、PR200 space X01
B
p:
Compal Changer PR89 from PR89 from 143K ohm to 97.6K ohm
X01
29 39 Charger 03/20 Change 65W CP setting
Antony
tt
+1.05V_VCCP/
h
03/20 Compal For phash margin improved Add PC87 1000pF capacitor between PU13 pin6 and pin7 X01
30 41 +1.8VSP
Antony
+1.05V_VCCP/ Compal Add PC126 10uF capacitor between PU13 pin6 and GND X01
31 41 03/20 For phash margin improved
+1.8VSP Antony
Compal Reserve PQ26,PD19,PD20,PC203,PR115,PR133 space

32 39 Charger 05/06 TI FAE request X02
Antony
A A
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Item Page# Title D ate O w ner Issue D escription Solution D escription R ev.
Compal Change PQ4,PQ5,PQ7 from FDS4435 to
33 39 Charger 05/06 slove PQ5 design margin issue X02
D Antony FDS6675 (SB966750080) D
Compal
34 43 CPU_CORE 05/06 Montavina platform design Change PC136 from 15nF to 22nF X02
Antony
Compal Reserve PQ26,PD19,PD20,PC203,PR115,PR133,PC25

35 39 Charger 05/06 TI FAE request X02
Antony space
Compal X03
36 39 Charger 06/04 TI FAE request Delete PQ26,PD19,PD20,PC203,PR115,PR133
Antony
/
Compal Reserve PR90 0ohm , PR37 0ohm , PC100 space
37 39 Charger 06/04 TI request to reserve protection circuit X03
Antony ,PC25 0.022uF ,PC20 change to 0603 size
/x
38 39 Charger 06/04 Compal Recover a correct component recover correct component PR89 to 97.6K ohm
X03
Antony
su
C C
Compal Change PQ2 from SB502060000 (RHU002N06_SOT323-3)
39 38 DCIN/Precharge 06/04 DELL command X03
Antony to SB50301008L (FDV301N 1N SOT23-3)
p.
om
yc
m
//
B B
p:
tt
h
A A
LA-5152P
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A B C D E

Model Name: KAT00 UMA

BOM P/N: 43169631L01

DA80000E510 PCB 080 LA-5152P

Block Diagram Clock Generator

INTEL Right Front Side. To Card-reader

Mini Card 3 Mini Card 2 Mini Card 1 92HD73C MAX9736A

DC IN To MMB subboard Dig. MIC

Power Sequence ME & LED CHARGER 3V/5V

O MEANS ON X MEANS OFF

1 Reader/BD 1 JSATA1 2 JWLAN1

4800BDY TPS2062ADR SI3456BDY FBM-11-160808-601-T SI4392DY RT9025

0 Ohm +DVDD_AUDIO +LCDVDD

G16 ICH_SMBCLK ICH_SM_DA 200

10 SMBUS Address Read D3 (H)

77 EC_SMB_CK1 100 ohm 7

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

H_STP_CPU# SRCC2_LPR/SATAC_LPR CLK_PCIE_SATA# <19>

13 39 R_CLK_PCIE_WLAN @ R18 1 2 0_0402_5% CB_CLKREQ# R22 1 2 10K_0402_5%

CLK_XTAL_IN 5 X1 CPUT2_ITP_LPR/SRCT8_LPR 64 R_DMI_ICH @ R31 1 2 0_0402_5% SRC0 PCIE_VGA

47 R_MCH_3GPLL# @ R15 1 2 0_0402_5%

GND CR#9 GLAN_CLKREQ# <24>

42 21 @ R44 1 2 0_0402_5% PCI2_TME

0 1 0 200 100 33.3 14.318 96.0 48.0 0103 modify it.

XDP_TMS R58 1 2 54.9_0402_1%

XDP_TRST# R59 1 2 54.9_0402_1%

XDP_TCK R60 1 2 54.9_0402_1%

H_A#18 A[17]# HITM# H_HITM# <10>

H_FERR# A5 C7 H_THERMTRIP# Spacing = 10 / 10 mil

RSVD[10] C21 10U_0805_10V4Z~D

The trace width/space/other

800 200 0 1 0 +CPU_CORE

R70 1 2 100_0402_1% VCCSENSE

R71 1 2 100_0402_1% VSSSENSE

Close to CPU pin

within 500mils. Zo = 55 ohm

Cpu Quad Core, R=1.74K_0402_1% R73

Compal Electronics, Inc.

High Frequence Decoupling

H_D#26 N6 B18 H_A#30

H_D#29 H_D#_28 H_A#_32 H_A#33

H_D#45 AD11 H9 H_HIT# H_HIT# <7>

H_D#54 AD7 L3 H_DINV#1

H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1

H_D#63 AD6 L9 H_DSTBP#0 H_DSTBP#0 <8>

H_REQ#_3 H_REQ#3 <7>

DDR CLK/ CONTROL/

iTPM Host Low = iTPM enable

<18> PM_EXTTS#1 PM_EXT_TS#_1

BC48 AJ35 CL_RST#

BF46 M28 HDMI_C_DATA

R99 2 1 0_0402_5% PM_PWROK_R BH6 H36 MCH_ICH_SYNC#

NC_24 HDA_SYNC HDA_SYNC_NB <19>

Note: All LVDS data

CRT_DDC_CLK PEG_TX_7 HDC_CLK_P_C <36>

R118 CANTIGA ES_FCBGA1329

BB41 SA_DQ_22 DDR_A_DQS[0..7] <17> BC41 SB_DQ_21 SB_DM_6 AP1

DDR_A_D27 SA_DQ_26 SA_DQS_3 DDR_A_DQS4 DDR_B_D26 SB_DQ_25 SB_DQS_0 DDR_B_DQS1

AU13 BD37 BG8 AL46

DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D45 BF5 AV17 DDR_B_MA0

DDR_A_D57 SA_DQ_56 SA_MA_12 DDR_A_MA13 DDR_B_D56 SB_DQ_55 SB_MA_10 DDR_B_MA11

DDR_A_D62 SA_DQ_61 DDR_B_D61 SB_DQ_60