Digital

GATE THE Direction
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Electronics & Communication

Engineering
Digital Circuits
Vishesh Agrawal
(M.Tech VLSI)
(IIT Kharagpur)
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GATE THE Direction Digital Circuits
CONTENTS
CHAPTER I LOGIC GATES 3
CHAPTER II BOOLEAN ALGEBRA 19
CHAPTER III NUMBER SYSTEM 35
CHAPTER IV LOGIC FAMILIES 52
CHAPTER V COMBINATIONAL LOGIC CIRCUITS 68
CHAPTER VI SEQUENTIAL LOGIC CIRCUITS 90
CHAPTER VII ADC & DAC 116
CHAPTER VIII SEMICONDUCTOR MEMORY 128
CHAPTER VIII MICROPROCESSOR 140
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GATE THE Direction Logic Gates
CHAPTER I
LOGIC GATES
INTRODUCTION
Everything in the digital world is based on the binary number system. Numerically, this
involves only two symbols: 0 and 1. Logically, we can use these symbols or we can equate them
with others according to the needs of the moment. Thus, when dealing with digital logic, we
can specify that: 0 =low = false = no
1 = high= true = yes
Using this two-valued logic system, every statement or condition must be either "true"
or "false;" it cannot be partly true and partly false. While this approach may seem limited, it
actually works quite nicely, and can be expanded to express very complex relationships and
interactions among any number of individual conditions.
Representation of logic ‘1’ & ‘0’:

a. Positive logic representation:
If logic ‘1’ represent by higher voltage than logic ‘0’ then its called as positive logic
representation.
eg. 1. Logic ‘1’ ------> +5 V and Logic ‘0’ ------> 0 V
2. Logic ‘1’ ------> 0 V and Logic ‘0’ ------> -5 V
b. Negative logic representation:
If logic ‘0’ represent by higher voltage than logic ‘1’ then its called as negative logic
representation.
eg. 1. Logic ‘0’ ------> +5 V and Logic ‘1’ ------> 0 V
2. Logic ‘0’ ------> 0 V and Logic ‘1’ ------> -5 V
Truth Table:
The table contain all possible combination of inputs and corresponding outputs called as truth
table.
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LOGIC GATES
The flow of digital signals is controlled by transistors in various configurations depending
on the logic family. For most purposes we can imagine that the logic gates are composed of
ideal switches with just two states: OPEN and CLOSED. The state of a switch is controlled by a
digital signal. The switch remains closed so long as a logical 1 (high) signal is applied and switch
is open as logical 0 (low) signals is applied. Logic signals interact by means of gates. The three
fundamental gates AND, OR, and NOT, are named after the three fundamental operations of
logic that they carry out. The AND and OR gates each have two or more inputs and one output.
The output state is determined by the states of the inputs. The function of each gate is defined
by a truth table. The logic gates are:
1. NOT Gate
2. AND Gate
3. OR Gate
4. Exclusive-OR Gate
5. Exclusive-NOR Gate
6. NAND Gate
7. NOR Gate
1. Not Gate: This operation changes a logic level by its complementary i.e. 1 become 0 and 0
become 1. A NOT gate is also called an ‘inverter’.
Truth table: Symbol: Using NAND Gate
A Q= A’
0 1
1 0
 IC 7404 contains six NOT gates.
Propagation delay (tp): Practically the output of the gate is come after some delay called as
propagation delay.
 If we provide feedback from output to input between odd number of inverter

connected in cascade then output become square wave with time period of T= 2.N.t p
Where N: Number of inverters, t p: propagation delay.
Ex. Find the output waveform of output Y of following diagram if propagation delay of inverter
is tp.
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Solution: The output will be flip (1<---> 0) between 0 and 1 after every tp time as shown below:
 Square wave with time period T = 2tp (2.N.tp ,here N=1 ).

𝟏 𝟏
 Frequency of square wave is 𝑭 = = , here F = 1/(2tp)
𝑻 (𝟐.𝑵.𝒕𝒑)
 Its also called as astable multivibrator or ring oscillator (when feedback between odd
number of invert connected in series)
 If feedback between even number of inverter connected in cascade then output is
stable (no change) so its called as bistable multivibrator.
2. AND Gate: The AND Gate operation is performed like multiplication of 1s and 0s. If all inputs
are 1 (high) then only output is 1 (high) otherwise output is 0 (low).
A B Q=A.B
0 0 0
0 1 0
1 0 0
1 1 1
 AND operation is same as connection of switches in series. In below diagram light is on

(i.e. output is logic ‘1’) only in last case when both the switches are close (i.e. input is
logic ‘1’).
1. 2.
3. 4.
 TTL IC’s of AND gates: The IC 7408 contains four two inputs AND gates, IC 747411
contain three 3 inputs AND gates, IC 7421 contains two 4 inputs AND gates.
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3. OR Gate: The OR Gate operation is performed like addition of 1s and 0s. If all inputs are 0
(low) then only output is 0 (low), all other cases output is 1 (high).
A B Q=A+B
0 0 0
0 1 1
1 0 1
1 1 1
1. 2.
3. 4.
 OR operation is same as connection of switches in parallel. In above diagram light is on

(i.e. output is logic ‘1’) when any switches is close (i.e. any input is logic ‘1’).
 IC 7432 contains four 2 inputs OR gates.
4. NAND Gate: The NAND Gate operation output is 0 (low) when all inputs are 1 (high), All
other cases output is 1 (high).
Truth table: Symbol:
A B Q=(A.B)’
0 0 1
0 1 1
1 0 1
1 1 0
 Bubble OR gate is NAND gate
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 NAND & NOR gate is universal gate since any Boolean expression (any gate) can be
construct by only NAND gate.
Implementation of other gates by using only NAND gate:
i. Inverter:
ii. AND:
iii. OR:
iv. NOR:
v. XOR:
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vi. XNOR:
Step for representing any function by NAND only:
1. Write the boolean expression in reduce SOP form and construct logic diagram by AND –
OR gates.
2. For AND gate apply bobble at output and one inverter in series to compensate the effect
of the bubble.
3. For OR gate apply bubble at the input side and inverter in series to compensate the
effect of the bubble.
4. If two inverter in series then neglect them (construct inverter by single NAND gate)
Ex.1: How many two input NAND gate require for boolean function f(A,B,C)=ABC
Solution:
After step 1:
After step 2 & 3:
After step 4:
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Their for 4 NAND gate require.
Ex. 2: Find the number of minimum two input NAND gate require to construct boolean function
f(A,B,C) = (A+B)(B+C)
Solution:
1. Convert in reduce SOP form: f(A,B,C) = (A+B)(B+C) = B + AC

2. Construct logic diagram by AND – OR gates and convert AND , OR, and inverter into
its equivalent NAND form
Their fore for the construction of f(A,B,C)=(A+B)(B+C), we require minimum 3 two input NAND
gates.
 AND – OR is analogous to NAND – NAND representation
5. NOR Gate: The NOR Gate operation output is 1 (high) when all inputs are 0 (low), All other
cases output is 0 (low).
Truth table: Symbol: Using NAND Gate:
A B Q=(A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
 Bubble AND gate is NOR gate:
Implementation of other gates by using only NOR gate:
i. Inverter:
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ii. AND:
iii. OR:
iv. XOR:
v. XNOR:
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Step for representing any function by NOR only:
1. Write the boolean expression in reduce POS form and construct logic diagram by OR -
AND gates.
2. For AND gate apply bobble at input and inverter in series to compensate the effect of
the bubble.
3. For OR gate apply bubble at output side and inverter in series to compensate the effect
of the bubble.
4. If two inverter in series then neglect them (construct inverter by single NOR gate)
 OR - AND is analogous to NOR - NOR representation
Ex.1: Find the number of minimum two input NAND gate require to construct boolean function
f(A,B,C) = (A+B)(B+C)
Solution:
1) f(A,B,C) = (A+B)(B+C) is in reduce POS form.

2) Construct logic diagram by OR– AND gates and convert AND , OR, and inverter into its
equivalent NOR form
Three NOR gate require
6. XOR Gate: The XOR Gate operation output is 1 (high) when odd numbers of inputs are 1
(high), otherwise output is 0 (low).
A B Q=A B
0 0 0
0 1 1
1 0 1
1 1 0
 Act as inverter if one input is logic 1.
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 Act as buffer if one input is logic 0.
 Act as odd parity checker and even parity generator.

o It is odd parity checker science if odd number of logic ‘1’ at input then only
output is logic ‘1’.
o It is even parity generator because number of addition of logic ‘1’ at inputs and
output are always even.
 Equivalent:
Examples:
1. What is output Q?
Here one input to XOR gates is logic ‘1’, so these gates are acts as inverter. Suppose Q1, Q2 are
outputs of first, second output and goes on then
Q1 = A’, Q2 = A, Q3 = A’, Q4 = A,…..
So Q50 = Q = A.
2. What is output Q?
Q1 = A’, Q2 = 1, Q3 = A’, Q4 = 1,…..
So Q50 = Q = 1.
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7. XNOR Gate: For two input XNOR Gate operation output is 1 (high) when both the inputs are
same, otherwise output is 0 (low).
A B Q=AʘB
0 0 0
0 1 1
1 0 1
1 1 0
 Act as inverter if one input is logic 0.
 Act as buffer if one input is logic 1.
 Output of even number of fan-in (input) XOR and XNOR gates are complement to each
other if inputs are same.
 Output of odd number of fan-in (input) XOR and XNOR gates are same to each other if
inputs are same.
Truth table for two (even) fan-in XOR and XNOR gates
A B A B AʘB
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1
Truth table for three(odd) fan-in XOR and XNOR gates
A B C A B C AʘBʘC
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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NOTE:
A B’ = A’ B = (A B )’ = A ʘ B.
(A B C)=(AʘBʘC)
NAND and NOR Gate are universal Gate because by using only NAND or NOR Gate only
we can construct any Boolean logic (other logic Gates). Number of NAND and NOR Gate
require to formation of other Gates.
Logic Gate No. of NAND Gate require No. of NOR Gate require
NOT 1 1
AND 2 3
OR 3 2
NAND 1 4
NOR 4 1
XOR 4 5
XNOR 5 4
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Problems:
1) How many 2-input NOR Gate require to design 2-input XOR gate
A) 3 B) 4 C) 5 D) none
2) How many 2 input NAND gate require for following logic expression Y= AB’C’
A) 4 B) 5 C) 6 D) 7
3) How many 2 input NAND gate require to construct logic expression ABC’+ABC
A) 1 B) 2 C) 3 D) 8
4) How many NOR gate require to construct XNOR gate
A) 3 B) 4 C) 5 D) 6
5) If XY = 0 and (X+Y)’ = 0 then find X ʘ Y
A) 0 B) 1 C) X+Y D) Data insufficient
6) If A.B=0 and A B=0 then (A+B)’ is
A) A’ B) A C) 0 D) Data insufficient
7) Which logic is generated by following ckt
A) OR B) AND C) NOR D) NAND

8) Which of the following gate is redundant?
A) 1 B) 2 C) 3 D) both A and C
9) Find out Y
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A) 1 B) 0 C) A XOR B D) none
10) The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either
A) a NAND or an EX-OR B) an OR or an EX-NOR
C) an AND or an EX-OR D) a NOR or an EX-NOR
11) The logic circuit shown in the given figure can be minimised to
12) Minimum number of NAND gates required to implement XNOR gate

A) 4 B) 5 C) 3 D) 6
13) If the input to the digital circuit consist of a cascade of 20 X-NOR gates is X, then the output
Y is equal to_______.
A) 1 B) 0 C) X D) X’
14) Output Y of the circuit shown in figure is equal to
A) (ABC)’ B) A’+B’+C’ C) (AB)’+(BC)’+A’+C’ D) both A and B
15) The circuit shown in figure is functionally equivalent to
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A) NOR gate B) OR gate C) X-OR gate D) NAND gate
16) How many two inputs X-NOR gates are required to implement three inputs X-NOR gate?
A) 1 B) 2 C) 3 D) 4
17) If AB’ + A’B= Y, then BY’ + B’Y is
A) A B) B C) Y’ D) 0
18) A B A’ is
A) 0 B) B C) B’ D) A
19) The number of minimum 2-inputs NAND gate require to implement A + AB’ + ABC’ is
A) 0 B) 1 C) 4 D) 7
20) If A.B = 0, then A B is
A) A’ + B’ B) 1 C) 0 D) A + B
21) A Boolean function of two variables A and B is define as f(0,0) = f(1,0) = f(1,1) =1 and
f(0,1)=0. The minimum cost solution for realization of f(A,B) by using NOR and OR gates
only. Assume cost of both the gate is one unit and complement of A and B are not
available.
A) 1 unit B) 2 unit C) 3 unit D) 4 unit
22) What are A,B,C respectively, so output Q become zero
A) 0, 1, 0 B) 1, 0, 1 C) 1, 1, 0 D) All
23) Find output Q if B is connected to logic ‘1’
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A) 0 B) A’ C) C D) A’ + C’
24) Find the minimum number of 2-input NAND gate require for implementation of following
logic function
A) 2 B) 3 C) 4 D) 5
25) Find the frequency of square wave generated by following circuit if propagation delay of
each inverter is 20 ns.
A) 50 MHz B) 25 MHz C) 8.33 MHz D) 16.66 MHz

26) How many two-input AND and OR gates are required to realize Y=CD+EF+G
A) 2,2 B) 2,3 C) 3,3 D) none of these
Answers
1. C 2. C 3. B 4. B 5. A 6. A 7. A 8. D 9. C
10. D 11. D 12. B 13. A 14. D 15. C 16. B 17.A 18.C
19.A 20.D 21.B 22.D 23.C 24.B 25.C 26.A
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GATE THE Direction Boolean Algebra
CHAPTER II
BOOLEAN ALGEBRA
Why Boolean simplification:
Boolean algebra finds its most practical use in the simplification of logic circuits. If we
translate a logic circuit's function into symbolic (Boolean) form, and apply certain algebraic
rules to the resulting equation to reduce the number of terms and/or arithmetic operations,
the simplified equation may be translated back into circuit form for a logic circuit performing
the same function with fewer components. If equivalent function may be achieved with fewer
components, the result will be increased reliability and decreased cost of manufacture.
Boolean algebra:
The algebra that can be done with binary states (0 and 1) and the operation perform by logic
gates known as Boolean algebra.
• Commutative composition laws: A+B=B+A
• Associative laws: a) A + (B + C) = (A + B) + C
b) A (BC) = (AB) C
• Distributive law: A (B + C) = AB + AC
• Boolean Algebra rules:
1. A + 0 = A 7. A.A = A
2. A + 1 = 1 8. A.A’ = 0
3. A.0 = 0 9. (A’)’ = A
4. A.1 = A 10. A + AB = A
5. A + A = A 11. A + A’B = A + B
6. A + A’ = 1 12. (A + B)(A + C) = A + BC
• DeMorgan laws: a) (A + B)’ = A’.B’
b) (AB)’ = A’ + B’
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Representation of Boolean Expression:
Any Boolean expression is represented in two forms
1) Sum of product (SOP)
2) Product of sum (POS)
Both these forms are known as Canonical forms i.e. each term contain all the variables.
1. SOP:
Sum-Of-Products, or SOP, Boolean expressions may be generated from truth tables
quite easily, by determining which rows of the table have an output of 1, writing one product
term (minterm) for each row has output logic ‘1’ and finally summing all these product terms.
This creates a Boolean expression representing the truth table as a whole Sum-Of-Products
expressions lend themselves well to implementation as a set of AND gates (products) feeding
into a single OR gate (sum).
 In SOP form each individual term is known as minterm and expression is written as sum of
minterm.
 In SOP representation AND functions are followed by an OR function.
 In SOP form, any variable, A represent as logic 1 (high) and A’ represented as 0 (low).
Example: For given truth table represent output Q in SOP form
(input) (input) (otput) Min

A B Q term
0 0 1 A’B’
0 1 0 A’B
1 0 1 AB’
1 1 0 AB
Solution: SOP form is sum of minterm for which output is logic’1’
Therefore, Q= A’B’+AB’
Since SOP form give logic 1(high) output.
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 SOP form is denoted by 𝑓 = 𝑚 {𝑚𝑖𝑛𝑡𝑒𝑟𝑚𝑠 𝑓𝑜𝑟 𝑤𝑕𝑖𝑐𝑕 𝑜𝑢𝑡𝑝𝑢𝑡 𝑖𝑠 𝑙𝑜𝑔𝑖𝑐 ′1′}

 Above example can be represent in SOP form as f(A,B) = 𝑚 {0,2}
2. POS:
Product-Of-Sums, or POS, Boolean expressions may also be generated from truth tables quite
easily, by determining which rows of the table have an output of 0, writing one sum term for
each row, and finally multiplying all the sum terms. This creates a Boolean expression
representing the truth table as a whole. Product-Of-Sums expressions lend themselves well to
implementation as a set of OR gates (sums) feeding into a single AND gate (product).
 In POS each individual term is called as maxterm and expression is represented as product
of maxterm.
 In POS form, any variable A represent as logic 0 (low) and A’ represented as 1 (high).
Example: For given truth table represent output Q in POS form
(input) (input) (otput) Max

A B Q term
0 0 1 (A+B)
0 1 0 (A+B’)
1 0 1 (A’+B)
1 1 0 (A’+B’)
Solution: POS form is product of maxterm for which output is logic’0’
Therefore, Q= (A+B’) (A’+B’)
Since POS form give logic 0(low) output.
 POS form is denoted by 𝑓 = 𝑀 {𝑚𝑎𝑥𝑡𝑒𝑟𝑚 𝑓𝑜𝑟 𝑤𝑕𝑖𝑐𝑕 𝑜𝑢𝑡𝑝𝑢𝑡 𝑖𝑠 𝑙𝑜𝑔𝑖𝑐 ′0′}

 Above example can be represent in POS form as f(A,B) = 𝑀{1,3}
 Both maxterm and minterm are in Canonical forms
Ex. Represent following truth table in standard SOP and POS form
A B C f(A,B,C)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
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Solution:
SOP: Addition of minterms for which output is logic ‘1’. Here output is logic ‘1’ for following
input combination of A, B and C: (010)2 ---> (2)10, (100)2 --->(4)10, (101)2--->(5)10. So
standard SOP is represented as:
𝒇= 𝒎{𝟐, 𝟒, 𝟓}
POS: Multiplication of maxterms for which output is logic ‘0’. Here output is logic ‘0’ for
following input combination of A, B and C: (000)2 ---> (0)10, (001)2 --->(1)10, (011)2--->(3)10, (110)2
--->(6)10, (111)2--->(7)10 So standard POS is represented as:
𝒇= 𝑴{𝟎, 𝟏, 𝟑, 𝟔, 𝟕}
 From above we conclude that for the same truth table (i.e. sane Boolean function) The
term contain in standard POS form are the all possible term except the term presents in
standard SOP and vice versa.
Ex. Distinguish between min terms and max terms.
Ans: Distinguish between Minterms and Maxterms:
 Each individual term in standard Sum Of Products form is called as minterm whereas
each individual term in standard Product Of Sums form is called maxterm.
 The unbarred letter represent 1’s and the barred letter represent 0’s in min terms,
whereas the unbarred letter represent 0’s and the barred represent 1’s in maxterms.
 Suppose the minterm designation for three variable expression be Y= 𝑚 (1, 3, 5, 7)
Where the represents the sum and ‘m’ stands for minterms.
Decimal number 1 corresponds to binary number 001 and minterm is A’ B’ C
Decimal number 3 corresponds to binary number 011 and minterm is A’BC
Decimal number 5 corresponds to binary number 101 and minterm is A B’ C
Decimal number 7 corresponds to binary number 111 and minterm is ABC.
Therefore Y = A’B’C + A’BC + AB’C + ABC (The sum of all above min term)
 Whereas the Maxterm designation for three variable expression be Y= 𝑀(0, 1, 3, 4)
Where the represents the product and M stands for maxterms.
Decimal 0 means binary 000 and max term is A+B+C
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Decimal 1 means binary 001 and max term is A+B+C’
Decimal 3 means binary 011 and max term is A+ B’ +C’
Decimal 4 means binary 100 and term is A’+B+C
Therefore Y = (A+B+C)(A+B+C’)(A+B’+C’)(A’+B+C) (The product of all above max term)
Ex. Write the given Boolean function f(A,B,C,D)= 𝑚{0,4,5,6,7,9,10,12,13} in POS form
Solution: In POS form contain the term which are absent in SOP form.
Therefore, POS form is, f(A,B,C,D)= 𝑀(1,2,3,8,11,14,15)
Formation of standard SOP form: In SOP form if any variable is absent in any product term then
multiply that product term with (x + x’), where ‘x’ is the missing variable.
 (x + x’) = 1 and multiply by 1 is not affect any Boolean function.
Ex. f(A,B,C) = AB + BC, given Boolean function f(A, B, C) write down in standard SOP form
Solution: In first product term ‘AB’ the variable ‘C’ is missing so multiply it with (C + C’) and in
second product term ‘BC’ the variable ‘A’ is missing so multiply it with (A + A’)
Therefore, f(A, B,C) = AB(C + C’) + BC(A + A’)
= ABC + ABC’ + ABC + A’BC
f(A, B,C) =ABC + ABC’ + A’BC, in standard SOP form.
f(A, B,C) = 𝑚{3,6,7} as in SOP X as 1 and X’ as 0 where X is any variable
as A’BC---> (011)2--->(3)10, ABC’---> (110)2--->(6)10, ABC---> (111)2--->(7)10
Formation of standard POS form: In POS form if any variable is absent in any sum term then
add that sum term with (xx’), where ‘x’ is the missing variable.
 (xx’) = 0 and addition of 1 is not affect any Boolean function.
Ex. f(A,B,C) = (A + B) (B + C), given Boolean function f(A, B, C) write down in standard POS form
Solution: In first sum term ‘(A + B)’ the variable ‘C’ is missing so add it with (CC’) and in second
sum term ‘(B + C)’ the variable ‘A’ is missing so add it with (AA’)
Therefore, f(A, B,C) = (A + B + C C’)(B + C + AA’)
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= ( A + B + C) (A + B + C’) (A + B + C) (A’ + B + C)
f(A, B,C) = (A +B +C) (A + B + C’) + (A’ + B + C), in standard SOP form
f(A, B,C) = 𝑀{0, 1, 4} as in pos X as 0 and X’ as 1 where X is any variable
as (A + B + C)---> (000)2--->(0)10, (A + B + C’)---> (001)2--->(1)10, (A’ + B + C)---> (100)2--->(4)10
Number of possible Boolean expression or switching function:

𝒏
 We can form total 𝟐𝟐 different Boolean functions by using n variables.
𝒏 𝟎
For n=0; 𝟐𝟐 = 𝟐𝟐 = 2. These are {0, 1}.
𝒏 𝟏
For n=1; 𝟐𝟐 = 𝟐𝟐 = 4. These are ,0, 1, A, A’- suppose that variable is A.
𝒏 𝟐
For n=2; 𝟐𝟐 = 𝟐𝟐 = 16. These are ,0, 1, A, A’, B, B’, AB, AB’, A’B, A’B’,(A + B), (A + B’), (A’ + B),
(A’ + B’), AB’ + A’B, A’B’ + AB-.
Ex. How many different Boolean function can be possible by using 5-variable.
𝒏 𝟓
Solution: 𝟐𝟐 = 𝟐𝟐 = 232
Dual Expression: Dual expression is equivalent to writing negative logic for given positive logic.
In dual expression:
 AND and OR Gates are interchange

 NAND and NOR gates are interchange
 Zero and one also interchange
Ex: Q=AB+BC its dual as Qd= (A+B)(B+C).
Self dual function: Some function have their dual expression same as original function. These
function called as self dual function.
Ex: Q=AB+BC+CA its dual as Qd=(A+B)(B+C)(C+A) after simplification it will give same as Q.
i.e. Qd = Q = AB+BC+CA = (A+B)(B+C)(C+A)

𝒏−𝟏
 With N variable, maximum possible self dual function is 𝟐𝟐
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Simplification of Boolean function using k-map:

The k-map method is a systematic method of simplification of Boolean function. It is
graphical representation of Boolean expression in which each cell correspond to unique input
combination and we write 0 or 1 in that cell depend on inputs.
The groups generated are then converted to a Boolean expression by: locating and
transcribing the variable possibility attributed to the box, and by the axiom laws of Boolean
algebra in which if the (initial) variable possibility and its inverse are contained within the same
group the variable term is removed. Each group provides a “product” to create a reduce “sum-
of-products” in the Boolean expression.
For SOP:
 K-map is work on the principle of grey code

 Make least number of group of adjacent one that will cover all the one’s in at least one
group
 Each group contain maximum possible number of adjacent one’s
 In any group the number of adjacent one’s should be of the order of 2 m (i.e. group of 1,
2, 4, 8, 16 etc)
 By grouping 2m number of one’s we reduce the m number of variable in reduce product
term i.e. suppose in k-map of n-variable we group 2m number of one’s then in product
term the available variable will be (n-m) since m number of variable will reduce.
Therefore By grouping two 1’s the one variable will reduce
Four 1’s the two variables will reduce
Eight 1’s the three variables will reduce
Ex. Find the number of literal present in product term form by grouping of 16 one’s in 5-
variable k-map
Solution: Group of 16 one’s i.e. 24 one’s, so we reduce 4 variable in product term, so
number of literal present in product term is (n-m) = (5 - 4) = 1
 For n-variable Boolean function the k-map has 2n cell.
 k-map is use to reduce Boolean function upto six variable. For more than six variable
Boolean function Quine–McCluskey Tabular Method is use for reduction.
For POS:
 For generation of reduce POS form replace ‘1’ by ‘0’
Two variable k-map:
 Total number of cell is 2n = 22 =4. Each cell contain two literal.
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 Where A is MSB and B is LSB
Three variables k-map:
 Where A is MSB and C is LSB
Four variables k-map:
 Where A is MSB and D is LSB
Ex. Minimize the given Boolean function f(A,B,C) = 𝑚(1,3,5)
Solution:
Therefore, f(A,B,C) = A’C + B’C
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Ex. Minimize the given Boolean function f(A,B,C,D) = 𝑚(0,1,2,6,8,10,11,12)
Solution:
Therefore, f(A,B,C,D) = A’B’C’ +

AC’D’ + A’CD’ + AB’C
Ex. Minimize the given Boolean function f(A,B,C,D) = 𝑀{0,1,2,5,6,7,8,9,10,11,14}
Solution:
Therefore, f(A,B,C,D) = (B+C)(C’+D)(A’+B)(A+B’+D’)
Ex. Minimize the given Boolean function f(A,B,C,D) = 𝑀{0,1,9,10,11,14} in POS and SOP form
Solution: f(A,B,C,D) = 𝑀 0,1,9,10,11,14 = 𝑚{2,3,4,5,6,7,8,12,13,15}
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Use of don’t care condition

 Don’t care can be use as one or zero, no need to cover all the don’t care term
 Use as one if it is increase numbers of one in group without increasing the number of
group, otherwise use it as zero.
Fig. a Fig. b
Don’t care are only used to make the pair quad etc. If all the minterm or maxterm can be
covered by making pair without using don’t care term then we should not use don’t care term.
As shown in fig. a and fig. b both have same pairing even in fig. b there’s extra don’t care is
available.
Ex: Solve following k-map
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Solution:
Q = AB’ + B’D Q = B’D
 For k- map in fig. a use don’t care as one because it increase the numbers of one in group.
 For k- map in fig. b use don’t care as zero because it increase the numbers of group.
Ex. Minimize the given Boolean function f(A,B,C,D) = 𝑚(0,1,2,6,11,12) + 𝑑{5, 7,8}.
Solution:
f(A,B,C,D) = A’B’C’ + AC’D’ + A’CD’ + AB’CD
Implicants (I): All minterm of k-map are called implicants. ie. numbers of ‘1’ in k-map is nothing
but numbers of implecants.
Prime Implicant (PI): The all the product term in any reduced expression of k-map are called as
prime Implicant.
Essential prime Implicant (EPI): Prime Implicant which is present in all reduce expression is
called essential prime Implicant.
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Selective prime Implicant (SPI): The prime implicant rather than Essential prime implicant are
called as selective prime implicant.
Literal: Each occurrence of variable or its complement in expression is called as literal.
Ex. Find the implicant, PI, EPI and literal for f(A,B,C) = 𝑚{0,2,4,5,7} .
Solution:
AB A’C’ B’C’ C AB
C 1 1 1 1 1 1
1 1 1 1
AC
Q = A’C’ + AC + B’C’ Q = A’C’ + AC + AB’;
Here two expressions for output are possible as shown above.
1. Here number of minterm in k-map is 5 so number of Implicants are 5. These are A’B’C’,
A’BC’, AB’C’, ABC, AB’C.
2. Here 4 different reduce combinations are possible so numbers of prime Implicants are also
4. These are A’C’, AB’, B’C’, AC.
3. Here two prime Implicants are common in both output expression of ‘Q’, so essential
prime Implicants are 2. There are A’C’ and AC.
4. Here total 6 variable or their compliment present in both of the expression so number of
literal are 6.
 K-map may have different reduce solution for the given function (In the above
example we having 2 different solution.) i.e. k-map solution not necessary to always
unique.
Note:
𝒏
With N variable, maximum possible distinct Boolean function can be made are 𝟐𝟐
𝒏−𝟏
With N variable, maximum possible self dual function is 𝟐𝟐
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Problems:
1) How many self dual Boolean functions will possible for 3 variable functions?
A) 16 B) 3 C) 256 D) none
2) Reduce the k-map
A) A+ B’ + D’ B) A + B +D’ C) A + B’ + D D) B’ + D’
3) Simplify the logic expression Y(ABCD) = m(0,2,3,6,8,10,14)

A) B’D’ + A’B’C + A’CD’ B) B’D’ + A’B’C + CD’
C) B’D’ + B’C’D’ + CD’ D) none
4) A function with don’t care condition is as follows f (A,B,C,D) = m(3, 4, 5, 7, 9, 13, 14, 15 )
+ dc(10) The minimized expression for this function is
A) A’BC’+ABC+A’CD+AC’D B) ABC+A’BC’+AD+CD
C) A’BC’+ABC+A’CD+AD D) none
5) A function with don’t care condition is as follows f (A,B,C,D) = m(3, 4, 5, 7, 9, 13, 14, 15 )
+ dc(11) The minimized expression for this function is
A) A’BC’+ABC+A’CD+AC’D B) ABC+A’BC’+AD+CD
C) A’BC’+ABC+A’CD+AD D) none
6) A four-variable switching function has minterms m7 and m8. If the literals in these
minterms are complemented, the corresponding minterm numbers are
A) m7 and m8 B) m9 and m6 C) m2 and m0 D) m9 and m0
7) Simplify the following Boolean expressions:
f(A,B,C)= ABC +ABC’ +AB’C +AB’C’ +A’BC +A’BC’ +A’B’C + A’B’C’;
A) A B) 1 C) 0 D) BC
8) In 5- variable k-map how many literals will present in prime Implicant form by group of
four 1’s
A) 1 B) 2 C) 3 D) 4
9) The output of logic circuit is HIGH only when A and B both are low and C and D both are
high. Then output logic function is
A) (AB)’+CD B) (AB)’CD C) (A’B’)+CD D) (A’B’)CD
10) Reduce the logic expression AB+A’B+AB’+A’B’
A) A B) B C) 1 D) 0
11) Write following logic expression in canonical form XY+XYZ+XYZ’
A) XYZ+XYZ’ B) XY C) XYZ+XYZ’+XY’Z D) Z
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12) What is dual of Y= AB + BC

A) (A’+B’)(B’+C’) B) (A+B)(B+C) C) AB + BC D) (A+B)’(B+C)’
13) The simplification of the Boolean expression (ABC) + (ABC) is
A) 0 B) 1 C) A D) BC
14) The Boolean expression A. B + A. B + A. B is equivalent to
A) A + B B) A.B C) A’ + B’ D) A’.B’
15) When simplified with Boolean Algebra (x + y)(x + z) simplifies to
A) x B) x + x(y + z) C) x(1 + yz) D) x + yz
16) Karnaugh map is used for the purpose of
A) Reducing the electronic circuits used.
B) To map the given Boolean logic function.
C) To minimize the terms in a Boolean expression.
D) To maximize the terms of a given a Boolean expression.
17) Simplify the Boolean expression F = C(B + C)(A + B + C).
A) C B) A C) A+B D) B+C
18) Simplify the Boolean expression 𝐹 = 𝑋𝑌 + 𝑋𝑌𝑍 + 𝑋 (𝑌 + 𝑋𝑌 )
A) XY B) X+Y+Z C) 0 D) 1
19) In the logic equation A A + BC + C + B C + A + BC A + BC + AC = 1, if C = A, then
A) A+B=1 B) A’+B=1 C) A+B’=1 D) A=1
20) Which one of the following Boolean expression is NOT correct?
A) X + Y = X Y B) X + Y = X Y C) X Y = X + Y D) X + Y = X Y
21) Boolean function can be expressed
A) as sum of maxterm or product of minterm
B) as product of maxterm or sum of minterm
C) partly as product of maxterm and partly as sum of minterm
D) partly as sum of maxterm and partly as product of minterm
22) For the truth table given in figure, the Boolean expression is
Input Output
X Y Z P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
A) p = x⨁y⨁z B) p = x⨁y⨁z
C) p = x y⨁z + x(y⨁z) D) both A and B
23) The Boolean expression (A+B)(A’+B’) is equivalent to a two-input
A) NAND gate B) NOR gate C) X-OR gate D) X-NOR gate
24) The total number of Boolean function that can be constructed for n Boolean variables is
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𝑛
A) n B) 2n C) (2n)n D) 22
25) Number of product terms in the minimized sum of product expression obtained through
the following K map is
00 01 11 10
00 1 0 0 1
01 0 X 0 0
11 0 0 X 1
10 1 0 0 1
A) 2 B) 3 C) 4 D) 5
26) Minterm (sum of product ) expression for a Boolean function is given as

f(A,B,C)=∑m(0,1,2,3,5,6). Where A is MSB and C is LSB. The minimized expression for the
function is
A) A+(B⨁C) B) (A⨁B)+C C) A’+(B⨁C) D) (ABC)’
27) Minterm (sum of product ) expression for a Boolean function is given as
f(A,B,C)=∑m(0,1,2,3,4,5,6) + d(7). Where A is MSB and C is LSB. The minimized expression
for the function is
A) A’+B’+C’ B) A’B’C’ C) 0 D) 1
28) The product of all the max terms of a given Boolean function is always equal to______
A) Two B) Complement of function C) One D) Zero
29) In an n-variable K map combining 16 cells containing 1’s as a single group will result a
term of _______ literals.
A) 4 B) n-4 C) n+4 D) 4n
30) In an n-variable K map combining 8 cells containing 1’s as a single group will reduce the
number of variable in prime Implicant is
A) 3 B) n-3 C) n-8 D) 8
31) The complement of the function F=(A+B’) (C’+D) (B’+C) is
A) A’B+CD’+BC’ B) AB’+C’D+B’C C) AB’+CD’+BC D) AB+BC+CD
32) The sum of all the min terms of a given Boolean function is equal to_______
A) zero B) one C) Two D) complement of function
33) What is the other canonical form of the given equation F(x,y,z)=∑m(0,1,2,3,4,5,6,7)
A) F(x,y,z)=∏M(0,1,2,3,4,5,6,7) B) F(x,y,z)=∏m(0,1,2,3,4,5,6,7)
C) F(x,y,z)=∑M(0,1,2,3,4,5,6,7) D) Does not exist
34) Simplify the following Boolean expressions:
f(A,B,C,D,E)= (A’+B+C’)(A’+B+C)(C+D)(C+D+E)
A) (A’+B)(C+D) B) (A’+B)(C+D) (C+E)
C) (A’+B)(C+D)(C+D+E) D)(A’+B)(C+D+E)
35) Find the dual of ABCD’+AB’C’D+AB’C’D’.
A) (A+B+C +D’) + (A+B’+C’ +D) + (A+B’+C’ +D’) B) (A+B+C +D’)(A+B’+C’ +D)(A+B’+C’ +D’)
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C) (A’+B’+C’ +D) + (A’+B+C +D’) + (A’+B+C +D) D) (A’+B’+C’ +D)(A’+B+C +D’)(A’+B+C +D)
36) Find the complement of A+*(B+C’)D+E’+F
A) A’*(B’C + D’)E+ + F’ B) A’*(B’C + D’E+ + F’ C)A’*(B’C + D’)E + F’+ D) A’*(B’C + D’)E+ F’
37) The dual of the complement of a certain Boolean expression is given by ABC +D’E +BC’E.
Find the expression.
A) A’B’C’ + DE’+ B’CE’ B) ABC + D’E+ BC’E
C) (A’+B’+C’)(D+E’)(B’ + C + E’) D) (A+B+C)(D’+E)(B + C’ + E)
Answers:
1. A 2. D 3. B 4. A 5. B 6. A 7. B 8. C 9. D
10. C 11. A 12. B 13. B 14. A 15. D 16. C 17. A 18. C
19. C 20. D 21. B 22. D 23. C 24. D 25. A 26. C 27. D
28. D 29. B 30. A 31.A 32. B 33. D 34. A 35.B 36.C
37.A
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GATE THE Direction Number system
CHAPTER III
NUMBER SYSTEM
NUMBER SYSTEMS
The base or radix ‘r’ of the number system is representing the number of different symbol
used in that number system.
Using ‘n’ digit in number system of radix ‘r’ we can make rn different number.
Eg. In decimal r =10 when
n=1 total different possible number are 101 i.e. 10 there are 0 to 9.
n=2 total different possible number are 102 i.e. 100 there are 00 to 99.
The range of number is from 0 to rn - 1.
The number system having base-r and n digits, the value of that number in decimal is calculated
as: (An-1……..A2A1A0)r = (An-1×rn-1) +…… +(A2×r2 ) + (A1×r1 ) +(A0×r0 ).
Binary numbers:
Binary number has radix 2 therefore it use 2 symbols namely 0 and 1. It is represented as:
(abc)2 = a × 22 + b × 21 + c × 20
Each digit is known as a bit and can take only two values 0 and 1. The left most bit is the
Highest-order bit and represent the most signiﬁcant bit (MSB) while the lowest-order bit is the
least signiﬁcant bit (LSB).
Nibble have 4-bit and Byte have an 8-bit
r’s and (r-1)’s compliment of the number

(r-1)’s compliment of any number N having base ‘r’ and number of digits ‘n’ is given by
(rn -1) – N (Answer is in decimal).
 Short cut: (r-1)’s compliment can be find by subtracting given number by highest
possible number of given digit.
Ex. Find the 7’th compliment of (432)8
Solution:
 Highest possible number of 3-digit in octal is (777)8

 7’th compliment (i.e. r-1th compliment) of (432)8 is (777)8 – (432)8 = (345)8
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r’s compliment of any number N having base ‘r’ and number of digits ‘n’ is given by
rn –N (Answer is in decimal).
 r’s complicate = (r-1)’s complicate + 1
Ex. Find the 9th and 10th compliment of (4581)10
Solution:
 Highest possible number of 4-digit in decimal is (9999)10

 9th compliment (i.e. r-1th compliment)of (4581)10 is (9999)10–(4581)10= (5418)10
 10th compliment = 9th compliment +1 (since rth compliment = (r-1)th compliment
+1) therefore 10’s compliment of (4581)10 is (5418)10+1=(5419)10
1-complement
The 1-complement of a binary number is obtained just changing each 0 to 1 and each 1 to 0:
Binary number 1 0 1 1 1 0 1 0
↓↓↓↓↓↓↓↓
1-complement 0 1 0 0 0 1 0 1
2- complement:
See from the left side and write down the digit as it is till first 1’s come and after that start
replacing 0’s to 1 and 1’s to 0.
2’s compliment = 1’ compliment + 1.
Eg. 110010 2’s compliment 001110
101010 2’s compliment 010110
100000 2’s compliment 100000
Binary number system:

Number representation in binary number system can be of three types
1. Sign magnitude representation.
2. 1’s compliment
3. 2’s compliment
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1. Sign magnitude representation:
In sign magnitude representation MSB bit is use for representing the sign of the number (‘0’
indicate ‘+’ number and ‘1’ indicate negative number) and other bits are used to represent the
magnitude of the number.
Eg: 1) -9 Sign magnitude 11001
2) +9 Sign magnitude 01001
2. 1’s compliment:
In 1’s compliment representation, the positive number is represented as simple as we

represent any binary number magnitude and for representation of negative number we take 1’s
compliment of magnitude representation of that number.
Eg: 1) -9 1’s compliment 10110
2) +9 1’s compliment 01001
3. 2’s compliment:
In 2’s compliment representation, the positive number is represented as simple as we

represent any binary number magnitude and for representation of negative number we take 2’s
compliment of magnitude representation of that number.
Eg: 1) -9 2’s compliment 10111
2) +9 2’s compliment 01001
Sign magnitude and 1’s compliment representation assign different value for 0 and -0,
But 2’s compliment assign same value for 0 and -0 so that 2’s compliment
representation use in the processing unit.
1’s compliment and sign magnitude range from – (2n-1 -1) to (2n-1 -1).
2’s compliment range from – 2n-1 to (2n-1 -1).
Range of 2’s compliment is one more than 1’s compliment and sign magnitude because
it has only one representation for 0.
For all the representation (sign magnitude, 1’s compliment and 2’s compliment) the
MSB is ‘1’ for negative number and ‘0’ for positive number.
1’s compliment of 1’s compliment of any number is same number
2’s compliment of 2’s compliment of any number is same number
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Input Sign magnitude 1’s compliment 2’s compliment

000 0 0 0
001 1 1 1
010 2 2 2
011 3 3 3
100 -0 -3 -4
101 -1 -2 -3
110 -2 -1 -2
111 -3 -0 -1
In above table n=3 so for sign magnitude and 1’s compliment range is from -3 to 3 as seen in
table and for 2’s compliment range is from -4 to 3.
Step for addition and subtraction in 2’s compliment number system:
1. Convert the number into decimal equivalent.

2. Perform the operation that ask
3. Convert back the result in 2’s compliment form
Ex. 1: X = 0101 and Y = 1001 are two 4-bit binary numbers represented in two’s complement
format. The sum of X and Y represented in two’s complement format using 5 bits is
Solution:
1. Convert the given number in decimal form X= (0101)2 = (5)10 and Y = (1001)2 = (-7)10
2. Perform the given operation X + Y = 5-7 = (-2)10
3. Convert back the result in 2’s compliment form. (-2)10 = (11110)2
Ex. 2: X = 11101 and Y = 11001 are two 5-bit binary numbers represented in two’s complement
format. Find (X-Y) and represented in two’s complement format using 6 bits is
Solution:
1. Convert the given number in decimal form X= (11101)2 = (-3)10 and Y = (11001)2 = (-7)10
2. Perform the given operation X - Y = (-3) – (-7) = (4)10
3. Convert back the result in 2’s compliment form. (4)10 = (000100)2
Conversion
Binary-to-Decimal Conversion
The decimal equivalent of the binary number (1101.0101)2 is determined as follows:
• The integer part = 1101
• The decimal equivalent = 1 × 20 + 0 × 21 + 1 × 22 + 1 × 23 = 1 + 0 + 4 + 8 = 13
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• The fractional part = .0101
• Therefore, the decimal equivalent = 0 × 2−1 + 1 × 2−2 + 0 × 2−3 + 1 × 2−4
= 0 + 0.25 + 0 + 0.0625 = 0.3125
• Therefore, the decimal equivalent of (1101.0101)2 = (13.3125)10
Octal-to-Decimal Conversion
The decimal equivalent of the octal number (721.25)8 is determined as follows:
• The integer part = 721
• The decimal equivalent = 1 × 80 + 2 × 81 + 7 × 82 = 7 + 24 + 64 = 465
• The decimal equivalent = 2 × 8−1 + 5 × 8−2 = 0.328
• Therefore, the decimal equivalent of (137.21)8 = (465.328)10
Hexadecimal-to-Decimal Conversion
The decimal equivalent of the hexadecimal number (CAB.2F)16 is determined as follows:
• The integer part = CAB
• The decimal equivalent = 11 × 160 + 10 × 161 + 12 × 162 = 3243
 Since A=10, B=11, C=12, D=13, E=14, F=15.
• The fractional part = 2F
• The decimal equivalent = 2 × 16−1 + 15 × 16−2 = 0.1835
• Therefore, the decimal equivalent of (CAB.2F)16 = (3243.1835)10
Decimal-to-Binary Conversion
For the integer part, the binary equivalent can be found by successively dividing the
integer part of the number by 2 and recording the remainders until the quotient becomes ‘0’.
The remainders written in reverse order constitute the binary equivalent. For the fractional
part, it is found by successively multiplying the fractional part of the decimal number by 2 and
recording the carry until the result of multiplication is ‘0’. The carry sequence written in forward
order constitutes the binary equivalent of the fractional part of the decimal number. If the
result of multiplication does not seem to be heading towards zero in the case of the fractional
part, the process may be continued only until the requisite number of equivalent bits has been
obtained. This method of decimal–binary conversion is popularly known as the double-dabble
method.
39
For Example: Find the binary equivalent of (15.425)10.
Sol: The integer part = 15
Divisor Dividend Remainder
2 15 —
2 7 1
2 3 1
2 1 1
— 0 1
• The binary equivalent of (15)10 is therefore (1111)2
0.425 × 2 = 0.85 i.e. carry is 0
0.85 × 2 = 1.7 i.e. carry is 1
0.7 × 2 = 1.4 i.e. carry is 1
0.4 × 2 = 0.8 i.e. carry is 0
0.8 × 2 = 1.6 i.e. carry is 1
0.6 × 2 = 1.2 i.e. carry is 1
• The binary equivalent of (0.425)10 = (.011011)2
• Therefore, the binary equivalent of (15.425)10= (1111.011011)2
Decimal-to-Octal Conversion
The process of decimal-to-octal conversion is similar to that of decimal-to-binary
conversion. The progressive division in the case of the integer part and the progressive
multiplication while working on the fractional part here are by ‘8’ which is the radix of the octal
number system. Again, the integer and fractional parts of the decimal number are treated
separately.
For Example: Find the octal equivalent of (77.25)10
40
8 77 —
8 9 5
8 1 1
— 0 1
• The octal equivalent of (73)10 = (115)8
• The fractional part = 0.25
0.25 × 8 = 2.0 i.e. carry is 2
0 × 8 = 0.0 i.e. carry is 0
• The octal equivalent of (0.75)10 = (.20)8
• Therefore, the octal equivalent of (77.25)10= (115.20)8
Decimal-to-Hexadecimal Conversion
The process of decimal-to-hexadecimal conversion is also same. Since the hexadecimal number
system has a base of 16, the progressive division and multiplication factor in this case is 16.
For Example: Find the hexadecimal equivalent of (95.50)10
16 95 —
16 5 15 i.e. F
— 0 5
• The hexadecimal equivalent of (95)10 = (5F)16
• The fractional part = 0.25
0.50 × 16 = 8.0 i.e. carry is 8
0 × 16 = 0.0 i.e. carry is 0
• Therefore, the hexadecimal equivalent of (82.25)10 = (5F.80)16
Binary–Octal and Octal–Binary Conversions

An octal number can be converted into its binary equivalent by replacing each octal digit with
its three-bit binary equivalent. We take the three-bit equivalent because the base of the octal
41
number system is 8 and it is the third power of the base of the binary number system, i.e. 2. All
we have then to remember is the three-bit binary equivalents of the basic digits of the octal
number system. A binary number can be converted into an equivalent octal number by splitting
the integer and fractional parts into groups of three bits, starting from the binary point on both
sides. The 0s can be added to complete the outside groups if needed.
Ex. Find the binary equivalent of (136.27)8
Solution:
• The given octal number = (136.27)8
• The binary equivalent = (001 011 110.010 111)2
• Any 0s on the extreme left of the integer part and extreme right of the fractional part of the
equivalent binary number can be omitted. Therefore, (001011110.010111)2 =
(1011110.010111)2
• The given binary number = (1110100.0100111)2
• (1110100.0100111)2
= (1 110 100.010 011 1)2
= (001 110 100.010 011 100)2
= (164.234)8
Ex. Find the octal equivalent of (11010001.0101011)2
Solution:
• The given binary number = (11010001.0101011)2
• (11010001.0101011)2 = (11 010 001.010 101 1)2 = (011 010 001.010 101 100)2 = (321.254)8
Hex–Binary and Binary–Hex Conversions

A hexadecimal number can be converted into its binary equivalent by replacing each hex digit
with its four-bit binary equivalent. We take the four-bit equivalent because the base of the
hexadecimal number system is 16 and it is the fourth power of the base of the binary number
system. All we have then to remember is the four-bit binary equivalents of the basic digits of
the hexadecimal number system. A given binary number can be converted into an equivalent
hexadecimal number by splitting the integer and fractional parts into groups of four bits,
starting from the binary point on both sides. The 0s can be added to complete the outside
groups if needed.
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Ex. Find the binary equivalent of (1FB.ACC)16
Solution
• The given hex number = (1FB.ACC)16
• The binary equivalent = (0001 1111 1011.1010 1100 1100)2
• The 0s on the extreme left of the integer part and on the extreme right of the fractional part
can been omitted so (000111111011.101011001100)2 = (111111011.1010110011)2
Ex. Find the hex equivalent of (11011001110.011011101)2.
•(11011001110.0110111011)2 =(110 1100 1110.0110 1110 11)2 = (0110 1100 1110.0110 1110
1100)2 = (6CE.6EC)16
Hex–Octal and Octal–Hex Conversions

For hexadecimal–octal conversion, the given hex number is firstly converted into its binary
equivalent which is further converted into its octal equivalent. An alternative approach is firstly
to convert the given hexadecimal number into its decimal equivalent and then convert the
decimal number into an equivalent octal number. The former method is definitely more
convenient and straightforward. For octal–hexadecimal conversion, the octal number may first
be converted into an equivalent binary number and then the binary number transformed into
its hex equivalent. The other option is firstly to convert the given octal number into its decimal
equivalent and then convert the decimal number into its hex equivalent. The former approach
is definitely the preferred one. Two types of conversion are illustrated in the following example.
Ex. Find the octal equivalent of (1F.B4)16
Solution
• The given hex number = (1F.B4)16.
• The binary equivalent = (0001 1111.1011 0100)2 = (011 111.101 101)2 = (37.55)8
Ex. Find the hex equivalent of (734.641)8
• The octal number (734.641)8 = (111 011 100.110 100 001)2 = (0001 1101 1100.1101 0000
1000)2 =(1DC.D08)16
43
Ex. The 7’s complement of a certain octal number is 1354. Determine the binary and
hexadecimal equivalents of that octal number.
Solution
• The 7’s complement is (1354)8 , Therefore, the octal number is (7777)8 - (1354)8 = (6423)8
• The binary equivalent is (110 100 010 011)2
• The hex equivalent is (1101 0001 0011)2 = (D13)16
Binary–Gray Code Conversion

A given binary number can be converted into its Gray code equivalent by going through the
following steps:
1. Begin with the most significant bit (MSB) of the binary number. The MSB of the Gray
code equivalent is the same as the MSB of the given binary number.
2. The second most significant bit, adjacent to the MSB, in the Gray code number is
obtained by XOR of MSB and the second MSB of the binary number.
3. The third most significant bit, adjacent to the second MSB, in the Gray code number is
obtained by XOR of second MSB and the third MSB in the binary number
4. The process continues until we obtain the LSB of the Gray code number by the XOR of
the LSB and the next higher adjacent bit of the binary number.
5. Let an n-bit binary number Bn-1 Bn-2…… B0 and its equivalent gray code is Gn-1 Gn-2…… G0,
with Bn-1 and Gn-1 are MSB. The gray code is
Gn-1 = Bn-1. Gn-2 = 𝐁n-1⊕ 𝐁n-2 Gn-3 = 𝐁n-2⊕ 𝐁n-3 ……. G0 = 𝐁1⊕ 𝐁0
The conversion process is further illustrated with the help of an example showing step-by-step
conversion of (1011)2 into its Gray code equivalent:
Binary code 1011 Gray code 1- - -
Binary code 1011 Gray code 11- -
Binary code 1011 Gray code 111-
Binary code 1011 Gray code 1110
 MSB of binary and gray code is always same.

 Gray code is non-weighted code.
 In gray code, consequent number is change by only one bit.
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Gray Code–Binary Conversion

A given Gray code number can be converted into its binary equivalent by going through the
following steps:
1. Begin with the most significant bit (MSB). The MSB of the binary number is the same as
the MSB of the Gray code number.
2. The bit next to the MSB (the second MSB) in the binary number is obtained by XOR of
the MSB and second MSB in the Gray code number.
3. The third MSB in the binary number is obtained by XOR of MSB to the third MSB in the
Gray code number.
4. The process continues until we obtain the LSB of the binary number.
5. Let an n-bit binary number Bn-1 Bn-2…… B0 and its equivalent gray code is Gn-1 Gn-2…… G0,
with Bn-1 and Gn-1 are MSB. The gray binary code is
Bn-1 = Gn-1. Bn-2 = 𝑮n-1⊕ 𝐆n-2 Bn-3 = 𝑮n-1⊕ 𝐆n-2⊕ 𝐆n-3 ……. B0 = 𝑮n-1⊕ 𝐆n-2 ⊕ 𝐆n-3
……. ⊕ 𝐆1⊕ 𝐆0
The conversion process is further illustrated with the help of an example showing step-by-step
conversion of the Gray code number 1110 into its binary equivalent:
Gray code 1110 Binary code 1- - -
Gray code 1110 Binary code 10 - -
Gray code 1110 Binary code 101
Gray code 1110 Binary code 1011
 The Gray code is used in the transmission of digital signals as it minimizes the
occurrence of errors.
 The Gray code is preferred over the straight binary code in angle-measuring devices.
Use of the Gray code almost eliminates the possibility of an angle misread, which is
likely if the angle is represented in straight binary.
 The Gray code is used in Karnaugh maps, a graphical technique used for minimization of
Boolean expressions.
 The use of Gray codes to address program memory in computers minimizes power
consumption. This is due to fewer address lines changing state with advances in the
program counter.
 Gray codes are also very useful in genetic algorithms
Binary Coded Decimal:

The binary coded decimal (BCD) is a type of binary code used to represent a given decimal
number in an equivalent binary form. The BCD equivalent of a decimal number is written by
replacing each decimal digit in the integer and fractional parts with its four-bit binary
45
equivalent As an example, the BCD equivalent of (15.46)10 is written as (0001 0101.0100

0110)BCD.
BCD-to-Binary Conversion
A given BCD number can be converted into an equivalent binary number by first writing its
decimal equivalent and then converting it into its binary equivalent.
Ex: Find the binary equivalent of the BCD number 0110 0011.0011 1001
• BCD number: 0110 0011.0011 1001
• Corresponding decimal number: (63.39)10
• The binary equivalent of (63.39)10 is (0111111.0110)
Binary-to-BCD Conversion
The process of binary-to-BCD conversion is the same as the process of BCD-to-binary

conversion executed in reverse order. A given binary number can be converted into an
equivalent BCD number by first determining its decimal equivalent and then writing the
corresponding BCD equivalent.
Ex. Find the BCD equivalent of the binary number 101110.11
• The decimal equivalent of this binary number can be determined to be 46.75
• The BCD equivalent can then be written as 0100 0110.0111 0101
Packed and Unpacked BCD Numbers:
In the case of unpacked BCD numbers, each four-bit BCD group corresponding to a decimal digit
is stored in a separate register inside the machine. In such a case, if the registers are eight bits
or wider, the register space is wasted.
In the case of packed BCD numbers, two BCD digits are stored in a single eight-bit register. The
process of combining two BCD digits so that they are stored in one eight-bit register involves
shifting the number in the upper register to the left 4 times and then adding the numbers in the
upper and lower registers. The process is illustrated by showing the storage of decimal digits ‘5’
and ‘7’:
• Decimal digit 5 is initially stored in the eight-bit register as: 0000 0101.
46
• Decimal digit 7 is initially stored in the eight-bit register as: 0000 0111.
• After shifting to the left 4 times, the digit 5 register reads: 0101 0000.
• The addition of the contents of the digit 5 and digit 7 registers now reads: 0101 0111.
Ex. How many bits would be required to encode decimal numbers 0 to 9999 in straight binary
and BCD codes? What would be the BCD equivalent of decimal 19 in 16-bit representation?
Solution
• Total number of decimals to be represented=10 000=104 =213.29.
• Therefore, the number of bits required for straight binary encoding=14.
• The number of bits required for BCD encoding=16 (as four bit for one decimal digit so sixteen
bit for 4 decimal digits).
• The BCD equivalent of 19 in 16-bit representation=0000 0000 0001 1001.
Excess-3 Code:
The excess-3 code is another important BCD code. It is particularly significant for arithmetic
operations as it overcomes the shortcomings encountered while using the 8421 BCD code to
add two decimal digits whose sum exceeds 9. The excess-3 code has no such limitation, and it
considerably simplifies arithmetic operations. The excess-3 code for a given decimal number is
determined by adding ‘3’ to each decimal digit in the given number and then replacing each
digit of the newly found decimal number by its four-bit binary equivalent. It may be mentioned
here that, if the addition of ‘3’ to a digit produces a carry, as is the case with the digits 7, 8 and
9, that carry should not be taken forward. The result of addition should be taken as a single
entity and subsequently replaced with its excess-3 code equivalent.
 Excess-3 code are self complementary
Decimal number Binary number Gray code BCD Excess-3 code

0 0000 0000 0000 0011
1 0001 0001 0001 0100
2 0010 0011 0010 0101
3 0011 0010 0011 0110
4 0100 0110 0100 0111
5 0101 0111 0101 1000
6 0110 0101 0110 1001
7 0111 0100 0111 1010
8 1000 1100 1000 1011
47
9 1001 1101 1001 1100

10 1010 1111 - -
11 1011 1110 - -
12 1100 1010 - -
13 1101 1011 - -
14 1110 1001 - -
15 1111 1000 - -
Ex. Find the excess-3 code for (354.79)10
Ans: (0011 0101 0100.0111 1001)2
Ex: Find the decimal equivalent of the excess-3 number 100101010111.10001011
Solution: given number is 1001 0101 0111.1000 1011 = (624.58)10
Other codes:
 Alphanumeric code: These are used to encode the characters of alphabet in addition to the
decimal digits. eg. ASCII, EBCDIC
 ASCII code: American standard code for information interchange (ASCII) is widely use
alphanumerical code. It is basically 7-bit code, so number of character can create by 7-bits
are 27 = 128. It is use to encode both upper and lower case alphabets, digits (0 to 9) and
some special symbols.
48
Problems:
1) What will be the decimal equivalent of (456)7
A) (237)10 B) (238)10 C) (236)10 D) Can’t convert
2) What is 5th compliment of (231)6
A) (325)6 B) (325)10 C) (324)6 D) (324)10
3) 2’s compliment representation of + 11 is
A) 10101 B) 01011 C) 00101 D) 11011
4) X = 0111 and Y = 1101 are two 4-bit binary numbers represented in two’s complement
format. The sum of X and Y represented in two’s complement format using 5 bits is
A) 00100 B) 10100 C) 01100 D) 10011
5) A signed integer has been stored in a 8-bit using 1’s complement format. We wish to store
the same integer in 16-bit word. We should copy the original byte to the less significant
byte of the word and fill the more significant byte with
A) 0 B) equal to the MSB of the original byte
C) 1 D) complement of the MSB of the original byte
6) What is addition of (− 60)10 and (60)16 ?
A) (36)10 B) (00)10 C) (36)16 D) (-36)16
7) Which number system used for k-map design
A) Gray code B) Excess 3 code C) binary weighted code D) none
8) 11011, 1011 and 00101 correspond to the 2’s complement representation of following
decimal numbers respectively.
A) 5, 5, 5 B) -5,-5,-5 C) -5,-5, 5 D) 27, 11, 5
9) Find the base x, If (204)x= (123)9.
A) 7 B) 8 C) 9 D) 10
10) The decimal equivalent of the binary number 101101 is
A) 48 B) 45 C) 57 D) 75
11) The octal equivalent of the decimal number 375 is
A) 560 B) 567 C) 565 D) none
12) The octal equivalent of the decimal number 27.125 is
A) 33.23 B) 33.28 C) 33.1 D) 33.01
13) The decimal equivalent of the hexadecimal number 3A.2F is
A) 58.1835 B) 58.1385 C) 58.23 D) none
14) The octal equivalent of the binary number 11010111 is
A) 656 B) 327 C) 653 D) D7
15) The decimal equivalent of hex number 1A53 is
A) 6793 B) 6739 C) 6973 D) 6379
16) The Gray code for decimal number 6 is equivalent to
A) 1100 B) 1001 C) 0101 D) 0110
17) The 2’s complement of the number 1101101 is
A) 0101110 B) 0111110 C) 0110010 D) 0010011
18) -8 is equal to signed binary number
A) 10001000 B) 00001000 C) 10000000 D) 11000000
19) When signed numbers are used in binary arithmetic, then which one of the following
notations would have unique representation for zero.
49
A) Sign-magnitude. B) 1’s complement. C) 2’s complement. D) none.

20) 1’s complement representation of decimal number of -17 by using 8 bit representation is
A) 1110 1110 B) 1101 1101 C) 1100 1100 D) 0001 0001
21) The excess 3 code of decimal number 26 is
A) 0100 1001 B) 0101 1001 C) 1000 1001 D) 0100 1101
22) The hexadecimal number for (95.5)10 is
A) (5F.8) 16 B) ( 9A.B) 16 C) ( 2E.F) 16 D) ( 5A.4) 16
23) The result of adding hexadecimal number A6 to 3A is
A) DD B) E0 C) E1 D) EF
24) Decimal number 25.5 is equal to the binary number
A) 11001.1 B) 10011.1 C) 11001.0 D) 10011.0
25) When two n-bit binary numbers are added then the sum will contain at the most
A) n-bit B) (n+1) bits C) (n+2) bits D) (n+n) bits
26) The Twos complement of the twos complement of the given number 1011001 is
A) 1011000 B) 1010110 C) 1011001 D) 0100111
27) The maximum positive & negative numbers which can be represented in twos
complement form using n bits are respectively
A) +(2n-1-1), -(2n-1-1) B) +(2n-1-1), -2n-1 C) +2n-1, -2n-1 D) +2n-1, -(2n-1+1)
28) The maximum positive & negative numbers which can be represented in ones
complement form using n bits are respectively
A) +(2n-1-1), -(2n-1-1) B) +(2n-1-1), -2n-1 C) +2n-1, -2n-1 D) +2n-1, -(2n-1-1)
29) The 2’s complement representation of -17 is
A) 101110 B) 101111 C) 111110 D) 110001
30) 4 bit 2’s complement representation of a decimal number is 1000, the number is
A) +8 B) 0 C) -7 D) -8
31. The number system with radix-2 is called as
A) Binary B) Decimal C) Octal D) Hexadecimal
32. A group of four bits is known as
A) bit B) byte C) nibble D) word
33. The knowledge of binary number system is required for the designers of computer
and other digital systems because
A) It is easy to learn binary number system
B) It is easy to learn Boolean algebra
C) It is easy to use binary codes
D) The devices used in these systems operates in binary
34. The ones complement of the binary number 10001011 is
A) 01110100 B) 11111111 C) 01110101 D) 11111110
35. The twos complement of the number 100101000 is
A) 011010110 B) 111 111111 C) 011010111 D) None
36. The ones complement of one’s complement of the given binary number is
A) same binary number B) zero C) non-zero D) none
37. The base or radix a Hexadecimal number system is
A) 2 B) 8 C) 16 D) 15
38. The decimal equivalent of the binary number 1001.0101 is
50
A) 9.125 B) 9.6125 C) 9.3125 D) 9.6215

39. The binary equivalent of decimal number 255 is
A) 11111110 B) 11111101 C) 11111111 D) none
40. Identify the binary number represented by the decimal number 10.625
A) 1010.011 B) 1010.101 C) 1010.110 D) none
41. The binary equivalent of the decimal number 0.6875 is
A) 0.1010 B) 0.1011 C) 0.1101 D) 0.0110
42. The decimal equivalent of the octal number 237 is
A) 159 B) 165 C) 162 D) 160
43. The hexadecimal equivalent of the decimal number 375 is
A) 177 B) 17A C) 1A0 D) none
44. The decimal equivalent of the hexadecimal number "BEED" is
A) 47877 B) 48877 C) 48777 D) none
45. Encode the decimal number 327.87 in BCD code
A) 001 10010 01 11.1000 0111 B) 001100100110.10011000
C) 0011 00100111. 1100 1010 D) none
46. The binary equivalent of the hexadecimal number AOB5 is
A) 10100001 1011 0101 B) 10100000 10100101
C) 1010 0000 101 1 0101 D) none
47. The decimal equivalent of the binary number 11010111 is
A) 215 B) 225 C) 250 D) none
48. The octal equivalent of the decimal number 215 is
A) 327 B) 372 C) 237 D ) none
49. The largest positive number that can be stored in a computer that has 16-bit word
length and uses twos complement arithmetic is
A) 32 B) 32767 C) 32768 D ) 65536
Answers:
1. A 2. C 3. B 4. A 5. B 6. A 7. A 8. C 9. A
10. B 11. B 12. C 13. A 14. B 15. B 16. C 17. D 18. A
19. C 20. A 21. B 22. A 23. B 24. A 25. B 26. C 27. B
28. A 29. B 30. D 31. A 32. C 33. D 34. A 35. D 36. A
37. C 38. C 39. C 40. B 41. B 42. A 43. A 44. B 45. A
46. C 47. A 48. A 49. B
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GATE THE Direction Logic Families
CHAPTER IV
LOGIC FAMILIES
LOGIC FAMILIES
There are a variety of circuit configurations or more appropriately various approaches
used to produce different types of digital integrated circuit. Each such fundamental approach is
called a logic family. The idea is that different logic functions, when fabricated in the form of an
IC with the same approach, or in other words belonging to the same logic family, will have
identical electrical characteristics. These characteristics include supply voltage range, speed of
response, power dissipation, input and output logic levels, current sourcing and sinking
capability, fan-out, noise margin, etc. In other words, the set of digital ICs belonging to the
same logic family are electrically compatible with each other.
Digital IC gates are classified not only by their logic operation, but also by specific logic circuit
family to which they belong. Each logic family has its own basic electronic circuit upon which
more complex digital circuits and functions are developed.
Positive and negative logic system:-
logic Positive logic Negative logic
Logic ‘1’ HIGH voltage LOW voltage
Logic ‘0’ LOW voltage HIGH voltage
Bipolar saturated logic families:-
In this the bipolar devices transistors are used and the transistors are going to be saturated.
52
 transistors on (saturation region) and off (cut off region)
1. Resistor Transistor Logic (RTL)
2. Direct Coupled Transistor Logic (DCTL)
3. Integrated Injection Logic (IIL) or (I2 L)
4. Diode Transistor Logic (DTL)
5. High Threshold Logic (HTL)
6. Transistor Transistor Logic (TTL)
Bipolar unsaturated logic families;-
In this the transistor are not going to be saturated.
 transistors on (active region) and off (cut off region)
1. Schottky TTL
2. Emitter Coupled Logic (ECL)
Uni-polar logic family:-
In this uni-polar transistors are used
1. PMOS
2. NMOS
3. Complementary MOS (CMOS)
NOTE:-
1. HTL is a modified form of DTL and IIL is a modified form of DCTL.
2. The MOS and IIL logic families are used for large scale Integration functions because high
package density.
3. TTL, ECL, CMOS are used for medium scale integration (MSI) or small integration (SSI).
4. Each logic gate family is identified with a serial number.

Example:- TTL family IC’s are available in 74/54 series, CMOS IC's usually designated with 4000
series, ECL family with 10,000 series.
53
Characteristic Parameters:
1) Propagation delay (tp):
The propagation delay is the time delay between the occurrence of change in the logical
level at the input and before it is reflected at the output. It is the time delay between the
specified voltage points on the input and output waveforms. Propagation delays are
separately defined for LOW-to-HIGH and HIGH-to-LOW transitions at the output.
 Propagation delay tpLH. This is the time delay between specified voltage points on the
input and output waveforms with the output changing from LOW to HIGH.
 Propagation delay tpHL. This is the time delay between specified voltage points on the
input and output waveforms with the output changing from HIGH to LOW.
Figure shows the two types of

propagation delay parameter.
𝒕𝒑𝑳𝑯 + 𝒕𝒑𝑯𝑳
tp = 𝟐
2) Power dissipation:
The power dissipation parameter for a logic family is specified in terms of power
consumption per gate and is the product of supply voltage V CC and supply current ICC. The
supply current is taken as the average of the HIGH-level supply current ICCH and the LOW-
level supply current ICCL.
PD = VCC X ICC(avg) As: ICC(avg) = (ICCH + ICCL )/2
3) Fan-out:
The fan-out is the number of identical inputs of a logic function that can be driven from a
same single output without causing any false output. It is a characteristic of the logic family
to which the device belongs. It can be computed from I OH/IIH in the logic HIGH state and
from IOL/IIL in the logic LOW state. If, in a certain case, the two values I OH/IIH and IOL/IIL are
different, the fan-out is taken as the smaller of the two. This description of the fan-out is
true for bipolar logic families like TTL and ECL. When determining the fan-out of CMOS
logic devices, we should also take into consideration how much input load capacitance can
be driven from the output without exceeding the acceptable value of propagation delay.
Fan-out = min { IOH/IIH , IOL/IIL }
4) Fan-in:
The maximum number of inputs that can be applied to the logic gate.
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5) Noise margin:
This is a quantitative measure of noise immunity offered by the logic family. When the
output of a logic device feeds the input of another device of the same family, a legal HIGH
logic state at the output of the feeding device should be treated as a legal HIGH logic state
by the input of the device being fed. Similarly, a legal LOW logic state of the feeding device
should be treated as a legal LOW logic state by the device being fed.
Figure shows the generalized case of legal HIGH and LOW voltage levels for output (a) and
input (b). As we can see from the two diagrams, there is a disallowed range of output
voltage levels from VOL (max.) to VOH (min.) and an indeterminate range of input voltage
levels from VIL (max.) to VIH (min.). Since VIL (max.) is greater than VOL (max.), the LOW
output state can therefore tolerate a positive voltage spike equal to VIL (max) − VOL (max)
and still be a legal LOW input. Similarly, VOH (min.) is greater than VIH (min.), and the HIGH
output state can tolerate a negative voltage spike equal to VOH (min.) – VIH (min.) and still
be a legal HIGH input.
VOH (min):- It is the minimum voltage level at a logic circuit output in the logic ‘1’ state
under defined load conditions.
VIH (min):- It is the minimum voltage level required for a logical '1' at an input. Any voltage
below this level will not be accepted as a 'High' by the logic circuit.
VIL (max):-It is defined as the maximum voltage level required for a logic ‘0’ at an input. Any
voltage above this level will not be accepted as a 'Low' by the logic circuit.
VOL (max):-It is maximum voltage level at a logic circuit output in the logical '0' state under
defined load conditions.
NML= VIL (max.) – VOL (max.)
NMH= VOH (min.) − VIH (min.)
The overall noise margin of gate is minimum of NML and NMH
NM = min { NML, NMH }
Figure of merit:-
The product of propagation delay time and power dissipation is known as figure of merit of
performance of a gate. Normally minimum values are desired.
55
FOM = tp X PD
Logic swing:-
The difference between the two output voltages (VOH - VOL) is known as the logic swing of the
circuit.
Noise immunity:-
The ability to with stand variations in the input levels.
NOTE:-
1. ECL has ultra-fast-switching speed & low Logic swing.
2. The temperature range of 74-series of TTL logic gate family is 0°c to70°c.This series of IC's
used for commercial applications.
3. The temperature range of 54-series TTL logic gate family is -55°c to 125°c. This series of IC's
used in military applications.
Breadth:-
The number of various functions available in a logic family known as breadth of the logic family.
Wired logic:-
Where the output of logic gates is connected together additional logic functions are performed.
This known as wired logic.
Passive pull-up:-
In a bipolar logic circuit a resistance 'RC' used in the collector circuit of the output transistor is
known as passive pull-up.
Active pull up;-
In a bipolar logic circuit a BJT and diode circuit used in the collector circuit of the output
transistor instead of 'RC.' is known as active pull-up. This facility is available in TTL family.
NOTE:-
The advantage of active pull up over passive pull-up are increased speed of operation and
reduced power dissipation.
Open collector output:-
In a bipolar logic circuit if nothing is connected at the collector of the output transistor and this
collector terminal is available to all IC pins known as open-collector output.
56
Tri-state logic:-
In the Tri-state logic in addition to low impedance 0 and 1 there is a third state known as high
impedance state where the gate is disabled it is in the third state.
Types of Logic Family

1) RTL (Resistor Transistor Logic):
The basic circuit of the RTL digital logic family is the NOR gate shown in figure. Each input is
associated with one resistor and one transistor. The collectors of the transistors are tied
together at the output. The voltage levels for the circuit are 0.2 V for the low level and
from 1 to 3.6 V for the high level.
The fan-out of the RTL gate is limited by the value of the output voltage when high. The
power dissipation of the RTL gate is about 12 mW and the propagation delay averages 12
ns.
 Act ac wire AND logic

 For an 'N" input NOR gate use 'N' transistors.
2) DTCL (Direct couple transistor logic):

In DCTL the inputs are directly connected to bases of transistors. It can be defined as
the RTL logic without base resistance.
 DCTL is never famous because of current hogging problem.
2-input NOR gate:
57
3) DTL (Diode Transistor Logic):

The basic circuit in the DTL digital logic family is the NAND gate shown in figure. Each input
is associated with one diode. The diodes and the 5-kΩ resistor form an AND gate. The
transistor serves as a current amplifier while inverting the digital signal. The two voltage
levels are 0.2 V for the low level and between 4 and 5 V for the high level.
The power dissipation of a DTL gate is about 8-12 mW and the propagation delay averages
30 ns. The noise margin is about 1 V and a fan-out as high as 8 is possible. The fan-out of
the DTL gate is limited by the maximum current that can flow in the collector of the
saturated transistor. The fan-out of a DTL gate may be increased by replacing one of the
diodes in the base circuit with a transistor.
 Act ac wire AND logic
4) TTL (Transistor Transistor Logic):
The original basic TTL gate was a slight improvement over the DTL gate. There are several
subfamilies or series of the TTL technology. The standard TTL gate was the first version in
the TTL family. This basic gate was then designed with different resistor values to produce
gates with lower power dissipation or with higher speed.
TTL gates in all the available series come in three different types of output configuration:
1. Open-collector output
2. Totem-pole output
3. Three-state (or tristate) output
We will consider here, TTL logic with totem-pole output.
58
The TTL gate with the totem-pole output is shown in figure above. Transistors Q3 and Q4
constitute what is known as a totem-pole output arrangement. In such an arrangement,
either Q3 or Q4 conducts at a time depending upon the logic status of the inputs. The
totem-pole arrangement at the output has certain distinct advantages. The major
advantage of using a totem-pole connection is that it offers low-output impedance in both
the HIGH and LOW output states. In the HIGH state, Q 3 acts as an emitter follower and has
an output impedance of about 70Ω. In the LOW state, Q 4 is saturated and the output
impedance is approximately 10Ω.
If any one of the input is low or all the inputs are low then emitter base junction of
transistor is forward biased and collector base junction is reverse biased due to this
transistor Q2 and Q3 are cutoff where as Q4 is in saturation hence output is logic 1. When
all the inputs are 1 then, emitter base junction is reverse biased and collector base junction
is forward biased due to this Q1 is reverse active mode while Q2 and Q3 are in saturation
and Q4 is in cutoff and output is logic 0.
Note:-
1. In TTL logic gate family three different types of output configurations are available, they
are open collector and totem pole and tri-state output type.
2. The advantage of open collector output is wired- logic can be performed and loads other
than the normal gate can be used.
3. If any input of TTL circuit is left floating it will function as if it is connected to logic 1
level.
4. The supply voltage range of 74-series is 5±0.25V
54-series is 5±0.5V
5. Different versions available in TTL logic gate family.
74/54L -Low power
74/54H -High power/High speed
74/54LS -Low power Schottky
74/54S -Schottky
74/54AS -Advanced Schottky
74/54ALS -Advanced low power Schottky
2-Input NAND gate with open collector output configuration:-
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Gates with open collector output can be used for wired AND operation.
Wired AND operation is equivalent to AND-OR-INVERT.
5) ECL (Emitter Couple Logic):

The ECL family is the fastest logic family in the group of bipolar logic families. Emitter-
coupled logic (ECL) is a non saturated digital logic family. Since transistors do not saturate,
it is possible to achieve propagation delays of 2 ns and even below 1ns. This logic family
has the lowest propagation delay of any family and is used mostly in systems requiring very
high-speed operation. Its noise immunity and power dissipation, however, are the worst of
all the logic families available. A typical basic circuit of the ECL family is shown in Figure.
The output provide both the OR and NOR functions. Each input is connected to the base of
a transistor. The bias network configured around transistor Q6 produces a voltage of
typically -1.29V at its emitter terminal. This leads to a voltage of -2.09V at the junction of
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all emitter terminals of various differential transistors Q1–Q4, assuming 0.8V to be the
required forward-biased P–N junction voltage. Now, let us assume that all inputs are in a
logic ‘0’ state, i.e the voltage at the base terminals of various input transistors is -1.75 V.
This means that the transistors Q1, Q2, Q3 and Q4 will remain in cut-off as their base
emitter junctions are not forward biased by the required voltage. This leads us to say that
transistor Q7 is conducting, producing a logic ‘0’ output and transistor Q8 is in cut-off,
producing logic ‘1’ output.
In the next step, let us see what happens if any one or all of the inputs are driven to logic
‘1’ status, that is, a nominal voltage of -0.9V is applied to the inputs. The base-emitter
voltage of differential transistors Q1–Q4 exceeds the required forward-biasing threshold,
with the result that these transistors start conducting. This leads to a rise in voltage at the
common-emitter terminal, which now becomes approximately -1.7V as the common-
emitter terminal is now 0.8V more negative than the base terminal voltage. With rise in the
common-emitter terminal voltage, the base-emitter differential voltage of Q5 becomes
0.31 V, driving Q5 to cut-off. The Q7 and Q8 emitter terminals respectively go to logic ‘1’
and logic ‘0’. The propagation delay of the ECL gate is 2 ns, and the power dissipation is 25
mW.
 Act ac wire OR logic
6) MOS:
Input PMOS NMOS

0 (0 V) On Off
1 (1.8 V) Off On
PMOS Inverter:- NMOS Inverter:-
7) CMOS (Complementary Metal Oxide Semiconductor) Logic:

The CMOS logic family uses both N-type and P-type
MOSFETs (enhancement MOSFETs, to be more precise) to
realize different logic functions.
CMOS Inverter: When the input is in the HIGH state (logic ‘1’),
P-channel MOSFET Q1 is in the cut-off state while the N-channel
MOSFET Q2 is conducting. The conducting MOSFET provides a
path from ground to output and the output is LOW (logic ‘0’).
When the input is in the LOW state (logic ‘0’), Q1 is in
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conduction while Q2 is in cut-off. The conducting P-channel device provides a path for VDD
to appear at the output, so that the output is in HIGH or logic ‘1’ state.
CMOS NAND: Two P-channel MOSFETs (Q1 and Q2 are

connected in parallel between VDD and the output
terminal, and two N-channel MOSFETs (Q3 and Q4 are
connected in series between ground and output
terminal. For the output to be in a logic ‘0’ state, it is
essential that both the series-connected N-channel
devices conduct and both the parallel-connected P-
channel devices remain in the cut-off state. This is
possible only when both the inputs are in a logic ‘1’ state.
When both the inputs are in a logic ‘0’ state, both the N-
channel devices are non conducting and both the P-
channel devices are conducting, which produces a logic
‘1’ at the output. For the remaining two input combinations, either of the two N-channel
devices will be non conducting and either of the two parallel-connected P-channel devices
will be conducting. The output in both cases is logic ‘1’. So it is act as NAND gate.
CMOS NOR: Two P-channel MOSFETs (Q1 and Q2 are

connected in series between VDD and the output
terminal, and two N-channel MOSFETs (Q3 and Q4 are
connected in parallel between ground and output
terminal. For the output to be in a logic ‘1’ state, it is
essential that both the series-connected P-channel
devices conduct and both the parallel-connected N-
channel devices remain in the cut-off state. This is
possible only when both the inputs are in a logic ‘0’
state. When both the inputs are in a logic ‘1’ state, both
the N-channel devices are conducting and both the P-
channel devices are non conducting, which produces a logic ‘0’ at the output. For the
remaining two input combinations, either of the two parallel N-channel devices will be
conducting and either of the two series-connected P-channel devices will be non
conducting. The output in both cases is logic ‘0’. So it is act as NOR gate
8) I2L (Integrated Injection Logic): Integrated injection logic (I2L), also known as current
injection logic, is well suited to implementing LSI and VLSI digital functions and is a close
competitor to the NMOS logic family. Figure shows the basic I2L family building block,
which is a multi collector bipolar transistor with a current source driving its base.
Transistors Q3 and Q4 constitute current sources. The magnitude of current depends upon
externally connected R and applied +V. This current is also known as the injection current,
which gives it its name of injection logic.
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If input A is HIGH, the injection current through Q3 flows through the base-emitter
junction of Q1. Transistor Q1 saturates and its collector drops to a low voltage, typically
50–100 mV. When A is LOW, the injection current is swept away from the base-emitter
junction of Q1. Transistor Q1 becomes open and the injection current through Q4
saturates Q2, with the result that the Q1 collector potential equals the base-emitter
saturation voltage of Q2, typically 0.7 V. If we take o/p from collector of Q1 then its act as
inverter.
Comparison of logic families:-

Parameter RTL DCTL DTL TTL ECL I2L CMOS
Resistors, Resistors, N Channel & P

Resistors & Resistors & Resistor &
Components used Diodes, Diodes & Transistors Channel
Transistors Transistors transistors
Transistors Transistors MOSFET.
Circuits Simple Simplest Moderate Complex Complex Simple Moderate
Noise margin Poor Poor High Medium Low High High
Fan-out Low(4) Low(4) Medium(8) More (10) High(25) 8 to 12 50
Power Dissipation 6 nW to70

12 30 8-12 10 40-55 0.01
(mW) Per gate uW
Basic gate NOR NOR NAND NAND OR-NOR NAND NAND/N OR
2(ECL 10k)
Propagation
12 10 30 10 0.75(ECL 25-250 70
delay(ns)
100K)
Speed power 100(ECL 10k)

144 300 300 100 <1 0.7
product (pJ) 40(ECL 100k)
Note:
For open terminal the

TTL family acts as logic ‘1’ and in ECL family act as logic ‘0’
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Problems:
1) What will be output logic?
A) C(A+B)
B) (C(A+B))’
C) AB+C
D) (AB+C)’
2) For negative logic the circuit is act as -------gate
A) OR
B) NOR
C) AND
D) NAND
3) ECL logic family is
A) Wire AND B) wire OR C) wire NOR D) wire NAND
4) The digital logic family which has minimum power dissipation is
A) TTL B) RTL C) DTL D) CMOS
5) Which of the following is the fastest logic family
A) TTL B) ECL C) CMOS D)IIL
6) Which of the following is the fastest saturated logic family
A) TTL B) ECL C) RTL D)DTL
7) Which TTL logic gate is used for wired ANDing
A) Open collector output B) Totem Pole
C) Tri state output D) ECL gates

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8) CMOS circuits consume power
A) Equal to TTL B) Less than TTL C) Twice of TTL D) Thrice of TTL
9) Among the following logic families, the one having highest noise margin is
A) Schottky TTL B) TTL C) ECL D) CMOS
10) In TTL gates, the totem pole output stage is primarily used to______.
A) increase noise margin of the gate B) decrease the output switching delay
C) facilitate a wired OR logic connection D) increase the output impendence of circuit.
11) The following circuit is a _______gate
A) CMOS NOR
B) CMOS NAND
C) PMOS NOR
D) NMOS NAND
12) The fan – out of MOS logic gate family is high because of______.
A) Low input impedance B) high input impedance
C) Low output impedance D) high output impedance
13) Ultra high switching speeds are possible in ECL family because of
A) Saturation logic used
B) Unsaturation logic used
C) Independent of saturation and unsaturation logic
D) Propagation delay is high
14) Which one of the gate family having minimum propagation delay
A) TTL B) MOS C) DTL D) ECL
15) A darlington emitter follower circuit is sometimes used in the output stage of a TTL gate in
order to _____
A) Increase its IOL B) reduce its IOH
C) Increase its speed of operation D) reduce power dissipation
16) Commercially available ECL gears use two ground lines & one -ve supply in order to_____
A) Reduce power dissipation
B) Increase fan-out
C) Reduce loading effect
D) Eliminate the effect of power line glitches or the biasing circuit
17) The output of the 74 series gate of TTL gate is taken from a BJT in
A) Totem pole and common collector configuration
B) Either totem pole or open collector configuration
C) Common base configuration
D) Common collector configuration
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18) Figure shown the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs
shown in the figure, the output y is
A) 0 B) 1
C) AB D) (AB)’
19) Consider the following statements regarding IC’s

1. ECL has the least propagation delay. 2. TTL has the largest fan-out.
3. CMOS has the biggest noise margin 4. TTL has the lowest power consumption.
Which of these statements are correct?
A) 1 and 3 B) 2 and 4 C) 3 and 4 D) 1 and 2
20) For a logic family,
VOH is the minimum output high level voltage,
VOL is the maximum output low level voltage,
VIH is the minimum acceptable input high level voltage,
VIL is the maximum acceptable input low level voltage,
The correct relationship among these is
A) VIH>VOH>VIL>VOL B) VOH>VIH>VIL>VOL C) VIH>VOH>VOL>VIL D) VOH>VIH>VOL>VIL
21) The figure of merit of a logic family is given by
A) gain X bandwidth B) Propagation delay time X power dissipation
C) Fan-out X propagation delay time D) Noise margin X power dissipation
22) Assertion (A): ECL has the highest speed of operation as compared to other logic families.
Reason (R): ECL gate dissipates more power.
A) Both A and R are true and R is the correct explanation of A
B) Both A and R are true but R is NOT the correct explanation of A
C) A is true but R is false
D) A is false but R is true.
23) Consider the logic families: 1. MOS 2. DTL 3. RTL 4. ECL
The sequence of these logic families in the order of their increasing noise margin is
A) 3,4,1,2 B) 3,4,2,1, C) 4,3,1,2 D) 4,3,2,1
24) Match List-I (Logic gates) with List-II and select the correct answer using the codes
List-I List-II
A. TTL 1. Low propagation delay
B. ECL 2. Low power consumption
C. MOS 3. Higher packing density on Si wafer
D. CMOS 4. Saturated bipolar logic
5. High fan-out
A) A-4,B-1,C-3,D-2 B) A-5,B-3,C-2,D-1 C) A-4,B-3,C-2,D-1 D) A-5,B-1,C-3,D-2
25) Assertion (A): The speed-power product is an important parameter for comparing various
TTL series.
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Reason (R): A low value of speed-power product indicates that a propagation delay can be
achieved without excessive power dissipation and vice versa.
26) Which one of the logic families can be operated using a supply voltage from 0.5 V to 5V?
A) TTL B) ECL C) IIL D) CMOS
Answers:
1. B 2. D 3. B 4. D 5. B 6. A 7. A 8. B 9. D
10. B 11. B 12. B 13. B 14. D 15. C 16. D 17. B 18. A
19. A 20. B 21. B 22. B 23. B 24. A 25. A 26. D
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GATE THE Direction Combinational Logic Circuits
CHAPTER V
COMBINATIONAL LOGIC CIRCUITS
Combinational logic circuitS
HALF ADDER: A B S C
A S 0 0 0 0
0 1 1 0
1 0 1 0
HALF ADDER
1 1 0 1
B C
S=A B & C = A.B
Fig A. Half adder B. Half adder using only NAND gate.
Half adder can be constructed by using 5 NAND gate or by 5 NOR gate.

Suppose half adder construct by NAND gate as show above and delay of each NAND
gate is tp then
 Propagation delay of half adder is 3tp
 Propagation delay of sum is 3tp
 Propagation delay of carry is 2t p
Ex: In above figure if propagation delay of each gate is 10 ns then calculate the propagation
delay of half adder.
A) 10/3 ns B) 10 ns C) 20 ns D) 30 ns
Solution: Propagation delay of half adder is 3t p = 30 ns
Ex: If we have all gate expect XOR and XNOR gate then how many minimum number of gate
require constructing half adder.
Solution:
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i.e. It require 3 gate as 1 AND gate and 2 NOR gate.
FULL ADDER:
A Sum
FULL ADDER
B
Cin Cout
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
Sum = A B C
0 1 0 1 0
Cout = AB + BC +CA 0 1 1 0 1
1 0 0 1 0
 Realization of full adder using half adder: 1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Full adder by using only NAND gates:
Implementation of Full adder require 9 NAND gate or 9 NOR gate.
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Suppose full adder construct by NAND gate as show above and delay of each NAND gate
is tp then
 Propagation delay of full adder is 6t p
 Propagation delay of sum is 6tp
 Propagation delay of carry is 5t p
HALF SUBTRACTOR:
A S A B S C
0 0 0 0
HALF SUBTRACTOR 0 1 1 1
B C 1 0 1 0
1 1 0 0
S=A B & C = A’B
Half subtractor using only NAND gate.
Half subtractor can be constructed by using 5 NAND gate or by 5 NOR gate.

Suppose half subtractor construct by NAND gate as show above and delay of each NAND
gate is tp then
 Propagation delay of half subtractor is 3tp
 Propagation delay of subtraction is 3tp
 Propagation delay of borrow is 2tp
FULL Subtractor:
A B Cin Sub Cout
0 0 0 0 0
0 0 1 1 1
A Sub 0 1 0 1 1
FULL Subtractor
B 0 1 1 0 1
1 0 0 1 0
Cin Cout 1 0 1 0 0
1 1 0 0 0
Sub = A xor B xor C 1 1 1 1 1
Cout = A’B + BC +CA’
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Implementation of Full subtractor require 9 NAND gate or 9 NOR gate.
4-bit parallel ADDER:

The Ripple Carry Binary Adder is simply n, full adders cascaded together with each full adder
represents a single weighted column in the long addition with the carry signals producing a
"ripple" effect through the binary adder from right to left. For example, suppose we want to
"add" together two 4-bit numbers, the two outputs of the first full adder will provide the first
place digit sum of the addition plus a carry-out bit that acts as the carry-in digit of the next
binary adder. The second binary adder in the chain also produces a summed output (the 2nd
bit) plus another carry-out bit and we can keep adding more full adders to the combination to
add larger numbers, linking the carry bit output from the first full binary adder to the next full
adder, and so forth. An example of a 4-bit adder is given below.
Co is always zero so we can connect it to ground or we can use half adder instead of FA 0. Final
result will be C4S3S2S1S0. It is parallel adder. It is called as Ripple carry adder.
For n-bit parallel adder the propagation delay is

 tp of adder = (n-1) tp carry + max (tp carry, tp sum) , Where tp carry : delay of carry and tp sum
:delay of sum of any full adder.
Example: In the 4-bit ripple carry adder, if delay of full adder for sum is 20 ns and for carry is 10
ns. Find time required to get result.
Solution: tp of adder = (n-1) tp carry + max (tp carry, tp sum) = 3 x 10ns + max (10 ns, 20 ns) = 30 ns + 20
ns = 50 ns.
Multiplexer:
A data selector, more commonly called a Multiplexer, shortened to "Mux" or "MPX", are
combinational logic switching devices that operate like a very fast acting multiple position
rotary switch. They connect or control, multiple input lines called "channels" consisting of
either 2, 4, 8 or 16 individual inputs, one at a time to an output. Then the job of a multiplexer is
to allow multiple signals to share a single common output.
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For example, a single 8-channel multiplexer would connect one of its eight inputs to the single
data output. Multiplexers are used as one method of reducing the number of logic gates
required in a circuit or when a single data line is required to carry two or more different digital
signals.
In above figure the output Y is one of input from I0 to Im-1 depend on select lines. In this we are
using n select line so 2n different combinations are possible so we can use at max 2n different
inputs (as assign one combination from 2 n to one input) so that m ≤ 2n. where m: number of
inputs and n: number of select line.
 Multiplexer is used to select one input from many inputs

 It is many to one convertor
 It is parallel to serial convertor
 It is universal circuit because we can form any Boolean function by using mux.
 Multiplex may have enable signal. If enable is active then mux is on and work as
above mention otherwise mux is off and output is zero.
4:1 Multiplexer
4-to-1 multiplexer. The input combinations 00, 01, 10 and 11 on the select lines respectively
switch I0, I1, I2 and I3 to the output
Y= S0’S1’I0 + S0S1’ I1 + S0’S1I2 + S0S1I3
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Here 2 select lines S0 and S1 and corresponding 22=4 inputs, select line use to select the desire
input.
Construct logic gate by using 4:1 mux:
i) AND gate ii) OR gate

I0 = I1 = I2 = 0; and I3 = 1. I0 = 0; I1 = I2 = I3 = 1.
Y = S0 S1 Y = S0S1 + S0’S1 + S0S1’ = S0 + S1
iii) NOT gate iv) NAND gate
I0 = I1=1; I2 = I3 = 0; S1 = 0. I0=I1=I2=1; I3=0.
Y=S0’ Y= S0’ S1’ + S0’S1 + S0S1’ = ( S0S1 )’
v) NOR gate vi) XOR gate
I0 = 1 and I1 = I2 = I3 = 0 I1 = I2 =1 and I0 = I3 =0
Y = S0’S1’ = ( S0 + S1 )’ Y = S0S1’ + S0’S1
vii) XNOR gate
I1 = I2 =0 and I0 = I3 =1
Y = S0S1 + S0’S1’
2: 1 Multiplexer
The 2-to-1 multiplexer show below, the mux functions as follows:
 For S = 0, the Boolean expression for the output becomes Y = I0.

 For S = 1, the Boolean expression for the output becomes Y = I1.
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Y = S’I0 + SI1
Construct logic gate using 2:1 Multiplexer
i) NOT gate
I0 = 1 and I1 = 0
Y = S’
ii) AND gate
I0 = 0 and I1 = A and S=B
Y = AB
iii) OR gate
I0 = B and I1 = A and S=A
Y = A’B+A = A+B
iv) NAND gate
Here we require two 2:1 mux (one for inverter)
I0 = 1 and I1 = B’ and S=A (here one mux require for B’ from B i.e. inverter)
Y = A’+ AB’= A’+B’= 𝐴𝐵
v) NOR gate
I0 = B’ and I1 = 0 and S=A (here one mux require for B’ from B i.e. inverter)
Y = A’B’= A + B
vi) XOR gate
I0 = B and I1 = B’ and S=A (here one mux require for B’ from B i.e. inverter)
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Y = A’B+AB’
vii) XNOR gate
I0 = B’ and I1 = B and S=A (here one mux require for B’ from B i.e. inverter)
Y = A’B’+AB
Implementing Boolean Functions with Multiplexers:
One of the most common applications of a multiplexer is its use for implementation of
combinational logic Boolean functions. The simplest technique for doing so is to employ a 2 n-to-
1 MUX to implement an n-variable Boolean function. The input lines corresponding to each of
the minterms present in the Boolean function are made equal to logic ‘1’ state. The remaining
minterms that are absent in the Boolean function are disabled by making their corresponding
input lines equal to logic ‘0’. As an
Ex. Implement the given Boolean function: f(A,B,C) = 𝑚 {2,4,7}
Solution: By sing 8:1 mux
 Connect variable (A,B,C) to select line (here number of inputs and select lines are same)
 Connect input of mux to 1’s, corresponding minterm is available in given Boolean
function and other mux input to 0’s
 For above Boolean function connect mux input 2,4,7 to logic 1 and other to logic 0.
By sing 4:1 mux:
 Here number of select line are less as compare to number of variable so connect high
significant variable to select line and least significant variable is connect to input of the
mux according to truth table as show below.
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Ex. Implement the given Boolean function: f(A,B,C) = 𝑀 {0,3,6} by using 4:1 mux.
• Let the Boolean function be f(A,B,C) = 𝑀 {0,3,6}
• The equivalent sum-of-products expression can be written as f(A,B,C) = 𝑚 1,2,4,5,7
Ex. The 8-to-1 multiplexer use to implement a certain four-variable Boolean function. From the
given logic circuit arrangement, derive the Boolean expression implemented by the given circuit
is.
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Solution:
 Construct the truth table from given circuit.
There for from truth table f(A,B,C,D) = 𝒎 {𝟑, 𝟒, 𝟓, 𝟖}
Number of mux require to design mux with more inputs:
For design N:1 mux we require atleast (N-1) number of 2:1 mux.
Ex. Find the minimum number of 2:1 mux require to design 7:1 mux
Solution: Atleast (N-1) number of 2:1 mux to design N:1 so here (N-1) = 7-1 = 6
Therefore six 2:1 mux require to design 7:1 mux.
Ex. Find the number of only 8:1 mux require to design 16:1 mux
Solution: On first stage we require two 8:1 mux and at second stage we require one 8:1 mux so
total three 8:1 mux require to design 16:1 mux.
Ex. Find the number of 4:1 mux require to design 10:1 mux
Solution: On first stage use two 4:1 mux that will cover eight inputs and on second stage use
one 4:1 mux which will cover remaining two inputs and two output of two 4:1 mux use at first
stage (one from each), so total three 4:1 mux require to design 10:1 mux.
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Demultiplexer
The data distributor, known more commonly as a Demultiplexer or "Demux", is the
exact opposite of the Multiplexer. It has one input line and many output lines. Input is
transmitted to one of the output line that output line is selected by select line.
 One input many outputs

 converts a serial data signal at the input to a parallel data at its output
1:4 Demultiplexer
Y0= S1’S0’In
Y1=S1’S0In
Y2=S1S0’In
Y3=S1S0In
1:2 Demultiplexer
Y0= S’ In
Y1=S In
Decoder
A decoder is a combinational circuit that decodes the information on n input lines to a
maximum of 2n unique output lines. Figure shows the circuit representation of 2-to-4 line
decoders. If there are some unused or ‘don’t care’ combinations in the n-bit code, then there
will be fewer than 2n output lines. A decoder can generate a maximum of 2n possible minterms
with an n-bit binary code.
It is binary to any other code(octal, decimal, hex etc.) converter.

A decoder can be conveniently used to implement a given Boolean function. The
decoder generates the required minterms and an external OR gate is used to produce
the sum of minterms.
2 to 4 Decoder:
Where A and B are binary inputs, E is enable signal and according to 4 different combination of
inputs the corresponding outputs are Y0 to Y3.
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Ex. Design the following Boolean function by using 3 to 8 decoder f(A,B,C) = Y = A’B’C +AB’C’
+ABC’ +ABC
Solution: A’B’C ---> 001 ---> 1; AB’C’ ---> 100 ---> 4;
ABC’ ---> 110 ---> 6; ABC ---> 111 ---> 7;
There connect OR gate to output terminal 1, 4, 6, 7.
Ex. Implement a full adder circuit using a 3-to-8 line decoder.
Solution: In full adder sum= A⊕B⊕C = 𝒎{𝟏, 𝟐, 𝟒, 𝟕}
Carry = AB + BC + AC = 𝒎{𝟑, 𝟓, 𝟔, 𝟕}
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Encoder
An encoder is a multiplexer without its single output line. It is a combinational logic function
that has 2n (or fewer) input lines and n output lines, which correspond to n selection lines in a
multiplexer. The n output lines generate the binary code for the possible 2 n input lines. Let us
take the case of an octal-to-binary encoder. Such an encoder would have eight input lines, each
representing an octal digit, and three output lines representing the three-bit binary equivalent.
It convert any other (octal, hex ect.) code to binary code

Encoder don’t have select line
Generally one of the input line is high and corresponding binary is available at the
output.
It is mainly used in keypad of computer, mobile etc.
Circuit:
Priority Encoder:
In this type of encoder, a priority is assigned to each input so that, when more than one input is
simultaneously active, the input with the highest priority is encoded. We will illustrate the
concept of priority encoding with the help of an example. Let us assume that the octal-to-
80
binary encoder described in the previous paragraph has an input priority for higher-order digits.
Let us also assume that input lines D2, D4 and D7 are all simultaneously in logic ‘1’ state. In that
case, only D7 will be encoded and the output will be 111. The truth table of such a priority. It
implies that, if D7 = 1, then, irrespective of the logic status of other inputs, the output is 111 as
D7 will only be encoded since D7 has highest priority. The truth table for that is show below:
Ex. We have an eight-line to three-line priority encoder circuit with D0, D1, D2, D3, D4, D5, D6
and D7 as the data input lines. the output bits are A (MSB), B and C (LSB). Higher-order data bits
have been assigned a higher priority, with D7 having the highest priority. If the data inputs and
outputs are active when LOW, determine the logic status of output bits for the following logic
status of data inputs:
(a) All inputs are in logic ‘0’ state.
(b) D0 to D3 are in logic ‘0’ state and D4 to D7 are in logic ‘1’ state.
(c) D7 and D3 is in logic ‘0’ state. The logic status of the other inputs is not known.
Solution:
(a) Since all inputs are in logic ‘0’ state, it implies that all inputs are active. Since D7 has the
highest priority and all inputs and outputs are active when LOW, the output bits are A = 0, B = 0
and C = 0(since output is active low).
(b) Inputs D0 to D3 are the zero that are active. among these, D4 has the highest priority.
Therefore, the output bits are A = 0, B = 1 and C = 1 (since output is active low).
(c) D7 is active. Since D7 has the highest priority, it will be encoded irrespective of the logic
status of other inputs. Therefore, the output bits are A = 0, B = 0 and C = 0(since output is active
low).
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Ex. Design a four-line to two-line priority encoder with active HIGH inputs and outputs, with
priority assigned to the higher-order data input line.
Solution: Suppose input are D0, D1, D2, D3 with D3 has highest priority and D0 has least priority
and the output bits are X & Y.
By solving above truth table X = D2 + D3; & Y = D3 + (D1 + D2’)
Programmable Logic Devices

A programmable logic device offers to the user a wide range of logic capacity in terms of
digital building blocks, which can be configured by the user to perform the intended function or
set of functions. In the case of programmable logic devices, users can change the circuit as
often as they want to until the design operates to their satisfaction. PLDs offer to the users
much more flexibility during the design cycle. There are many types of programmable logic
device, distinguishable from one another in terms of architecture, logic capacity,
programmability and certain other specific features-
1) PROM (Programmable ROMs)
When used as a PLD, it can be used to implement m different combinational functions, with
each function being a chosen function of n variables. A generalized ROM device with n inputs
and m outputs has 2n hard-wired AND gates at the input and m programmable OR gates at the
output. Thus, each OR gate can be used to generate any Boolean function of n variables.
 AND is Fixed and OR is programmable. (A cross (×) indicates programmable connection

and dot (•) indicates a hard-wired or fixed connection)
 Produces all possible minterms
 programmable OR array allows only the desired minterms to generate require output
 One of the major disadvantages of PROMs is their inefficient use of logic capacity and
use relatively higher power consumption
Ex. Design the given Boolean function F1(A,B,C) = 𝑚 0,2 & 𝐹2 = 𝑚 1,4,7
Solution: Step:
 Design all the minterm possible by using given variables (here three variables A, B, C).
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 Connect the minterm present in given function to programmable OR gate. Here function
F1 has minterm 0 & 2 and F2 has minterm 1, 4 &7.
2) PLA (Programmable Logic Array)

 Both AND & OR gates are programmable. which makes it one of the most versatile
PLDs.
 A PLA device makes more efficient use of logic capacity than a PROM
 disadvantages resulting from two sets of programmable fuses, which makes it relatively
more difficult to manufacture, program and test.
Steps:
1. Reduce the Boolean function write down in reduce SOP form.

2. Design all the reduce prime implicant by programmable AND gates at input side.
3. If any prime implicant is repeated in more than one function still design only once.
4. Connect the prime implicant present in given function to programmable OR gate at
output side.
Ex. Design an Boolean function 𝐹1 = 𝐴𝐵 + 𝐴𝐵′ 𝐶 + 𝐴′ 𝐵′ 𝐶 + 𝐴′ 𝐵𝐶 and 𝐹2 = 𝐴𝐵𝐶 + 𝐴′ 𝐵′ 𝐶 +

𝐴𝐶 ′ + 𝐴′𝐵𝐶
Solution: After reduction 𝐹1 = 𝐴𝐵 + 𝐶 and 𝐹2 = 𝐴′ 𝐶 + 𝐴𝐵 + 𝐴𝐶′
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3) PAL (Programmable Array Logic)

 AND gate is programmable & OR gates are fixed
 fan-in of each OR gate is fixed.
Steps:
1. Reduce the Boolean function write down in reduce SOP form.

2. Design all the reduce prime implicant by programmable AND gates at input side.
3. Connect the prime implicant present in given function to fixed OR gate at output side.
4. The minimum fan-in of OR gate is maximum prime implicant present in any reduce
Boolean function.
5. If fan-in of OR gate is more than the number of prime implicant in that function then
remaining input of OR gate connect to logic 0.
Ex. Design an Boolean function 𝐹1 = 𝐴𝐵 + 𝐵𝐶 + 𝐴𝐶 and 𝐹2 = 𝐴′ 𝐵′ 𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶′

Solution: After reduction 𝐹1 = 𝐴𝐵 + 𝐵𝐶 + 𝐴𝐶 and 𝐹2 = 𝐴′ 𝐵′ 𝐶 + 𝐴𝐵
The minimum fan-in of OR gate require is maximum prime implicant so here its 3 in F1.
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Problems:
1) How many 2 input NAND gate require to design of half adder
A) 6 B) 4 C) 5 D) 8
2) How many minimum 2:1 mux required to design 10:1 mux

A) 5 B) 7 C) 9 D) 11
3) If n= 5 then the range of m is (where ‘n’ is select line and ‘m’ is inputs)
A) (0, 31)
B) (1, 32)
C) (0, 32)
D) (1, 31)
4) The Boolean function realized by the logic circuit shown is (Where A

is MSB and D is LSB)
A) F= m(0,1,3,5,9,10,14) B) F= m(2,3,5,7,8,12,13)
C) F= m(1,2,4,5,11,14,15) D) F= m(2,3,5,7,8,9,12)
5) Find the f
A) A B) B C) 0 D) 1
6) What are the minimum number of 2- to -1 multiplexers required to generate a 2- input

AND gate and a 2- input OR gate respectively
A) 1 and 2 B) 2 and 1 C) 1 and 1 D) 2 and 2
7) Find the logic function f
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A) wx’y’z’+wxyz’ B) wx’y’z’+wxyz’+wxyz C) wx’y’z’ D) none
8) Find Y
A) D’(A’C+B’C) B) (A’B’C+A’BC+AB’C)’ C) 0 D) none
9) Encoder is used to convert
A) Binary to other code B) other code to binary C) both D) none
10) The gates required to build a half adder are
A) EX-OR gate and NOR gate B) EX-OR gate and OR gate
C) EX-OR gate and AND gate D) Four NAND gates.
11) The device which changes from serial data to parallel data is
A) Counter B) Multiplexer C) Demultiplexer D) Flip-Flop
12) A device which converts BCD to Seven Segment is called
A) Encoder B) Decoder C) Multiplexer D) Demultiplexer
13) The following switching functions are to be implemented using a Decoder:
f1=∑ m(1, 2, 4, 8, 10, 14) f2=∑m (2, 5, 9, 11) f3=∑m (2, 4, 5, 6, 7)
The minimum configuration of the decoder should be
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A) 2 – to – 4 line. B) 3 – to – 8 line. C) 4 – to – 16 line. D) 5 – to – 32 line.
14) The gate having two inputs (A, B) and one output (Y) is implemented using 4 to 1 mux as
shown in figure. A1 (MSB) and A0 are the control bits and I0-I3 are the inputs to the mux.
The gate is
A) NAND B) NOR C) XOR D) OR

15) The Boolean function F(A, B, C)=∏ (0, 2, 4, 7) is to be implemented using 4 x 1 mux
shown in the figure. Which one of the following choices of inputs to mux will realize the
Boolean function?
A) (I0, I1, I2, I3, S1, S0) =(1,0,A’,A,C,B) B) (I0, I1, I2, I3, S1, S0) =(1,0,A’,A,B,C)
C) (I0, I1, I2, I3, S1, S0) =(0,1,A’,A,C,B) D) (I0, I1, I2, I3, S1, S0) =(0,1,A,A’,B,C)
16) How many 2 to 4 line decoder with enable input are needed to construct a 4 to 16 line
decoder?
A) 4 B) 5 C) 6 D) 8
17) The function f(A, B, C, D) = ∑(5,7, 9, 11, 13, 15) is independent of variables
A) B B) C C) A and C D) D
18) An 8x1 mux has input A, B and C connected to the selection inputs S 2, S1 and S0
respectively. The data input I0 to I7 are as follows: I1=I2=I7=0; I3=I5=1; I0=I4=D; I6=D’. The
Boolean function that the mux implements is
A) f(A, B, C, D)=∑(1,6,7,9,10,11,12) B) f(A, B, C, D)=∑(0,3,4,5,11,12)
C) f(A, B, C, D)=∑(1,3,5,7,9,11,13,15) D) f(A, B, C, D)=∑(0,1,3,4,5,6,12)
19) Figure shown a 4 to 1 mux to be used to implement the sum S of a 1-bit full adder with
input bits P and Q and the carry input C. which of the following combination of inputs to
I0, I1, I2 and I3 of the mux will realize the sum S.
A) I0=I1=C; I2=I3=C’ B) I0=I1=C’; I2=I3=C’\ C) I0=I3=C; I2=I1=C’ D) I0=I3=C’; I2=I1=C

20) The output f of the 4 to 1 mux shown in the figure is
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A) (XY)’+X B) X + Y C) X’+Y’ D) XY + X’
21) Match the following:
List –I List – II
P. Full adder 1. Sequential digital circuit
Q. Multiplexer 2. One bit adder
R. Read/write Memory 3. Two bit adder
S. ROM 4. Universal gate
5. Universal element
6. Combination of decoder & demux
7. Combination of decoder & encoder
A) P-3,Q-5,R-1,S-7 B) P-2,Q-5,R-1,S-7 C) P-4,Q-1,R-7,S-2 D) P-4,Q-3,R-5,S-7
22) The following multiplexer circuit is equivalent to
A) implementation of sum equation of full adder

B) implementation of carry equation of full adder
C) implementation of borrow equation of full subtractor
D) all the above
23) A binary half-sub tractor having two inputs A and B, the correct set of logical expression
for the outputs D(= A minus B) and X (=borrow) are
A) D=AB+A’B, X=A’B B) D=A’B+AB’, X=AB’
C) D=A’B+AB’, X=A’B D) D=AB+A’B’, X=AB’
24) Full adder can be converted into full sub tractor with _______
A) An inverter B) A NAND gate C) A NOR gate D) All of these
25) To implement an n-variable Boolean equation, what is the minimum size of multiplexer
required
A) 2nx1 B) 2n-1x1 C) 2n+1x1 D) 2n-2x1
26) Assertion (A): A demultiplexer can be used as a decoder.
Reason (R): A demultiplexer is built by using AND gates only.
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27) Which one of the following statements correctly defines the full adder?
An adder circuit
A) Having 2 inputs used to add two binary digits. It produces their sum & carry as input.
B) Having 3 inputs used to add two binary digits plus a carry. It produces their sum &
carry as output.
C) used in the least significant position when adding two binary digits with no carry in to
consider. It produces their sum & carry as outputs.
D) Having two inputs and two outputs.
28) Which one of the following can be used as parallel to series converter?
A) Decoder B) Digital Counter C) Multiplexer D) Demultiplexer
29) Which of the below statements are correct for multiplexer
1. Select one of the several inputs and transmit it to a single output.
2. Routes the data from a single input to one of many output
3. Converts parallel data into serial data
4. Is a combinational circuit
A) 1,2 & 4 B) 2,3 &4 C) 1,3 &4 D) 1,2 &3
30) A 1-bit full adder takes 20ns to generate carry out bit and 40ns for the sum bit. What is
the maximum rate of addition per second when four 1-bit full adders are cascade?
A) 107 B) 1.25x107 C) 6.25x106 D) 105
31) If we have all gate expect XOR and XNOR gate then how many minimum number of gate
require constructing half adder.
A) 3 B) 4 C) 5 D) 2
32) PLA can be use as
A) to realize sequential logic B) counter
C) to realize combinational logic D) resister
Answers:
1. C 2. C 3. C 4. D 5. B 6. C 7. A 8. C 9. B
10. C 11. C 12. B 13. C 14. D 15. D 16. B 17. B 18. A
19. C 20. B 21. B 22. A 23. C 24. D 25. A 26. C 27. B
28. C 29. C 30. A 31. A 32. C 33. 34. 35. 36.
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GATE THE Direction Sequential Logic Circuits
CHAPTER VI
SEQUENTIAL LOGIC CIRCUITS
Combinational circuit: Combinational circuits are those whose output level at any instant of
time depends on only present inputs at that time.
Sequential circuit: sequential circuits are those whose output level at any instant of time
depends on present inputs and previous inputs or output or both. So sequential circuit has
memory element for storing previous inputs and output. F/F is basic element of memory so if
F/F is present in circuit then it is sequential otherwise it is combinational circuit.
Truth table or Characteristics table: It contain all the possible combination of inputs and
corresponding outputs.
Excitation table: It contain all the possible combination of outputs and corresponding possible
inputs.
Sequential Logic circuits

FLIP – FLOPS
Flip-Flop is the basic memory element. It can store one bit of information. It has two
outputs these are complement to each others. Flip-Flop is also called as Bistable multivibrator
because it has two stable states 0 and 1.
Basic design:
The basic design of latch come from cascade connection of inverters. In above fig. we connect
two inverter in cascade so it is design of bistable multivibrator. Its o/p is change iff i/p is change
otherwise o/p will be same i.e. store and it is the basic requirement of the flip/flop (the
connection of second diagram is as first one just representation is different). For designing basic
S-R latch the inverter design by using NOR & NAND gates as show below.
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S-R Latch using NOR gates: S R Qn Qn+1

0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 Not accepted
1 1 1 Not accepted
Here when S=R=1 then both the output Q and Q’ have same value as 0. But Q and Q’ are
compliment of each other so that S=R=1 condition is not acceptable in S-R latch using NOR
gates.
S-R Latch using NAND gates:

S R Qn Qn+1
0 0 0 Not accepted
0 0 1 Not accepted
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Here when S=R=0 then output Q=Q’=1. But actually Q and Q’ are compliment to each other so
S=R=0 is not acceptable in S-R latch using NAND gates.
S-R latch with enable:

Latch is the level trigger device.
Positive level trigger S-R latch Schematic of S-R latch
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Characteristics table of S-R latch:
S R Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 invalid
Characteristic equation: Qn+1 = S + R’Qn
Excitation table:
Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 x 0
Representation of clock:
Positive level trigger: The latch which respond to change in inputs when the clock is high
Negative level trigger: The latch which respond to change in inputs when the clock is low
Positive edge trigger: The flip-flop whose output is change only at positive edge of clock (i.e.
clock is changing from low to high).
Negative edge trigger: The flip-flop whose output is change only at negative edge of clock (i.e.
clock is changing from high to low).
 Truth table, excitation table is similar for latch and flip-flop (only difference is latch is
level trigger device and flip-flop is edge trigger device.)
 F/F’s are edge trigger device and latch’s are level trigger device.
Example: In following diagram, the frequency of clock is 10 kHz find frequency of output signal
Q.
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Answer: FQ = FClk/2 = 10k/2 = 5kHz
J-K latch:
Characteristics Table J K Qn Qn+1

0 0 0 0
J K Qn+1 0 0 1 1
0 0 Qn 0 1 0 0
0 1 0 0 1 1 0
1 0 1 1 0 0 1
1 1 Qn’ 1 0 1 1
1 1 0 1
Excitation table:
1 1 1 0
Qn Qn+1 J K
0 0 0 X
Characteristic equation: Qn+1 = K’Qn + JQn’
0 1 1 X
1 0 X 1
1 1 X 0
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Master – slave flip/flop:
Fig: Negative edge trigger J-K flip/flop
Here we design the flip-flop (master-slave) by using to positive level trigger latch.
When clk (clock) is high
 the master is active but slave is not active so any change in inputs at that time will
change the output of master but not affect the output of slave.
When clk is low
 the master is not active but slave is active so any change in inputs at that time will not
change the output of master so input to slave is not change (since output of master is
input to slave) so output of the slave also not change since inputs to slave is not change.
So the output of slave(in above dig.) is change only when clk is transit from high to low so it is
negative edge trigger master slave flip-flop.
Example1: In following circuit if clock frequency is 10 kHz find the frequency at output Q.
Answer: FQ = FClk/2 = 10k/2 = 5kHz
Example 2: In above circuit initially Q=0. Find Q after 5 clock pulse.
Sol: After 1st clock Q n+1-------1 (J=Q’n=1; K=Qn=0 so Qn+1=1)
After 2nd clock Qn+1-------0 (J=Q’n=0; K=Qn=1 so Qn+1=0)
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After 3rd clock Qn+1-------1 (J=Q’n=1; K=Qn=0 so Qn+1=1)
After 4th clock Qn+1-------0 (J=Q’n=0; K=Qn=1 so Qn+1=0)
After 5th clock Qn+1-------1 (J=Q’n=1; K=Qn=0 so Qn+1=1)
Example 3: In following circuit initially Q=0. Find Q after 10 clock pulse.
Sol: J=Q=0 and K=Q’=1
So that Qn+1=0 (always)
Example 4: In following circuit initially Q=0. Find Q after 4 clock cycle.
Sol: Here J=K=1 So Q n+1=Qn’
After 1st clock Q-------1
After 2nd clock Q-------0
After 3rd clock Q-------1
After 4th clock Q-------0
D Flip-flop:
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Characteristic table:
D Qn Qn+1
D Qn+1 0 0 0
0 0 0 1 0
1 1 1 0 1
1 1 1
Characteristics Equation: Qn+1=D
Excitation table:
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
 Just connect the input D to S and D’ to R for design D F/F from S-R F/F.
 Just connect the input D to J and D’ to K for design D F/F from J-K F/F.
Example 1: What will be the output after 5 clock cycle if initially Q=1.
Sol: For D F/F Qn+1=D
Here D=Q
So that Qn+1= Q = 1 (always)
Example 2: What will be the output after 10 clock cycle if initially Q=1.
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Sol: For D F/F Qn+1=D
Here D=Q’
So that Qn+1=Q’
After 1st clock Qn+1= 0
After 2nd clock Qn+1= 1
After 3rd clock Qn+1= 0
Similarly After 10th clock Qn+1= 1
T Flip-flop:
Characteristic table:
T Qn Qn+1
T Qn+1 0 0 0
0 Qn 0 1 1
1 Qn’ 1 0 1
1 1 0
Characteristics Equation: Qn+1 = TQn’ + T’Qn
Excitation table:
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
 S-R F/F is not used to design the T-f/f since S =R = 1 is invalid state.
 Just connect the input T to J and K for design T F/F from J-K F/F.
Conversion of Flip-flop:
 Write the characteristics of the Flip-flop which is to be design
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 write the excitation table of available Flip-flop
1. S-R Flip-flop to J-K Flip-flop
J K Qn Qn+1 S R
0 0 0 0 0 x
0 0 1 1 X 0
0 1 0 0 0 x
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 X 0
1 1 0 1 1 0
1 1 1 0 0 1
Simplify S and R by k-map  S= JQn’ and R=K’Qn
Similarly we can convert any Flip-flops to any other flip-flop.
2) S-R Flip-flop to D Flip-flop: S=D and R=D’
3) S-R Flip-flop to T Flip-flop: S= TQn’ and R=TQn
4) J-K Flip-flop to S-R Flip-flop: J=S and K=R and SR=0
5) J-K Flip-flop to D Flip-flop: J=D and K=D’
6) J-K Flip-flop to T Flip-flop: J=K=T
7) D Flip-flop to S-R Flip-flop: D= S + R’Qn
8) D Flip-flop to J-K Flip-flop: D= JQn’ + K’Qn
The input S-R, D, J-K is called synchronous input because Flip-flops are edge trigger device i.e.
output is change only at the occurrence of edge of clock (positive edge or –ve edge) i.e. the Flip-
flop output is synchronizing with edge of clock input.
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Asynchronous input to Flip-flop:
Preset: It set the output of Flip-flop i.e. Q=1. It don’t wait for edge of
clock signal and irrespective of input.
Clear: It reset the output of Flip-flop i.e. Q=0. It don’t wait for edge of
clock signal and irrespective of input.
Counters:
Counters are the sequential circuit, they are use to count number of pulse applied to
them, frequency divider, time measurement in digital watches, distant measurement in RADAR.
If N-number of Flip-flops are used in counter then 2n is maximum numbers of possible states. If
counter uses all possible state then it is also called as binary counter and if it uses less number
of states then it called as non binary counter.
The number of state of counter is represented by the modulus, so if counter has ‘N’
number of stage then it is called as MOD-N counter. If frequency of applied signal is Fclk Hz then
output frequency of MOD-N counter is Fclk/N.
Two type of counter are there:
1. Synchronous Counter: In a synchronous counter, the same clock is applied to all flip flops
simultaneously (directly). Synchronous counter is also known as parallel sequential circuit.
Examples of Synchronous Counters are as below:
 Ring Counter
 Johnson Counter (Switch Tail or Twisted Ring Counter)
Asynchronous Counter
In an asynchronous counter, the flip flop output act as clock of other flip flops i.e. clock to all
the flip-flop is different. Asynchronous counter is also known as serial sequential circuit.
Example of Asynchronous Counters are as below:
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 Binary Ripple Counter
Mod: The number of different states used is nothing but the mod of counter.
Synchronous counter Asynchronous counter

1. Same clock to all flip-flop is provide 1. Different clock to different flip-flop is provide
2. It is faster than Asynchronous counter 2. It is slower than synchronous counter
3. No intermediate stages are present 3. Intermediate stages are present
4. Only fixed sequence can be realized 4. Any sequence can be realized
Ripple counter:
1. Ripple UP-counter:
These counter are asynchronous type. The ripple UP-counter is shown below:
The external clock is applied to only one Flip-flop then output of that flip-flop take as LSB. The
above counter has 3-F/F so it has maximum 23=8 states. Here we are using all states so it is
binary counter also called MOD-8 counter. Here we used either J-K F/F of T-F/F for designing
ripple counter with J=K=1 or T=1 so at the occurrence of edge of clock the output of that F/F
toggle (i.e. if previous output is 0 then next output become 1 and vice versa). The clock and
output waveform at the output of all the f/f are given below. In this counting is increasing as 0,
1, 2 etc so its called as up counter.
Clk QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
100
6 1 1 0
7 1 1 1
8 0 0 0
2. The Ripple DOWN-counter: It is shown below
Clk QC QB QA
 In this counting is decreasing
0 0 0 0 as 7, 6, 5 etc so its called as down counter.
1 1 1 1  In down counter +ve edge
2 1 1 0 trigger f/f is used
3 1 0 1  In up counter -ve edge trigger
4 1 0 0 f/f is used
5 0 1 1  In ripple counter
6 0 1 0 (Asynchronous counter) the worst case
7 0 0 1 propagation delay is n.tp i.e. tpcount = n.tp. Where
8 0 0 0 n: number of f/f and tp: propagation delay of each
f/f.
 Therefore maximum frequency of clock that that can be apply to ripple counter is
𝟏 𝟏
Fclk max = =
𝒕𝒑𝒄𝒐𝒖𝒏 𝒏.𝒕𝒑
Example.1: In above counter each Flip-flop has delay of t pd. So find the maximum frequency of
clock pulse
Solution: For worst case resultant output will come after 3 t pd sec. so time period of clock tclk ≥
3 tpd
1 1
So that Fclk ≤ 3𝑡 so Fclk(max) = 3𝑡𝑝𝑑
𝑝𝑑
If strobe time or strobe signal is used then
101
1
Fclk ≤ 3𝑡 +𝑡
𝑝𝑑 𝑠𝑡𝑟𝑜𝑏𝑒
Strobe: It is input signal given to observe the permanent output. If n-Flip-flop are used and each
have delay of tpd then strobe signal should be apply after ntpd time.
Example.2: In 4-bit ripple counter propagation delay of each Flip-flop is 25 nsec what is
maximum clock frequency that can applied
1 1
Fclk(max)= = = 10 MHz
4𝑡 𝑑 4×25×10 −9
In ripple counter J-K Flip-flop are used and J=K=1 and same counter can be made using T Flip-
flop with T=1. It can also be implemented using D and S-R Flip-flop.
Ring counter:
Ring counter is synchronous counter. It is serial in serial out counter. It is also called as
end carry counter. One limitation in this counter is that first we have to ON it by applying 1 as
input, so this counter is not self starting counter.
Clk Q3 Q2 Q1 Q0 In table we can see that it repeats after

0 0 0 0 0 every 4 states. Since 0000 will not come
1 1 0 0 0 again so it is MOD-4 counter having four
2 0 1 0 0 Flip-flops. The ring counter is MOD-n
3 0 0 1 0 counter if n is the number of Flip-flop.
4 0 0 0 1 Since above counter is MOD-4 counter
5 1 0 0 0 so output frequency of last flip-flop is
Fclk/4 Hz and as it is synchronous counter
so output frequency of all flip-flop is same.
 D-f/f is used for the design of Ring counter.

 It is synchronous counter, so the maximum frequency that can be use is
𝟏
𝑭𝒎𝒂𝒙 = 𝒕 (Delay of synchronous counter is the delay of one f/f).
𝒑
 By using n-f/f total possible states are 2n and in ring counter used state are only ‘n’, so
Total unused states = total states – used states
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Total unused states = 2n – n

 Here all states are not used so it is non binary type of counter.
Uses of ring counter:
1. Analog to digital convertor 2. Stepper motor control
3. Control signal generation like interrupt in microprocessor
Twisted Ring Counter:

It is also called as Johnson counter, switch tail ring counter, creeping counter.
Clk Q3 Q2 Q1 Q0 Here 0000 state repeat itself so it contain

0 0 0 0 0 total 8 states therefore, it is MOD-8 counter
1 1 0 0 0 with four counters.
2 1 1 0 0
The twisted ring counter is MOD-2n if n
3 1 1 1 0
number of flip-flop is used.
4 1 1 1 1
5 0 1 1 1 The output frequency of above MOD-8
6 0 0 1 1 Johnson counter is Fclk/8.
7 0 0 0 1
8 0 0 0 0 In ring counter and twisted ring counter if
9 1 0 0 0 delay of each flip-flop is td then clock
frequency will be Fclk ≤ 1/tp (Science they are
synchronous counter; for any synchronous counter Fclk ≤ 1/tp )
 D-f/f is used for the design of twisted Ring counter.

 It is synchronous counter, so the maximum frequency that can be use is
𝟏
𝑭𝒎𝒂𝒙 = 𝒕 (Delay of synchronous counter is the delay of one f/f).
𝒑
 By using n-f/f total possible states are 2n and in twisted ring counter used state are only
‘2n’, so
Total unused states = total states – used states
Total unused states = 2n – 2n
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 Here all states are not used so it is non binary type of counter.
Design of given sequence:
1. From the given sequence we can find out minimum number of f/f require for design (as
number of count ≤ 2𝑛 , 𝑤𝑕𝑒𝑟𝑒 𝑛: 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑓/𝑓)
2. Write down all possible state
3. Write down corresponding next state
4. Used excitation table.
Example: Given circuit of 2-bit counter using T- flip-flop giving the following sequence 0,2,3,1,0
and so on.
To complete the circuit input at X should be
1) Q1+Q2 2) Q1Q2 3) Q1 XOR Q2 4) Q1 XNOR Q2
Solution:
 Here total different states are four so min 2 f/f require.

 Write down all the states and corresponding next state and excitation table.
Previous state Next state

Q1 Q2 Q 1+ Q 2+ T1 T2
T2= Q1’Q2 + Q1Q2’ = Q1 XOR Q2
0 0 1 0 1 0
0 1 0 0 0 1 T1=X=Q1’Q2’ + Q1Q2 = Q1 XNOR Q2
1 0 1 1 0 1
1 1 0 1 1 0
Example: Design MOD-10 ripple up counter
In MOD-10 counter there will be 10 states from 0000 to 1001 and number of flip-flop required
are four so in this counter we want 0000 outputs after 1001.
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Clk Q3 Q2 Q1 Q0 In this truth table we can see that the output

0 0 0 0 0 after 10th clock pulse should be 0000 instead of
1 0 0 0 1 1010 so we have to make Q3 and Q1 zero since
2 0 0 1 0 Q3 and Q1 are not one together before that so
3 0 0 1 1 we will AND the Q3 AND Q1 and output is
4 0 1 0 0 connected to clear (suppose clear signal is
5 0 1 0 1 active high). So when Q3 and Q1 both are 1
6 0 1 1 0 then all flip-flop will reset and counter will start
7 0 1 1 1 from 0000 once again.
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 0 0 0 0
The frequency of output at Q3 is F/10 which is obvious since it is MOD-10 counter.
Register:
Register are use to store the information in binary form. For storing 1 bit information require 1
flip-flop. In storage register mostly D flip-flop is used.
Base on input and output techniques register can be classified in four type:
1) SISO 2) SIPO 3) PISO 4) PIPO
1) SISO (Serial in serial out):
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If we have to enter data 1101
Clk Q3 Q2 Q1 Q0 To write n-bit number we require n clock

0 0 0 0 0 pulse
1 1 0 0 0
To read n-bit number we require n-1 clock
2 0 1 0 0
pulse
3 1 0 1 0
4 1 1 0 1 Once we read data, the data will be lost
2) SIPO (Serial in parallel out):
Suppose we have to enter data 1010 then
Number of clock pulse require to write the data = 4
Number of clock pulse require to read the data = 0 (since data is available in parallel)
 To write n-bit number we require n clock pulse

 To read n-bit number we require 0 clock pulse
It is use as serial to parallel convertor
It can also be used as SISO if output is taken from Q0 only
Example: The clock shown in figure is SIPO with initial data 1010 after 3 clock pulse the data
present in the register will be
Sol:
106
After 1st clock: 1101
After 2nd clock: 1110
After 3rd clock: 1111
Example: In 4-bit SISO register, 8-bit data is applied serially. Minimum number of clock pulse
required to get total data output serially.
Sol: Here 1st bit applied to register will be available at output after 4th clock so 2nd bit after 5th
clock similarly 8th bit will available after 11 clock pulse.
Example: The shift register show in figure has 1010 initially after how many clock pulses the
content of shift register will become 1010
(Ans: 7)
3) PISO (Parallel in serial out):
If we have to enter data 1001
Number of clock pulse required to enter data: 1 (As data enter in parallel)
Number of clock pulse requires to read data: (n-1) (for above example clock pulse require is 3)
For n bit data to enter we require n flip-flop and only one clock pulse is required and for reading
data n-1 clock pulse are required since data can be read serially only. Here MUX is used
between Q3 and I2, Q2 and I1, Q1 and I0 when input is to be given then MUX is used to select the
input line I0, I1, I2, I3, and when output is to be taken then MUX is used to select the output of
each flip-flop Q3, Q2, Q1.
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PISO is used as parallel to serial convertor.
4) PIPO (Parallel in parallel out):
Here data is given in parallel and taken in parallel
For n-bit data
Number of clock pulse required to enter data is 1
Number of clock pulse required to read data is 0
Here it seems that flip-flops are of no use but these flip-flops store the data bit as long as we
want.
PIPO register is actually not a shift register because all flip-flop are individual. It is the fastest
register. This register is used mostly in microprocessor
108
Problems:
1) Which of the following is not a shift resister?
A) SISO B) SIPO C) PISO D) PIPO
2) Number of comparator required for 8 bit flash type ADC
A) 127 B) 7 C) 255 D) 256
3) What will be sequence of output (Q0 Q1)
A) 00,10,01,00,10 B) 00,10,10,00,01 C) 00,01,11,00,01 D) 00,00,11,00,10
4) For the circuit shown in figures below, two 4 - bit parallel - in serial - out shift registers
loaded with the data shown are used to feed the data to a full adder. Initially, all the flip -
flops are in clear state. After applying two clock pulses, the output of the full-adder
should be
A) S = 0, C0 = 0 B) S = 0, C0 = 1 C) S = 1, C0 = 0 D) S = 1, C0 = 1
5) Initially S=R=0 and after that S change as 1,0,1,0,1 then what will be the corresponding
output Q
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A) 10101 B) 11101 C) 11111 D) 00000
6) In following circuit initially Q=0. Find Q after 4 clock cycle.
A) 1 B) 0 C) any D) depend on propagation delay
7) D Flip-flop to S-R Flip-flop
A) D= S + R B) D= S + R’ C) D= S D) D= S + R’Qn
8) Given circuit of 2-bit counter using T- flip-flop giving the following sequence 0,3,2,1,0 and
so on.
To complete the circuit input at X should be
A) Q1’ B) Q2’ C) Q1 XOR Q2 D) Q1 XNOR Q2
9) Find output frequency of MSB F/F if clk frequency is 1 MHz
A) 1/10 MHz B) 1/11 MHz C) 1/13 MHz D) 1/12 MHz
10) Sequential circuits are essentially
A) Asynchronous circuits B) Astable multivibrators
C) With memory D) Synchronous circuits
110
11) In a JK flip-flop the output state will toggle only when
A) J = 1, K = 0 B) J = 0, K = 1 C) J = 0, K = 0 D) J = 1, K = 1
12) The given figure shows a ripple counter using -ve edge triggered flip-flops. If the present
state of the counter is Q2Q1Q0 = 011 then is next state Q2Q1Q0 will be
A) 111 B) 010 C) 100 D) 110
13) Soppose in the above dig. We use positive edge trigger f/f. If the present state of the
counter is Q2Q1Q0 = 011 then is next state Q2Q1Q0 will be
A) 111 B) 010 C) 100 D) 110
14) A master - slave flip flop has the characteristic that
A) Change in the input immediately reflected in the output
B) Change in the output occurs when the state of the master is affected
C) Change in the output occurs when the state of the slave is affected
D) Both the master and the slave states are affected at the same time
15) What will be output of flip-flop if initially they are reset?
A) 00, 11, 11, 11, 11 B) 00, 10, 01, 00 C) 00, 11, 00, 11 D) 00, 01, 11, 00
16) Initially D-flip flop is clear and SISO shift resister is filled with 01011100 then what will be
data available in shift resister after 3 Clock
111
A) 11100000 B) 01011000 C) 11100010 D) none
17) Minimum number of flip-flop require to construct MOD-20 counter

A) 20 B) 4 C) 5 D) 19
18) How many Flip-Flops are required for mod–16 counter?
A) 5 B) 6 C) 3 D) 4
19) Data can be changed from special code to temporal code by using
A) Shift registers B) counters C) Combinational circuits D) A/D converters.
20) A ring counter consisting of five Flip-Flops will have
A) 5 states B) 10 states C) 32 states D) Infinite states.
21) In a JK Flip-Flop, toggle means
A) Set Q = 1 and Q’ = 0.
B) Set Q = 0 and Q’ = 1.
C) Change the output to the opposite state.
D) No change in output.
22) A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each.
The maximum possible time required for change of state will be
A) 15 ns. B) 30 ns. C) 45 ns. D) 60 ns.
23) How many flip flops are required to construct a decade counter
A) 10 B) 3 C) 4 D) 2
24) Shifting a register content to left by one bit position is equivalent to
A) Division by two. B) Addition by two.
C) Multiplication by two. D) Subtraction by two.
25) The sequence (Q2Q1) generated by the following ckt (initially Q2Q1 = 00).
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A) 00, 11, 01, 01, 01 B) 00, 01, 01, 01, 01 C) 00, 11, 00, 11, 00 D) 00, 01, 00, 01, 00
26) What will be the Y after four clock pulse and also type of circuit.
A) synchronous, Y= 0 B) synchronous, Y= 1
C) Asynchronous, Y= 0 D) Asynchronous, Y= 0
27) The following ckt is
A) a MOD–2 counter B) a MOD–3 counter

C) a MOD–4 counter D) a MOD–1 counter
28) The following ckt is (if initially QCQBQA)
A) a MOD–2 counter B) a MOD–4counter

C) a MOD–6 counter D) a MOD–8 counter
29) Find the frequency at Q4 and Fclk = 1 MHz
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1 1 1 1
A) 25 𝑀𝐻𝑧 B) 24 𝑀𝐻𝑧 C) 32 𝑀𝐻𝑧 D) 23 𝑀𝐻𝑧
30) Find the output frequency
A) 125 Hz B) 250 Hz C) 500 Hz D) 1 kHz

31) If initially Q2 Q1 Q0 =000 then find them after two clock pulse
A) 100 B) 101 C) 110 D) 010

32) A 5 bit ripple counter and a 6 bit synchronous counter are made by flips flops having a
propagation delay of 5 ns each. If the worst case delay in the ripple counter and the
synchronous counter be A and B respectively, then
A) A= 5 ns, B= 5 ns B) A= 5 ns, B= 30 ns
C) A= 25 ns, B= 30 ns D) A= 25 ns, B= 5 ns
33) A 2- bit modulo–3 ripple counter uses JK flip-flop. If the propagation delay of each FF is
50 ns, the maximum clock frequency that can be used is equal to
A) 10 MHz B) 20 MHz C) 6.66 MHz D) 3.33 MHz
34) The initial contents of the 4-bit serial-in-parallel-out right-shift, register as shown below
is 1010. After four clock pulses are applied, the contents of the shift register will be
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A) 1011 B) 0111 C) 1111 D) 1110

35) Find the unused state in mod-10 twisted ring counter
A) 10 B) 22 C) 5 D) 1014
36) If the input to T-flip-flop is 1000 Hz signal, the final output output frequency of the three
T-flip-flops in cascade is
A) 1000 Hz B) 500 Hz C) 333 Hz D) 125 Hz
37) In synchronous counter
A) input frequency of all f/f is same and output frequency is different
B) input frequency of all f/f is different and output frequency is same
C) Both input and output frequency of all f/f is same
D) Both input and output frequency of all f/f is different
38) For JK flip flop with J=1, K=0, the output after clock pulse will be
A) 0 B) 1 C) high impedance D) no change
39) An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds.
The
pulse width of the strobe is 50ns. The frequency of the input signal which can be used for
proper operation of the counter is approximately
A) 1.5 MHz B) 500 MHz C) 2 MHz D) 4 MHz
40) Race around condition occur in S-R f/f when
A) S=1, R=1 B) S=0, R=0 C) either A or B D) never
Answers:
1. D 2. C 3. A 4. B 5. C 6. B 7. D 8. A 9. C
10. C 11. D 12. C 13. B 14. C 15. C 16. A 17. C 18. D
19. A 20. A 21. C 22. A 23. C 24. C 25. A 26. B 27. B
28. A 29. B 30. A 31. C 32. D 33. A 34. C 35. B 36. D
37. C 38. B 39. A 40. D
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GATE THE Direction ADC and DAC
CHAPTER VII
ADC and DAC
Digital to Analog convertor (DAC):

OPAMP in open loop act as one bit quantizer.
V1 > V2 V0 = Vsat (Logic ‘1’)
V1 < V2 V0 = -Vsat (Logic ‘0’)
Resolution: It is the change in analog voltage at the output corresponding to one LSB change in
digital input
The output voltage correspond to the digital input one is nothing but resolution of DAC.
𝑽𝒓𝒆𝒇
 Resolution =
𝟐𝒏 −𝟏
𝟏
 % Resolution = *100
𝟐𝒏 −𝟏
Example: A 4-bit D/A convertor has reference voltage 5 V. Find the resolution.
𝑉𝑟𝑒𝑓 5 1
Solution: Resolution = = = V
2𝑛 −1 24 −1 3
 Analog output voltage = Digital input x Resolution
Example: 4-bit DAC and voltage corresponding to 1000 is 6 V. find the resolution and voltage
corresponding to 0101
Here 1000 (8) 6V
So for 0001 (1)  6/8 = 3/4 V
So resolution (The voltage correspond to 1) = ¾
116
Voltage corresponding to 0101 (5) is Resolution x digital number = 3/4 x 5 = 15/4 V
Example: 8 bit DAC produces 0.05 V for digital input 000000001 find resolution and V out for
input 00101010
Here resolution is 0.05 V (The voltage correspond to 1)
Voltage corresponding to 00101010 i.e . (42)10 is
Resolution x digital number = 42 x 0.05 = 2.1 V
1. Weighted Resistor type D/A:
It is a 4 bit D/A convertor here maximum value of resistor used is 24-1 R = 23 R = 8R
There for n-bit Maximum value of resistance that is used will be 2n-1 R
To apply 1 at b0, b1, b2, b3 we connect that them to +5 V and to apply 0 at b0, b1, b2, b3 connect
them to the ground.
 Logic ‘1’ ---> Vref

 Logic ‘0’ ---> Gnd
Here:
V ref V ref V ref V ref
I = b0 + b1 + b2 + b3
8R 4R 2R R
Rf b3 b2 b1 b0
V0 = -IRf = - Vref [ + + + ]
R 1 2 4 8
For n-bit
Rf n−1 bi
V0 = - Vref i=0 ( )
R 2 −1−i
n
Disadvantage: 1. Value of resistor goes on increase as number of bits increasing
2. Due to use of different resistor the accuracy is less
117
3. The linearity of this DAC is less
4. i/p impedance is not constant (by looking from different bits)
Ex. Find the output voltage of Weighted Resistor type 4-bit DAC. As Vref = 5 V and digital i/p is
1101 (R = 2Rf).
Rf b3 b2 b1 b0 R 1 1 0 1
Solution: V0 = - Vref [ + + + ]= - 5 2Rf [ 1 + + + 8 ] = 4.0625 V
R 1 2 4 8 f 2 4
2. R-2R Ladder type DAC
Here we can see that only two type of resistor of values R and 2R
If we apply 1000 s input [+5V as 1 and ground as 0] then

equivalent circuit is
5 x 2R 5
V1 = = V
4R 2
5
V0 = V1 = V
2
O/p voltage to 1000 applied digital i/p is 5/2 V.
i.e. If we apply Vref at D3 then output due to D3 only will be Vref/2
Similarly if we apply Vref at D2 then output due to D2 only will be Vref/4
As op-amp is linear device so the response due to all i/p is just addition of response due to
individual i/p’s.
𝑫𝟑 𝑫𝟐 𝑫𝟏 𝑫
Therefore VO= Vref + + + 𝟏𝟔𝟎
𝟐 𝟒 𝟖
118
More generalize form as:

𝑫𝒏−𝟏 𝑫𝒏−𝟐 𝑫𝒏−𝟑 𝑫
VO=Vref + + … … 𝟐𝒏𝟎
𝟐𝟏 𝟐𝟐 𝟐𝟑
Example: If we applied input 0101 and Vref=5V then what will be the output voltage.
𝑫𝟑 𝑫𝟐 𝑫𝟏 𝑫 𝟎 𝟏 𝟎 𝟏
Sol: V O= Vref + + + 𝟏𝟔𝟎 = 5 + 𝟒 + 𝟖 + 𝟏𝟔
𝟐 𝟒 𝟖 𝟐
VO=1.5625 V
Analog to Digital Convertor:

There is always loss of information when we convert analog signal to digital and whole analog
signal never converted into digital, only sample of analog signal are converted into
corresponding digital value.
If resolution of DAC is decrease then accuracy will be increased.
1. Digital Ramp type or counter type:
It is simplest type of ADC
To convert analog signal to digital first of all samples of analog signal is taken and these
sample are converted into corresponding value of Digital.
The sampling frequency is fs ≥ 2fm (Nyquist criteria)
Here the sample take is given as voltage Va input to OPAMP. Initially ripple counter is set to
0000. Here 4-bit counter is used so that input to DAC is 0000 and output from DAC will be 0 V
which compare with Va and when Va > Vb the V0 = + Vsat and which is input given to the AND gate
the output of AND gate is high so clock is applied to counter so value of counter is increase by 1
and corresponding voltage comes out from DAC which again compare with V a. If Va > Vb the
process is goes on as discuss above till Va < Vb. When Va < Vb then V0 = -Vsat and then clock will
not applied and value at the output of counter will be the corresponding digital value to sample
of analog signal.
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Conversion time (tc): Time require to convert analog voltage (sample) to corresponding digital
value.
 1st analog sample should be converted into corresponding digital before the occurrence
of next analog sample.
So tc ≤ ts There tcmax = ts (where ts is time period between two sample taken i.e. t s =
1/fs)
 Here 𝑫𝒊𝒈𝒊𝒕𝒂𝒍 𝒐𝒖𝒕𝒑𝒖𝒕 × 𝑹𝒆𝒔𝒐𝒍𝒖𝒕𝒊𝒐𝒏 > 𝑉𝒂
Maximum conversion time (tcmax) = (2n - 1)Tclk
(For 4-bit counter maximum output is 1111 so maximum time that it will take to convert a
sample into digital is (24 - 1)Tclk = 15 Tclk)
Here as number of bit increase, then number of clock pulse required also increase and ADC
become slow. The counter reset after each conversion. Conversion time depend on magnitude
of analog signal. It is said counter type because here counter is used and digital ramp because
output of counter is ramp type.
Ex: Determine maximum conversion time that an ADC can have, if it is used to convert signal in
the range of 1 kHz to 50 kHz.
Solution: fs = 2x fm = 2x50 kHz = 100 kHz (Where fm = maximum massage frequency)
ts = 1/fs = tcmax = 1/100k = 10 us.
2. SAR (Successive Approximation Register Type):
EOC: End of conversion
SOC: Start of conversion
It is most popularly used ADC
120
In Digital ramp type ADC conversion time depend on magnitude of signal.
In successive approximation register type ADC conversion time does not depend on
magnitude of sample.
When SOC pin is on then MSB will set and corresponding analog voltage (Vb) will get at the
output of DAC that compare with analog sample voltage (Va) if
 Va > Vb (i.e. o/p of comparator is +Vsat) then MSB bit (‘1’) is not change.
 Va < Vb (i.e. o/p of comparator is - Vsat) then MSB bit is reset (‘0’).
This will decide is MSB is ‘1’ or ‘0’ and all the other bits are also check by same way one by one from
MSB to LSB.
 Its conversion time is tc = ‘n TClk’ (n number of o/p digital bits)

Ex. Convert the analog sample Va = 3.4 V. Suppose resolution of DAC is 1 V.
Solution: When SOC pin is ‘on’ D3 (msb) will set first and we get 1000. DAC convert it into
analog signal of 8V (as 1V resolution) Since 3.4 V < 8. So -Vsat input goes to control circuit (so
MSB become reset and we check next bit) and so next output will be 0100 (D2 set) and output
of DAC is 4V. Then 3.4 < 4 V and then again output from SAR will be (0010) and output of DAC is
2V and 3.4 > 2 then output from SAR will be (0011) = 3V then the output for sample 3.4 will be
0011. For any input voltage between 3 to 4 V the corresponding digital output will be 0011
 Here 𝑫𝒊𝒈𝒊𝒕𝒂𝒍 𝒐𝒖𝒕𝒑𝒖𝒕 × 𝑹𝒆𝒔𝒐𝒍𝒖𝒕𝒊𝒐𝒏 < 𝑉𝒂
Link question:
Ex: If 4 bit ADC is used with clock frequency of 2 MHz, then find the maximum conversion time
A) 2 us B) 7.5 us C) 15 us D) 1 us
Sol: Tc=nTclk= 4 x 1/(2X106)=2x10-6 = 2us
Ex: What will be the maximum frequency of input analog voltage that can be safely converted
into digital output?
A) 250 kHz B) 1000 kHz A) 500 kHz A) 2 MHz
Sol: Fsampl(max)=1/ Tc = 500 kHz
Fanolog (max)= Fsampl(max)/2 = 250 kHz
121
3. Flash type analog to digital convertor:
It is also called parallel type or parallel comparator type analog to digital convertor.
It is fastest type of ADC.
In this ADC no clock is required; therefore it is the fastest ADC. The conversion takes place
continuously. The delay occurs is in the comparator and the priority encoder.
Suppose Vcc= 8 V and Va=3.5V then Vcc will divide in the resistor connected in series and
Va is applied to each comparator therefore each comparator will compare 3.5V with other
voltage and give the corresponding output. The output of last 3 comparator will be logic 1.
Since priority encoder will select the input line according to the priority. Here highest
priority is D3; therefore output will be logic 011.
Here since vref= 8V so this ADC will give output 011 for input (3.00001 to 3.9999). if we
want to increase accuracy then we have to reduce the value of v ref but then we cannot convert
high amplitude analog signal into digital or we have to use more number of bits (also
hardware).
Disadvantages
1. It has complex circuitry since for n-bit it uses 2n-1 comparator, 2n resistor and priority
encoder.
2. It is most expensive.
Advantages
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1) It is fastest ADC
2) No clock is required
3) It is very useful for high freq.
4. Dual Slope Integrating type ADC:
This is the slowest but most accurate type ADC being most accurate it is used in measuring
instrument like multimeter where slow conversion is not a problem.
Here assume counter is reset. The input sample is applied to negative terminal of OPAMP. Since
1st OPAMP act as integrator it will integrate the Va till counter reach 1111. Let this time be T1.
𝟏 𝑽
Output of integrator is V0 = − 𝑹𝑪 𝑽𝒊𝒏 𝒅𝒕 = − 𝝉𝒂 𝑻𝟏 Where T1 = 2n Tclk and 𝜏 = 𝑅𝐶
The reference voltage which is taken as negative if Va is positive and it is applied to integrator.
Then since - VR is negative then it will integrate in opposite direction and the V0 tend toward
zero. The time at which V0 become zero is counted by counter and it is the corresponding output
value to the input analog sample.
Here it is clear that T1 = 2n Tclk and T2 =NTclk
Where N: number of clock that counters count when output reaches from –VaT1/𝜏 to 0.
Here – VR is applied when V0 = –VaT1/𝜏 (i.e. it’s a initial voltage)
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1 1 𝑉𝑎 𝑇1 1
V0 =− 𝑅𝐶 𝑉𝑖𝑛 𝑑𝑡 + 𝑐′ = − 𝜏 −𝑉𝑅 𝑑𝑡 − = 𝜏 𝑉𝑅 𝑇2 − 𝑉𝑎 𝑇1 /𝜏 Where 𝜏 = 𝑅𝐶 and c’ is
𝜏
initial voltage (integration constant)
When o/p become zero T2 =NTclk

1
0 =𝜏 𝑉𝑅 𝑇2 − 𝑉𝑎 𝑇1 /𝜏
𝑉𝑅 𝑇2 = 𝑉𝑎 𝑇1 𝑡𝑕𝑒𝑟𝑒𝑓𝑜𝑟𝑒 𝑉𝑅 𝑁𝑇𝑐𝑙𝑘 = 𝑉𝑎 2𝑛 𝑇𝑐𝑙𝑘

𝑵𝑽𝑹
∴ 𝑽𝒂 = 𝑎𝑠 2𝑛 & 𝑉𝑅 𝑎𝑟𝑒 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝟐𝒏
∴ 𝑽𝒂 ∝ 𝑵
 The maximum value of the N is 2n-1

 Total conversion time (Tc) = T1+T2
 Maximum conversion time (Tcmax) = T1+T2max = 2n Tclk+(2n -1)Tclk = (2n+1 -1)Tclk
Tcmax = (2n+1 -1)Tclk
note:
 In flash ADC, clk is not use

 In flash ADC and dual slope ADC the DAC is not used
 Flash type ADC is fastest type and most complex
 Dual slope type ADC is slowest and most accurate
 SAR and Flash type DAC convert all voltage of different amplitude into same time.
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Problems:
1) A weighted resistor digital to analog converter using N bits requires a total of
A) N precision resistors. B) 2N precision resistors.
C) N + 1 precision resistors. D) N – 1 precision resistor.
2) A 4 - bit D/A converter is connected to a free - running 3 - big UP counter, as shown in the
following figure. Which of the following waveforms will be observed at V0 ?
3) Find output of weighted resister type DAC if digital input is 1101
65 55
A) 16 V B) 16 V C) 5 V D) Depend on R and Rf value
4) What will be minimum Fclk for 8 bit Successive approximation register type ADC having
sampling time of Tsample=8ns
A) 1 GHz B) 25M Hz C) 125MHz D) 200MHz
5) The speed of conversion is maximum in
A) Successive-approximation A/D converter.
B) Parallel-comparative A/D converter.
C) Counter ramp A/D converter.
D) Dual-slope A/D converter.
6) The A/D converter whose conversion time is independent of the number of o/p digital bits
is
A) Dual slope B) Counter type
C) Successive approximation. D) none
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7) The A/D converter whose conversion time is independent of input analog sample is
A) Dual slope B) Counter type
C) Successive approximation. D) none
8) In successive-approximation A/D converter, offset voltage equal to ½ LSB is added to the
D/A converter’s output. This is done to
A) Improve the speed of operation.
B) Reduce the maximum quantization error.
C) Increase the number of bits at the output.
D) Increase the range of input voltage that can be converted.
9) Find the percentage resolution of 8-bit DAC
A) 0.392% B) 0.781% C) 1.96% D) 1.52%
10) The 4-bit DAC has step size of 150 mV. Determine the full scale o/p
A) 2.4 V B) 0.6 V C) 2.1 V D) 2.25 V
11) An 8-bit DAC produce Vout = 0 V for digital input 00000000 & Vout = 2.8 V for digital input
11000000 then find the Vout for digital input 10101010
A) 2.479 V B) 2.956 V C) 1.967 V D) 1.523 V
12) Find the LSB and MSB output (in V) respectively for 8-bit DAC has Vref = 5 V
5 128 128 5 5
A) 255 & 51 B) 0 & 51 C) 255 & 2 D) 0 & 5
13) The analog sample (Va) of 3.563 V is apply to 8-bit dual slope ADC with reference voltage
(VR) of -10 V. find equivalent digital o/p.
A) 01011100 B) 11001101 C) 01101001 D) 01011101
14) Find the 4-bit digital o/p of digital ramp type ADC. For analog sample of 5.7 V and resolution
of DAC is 0.5 V
A) 1100 B) 1011 C) 1010 D) 1101
15) Find the 4-bit digital o/p of SAR ADC. For analog sample of 5.7 V and resolution of DAC is 0.5
V
A) 1100 B) 1011 C) 1010 D) 1101
16) A 8 - bit ADC is operating with a 1us clock period and period between two analog sample is
10 ns, for proper operation the ADC must be
A) Digital ramp type B) SAR type C) flash type D) dual slope type
17) Which of the following ADC’s uses over sampling in its operation (ISRO)
A) Sigma-delta ADC B) SAR ADC C) flash ADC D) counter ramp ADC
18) For an 8-bit DAC having reference voltage of 8 V, the least significant 4 bit of the i/p are
grounded and most significant 4 bits are driven by 4 bit data binary counter. The maximum
obtainable peak-to-peak amplitude of a waveform at the o/p of DAC is (DRDO)
A) 4 V B) 6 V C) 7.2 V D) 7.5 V
19) A 5 bit DAC has a current o/p, for the digital i/p 10100 is 10 mA. What will be the current for
a digital i/p of 11101 is (ISRO)
A) 14.5 mA B) 10 mA C) 100 mA D) cant calculate
20) Find the number of comparator require for 12 bit flash ADC
A) 2048 B) 11 C) 4096 D) 4095
21) The 4-bit digital ramp type ADC with full scale reading of 7.5 has an conversion time 10 us
for 1.3 V analog sample then find conversion time for 2.6 V analog sample
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A) 10 us B) 5 us C) 20 us D) can’t determine
22) The 4-bit SAR type ADC with full scale reading of 7.5 has an conversion time 10 us for 1.3 V
analog sample then find conversion time for 2.6 V analog sample
A) 10 us B) 5 us C) 20 us D) can’t determine
23) A certain 6-bit DAC has a full scale output of 2 mA and full scale error of ± 0.5%. what is the
range of possible output for an i/p of 100000
A) 1.004 to 1.024 mA B) 1 to 1.2 mA C) 1.004 to 1.014 mA D) none
24) What will be output voltage due to MSB in 8 bit ladder if input level for 0 is 0 V and for 1 is 5
V
A) 2.5 V B) -2.5 V C) 5 V D) -5 V
25) Find the output voltage correspond to LSB if logic 0 is 0V and logic 1 is 5 V
A) -0.5 V B) 0.5 V C) 0.25 V D) – 0.25 V

26) The 4 bit weighted resistor DAC whose full scale output voltage is – 10 volt. The logic 0 is 0V
and logic 1 is 10 V. What is output voltage for digital i/p 1010 is
A) -6.66 V B) -6.33 V C) 6.66 V D) 6.33 V
Answers:
1. A 2. C 3. D 4. A 5. B 6. D 7. C 8. D 9. A
10. D 11. A 12. A 13. A 14. A 15. B 16. B 17. A 18. D
19. A 20. D 21. C 22. A 23. A 24. A 25. D 26. A 27.
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GATE THE Direction Semiconductor Memory
CHAPTER VII
SEMICONDUCTOR MEMORY
Memory:
There are several types of memory. They can be classified as primary memory and secondary
memory.
Primary memory can be classified into random access memory (RAM), cache memory
and read only memory (ROM). Random access memory (RAM) stores the programs that are
currently being run and the data related to these programs. It is a volatile memory and is used
for temporary storage of data and programs. Cache memory is a special type of internal memory
that can be accessed much faster than the RAM. ROM is a nonvolatile memory that stores the
system programs including the basic input/output system (BIOS), start-up programs and so on.
Secondary memory has a much greater capacity than primary memory, but it is much
slower than the primary memory. It is used to store programs and data for future use. Most
commonly used secondary memory devices include the hard disk, floppy disks, magnetic tape,
compact disks (CDs), and USB disks. The secondary memories are cheap as compare to primary
memories.
Memory is the portion of a system for storing binary data in large quantities. Semiconductor
memories consist of arrays of storage elements that are generally either latches (or) capacitors.
Units of binary data:
1. The smallest unit of binary data is bit.
2. 8-bit unit is called a byte (or) in multiples of 8-bit units.
3. The byte can be split into two 4-bit units called nibble
4. A complete unit of information is called a word, generally consist of one (or) more
bytes.
Cell: Each storage element in a memory can retain a '1' (or) '0' and is called a cell. Memories are
made up of array of cells.
A 64-cell array can be organized in several ways based on units of data.

1. 8x8 array - 8 byte memory
2. 16x4 array - 16-nibble memory
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3. 64 x 1 array - 64 bit memory
Ex: A 16K x 8 memory can store 16,384 words of eight bits each. (1k = 1024)
Memory address & capacity:
The location of a unit of data in memory array is called address. The capacity of a memory is the
total number of units that can be stored.
Random Access Memory (RAM)

RAM is a read/write memory where the data can be read from or written into any of the
memory locations regardless of the order in which they are arranged. Therefore, all the memory
locations in a RAM can be accessed at the same speed. RAM is used to store data, program
instructions and the results of any intermediate calculations during the execution of a program.
Also, the same data can be read any number of times and different data can be written into the
same memory location, with every fresh data item overwriting the existing one. It is typically
used for short-term data storage as it cannot retain data when the power is turned off. The
capacity or size of a RAM is measured in bytes. RAM chips are available in the memory capacities
ranging from 2 kB to as much as 32 MB. 1 kB of memory equals 2 10 = 1024 bytes and 1 MB of
memory equals 220 bytes.
RAM has three basic building blocks, namely an array of memory cells arranged in rows
and columns with each memory cell capable of storing either a ‘0’ or a ‘1’, an address decoder
and a read/write control logic. Depending upon the nature of the memory cell used, there are
two types of RAM, namely static RAM (SRAM) and dynamic RAM (DRAM).
RAM Family:
In SRAM, the memory cell is essentially a latch and can store data indefinitely as long as the DC
power is supplied. DRAM on the other hand, has a memory cell that stores data in the form of
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charge on a capacitor. Therefore, DRAM cannot retain data for long and hence needs to be
refreshed periodically. SRAM has a higher speed of operation than DRAM but has a smaller
storage capacity.
Static RAM
Basic element of SRAM is a latch memory cell. Figure shows a basic SRAM memory cell.
The memory cell is selected by setting the ‘select’ line active. The data bit is written into the cell
by placing it on the ‘data in’ line and is read from the ‘data out’ line.
Storage Cell: All static RAM's are characterized by flip-flop storage cells that are typically
implemented with several MOS transistors (MOSFETS). Some smaller RAMS also implemented
using BJT's.
Asynchronous SRAM: In which the operation is not synchronized with a system clock.
Synchronous SRAM: A synchronous SRAM is synchronized with the system clock.
The burst feature in synchronous SRAM's: Synchronous SRAM's have an address burst feature,
which allow the memory to read (or) write at up to four locations using a single address.
Burst logic: The address burst logic in a typical synchronous SRAM consists of a binary counter
and EX-OR gates.
Application of SRAM:
Cache memory: It is a relatively small and high speed memory that stores the most recently
used instructions (or) data from the larger but slower main memory. It is very costly.
Dynamic RAM
The memory cell in the case of a DRAM comprises a capacitor and a MOSFET. The cell
holds a value of ‘1’ when the capacitor is charged and ‘0’ when it is discharged. The main
advantage of this type of memory is its higher density, or more bits per package, compared with
SRAM. This is because the memory cell is very simple compared with that of SRAM. Also, the
cost per bit is less in the case of a DRAM. The disadvantage of this type of memory is the leakage
of charge stored on the capacitors of various memory cells when they are storing a ‘1’. To
prevent this from happening, each memory cell in a DRAM needs to be periodically read, its
charge (or voltage) compared with a reference value and then the charge restored to the
capacitor. This process is known as ‘memory refresh’ and is done approximately every 5–10 ms.
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Figure shows the basic memory cell of a DRAM and its principle of operation. The
MOSFET acts like a switch. When in the ‘write’ mode (R/W = 0, the input buffers are enabled
while the output buffers are disabled. When ‘1’ is to be stored in the memory, the ‘data in’ line
must be in the HIGH state and the corresponding ‘row line’ should also be in the HIGH state so
that the MOSFET is switched ON. This connects the MOSFET to the ‘data in’ line, and it charges
the capacitor to a positive voltage level. When ‘0’ needs to be stored, the ‘data in’ line is LOW
and the capacitor also acquires the same level. When the ‘row line’ is taken to the LOW state,
the MOSFET is switched OFF and is disconnected from the bit line. This traps the charge on the
capacitor. In ‘read’ mode (R/W = 1, the output buffers are enabled while the input buffers are
disabled. When the ‘row line’ is taken to HIGH logic, the MOSFET is switched ON and connects
the capacitor to the ‘data out’ line through the output buffer. The refresh operation is
performed by setting R/W = 1 and by enabling the refresh buffer.
Storage cell: It can store a data bit in a small capacitor rather than a latch. It having capacitors &
MOS transistors.
Advantages: Low Cost, small size.
Disadvantages: The storage capacitor cannot hold its charge over an extended period of time
and will lose the stored data bit unless its charge is refreshed periodically. To refresh requires
additional memory circuit and complicated the operation of DRAM.
Types of DRAMS:
FPM DRAM: Fast Page Mode DRAM. The page in memory is all of the column address as
contained within one row address.
EDO DRAM: Extended data output DRAM. It is also called hyper page mode DRAM. The
difference between FPM DRAM & EDO DRAM is the access time "speed up in EDO DRAM".
BEDO RAM: It is an EDO DRAM with address burst capabilities.
SDRAM: It is faster DRAM.
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Read Only Memory (ROM)

ROM is a nonvolatile memory that is used for permanent or semi-permanent storage of
data. The contents of ROM are retained even after the power is turned off.
In the case of ROM, instructions can be written into the memory only once at the
manufacturer’s premises. These instructions can, however, be read from a ROM as many times
as desired. Once it is written, a ROM cannot be written into again. The internal structure or
architecture of a ROM comprises three basic parts, namely the array of memory cells, the
address decoder and the output buffers. The address decoder comprises a single decoder in the
case of small memories. In the case of large memories it comprises two decoders referred to as
row and column decoders. The operation of a ROM can be best explained with the help of the
simplified representation of a 32×8 ROM, as shown in figure.
The array of memory cells stores the data to be programmed into the ROM. The
number of memory cells in a row equals the word size, and the number of memory cells in a
column equals the number of such words to be stored. In the memory shown in Figure, the word
size is eight bits and the number of words is 32. The data outputs of each of the memory cells in
the array are connected to an internal data bus that runs through the entire circuit. The address
decoder, a 1-of-32 decoder in this case, sets the corresponding ‘row line’ HIGH when a binary
address is applied at its input lines. A five-bit address code (A4A3A2A1A0) is needed to address 32
memory cells.
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Mask ROM:
It simply refers ROM. It is permanently programmed during the manufacturing process to

provide widely used standard function. Once the memory is programmed it cannot be changed.
ROM Cells: MOS transistors.
ROMs can use look up tables (LUT's) for code conversions and logic function generation.
PROM: PROM's are same as mask ROM's, once they have been programmed. The difference is
that PROM's come from manufacturer un programmed and are custom programmed in the field
to meet the user's needs.
Once a PROM is programmed it cannot be changed. Cells: MOS transistors with fusible links.
EPROM (Erasable Programmed ROM): Unlike an ordinary PROM, EPROM can be reprogrammed
if an existing program in the memory array is erased first.
Cell: NMOSFET array with an isolated gate structure.
Two types of EPROMS: (1) UVEPROM (2) EEPROM
UVEPROM: Ultra Violet EPROM: Here erase can be done by exposure of the memory array chip
to high intensity UV radiation through quartz window on top of the package.
The memory cell in a UV EPROM is a MOS transistor with a floating gate. UV EPROMs suffer from
disadvantages such as the need to remove the chip from the circuit if it is to be reprogrammed,
the non feasibility of carrying out selective erasure and the reprogramming process taking
several tens of minutes. These are overcome in the EEPROMs.
EEPROM: Electrically Erasable PROM's can be both erased and programmed with electrical
pulses. The memory cell of an EEPROM is also a floating-gate MOS structure with the slight
modification that there is a thin oxide layer above the drain of the MOS memory cell. Application
of a high-voltage programming pulse between gate and drain induces charge in the floating-gate
region which can be erased by reversing the polarity of the pulse. Since the charge transport
mechanism requires very low current, erasing and programming operations can be carried out
without removing the chip from the circuit. EEPROMs have another advantage that, it is possible
to erase and rewrite data in the individual bytes in the memory array. The EEPROMs, however,
have lower density and higher cost compared with UV EPROMs.
Two types of EEPROMs: (1) Floating gate MOS (2) Metal Nitride - Oxide silicon (MNOS)
Flash memory: These are high density read/ write memories that are non volatile.
Storage Cell: Floating - gate MOS transistor.
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Comparison of Memories:
One IN-System
Memory Type Nonvolatile High density
transistor Cell writability
Flash Yes Yes Yes Yes

SRAM No No No Yes
DRAM No Yes Yes Yes
ROM Yes Yes Yes No
EPROM Yes Yes Yes No
EEPROM Yes No No Yes
Memory Expansion:
Available memory can be expanded to increase word length (number of bits in each address) or
the word capacity (number of different addresses) or both Memory expansion is accomplished
by adding an appropriate number of memory chips to the address ,data, and control busses.
Word-length expansion : - To increase word length in memory the number of bits in the data
bus must be increased.
Ex : - An 8 bit word length can be achieved using two memories, each with 4 - bit words.
Ex: Expand 65,536 x 4 ROM (64k x 4) to form a 64k x 8 ROM.
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Ex: Expand 64k x 4 ROM to form a 64k x 16 ROM.
Word Capacity expansion :
When memories are expanded to increase the word capacity the number of addresses is
increased.
Ex: Implement 2M x 8 RAM using 1M x 8 RAM:
Each individual memory has 20 address bits to select 1,048,576 address. The expanded memory
has 2,097,152 addresses requires 21 address bits. The 21st address bit is used to enable
appropriate memory chip.
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Points to remember: -
(2) Primary memories are semiconductor memories. They available in the form of IC's with
different memory capacities.
(3) The capacity of memory IC denotes as 2n x m. 2n - no. of memory locations m - no. of

bits stored in each memory location. Ex: 210x8 = 1024x8 =1kx8. Here we have 1k memory
location and each location is store 8 bit so total memory is 1kx8.
(4) The no. of address bits required to identify 2 n memory locations are ‘n'.
(5) To increase the bit capacity (or) length of each memory location, memory IC's connected
in parallel.
Ex: 1024 x 8 - memory capacity can be obtained by using '2' IC's of memory capacity 1024x4.
5. To increase the no. of memory locations, the memory IC's connected such that at any
time only one memory IC must be selected.
Ex: - To get 4k x 8 memory capacity: it is required to use four 1k x 8 IC's and at any time one of
the four memory IC's can be selected using decoder.
6. The number of memory IC's of capacity 1k x 4 required to construct a 8k x 8 are 16. (16
memory IC's of 1 k x 4 capacity).
𝐫𝐞𝐪𝐮𝐢𝐫𝐞𝐝 𝐦𝐞𝐦𝐨𝐫𝐲 𝐬𝐢𝐳𝐞
𝐧𝐮𝐦𝐛𝐞𝐫 𝐨𝐟 𝐦𝐞𝐦𝐨𝐫𝐲 𝐈𝐂 ′ 𝐬 =
𝐚𝐯𝐚𝐢𝐥𝐚𝐛𝐥𝐞 𝐦𝐞𝐦𝐨𝐫𝐲 𝐬𝐢𝐳𝐞
7. Access time : It is the time for a memory to access a memory location for reading or writing.
8. Access rate : Reciprocal of access time. Units - words per second.
9. Random access : If the access time is independent of position of memory location called
Random access. The access time of every memory location is same eg. RAM.
10. Sequential access : A memory in which the locations can be accessed in a sequence. eg.
magnetic tape, magnetic bubble.
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11. SRAM : The data stored in terms of voltage. Storage cells are conventional flip flops.
12. DRAMs: The data stored in form of charge on capacitor. Storage cells are - charge storage
capacitors with driver transistors. SRAMs are faster than DRAMs.
Magnetic memories: -
Access time: The access time of a magnetic drum defined as the sum of seek time & transfer
time.
Seeking time: It is the time for moment of read/write head to the desired track.
Magnetic hard disks: Computers use hard disks as the internal mass storage media. Hard disks
are rigid "platters" made up of aluminum alloy (on formatted into tracks and sectors. Each track
divided into number sectors, and each track and sector has a physical address that is used by the
OS to locate a particular data record.
Latency period: It is the time takes for the desired sector to spin under the head is positioned
over the desired track.
Floppy disks: It is made up of a flexible polyester material with a magnetic coating on both
sides. Floppy disks are formatted into tracks, sectors like hard disks. Floppy disks are removable
disks but hard disks are not.
Magnetic tape: Tape is used for backup data from mass storage devices and is typically slower
than disks because data on tape is accessed serially rather than randomly.
Points to remember :
1. Destructive Read out memory (DRO): If the reading method destroys its contents that
memory called DRO. For such memories each read operation must be followed by write
operation to restore the contents eg. Magnetic core.
2. Non destructive Read out: (NDRO) if the read operation does not change its contents eg.
Magnetic tapes, disks, RAMS, ROMs.
3. CCD is a volatile memory and sequential access type.
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Problems:
1) SD RAM refers to
A) Synchronous DRAM B) Static DRAM
C) Semi DRAM D) Second DRAM
2) Which of the following is true with respect to EEPROM?
A) Contents can be erased byte wise
B) Contents of full memory can be erased together only
C) Contents can be erased using ultra violet rays
D) Contents cannot be erased
3) Which of the memory is volatile memory
A) ROM B) RAM C) PROM D) EEPROM
4) Which of following cannot be accessed randomly
A) DRAM. B) SRAM. C) ROM. D) Magnetic tape.
5) The minimum number of MOS transistor require for dynamic ram cell
A) 1 B) 2 C) 3 D) 4
6) Eight memory chip of 1k x 4 size have their address buses connected together. This system
will be of size
A) 8k x 4 B) 1k x 32 C) 4k x 16 D) 8k x 32
7) The number of address bus of memory size 1k x 4 is
A) 8 B) 9 C) 10 D) 11
8) Find the number of 1k x 8 memory chip require for designing of 4k x 16 memory chip
A) 4 B) 8 C) 16 D) 12
9) The access time of ROM using bipolar transistors is about
A) 1 sec B) 1 msec C) 1 μsec D) 1 nsec
10) Words having 8-bits are to be stored into computer memory. The number of lines required
for writing into memory are
A) 1 B) 2 C) 4 D) 8
11) In a RAM, information can be stored
A) By the user, number of times B) By the user, only once
C) By the manufacturer, a number of times D) By the manufacturer only once
12) Which of the following memories stores the most number of bits
A) 5M×8 memory B) 2M × 16 memory C) 5M× 4memory D) 4M×12 memory
13) The process of entering data into a ROM is called
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A) burning in the ROM B) programming the ROM
C) changing the ROM D) charging the ROM
14) Which of the following number of address bits can use to access a 32 K memory
A) 10 bits B) 12 bits C) 14 bits D) 16 bits
15) Which of following requires refreshing?
A) SRAM B) DRAM C) ROM D) EPROM
16) The information in ROM is stored
A) By the user any number of times.
B) By the manufacturer during fabrication of the device.
C) By the user using ultraviolet light.
D) By the user once and only once.
17) Which of the following is secondary memory

A) ROM B) RAM C) magnetic tape D) both A &C
18) Secondary memory are as compare to primary memory
A) Faster B) cheap C) smaller D) all
Answers:
1. A 2. A 3. B 4. D 5. A 6. B 7. C 8. B 9. C
10. D 11. A 12. D 13. B 14. D 15. B 16. B 17. D 18. B
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GATE THE Direction Microprocessor
CHAPTER VIII
MICROPROCESSOR
Microprocessor:
Internal Architecture of 8085 Microprocessor
Control Unit: Control unit generates signals with in uP to carry out the instruction, which has
been decoded. In reality causes certain connections between blocks of the uP to be opened or
closed, so that data goes where it is required, and so that ALU operations occur.
Arithmetic Logic Unit: The ALU performs the actual numerical and logic operation such as
‘add’, ‘subtract’, ‘AND’, ‘OR’, etc. It uses data from memory, resister and from Accumulator to
perform arithmetic and logical operation. It is always stores result of operation in Accumulator.
Registers: The 8085A-programming model includes six registers, one accumulator, and one
flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and
the program counter. They are described briefly as follows. The 8085A has six general-purpose
registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the figure. They
can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations. The
140
programmer can use these registers to store or copy data into the registers by using data copy
instructions.
Accumulator: The accumulator is an 8-bit register. This register is used to store 8-bit data and
to perform arithmetic and logical operations. The result of an operation is stored in the
accumulator. The accumulator is also identified as register A. It is generally used in every ALU
operation.
Flags: There are five flags, which are set or reset after an operation according to data
conditions of the result in the accumulator.
They are called-
Zero (Z), Carry (CY), Sign (S), Parity (P), Auxiliary Carry (AC)
They are listed in the Table and their bit positions in the flag register are shown in the Figure
below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these
flags to test data conditions. For example, after an addition of two numbers, if the sum in the
accumulator is larger than eight bits, the Carry flag uses to indicate a carry and Carry flag (CY) is
set to one. When an arithmetic operation results in zero, the flag called the Zero (Z) flag is set
to one. Five bit positions out of eight are used to store the outputs of the five flags. The flags
are stored in the 8-bit register so that the programmer can examine these flags (data
conditions) by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the microprocessor. The
conditions (set or reset) of the flags are tested through the software instructions. For example,
the instruction JC (Jump on Carry) is implemented to change the sequence of a program when
CY flag is set. The thorough understanding of flag is essential in writing assembly language
programs. The flag resister show as:
S Z X AC X P X CY
D7 D6 D5 D4 D3 D2 D1 D0
Sign flag: In case of arithmetic operations with signed numbers, the most significant bit D 7 is
reserved to indicate sign information, and the remaining seven bits are used to represent the
magnitude of the number. After the execution of an arithmetic or logic operation, the MSB of
the result (usually in the accumulator) is copied into sign flag. S =1 indicates result is negative, S
= 0 indicates result is positive.
Zero flag: Z =1 if the ALU operation results in zero. Z=0 if the result is not zero.
Auxiliary carry flag: In an arithmetic operation, the carry obtained from D3 to D4 bit position is
called Auxiliary carry. This flag is used only internally for BCD operation and is not available for
the programmer to change the sequence of a program with a jump instruction.
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Parity flag: After ALU operation, the result has an even number of 1 's then P=1 otherwise P =
0.
Carry flag: If an arithmetic operation results in a carry, the carry flag is set i.e. CY=1, Otherwise
it is reset. The carry flag also serves as a barrow flag for subtraction.
Note: Among the five flags, the Ac flag is used internally for BCD arithmetic; the instruction set
does not include any conditional jump instructions based on this flag.
> Accumulator register content and status register content together is called PSW (Program
Status Word or processor status word)
PSW
Ex. Find the flag condition after the execution of the ADD B (i.e. A<---A+B)instruction. If A=6C H
and B = 49 H.
Solution: A = 6C 0110 1100
B = 49 +0100 1001
1011 0101
 Carry is not generate so carry flag (cy)=0

 Total five (i.e. odd) 1’s in result so parity flag (p)=0
 Result is not zero so zero flag (z) = 0
 Carry is generated between lower nibble to upper nibble (i.e. between D 3 to D4) so
auxiliary carry flag (Ac) = 1
 MSB of the result is one so sing flag (s) = 1
Program Counter (PC): This 16-bit register deals with sequencing the execution of
instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and
that is why this is a 16-bit register. The microprocessor uses this register to sequence the
execution of the instructions.
 The function of the program counter is to point to the memory address from which the
next byte is to be fetched.
Stack Pointer (SP): The stack pointer is also a 16-bit register used as a memory pointer. It
points to a memory location in R/W memory, called the stack register (stack). The beginning of
the stack is defined by loading 16-bit address in the stack pointer.
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 It contain the address of top most of the stack register.
Instruction Register/Decoder: It is used to temporary store the current instruction of a

program. Decoder then takes instruction and ‘decodes’ or interprets the instruction. Decoded
instruction then passed to next stage.
Memory Address Register: It is holds address, received from PC, of next program
instruction.
8085 System Bus

The uP uses a number of busses and collections of wires for transmit binary numbers,
one bit per wire. A typical microprocessor communicates with memory and other devices (input
and output) using three busses: Address Bus, Data Bus and Control Bus.
Address Bus: The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits. A
16 bit binary number allows 216 different numbers (ie 0000000000000000 up to
1111111111111111). Each and every memory has unique address; the size of the address bus
determines number of different memory location, which can be used. To communicate with
memory the microprocessor sends an address on the address bus, eg 0000000000000011 (3 in
decimal), to the memory. It will select the memory location 3 for reading or writing data.
Question: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits), how many wires
does the address bus need, in order to be able to specify an address in this memory? Note: the
memory is organized in groups of 8 bits per location, therefore, how many locations must you
be able to specify?
Answer: The total 256 x 1024 different locations are available. So we require address bus width
(n) as 2n ≥ 256X1024 therefore n=18
Data Bus: It carries ‘data’, in binary form, between μP and other external units, such as
memory. Its size is 8 bits for uP 8085A. Data bus Size indicates the size of μP and so it helps to
determine performance of μP. Data bus used to transmit "data", ie information, results of
arithmetic, etc, between memory and the microprocessor. Data Bus is bi-directional. The size of
the data bus determines range of arithmetic can be done. If only 8 bits wide then largest
number is 11111111 (255 in decimal). Data Bus also carries instructions from memory to the
microprocessor so size of the bus also limits the number of possible instructions to 256.
Control Bus: Control Bus are various lines which have specific functions for coordinating and
controlling uP operations. Eg: Read/Write line. Typically μP has 10 control lines. The Up cannot
function correctly without these vital control signals. The Control Bus carries control signals
partly unidirectional, partly bi-directional.
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8085 Pin description

Properties:
 Single + 5V Supply
 Five hardware interrupt From which 4 Vectored Interrupts (One is Non Maskable)
 Serial In/Serial Out Port
 Decimal, Binary, and Double Precision Arithmetic
 Direct Addressing Capability to 64K bytes of memory
The 8085A uses a multiplexed lower byte address and data bus.
Pin Description
The following describes the function of each pin:
A8 - A15 (Output) : Address Bus; The most significant 8 bits of the memory address or the 8
bits of I/0 addresses.
AD0 - 7 (Input/Output): It Is multiplexed Address/Data Bus; Lower 8 bits of the memory

address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then
becomes the data bus during the second and third clock cycles.
ALE (Output): Address Latch Enable (ALE) occurs during the first clock cycle of a machine
state and enables the address to get latched into the on chip latch of peripherals. The falling
edge of ALE is set to guarantee setup and hold times for the address information. ALE can also
be used to strobe the status information.
S0, S1 (Output): Data Bus Status. Encoded status of the bus cycle:
S1 S0
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 and S0 can be used as an advanced R/W status.
RD (Output): READ; indicates the selected memory or I/O device is to be read and that the
Data Bus is available for the data transfer.
WR (Output): WRITE; indicates the data on the Data Bus is to be written into the selected
memory or I/O location. Data is set up at the trailing edge of WR.
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READY (Input): If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go
high before completing the read or write cycle.
HOLD (Input): HOLD; indicates that another Master is requesting the use of the Address and
Data Buses. It will relinquish the use of buses as soon as the completion of the current machine
cycle. Internal processing can continue. The processor can regain the buses only after the Hold
is removed.
HLDA (Output): HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request
and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold
request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.
INTR (Input): INTERRUPT REQUEST; is used as a general purpose interrupt. If it is active, the
Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During
this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service
routine. The INTR is enabled and disabled by software. It is disabled by Reset.
INTA (Output): INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as)
RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259
Interrupt chip or some other interrupt port.
RESET IN (Input):
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.
None of the other flags or registers (except the instruction register) are affected. The CPU is
held in the reset condition as long as Reset is applied.
RESET OUT (Output): Indicates CPU is being reset. It can be used as a system RESET. The
signal is synchronized to the processor clock.
X1, X2 (Input): Crystal or R/C network connections to set the internal clock generator X1, X2
can also be an external clock input instead of a crystal. The external input frequency is divided
by 2 to give the internal operating frequency.
CLK (Output): It use as a system clock when a crystal or R/ C network is used as an input to
the CPU. The period of CLK is twice the X1, X2 input period.
IO/𝑴 (Output): IO/𝑀 indicates whether the Read/Write is to memory or I/O (0 for memory
and 1 for I/O). It will be tristated during Hold and Halt modes.
SID (Input): Serial input data line, the data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.
SOD (output): Serial output data line. The output SOD is set or reset as specified by the SIM
instruction.
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Vcc: +5 volt supply.

Vss: Ground Reference.
Pin Diagram:
Interrupts:
Hardware interrupts are used by devices to communicate that they require attention
from the operating system. Internally, hardware interrupts are implemented using electronic
alerting signals that are sent to the processor from an external device, which is either a part of
the computer itself, such as a disk controller, or an external peripheral. For example, pressing a
key on the keyboard or moving the mouse triggers hardware interrupts that cause the
processor to read the keystroke or mouse position.
The 8085A has five hardware interrupt namely: INTR, RST5.5, RST6.5, RST 7.5, and
TRAP. INTR is identical in function to the 8080 INT. Each of the three RESTART interrupt, 5.5, 6.5
and 7.5, has a programmable mask. TRAP is also a RESTART interrupt except it is non-maskable.
The three RESTART interrupts cause the internal execution of RST (saving the program counter
in the stack and branching to the RESTART address) if the interrupts are enabled and if the
interrupt mask is not set. The non-maskable TRAP causes the internal execution of a RST
independent of the state of the interrupt enable or masks. The interrupts are arranged in a
fixed priority that determines which interrupt is to be recognized if more than one is pending as
follows: TRAP highest priority, RST 7.5, RST 6.5, RST 5.5, INTR lowest priority. The TRAP
interrupt is useful for catastrophic errors such as power failure or bus error. The TRAP input is
recognized just as any other interrupt but has the highest priority. It is not affected by any flag
or mask. The TRAP input is both edge and level sensitive.
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 Maskable interrupt (MI): a hardware interrupt that may be ignored by setting a mask bit in
SIM instruction.
 Non-maskable interrupt (NMI): It is a hardware interrupt that cannot be ignored by standard

interrupt masking techniques in the system. It is typically used to signal attention for non-
recoverable hardware errors
 Vector address interrupt: If the address of subroutine is predefine after the occurrence of
interrupt then its called as vector address interrupt.
All the interrupts are presented below in the order of their priority (from lowest to highest):
INTR is maskable, non-vector address 8080A compatible interrupt. it is used as a general

purpose interrupt. INTR is usually because of one of these instructions
 One of the eight software RST n instructions (RST0 - RST7). The processor saves current
program counter into stack and branches to memory location N * 8 (where N is a 3-bit
number from 0 to 7 supplied with the RST instruction).
 CALL instruction (3 byte instruction) The processor calls the subroutine, address of
which is specified in the second and third bytes of the instruction.
RST5.5 is a maskable, vector address interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to (vector address) 2C H address.
It is level sensitive interrupt.
saves the contents of the PC register into stack and branches to 34 H (vector address). It is level
sensitive interrupt.
saves the contents of the PC register into stack and branches to 3C H (vector address). It is edge
sensitive interrupt.
Trap is a non-maskable, vector address interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 24 H (vector address). It is both
level and sensitive interrupt.
 Trap also called as RST 4.5.
All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5
and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
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Interrupts Type Instruction Hardware Trigger Vector

address
Independent of No external Level & Edge

TRAP Non maskable 0024 H
El & DI Hardware sensitive
Controlled by El No external Edge

RST 7.5 Maskable & DI. Mask & un- OO3C H
Hardware sensitive
masked by SIM
Controlled by El Level
by SIM No external
RST 6.5 Maskable & DI. Mask & un- 0034 H
Hardware sensitive
masked by SIM
Controlled by El No external Level
RST 5.5 Maskable & DI. Mask & un- Hardware 002C H
sensitive
masked by SIM
Controlled by El RST Code from Level 0000 To
INTR Maskable & DI external sensitive 0038 H
Hardware
A software interrupt is caused either by an exceptional condition in the processor itself, or a

special instruction in the instruction set which causes an interrupt when it is executed. The
former is often called a trap or exception and is used for errors or events occurring during
program execution that are exceptional enough that they cannot be handled within the
program itself.
> Software interrupt instructions function similarly to subroutine calls
> Vectored addresses corresponds to the Software interrupts RST n is (08xn)H.
RST 0 0000 H
RST 1 0008 H
RST 2 0010 H
RST 3 0018 H
RST 4 0020 H
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H
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> SIM instruction is used for serial output data operation as well as to mask or unmask
different maskable vectored Interrupts
> RIM instruction is used for serial input data operation as well as to read the status of
different Maskable and pending Vectored interrupts
> The Accumulator register (A) is also called processor register
> 8085 is having 8 - bit flag register which is also called status register
8085 Functional Description

The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt
supply. Its basic clock speed is 3 MHz thus improving on the present 8080's performance with
higher system speed. Also it is designed to fit into a minimum system of three IC's: The CPU, a
RAM/ IO, and a ROM or PROM/IO chip. The 8085A uses a multiplexed Data Bus. The address is
split between the higher 8bit Address Bus and the lower 8bit Address/Data Bus. During the first
cycle the address is sent out. The lower 8bits are latched into the peripherals by the Address
Latch Enable (ALE). During the rest of the machine cycle the Data Bus is used for memory or l/O
data.
The 8085A provides RD, WR, and lO/Memory signals for bus control. An Interrupt
Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are synchronized.
The 8085A also provides serial input data (SID) and serial output data (SOD) lines for simple
serial interface. In addition to these features, the 8085A has three maskable, restart interrupts
and one non-maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus
control.
Status Information: Status information is directly available from the 8085A. ALE serves as a
status strobe. The status is partially encoded, and provides the user with advanced timing of
the type of bus transfer being done. IO/M cycle status signal is provided directly. So, S1 carries
the status information: halt, write, read,
fetch.
System Timing: The 8085A has a

multiplexed Data Bus. ALE is used as a strobe
to sample the lower 8bits of address on the
Data Bus. Note that during the I/O write and
read cycle that the I/O port address is copied
on both the upper and lower half of the
address. As in the 8080, the READY line is
used to extend the read and write pulse
lengths so that the 8085A can be used with
slow memory.
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System Interface:
8085A family includes memory components, which are directly compatible to the 8085A CPU.
For example, a system consisting of the three chips, 8085A, 8156, and 8355 will have the
following features:
· 2K Bytes ROM
· 256 Bytes RAM
· 1 Timer/Counter
· 4 8bit l/O Ports
· 1 6bit l/O Port
· 4 Interrupt Levels
· Serial In/Serial out Ports
In addition to standard I/O, the memory mapped I/O offers an efficient I/O addressing
technique. With this technique, an area of memory address space is assigned for I/O address,
thereby, using the memory address for I/O manipulation. The 8085A CPU can also interface
with the standard memory that does not have the multiplexed address/data bus.
Instruction Set Classification

1. On the basis of addressing mode (8085 Addressing Modes):
The instructions MOV B, A or MVI A, 82H are to copy data from a source into a
destination. In these instructions the source can be a register, an input port, or an 8-bit number
(00H to FFH). Similarly, a destination can be a register or an output port. The sources and
destination are operands. The various formats for specifying operands are called the
ADDRESSING MODES. For 8085, they are:
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Implied addressing.
Immediate addressing: In immediate addressing mode data is present in the instruction so

here load the immediate data to the destination provided.
Example: MVI rd, data (8 bit); LXI rp, data (16 bit)
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 Generally these instruction end with letter ‘i’ (i for immediate)

Register addressing: Data is provided through the registers i.e. operand are resister.
Example: MOV rd, rs (it will move the contain of rs to rd), MOV A,B.
Direct addressing: The address of operand is present in the instruction itself.

Example: STA 2000; IN 00H; OUT 01H
Indirect Addressing: The address of operand is present in the resister pair and that resister
pair is given in the instruction (by default take it as HL pair).
Example: MOV B, M; LDAX D
Implied addressing: In this type of instruction neither immediate data nor address and not
any resister is mention in instruction. The instruction contains only Mnemonics. It is generally
do operation on accumulator.
Example: CMA; RRC
Instruction Format:
An instruction is a command to the microprocessor to perform a given task on a
specified data. Each instruction has two parts: one is task to be performed, called the operation
code (opcode), and the second is the data to be operated on, called the operand. The operand
(or data) can be specified in various ways. It may include 8-bit (or 16-bit) data, an internal
register, a memory location, or 8-bit (or 16-bit) address.
In some instructions, the operand is implicit.
2. On the basis of Instruction word size

The 8085 instruction set is classified into the following three groups according to word size:
1. One byte instructions
2. Two byte instructions
3. Three byte instructions
One-Byte Instructions:
A 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are internal
register or data in memory whose address is given by register pair, Which are coded into the
instruction.
For example:
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Task Opcode Operand Binary Code Hex Code

Copy the content of the MOV C, A 0100 1111 4FH
accumulator in the register C
Add the content of register B to the ADD B 1000 0000 80H
content of the accumulator
Invert ( Complement ) each bit in CMA 0010 1111 2FH
the accumulator
These instructions are 1-byte instructions performing three different tasks. In the first
instruction, both operand registers are specified. In the second instruction, the operand B is
specified and the accumulator is assumed. Similarly, in the third instruction, the accumulator is
assumed to be the implicit operand. These instructions are stored in 8- bit binary format in
memory; each requires one memory location.
MOV rd, rs;
rd <-- rs copies contents of rs into rd. It will coded as 01 ddd sss where ddd is a code for one of
the 7 general registers which is the destination of the data, sss is the code of the source
register.
Example: MOV A,B
Coded as 01111000 = 78H
ADD r;
A <-- A + r
Two-Byte Instructions:
In a two-byte instruction, the first byte specifies the operation code and the second byte
specifies the operand. Source operand is a data byte immediately following the opcode. For
example:

Load an 8-bit data MVI A, Data 0011 1110 3E First byte
byte in the
accumulator. DATA DATA Second byte
Example:
The instruction would require two memory locations to store in memory.
a. MVI r, data
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r <-- data
Example: MVI A, 30H
It will coded as (3E 30) H as two contiguous bytes. This is an example of immediate addressing.
b. ADI data
A <-- A + data
OUT port: where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data but
points directly to where it is located this is called direct addressing.
Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and the following two bytes
specify the 16-bit address or 16-bit data. Note that the second byte is the low-order address or
data and the third byte is the high-order address or data. Opcode + data byte + data byte
For example:

Transfer the JMP 2085H 1100 0011 C3 First byte
program sequence 1000 0101 85 Second byte
to the memory 0010 0000 20 Third byte
location 2085H
This instruction would require three memory locations to store in memory.
Three byte instructions - opcode + data byte + data byte
LXI rp, data16
rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. Example:
a. LXI H, 0520H coded as 21H 20H 05H in three bytes. This is also immediate addressing. (where
21H is corresponding to opcode of LXI H, data)
b. LDA addr
A<--(addr) Addr is a 16-bit address.
Example: LDA 2134H coded as 3AH 34H 21H. This is also an example of direct addressing.
3. Classification Based on operation:

An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The entire group of instructions, called the instruction set, determines what functions
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the microprocessor can perform. These instructions can be classified into the following five
functional categories: data transfer (copy) operations, arithmetic operations, logical operations,
branching operations, and machine-control operations.
Data Transfer (Copy) Operations:

This group of instructions copy data from a location called a source to another location
called a destination, without modifying the contents of the source. In technical manuals, the
term data transfer is used for this copying function. However, the term transfer is misleading; it
creates the impression that the contents of the source are destroyed when, in fact, the
contents are retained without any modification.
The various types of data transfer (copy) are listed below together with examples of each type:
Types Examples
1. Between Registers 1. Copy the content of the register B into
register D.
MOV D,B
2. Specific data byte to a register or a 2. Load register B with the data byte 32H
memory location MVI B, 32H
3. Between a memory location and a 3. From a memory location 2000H to register B.

register MOV B, M; as H=20 and L=20
4. Between an I/O device and the 4. From an input keyboard to the accumulator.
accumulator IN 00H
I. Arithmetic Operations:
These instructions perform arithmetic operations such as addition, subtraction, increment, and
decrement.
Addition: Any 8-bit number, or the contents of a register or the contents of a memory
location can be added to the contents of the accumulator and the sum is stored in the
accumulator. No two other 8-bit registers can be added directly (e.g., the contents of register B
cannot be added directly to the contents of the register C). The instruction DAD is an exception;
it adds 16-bit data directly in register pairs.
Subtraction: Any 8-bit number, or the contents of a register, or the contents of a memory
location can be subtracted from the contents of the accumulator and the results stored in the
accumulator. The subtraction is performed in 2's compliment, and the results if negative, are
expressed in 2's complement. No two other registers can be subtracted directly.
Increment/Decrement: The 8-bit contents of a register or a memory location can be

incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such as BC) can
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be incremented or decrement by 1. These increment and decrement operations differ from

addition and subtraction in an important way; i.e., they can be performed in any one of the
registers or in a memory location.
II. Logical Operations:

These instructions perform various logical operations with the contents of the accumulator.
AND, OR, Exclusive-OR: Any 8-bit number, or the contents of a register, or of a memory
location can be logically ANDed, Ored, or Exclusive-ORed with the contents of the accumulator.
The results are stored in the accumulator.
Rotate: Each bit in the accumulator can be shifted either left or right to the next position.
Compare: Any 8-bit number, or the contents of a register, or a memory location can be
compared for equality, greater than, or less than, with the contents of the accumulator.
Complement: The contents of the accumulator can be complemented. All 0s are replaced by
1s and all 1s are replaced by 0s.
III. Branching Operations:

This group of instructions alters the sequence of program execution either conditionally or
unconditionally.
Jump: Conditional jumps are an important aspect of the decision-making process in the
programming. These instructions test for a certain conditions (e.g., Zero or Carry flag) and alter
the program sequence when the condition is met. In addition, the instruction set includes an
instruction called unconditional jump.
Call, Return, and Restart: These instructions change the sequence of a program either by
calling a subroutine or returning from a subroutine. The conditional Call and Return instructions
also can test condition flags.
Machine Control Operations:

These instructions control machine functions such as Halt, Interrupt, or do nothing. The
microprocessor operations related to data manipulation can be summarized in four functions:
1. Copying data
2. Performing arithmetic operations
3. Performing logical operations
4. Testing for a given condition and alerting the program sequence
Some important aspects of the instruction set are noted below:
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1. In data transfer, the contents of the source are not destroyed; only the contents of the
destination are changed. The data copy instructions do not affect the flags.
2. Arithmetic and Logical operations are performed with the contents of the accumulator, and
the results are stored in the accumulator (with some expectations). The flags are affected
according to the results.
3. Any register including the memory can be used for increment and decrement.
4. A program sequence can be changed either conditionally or by testing for a given data
condition.
Data transfer instructions: These instructions are used to transfer data from register to
register, register to memory or from memory to register. No flags will be affected for these
instructions. r1, r2, r can be any one out of B, C, D, E, H, L, A and r p can be any one out of three
register pairs BC, DE & HL.
MOV r1,r2 (r1)< (r2)
MOV r, M (r) < (M)
MOV M, r (M) < (r)
MVI(r/M),d8 (r/M) < (8 - bit data) d8
LXI rp 16-bit rp= BC, DE, HL or SP
LDA 16 - bit address
STA 16-bit address
LHLD 16-bit address
SHLD 16-bit address
LDAX rp rp can be either BC or DE pair only not HL pair
STAX rp
XCHG (HL) (DE)
PCHL (PC) (HL)
Arithmetic Instructions: This group consists of addition, subtraction, increment and decrement
operations. 8085 microprocessor does not support multiplication and division instructions
ADD r (A) (A) + (r)
ADD M (A) (A) + (M)
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ADI data (A) (A) + data
ADC r (A) (A) + (r) + Cy
ADC M (A) (A) + (M) + Cy
ACI data (A) (A) + data + Cy
SUB r (A) (A)-(r)
SUB M (A) (A)-(M)
SUI data (A) (A)- data
SBB r (A) (A)-(r)-Cy
SBB M (A) (A) - (M) - Cy
SBI data (A) (A)- data- Cy
INR r (r) (r) + 1
INR M (M) (M) + 1
INX rp (rp) (rp) + 1 (rp = BC, DE, HL or SP)
DCR r (r) (r)-1
DCR M (M) (M) - 1
DCX rp (rp) (rp) - 1 (rp = BC, DE, HL or SP)
DAD rp (HL) (HL) + (rp) (rp = BC, DE, HL or SP)
DAA
> In 8085, the service of AC flag is used by only one instruction. It is DAA.
> For INX and DCX instructions no flags affected
> Following table shows the list of flags affected for different instructions
Instruction S Z Ac P Cy
INR, DCR Yes Yes Yes Yes No
DAD No No No No Yes
ADD, ADC, SUB, SBB, DAA Yes Yes Yes Yes Yes
157
Logical Instructions: This group consists of AND, OR, NOT, XOR, Compare and Rotate perations
ORA r (A) (A) V (r)
ORA M (A) (A) V (M)
ORI data (A) (A) V data
ANA r (A) (A) A (r)
ANA M (A) (A) A (M)
ANI data (A) (A) A data
XRA r (A) (A) ⊕ (r)
XRA M (A) (A) ⊕ (M)
XRI data (A) (A) ⊕data

CMP r (A)  r)

CMPM (A)  (M)

CPI 45 (A)  45
CMA (A) ( A)
CMC Cy 𝐶𝑦
STC Cy 1
RLC Rotate accumulator left
RAL Rotate Accumulator left through carry
RRC Rotate accumulator right
RAR Rotate Accumulator right through carry
Following table shows how flags affected for different logical instructions
Instruction S Z Ac P Cy
ANA Yes Yes 1 Yes 0
158
ORA,XRA Yes Yes 0 Yes 0

RLC, RRC, RAL, RAR, STC,CMC No No No No Yes
CMP, CPI Yes Yes Yes Yes Yes
CMA No No No No No
Branch Instructions: These are also called program control transfer instructions. These are two
types: Un conditional branch and Conditional Branch instructions
> No flags will be affected for branch instructions
> Unconditional Branch Instructions:
JMP 16-bit address
CALL 16-bit address
RET
RST n (n = 0 to 7)
PCHL
> PCHL is one byte equivalent of three byte JMP Instruction
> RST n is one byte equivalent of three byte CALL instruction
Conditional branch instruction:
Jump Instructions Call Instructions Return Instruction Condition

JZ 16-bit addr CZ 16 -bit addr RZ Z=1
JNZ 16-bit addr CNZ 16 -bit addr RNZ Z=0
JC 16 -bit addr CC 16 -bit addr RC Cy=1
JNC 16-bit addr CNC 16 -bit addr RNC CY = 0
JP 16 -bit addr CP 16 -bit addr RP S=0
JM 16-bit addr CM 16 -bit addr RM S=1
JPO 16-bit addr CPO 16-bitaddr RPO P=0
JPE 16 -bit addr CPE 16-bitaddr RPE P=1
Machine Control, Stack and IO related Instructions: No flags affected for these instructions.
Machine Control: El, DI, SIM, RIM, NOP, HLT
159
Stack related:
PUSH rp (rp = BC, DE, HL)
PUSH PSW
POP rp
POP PSW
LXISP, 16-bit addr
SPHL
 IO Related:
IN 8 - bit Port address
OUT 8 - bit Port address
160
Instruction table:
161
COMPARISION OF PUSH AND POP INSTRUCTIONS WITH CALL AND RET INSTRUCTIONS
The instructions PUSH and POP are similar to the instructions CALL and RET. The Similarities and
differences are as follows:
162
PUSH and POP CALL and RET

The programmer uses the instructions PUSH to When CALL is executed, the microprocessor
save the contents of register Specified register automatically stores the 16-bit address of the
pair on the stack instruction next to CALL on the stack.
When PUSH is executed, the stack pointer When CALL is executed, the stack pointer
register is decremented by two register is decremented by two
The instruction POP transfers the contents of The instruction RET transfers the contents of the
the top two locations of the stack to the top two locations of the stack to Program
specified register pair. counter
When the instruction POP is executed the When the instruction RET is executed, the stack
stack pointer is incremented by two pointer is incremented by two
There are no conditional PUSH and POP In addition to the unconditional CALL and RET
instructions. instructions, there are eight conditional CALL
and RETURN instructions
Sample Programs
1) Write an assembly program to add two numbers 8B and 6F H and store result at port 1.
Program
MVI D, 8BH
MVI C, 6FH
MOV A, C
ADD D
OUT PORT1
HLT
2) Write an assembly program to multiply a number by 8 and store result at port 1.
Program
MVI A, 30H
RRC
RRC
RRC
OUT PORT1
HLT
3) Write an assembly program to find greatest between two numbers and send to port 1. If
both numbers are same then send 00 H to port 1.
Program
MVI B, 30H
MVI C, 40H
MOV A, B
163
CMP C
JZ EQU
JC GRT
OUT PORT1
HLT
EQU: MVI A, 00H
OUT PORT1
HLT
GRT: MOV A, C
OUT PORT1
HLT
> Each instruction cycle of the 8085 microprocessor can be divided into a few basic
operations called machine cycles, and each machine cycle can be divided into T-states.
Machine cycle: It is defined as the time required to complete the operation of accessing
either memory or I/O. In the 8085, the machine cycle may consist of three to six T-states.
> T-state is defined as one sub-division of the operation performed in one clock-period.
> The time required to complete the execution of an instruction is called instruction cycle.
> The 8085 instruction cycle consists of one to five machine cycles or one to five
operations.
> The first machine cycle of 8085 consists of four or six T-states and all other subsequent
machine cycles consist of three T-states only.
> Read or write signal is generated at the beginning of T2 and will be completed before the
end of T3 in every machine cycle.
> Types of machine cycles of 8085 : Op Code fetch cycle, Memory read cycle, Memory
write cycle, I/O read cycle, I/O write cycle, Interrupt acknowledge machine cycle and Bus
idle machine cycle.
> The first machine cycle of each instruction cycle is always Op Code fetch machine cycle.
> In 8085, CALL instruction is the lengthy instruction which takes 18-T states and the
shortest instruction takes only 4-T states (Ex: MOV A,B ).
> One machine is essential for each and every instruction. Other machine cycles depends on
operation of the instruction.
> ALE signal is generated during T1 state of each machine cycle since at that time lower order
data is available on multiplex AD0 to AD7 bus.
> Machine cycle format for CALL instruction is given below:
164
M1(opcode) M2(mw) M3(mw) M4(mr) M5(mr)

Tl T2 T3 T4 T5 T6 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
 For one byte instruction at least opcode fetch m/c is present

 For two byte instruction at least opcode fetch and one memory read m/c are present
 For three byte instruction at least opcode fetch and two memory read m/c are present
Mnemonic M/C Clock Cycles (T-State)
MOVE, LOAD, AND STORE
MOV r1 r2 1-opcode 4
MOV M r 1-opcode, 1-MW 7
MOV r M 1-opcode, 1-MR 7
MVI r 1-opcode, 1-MR 7
MVI M 1-opcode, 1-MR, 1-MW 10
LXI B 1-opcode, 2-MR 10
LXI D 1-opcode, 2-MR 10
LXI H 1-opcode, 2-MR 10
LXI SP 1-opcode, 2-MR 10
STAX B 1-opcode, 1-MW 7
STAX D 1-opcode, 1-MW 7
LDAX B 1-opcode, 1-MR 7
LDAX D 1-opcode, 1-MR 7
STA 1-opcode, 2-MR, 1-MW 13
LDA 1-opcode, 3-MR 13
SHLD 1-opcode, 2-MR, 2-MW 16
LHLD 1-opcode, 4-MR 16
XCHG 1-opcode 4
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STACK OPS
PUSH B 1-opcode, 2-MW 12
PUSH D 1-opcode, 2-MW 12
PUSH H 1-opcode, 2-MW 12
PUSH PSW 1-opcode, 2-MW 12
POP B 1-opcode, 2-MR 10
POP D 1-opcode, 2-MR 10
POP H 1-opcode, 2-MR 10
POP PSW 1-opcode, 2-MR 10
XTHL 1-opcode, 2-MR, 2-MW 16
SPHL 1-opcode 6
JUMP
JMP 1-opcode, 2-MR 10
JC 1-opcode, 2-MR/1-opcode, 1-MR 10/7
JNC 1-opcode, 2-MR/1-opcode, 1-MR 10/7
JZ 1-opcode, 2-MR/1-opcode, 1-MR 10/7
JNZ 1-opcode, 2-MR/1-opcode, 1-MR 10/7
JP 1-opcode, 2-MR/1-opcode, 1-MR 10/7
JM 1-opcode, 2-MR/1-opcode, 1-MR 10/7
JPE 1-opcode, 2-MR/1-opcode, 1-MR 10/7
JPO 1-opcode, 2-MR/1-opcode, 1-MR 10/7
PCHL H & L to program counter 6
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CALL
CALL 1-opcode, 2-MR, 2-MW 18
CC 1-opcode, 2-MR, 2-MW/1-opcode, 1-MR 18/9
CNC 1-opcode, 2-MR, 2-MW/1-opcode, 1-MR 18/9
CZ 1-opcode, 2-MR, 2-MW/1-opcode, 1-MR 18/9
CNZ 1-opcode, 2-MR, 2-MW/1-opcode, 1-MR 18/9
CP 1-opcode, 2-MR, 2-MW/1-opcode, 1-MR 18/9
CM 1-opcode, 2-MR, 2-MW/1-opcode, 1-MR 18/9
CPE 1-opcode, 2-MR, 2-MW/1-opcode, 1-MR 18/9
CPO 1-opcode, 2-MR, 2-MW/1-opcode, 1-MR 18/9
RETURN
RET 1-opcode, 2-MR 10
RC 1-opcode, 2-MR/1-opcode 12/6
RNC 1-opcode, 2-MR/1-opcode 12/6
RZ 1-opcode, 2-MR/1-opcode 12/6
RNZ 1-opcode, 2-MR/1-opcode 12/6
RP 1-opcode, 2-MR/1-opcode 12/6
RM 1-opcode, 2-MR/1-opcode 12/6
RPE 1-opcode, 2-MR/1-opcode 12/6
RPO 1-opcode, 2-MR/1-opcode 12/6
RESTART
RST n 1-opcode, 2-MW 12
INPUT/OUTPUT
IN 1-opcode, 1-MR, 1-IOR 10
OUT 1-opcode, 1-MR, 1-IOW 10
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INCREMENT AND DECREMENT
INR r 1-opcode 4
DCR r 1-opcode 4
INR M 1-opcode, 1-MR, 1-MW 10
DCR M 1-opcode, 1-MR, 1-MW 10
INX B 1-opcode 6
INX D 1-opcode 6
INX H 1-opcode 6
INX SP 1-opcode 6
DCX B 1-opcode 6
DCX D 1-opcode 6
DCX H 1-opcode 6
DCX SP 1-opcode 6
ADD
ADD r 1-opcode 4
ADC r 1-opcode 4
ADD M 1-opcode, 1-MR 7
ADC M 1-opcode, 1-MR 7
ADI 1-opcode, 1-MR 7
ACI 1-opcode, 1-MR 7
DAD B 10
DAD D 10
DAD H 10
DAD SP 10
168
SUBTRACT
SUB r 1-opcode 4
SBB r 1-opcode 4
SUB M 1-opcode, 1-MR 7
SBB M 1-opcode, 1-MR 7
SUI 1-opcode, 1-MR 7
SBI 1-opcode, 1-MR 7
LOGICAL
ANA r 1-opcode 4
XRA r 1-opcode 4
ORA r 1-opcode 4
CMP r 1-opcode 4
ANA M 1-opcode, 1-MR 7
XRA M 1-opcode, 1-MR 7
ORA M 1-opcode, 1-MR 7
CMP M 1-opcode, 1-MR 7
ANI 1-opcode, 1-MR 7
XRI 1-opcode, 1-MR 7
ORI 1-opcode, 1-MR 7
CPI 1-opcode, 1-MR 7
ROTATE
RLC 1-opcode 4
RRC 1-opcode 4
RAL 1-opcode 4
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RAR 1-opcode 4
SPECIALS
CMA 1-opcode 4
STC 1-opcode 4
CMC 1-opcode 4
DAA 1-opcode 4
CONTROL
EI 1-opcode 4
DI 1-opcode 4
NOP 1-opcode 4
HLT 5
RIM 1-opcode 4
SIM 1-opcode 4
Where MR: memory read, Mw: memory write, IOR: I/O read, IOW: I/O write.
Mapping: Assigning addresses to I/O devices or memory location is called mapping.

Memory mapping: Assigning address to memory locations is called memory mapping.
Memory mapping can be changed by changing the hardware logic used for the chip selection.
I/O devices can be connected to microprocessor in two different techniques.
1) Memory mapped I/O technique

2) I/O mapped I/O technique
Memory mapped I/O technique:

In memory mapped I/O, the I/O devices are also treated as memory location, under that
assumption they will be given 16-bit address. In memory mapped I/O, microprocessor uses
memory related instruction to communicate with I/O devices. Ex: STA; LDA; MOV A, M; etc.
In memory mapped I/O, MEMR and MEMW control signals are used to activate I/O devices. In
memory mapped I/O, the entire memory map is shared by memory locations and I/O devices.
One address can be used by once. This technique is used in a system where the numbers of I/O
170
devices are less. The maximum number of I/O devices can be connected to microprocessor in
this technique are 65536.
I/O mapped I/O technique:

In this technique the I/O devices are identified by the, microprocessor with separate 8-bit
address. This technique uses separate control signals ( IOR and IOW)to activate I/O devices and
separate instructions ( IN and OUT ) to communicate with I/O devices.
In this technique I/O mapping is independent of memory mapping. Same address can be used
to identify input device and output device. This technique is used in a system where numbers of
I/O devices are more. By using this method a maximum of 256 input devices & 256 output
devices can be connected to the processor (total of 512 I/O devices).
Interfacing:
Designing hardware circuit and writing software instruction to enable the
microprocessor to communicate with peripheral devices is called interfacing. And the hardware
circuit is called the interfacing devices.
There are two basic types of interfacing devices are available.
1) Non-programmable interfacing devices

2) Programmable interfacing devices
Non-programmable interfacing devices: once the microprocessor based system is

designed it is not possible to program this type of devices. For example- 8212- Non-
programmable I/O port, 74LS245- Bi-directional buffers, 74LS373- transparent latches, etc.
Programmable interfacing devices: writing a specific word, called the control word,
according to the internal logic, can program a programmable interfacing device.
1. 8155- Programmable Peripheral Interfacing (PPI) device with 256 bytes RAM and 16-bit
timer/counter. It is a general purpose interfacing device i.e. it can be used to interface
variety of I/O devices to the microprocessor.
2. 8255- PPI. It is also called programmable interface adapter (PIA). It consist of three 8-bit
ports.
3. 8253- Programmable Interval Timer. It can work in six different modes.
Mode 0- Interrupt on terminal count
Mode 1- Programmable one shot
Mode 2- Rate generator
Mode 3- Square wave generator
Mode 4- Software Triggered strobe
Mode 5- Hardware Triggered strobe
4. 8251- Programmable communication interfacing device. It is also called USART (universal
synchronous Asynchronous receiver transmitter).
171
5. 8257- Programmable DMA (Direct memory access) controller, DMA transfer is an I/O
technique used commonly for high speed data transfer. The 8257 is a four channel DMA
controller.
6. 8259- Programmable Interrupt Controller (PIC). It is equivalent to providing eight INTR
pins on 8085 microcontroller. By using nine 8259 IC’s it is possible to connect a maximum
of 64 I/O devices to the microprocessor with interrupt driven data transfer mode.
7. 8272- Programmable floppy disk controller
8. 8275- Programmable CRT controller
9. 8179- Programmable keyboard and display interfacing device. By using this it is possible
to connect sixteen seven segment display and sixty four keys (8 x 8 matrix) to the
microprocessor.
172
Problems:
1) In a DMA write operation the data is transferred
A) from I/O to memory. B) from memory to I/O.
C) from memory to memory. D) from I/O to I/O.
2) A certain SRAM has 𝐶𝑆 = 0 ,𝑊𝑅 = 0 and 𝑅𝐷 = 1. In which of the following modes this SRAM
is operating.
A) Read B) Write C) Stand by D) None of the above
3) Number of the times the instruction sequence below will loop before coming out of loop is
MVI A, 00 H
A1: INC A
JNZ A1
A) 01 B) 257 C) 255 D) 256
4) What will be the contents of register AL after the following has been executed
MVI B, 8C H
MVI A, 7E H
ADD A, B
A) 0A and carry flag is set B) 0A and carry flag is reset
C) 6A and carry flag is set D) 6A and carry flag is reset
5) Itanium processor of Intel is a
A) 32 bit microprocessor. B) 64 bit microprocessor.
C) 128 bit microprocessor. D) 256 bit microprocessor.
6) Which of the following statement is true?
A) The group of machine cycle is called a state.
B) A machine cycle consists of one or more instruction cycle.
C) An instruction cycle is made up of machine cycles and a machine cycle is made up of

number of states.
D) None of the above
173
7) Which microprocessor pins are used to request and acknowledge a DMA transfer?
A) reset and ready B) ready and wait
C) HOLD and HLDA D) None o these
8) The no. of address lines required to address a memory of size 32 K is
A) 15 lines B) 16 lines C) 18 lines D) 14 lines
9) Number of address lines required to address 8 k bytes of memory is
A) 13 B) 14 C) 15 D) 16
10) While an instruction is executed, the program counter should contain the address of
A) the current instruction B) the next sequential instruction
C) the operand D) the previous instruction
11) Static RAM
A) is a volatile memory B) is a non-volatile memory
C) needs refreshing to retain value D) cannot be modified
12) The duration of one T-state in the 8085 microprocessor that uses a crystal of 5 MHz is
A) 0.2us B) 0.4us C) 2.5us D) 5us
13) An instruction of the 8085 microprocessor that requires both memory read and memory
write machine cycle is
A) MVI M, 8F B) LHLD 8088 C) RST1 D) ADD M
14) An arithmetic operation of 8085 microprocessor sets the sign and parity flags. The content
of the accumulator after the execution of the operation can be
A) 1011 0100 B) 0010 1101 C) 1010 1101 D) 0110 0111
15) The contents of the HL register pair after the execution of the following program on the
8085 are
LXI H, 2095 H
LXI B, 8FBF H
LXI SP, 9FFF H
PUSH B
XTHL
POPH
HLT
A) 2095 H B) 9FFF H C) 9FFD H D) 8FBF H
16) The contents of the Accumulator after the execution of the following program on the 8085
are
XRA A
MVI B, F0 H
SUB B
A) 01H B) 0FH C) F0H D) 10H
174
17) The 8085 assembly language instruction that stores the content of L and H registers into
the memory locations 2050H and 2051H respectively is
A) SPHL 2050H B) SPHL 2051H C) SHLD 2050H D) STAX 2050H
18) A memory system has a total of 8 memory chips, each with 12 address lines and 4 data
lines. The total size of the memory system is
A) 16kbytes B) 32kbytes C) 48kbytes D) 64kbytes
19) Which one of the following is not a vectored interrupt?
A) TRAP B) INTR C) RST 7.5 D) RST 6.5
20) In an 8085 microprocessor, after the execution of XRA A instruction
A) the carry flag is set B) the accumulator contains FF H
C) the zero flag is set D) the accumulator contents are shifted by one bit
21) An 8085 assembly language program is given as follows. The execution time of each
instruction is given against the instruction in terms of T-state.
Instructions T-states
MVI B, 0A H 7T
LOOP: MVI C, 05H 7T
DCR C 4T
DCR B 4T
JNZ LOOP 10T/7T
The execution time of the program in terms of T-states is
A) 247 T B) 250 T C) 254 T D) 257 T
22) In an INTEL 8085 microprocessor the address bus and data bus are
A) Non-multiplexed B) Multiplexed
C) Duplicated D) same as control bus
23) Which of the following microprocessor has a 16-bit data bus?
A) 8085 B) Z-80 C) 68000 D) 6502
24) The address bus of any microprocessor is always
A) Unidirectional B) Bi-directional
C) Either unidirectional or bi-directional D) None
25) The number of hardware interrupt present in 8085 microprocessor are
A) 5 B) 8 C) 10 D) 16
26) Identify the non-maskable interrupt from the following
A) RST 7.5 B) RST 6.5 C) RST 5.5 D) RST 4.5
27) Maximum number of either input or output devices that can be addressed by 8085 in I/O
map I/O is
A) 65,536 B) 255 C) 512 D) 256
28) The interrupt vector address for TRAP is
A) 0000H B) 0024H C) 0018H D) 002CH
29) During OPCODE fetch the state of S0 and S1 is
A) 00 B) 01 C) 10 D) 11
30) The interrupt which is only edge-triggered is
A) INTR B) TRAP C) RST 7.5 D) RST 5.5
31) Consider the following loop
XRA A
175
LXI B ,0007H
LOOP: DCX B
JNZ LOOP
HLT
The loop will be executed
A) 1 TIMES B) 2 TIMES C) 7 TIMES D) INFINITE TIMES
Answers:
1. A 2. B 3. D 4. A 5. B 6. B 7. C 8. A 9. A
10. B 11. A 12. B 13. A 14. A 15. A 16. D 17. C 18. A
19. B 20. C 21. C 22. B 23. C 24. A 25. A 26. D 27. D
28. B 29. D 30. C 31. A
176
Additional questions on microprocessor:
1. An 8-bit microprocessor signifies that it has

(a) 8-bit address bus (b) 8-bit controller
(c) 8-interrupt lines (d) 8-bit data bus
2. Which of the following microprocessor is not an 8-bit microprocessor?

(a) 8085 (b)Z-80 (c) 68000 (d) 6502
3. Which of the following microprocessor has a 16-bit data bus?

(a) 8085 (b) Z-80 (c) 68000 (d) 6502
4. A microcomputer consists of
(a) a microprocessor (b) memory (c) I/O devices (d) all of the above
5. A microprocessor consists of
(a) ALU (b) Control unit (c) array of registers (d) all of the above
6. The address bus of any microprocessor is always

(a) Unidirectional (b) Bi-directional (c) Either unidirectional or bi- directional (d) None
7. The data bus of any microprocessor is always

(a) Unidirectional (b) bi-directional
(c) Either unidirectional or bi- directional (d) None
8. The multiplexing of address bus and data buses is used in

(a) all the microprocessors (b) depends on the internal architecture
(c) never multiplexed (d) none of these
9. The multiplexing of address bus and data buses is used in microprocessors

(a) To reduce speed of operation (b) To increase the number of pins
(c) To reduce the number of pins on IC (d) To improve the operation
10. The address bus width of a microprocessor which is capable of addressing 1K bytes of
memory is
(a) 10 (b) 12 (c) 16 (d) 20
11. The address bus width of a microprocessor which is capable of addressing 64K bytes of
memory is
(a) 8 (b) 12 (c) 16 (d) 20
12. The data bus width of a microprocessor which is capable of addressing 1M bytes of memory
is
(a) 16 (b) 8 (c) 20 (d) can not be predicated
177
13. An 8-bit microprocessor can have-------address lines.

(a) 8 (b)16 (c) 20 (d) can not be predicated
14. A number of 1-bit registers used in microprocessors to indicate certain conditions are
usually referred to as
(a) Shift registers (b) flags (c) latches (d) counters
15. A microprocessor has an 8-bit opcode. The maximum possible number of opcodes for this
microprocessor will be
(a) 256 (b)64 (c) 8 (d) 16
16. The Program Counter in a microprocessor always holds

(a) the number of programs being executed on the microprocessor
(b) the number of instructions being executed on the microprocessor
(c) the number of interrupts handled by the microprocessor
(d) the address of the next instruction to be fetched.
17. The word size of 8085 microprocessor is

(a) 4-bit (b) 8-bit (c) 16-bit (d) 20-bit
18. How many 16-bit special purpose registers are present in the 8085 microprocessor?
(a) 8 (b) 6 (c) 2 (d) 16
19. The Stack Pointer register in a microprocessor

(a) counts the number of programs being executing on the microprocessor
(b) counts the number of instructions being executing on the microprocessor
(c) keeps the address of the next instruction to be fetched
(d) holds the address of the top of the stack
20. The number of status flags present in 8085 microprocessor are

(a) 8 (b) 16 (c) 5 (d) 10
21. The number of hardware interrupts present in 8085 microprocessor are

(a) 5 (b) 8 (c) 10 (d)16
22. Which of the following statements is false?

(a) A microprocessor has bi-directional address bus
(b) A microprocessor has a unidirectional address bus
(c) A microprocessor has a bi-directional data bus
(d) A microprocessor has an ALU
23. Identify the non-maskable interrupt from the following

(a) RST 7.5 (b) RST 6.5 (c) RST 5.5 (d) RST 4.5
178
24. In microprocessor based systems DMA refers to

(a) direct memory access for the microprocessor
(b) direct memory access for the user
(c) direct memory access for the I/O devices
(d) none of the above
25. The interrupt facility is provided in microprocessor to

(a) change the sequence of instructions being executed
(b) stop the microprocessor when desired
(c) stop the microprocessor when it starts malfunctioning
(d) keep a control on the working of the microprocessor
26. A microprocessor differentiates between opcode, data/address at any time by

(a) the sequence in which memory contents are fetched by it
(b) Its internal registers
(c) the stack pointer
(d) the program counter
27. A microprocessor without the interrupt facility

(a) is best suited for a process control system
(b) is not useful for a process control system
(c) can not be used for DMA operation
(d) can not be interfaced with any I/O device
28. In microprocessor based systems I/O ports are used to interface

(a) The I/O devices and memory chips (b) the I/P device only
(c) The O/P devices only (d) all the I/O devices
29. The stack pointer

(a) Resides in RAM (b) resides in microprocessor
(c) Resides in ROM (d) may be in RAM or ROM
30. In a microprocessor based system, the stack is always in

(a) Microprocessor (b) RAM (c) ROM (d) EPROM
31. The instruction set of a microprocessor

(a) Is specified by the manufacturers (b) is specified by the user
(c) Can not be changed by the user (d) is stored inside the microprocessor
32. An 8085 microprocessor uses a crystal of frequency 6.25 MHz . The T stale vaiue is
(a) 340ns (b) 640ns (c) 960ns (d) 1280ns
33. In an 8085 microprocessor based system, the contents of SP are 1000H. PUSH B instruction
will transfer the contents of registers B and C respectively for memory locations
179
(a) OFFFH and OFFEH (b) OFFE H and OFFF H

(c)1000H and OFFFH (d) 1000 H and 1001 H
34. In an 8085 microprocessor based system, the contents of SP are 2000H. POPH instruction
will transfer the contents of memory location
(a) 2001H and 2002H to H and L registers respectively
(b) 2001H and 2000H to H and L registers respectively
(c) 2000H and 1FFFH to H and L registers respectively
(d) 2000H and 1999H to H and L registers respectively
35. PUSH B instruction in 8085 microprocessor causes

(a) the contents of register B only to be copied in the stack
(b) the contents of register B and C to be copied in the stack
(c) the contents of registers B and C to be transferred in the stack and the registers get cleared
(d) registers B and C to be cleared.
36. SUB A instruction in 8085

(a) resets carry and sign flags (c) sets zero and sign flags
(b) resets zero and parity flags (d) sets zero and carry flags
37. In 8085 microprocessor, let the accumulator contains the value 0AH and register C contains
the value 05H. After CMPC instruction is executed, the
(a) zero and carry flags will be set
(b) zero and carry flags will be reset
(c) zero flag will be set and the carry flag will be reset
(d) zero flag will be reset and the carry flag will be set
38. When an 8085 microprocessor is reset, the address bus contains

(a) 0000H (b) 002CH (c) 0043H (d) 003CH
39. Which of the data transfer is not possible in microprocessor

(a) memory to accumulator (b) accumulator to memory
(c) memory to memory (d) I/O device to accumulator
40. In 8085 microprocessor, in response to RST 7.5 interrupts the execution is transferred to
memory location
(a) 0000H (b) 002CH (c) 0034H (d) 003CH
41. In 8085 microprocessor, which of the following statements is false?

(a) there is a pin available for serial input
(b) there is a pin available for serial output
(c) serial I/O is possible through RIM and SIM instructions
(d) serial I/O is not possible
180
42. EPROM s are preferred for storing programs while developing new microprocessor based
system because of their
(a) non-volatile characteristic
(b) erasable and programmable characteristic
(c) random access characteristic
(d) all the above characteristics
43. When any data transfer instruction, for transfer of data between memory and
microprocessor, is executed the condition flags are
(a) not affected (b) always set
(c) always reset (d) affected indicating specific conditions
44. Let the contents of the accumulator and register B be 00000100 and 01000000 respectively
before execution of instruction SUB B. The contents of the accumulator after the execution of
this instruction will be
(a) 00000100 (b) 01000000 (c) 11000100 (d) 010001000
45. Let the contents of register C be 00000000 before DCR C is executed. The contents of C
after the execution of this instruction will be
(a) 00000000 (b) 11111111 (c) 00000001 (d) None
46. In an 8085 microprocessor based system the maximum possible number input/output
devices can be connected using I/O mapped I/O technique is given by
(a) 64 (b) 512 (c) 256 (d) 65536
47. Cycle-sealing mode of DMA operation involves

(a) DMA controller taking over the address, data, and control buses while a block of data is
transfer between memory and I/O device.
(b) While the microprocessor is executing a program an interface circuit takes over control of
address, data, control buses when not in use by microprocessor
(c) Data transfer takes place between the I/O device and memory during every alternate clock
cycle
(d) The DMA control waiting for the microprocessor to finish execution of the program and then
takes over the buses
48. Which of the following is not true during the execution of an interrupt service routine,
which does not contain any El instructions
(a) the microprocessor can be interrupted by a non-maskable interrupt
(b) the microprocessor can not be interrupted by any interrupt
(c) the microprocessor can not be interrupted by any masksble interrupt
(d) all interrupts except the non-maskable interrupt are disable
49. The reasons for the presence of ALE pin in 8085, but not in 6800 is that
(a) 8085 uses I/O mapped I/O, whereas 6800 uses memory mapped I/O
(b) 8085 has 5 interrupts lines, whereas 6800 has only two
181
(c) 8085 has multiplexed bus, whereas 6800 does not have
(d) None
50. Which of the following interrupt is both level and edge sensitive?
(a) RST5.5 (b) INTR (c) RST 7.5 (d) TRAP
51. The addressing mode used in the instruction PUSH B is

(a) direct (b) register (c) register indirect (d) immediate
52. On receiving an interrupt from an I/O device, the CPU

(a) halts for a predetermined time
(b) hands over control of address bus and data bus to the interrupting device
(c) branches off to the interrupt service routine immediately
(d) branches off to the interrupt service routine after completion of the current Instruction
53. The ALE line of an 8085 microprocessor is used to

(a) latch the output of an I/O instruction into an external latch
(b) deactivate the chip-select signal from memory devices
(c) latch the 8-bit of address lines AD7-ADO into an external latch
(d) find the interrupt enable status of the TRAP interrupt
54. What is the execution time for the instruction, "STA ADDR", in an 8085microprocessor if the
clock frequency is 3 MHz ?
(a) 4329ns (b) 3975ns (c) 3115ns (d) 3960ns
55. The first operation performed in INTEL 8085 after RESET is

(a) instruction fetch from location 0000H (b) memory read from the location 0000H
(c) instruction fetch from location 8000H (d) stack initialization
56. After the execution of CMP A instruction

(a) ZF is set and CY is reset (b) ZF is set and CY is unchanged
(c) ZF is reset and CY is set (d) ZF is reset and CY is unchanged
57. The 8085 microprocessor will enter into INA cycle after the recognition of
(a) any interrupt (b) TRAP only
(c) INTR only (d) RST 7.5, 6.5, and 5.5 only
58. Which of the following lists the interrupts in decreasing priority?

(a) TRAP, RST 5.5, RST 6.5, RST 7.5, INTR
(b) INTR, TRAP, RST 7.5, RST 6.5, RST 5.5
(c) TRAP, RST 7.5, RST 6.5, RST 5.5, INTR
(d) RST 7.5, RST 6.5, RST 5.5, TRAP, INTR
59. The interrupt vector address for TRAP is
182
(a) 0000H (b)0024H (c)0018H (d)002CH
60. In order to reset carry without affecting accumulator content, one has to use
(a) SUB A (b)XRA A (c)ORA A (d)CMC
61. Maximum number of I/O devices that can be addressed by INTEL 8085 is
(a) 65,536 (b)255 (c)512 (d)256
62. The microprocessor may be made to exit from HALT state by asserting
(a) RESTART (b) any of the five interrupts lines
(c) READY line (d) a (or) b (or) HOLD line
63. The 8085 microprocessor enters into bus idle machine cycle whenever
(a) INTR interrupt is recognized (b) RST X.5 is recognized
(c) DAD rp instruction is executed (d) none of the above
64. In order to complement the lower order nibble of the accumulator, one can use
(a) ANI 0FH (b) XRI 0FH (c) ORI 0FH (d) CMA
65. During OPCODE fetch the state of S0 and S1 is

(a) 00 (b)01 (c)10 (d)H
66. After RESET 8255 will be in

(a) made 0, all ports are input (b) mode 0, all ports are output
(c) mode2 (d) unchanged condition
67. The microprocessor issues ALE during first T-state of

(a) fetch cycle only (b) memory READ cycle only
(c) memory WRITE cycle only (d) every machine cycle
68. The data lines of 8085 processor are multiplexed with

(a) higher order address lines (b) lower order address lines
(c) status lines (d) none of the above
69. RST 3 instruction will cause the processor to branch to the location
(a) 0000H (b) 0018H (c) 0024H (d) 8018H
70. Which of the following instruction will never affect the zero flag?
(a)DCR reg (b)ORA reg. (c)DCX rp. (d)XRA reg.
71. The content of the A15-A8 (higher order address lines) while executing "IN” address
instruction are
(a) same as the contents of A7-AO (b) irrelevant
(c) all bits reset (i.e. 00H) (d) all bits set (i.e. FFH)
183
72. Which of the following peripheral ICs is used to interface keyboard and display?
(a) 8251 (b) 8279 (c) 8259 (d) 8253
73. The only interrupt which is edge-triggered is

(a) INTR (b) TRAP (c) RST 7.5 (d) RST 5.5
74. Which one of the following instruction may be used to clear the accumulator content (i.e. A
= 00H) irrespective of its initial value?
(a) CLR A (b) ORA A (c) SUB A (d) MOV A, 00H
75. The execution of RST n instruction causes the stack pointer to

(a) increment by two (b) decrement by two
(c) remain unaffected (d) none of the above
76. The stack is nothing but a set of

(a) reserved ROM address space (b) reserved RAM address space
(c) reserved I/O address space (d) none of the above
77. S0 and S1 pins are used for

(a) serial communication (b) indicating the processor's status
(c) acknowledging the interrupt (d) none of the above
78. Pick out the matching pair

(a) READY; RIM (b) HOLD; DMA (c) SID; SIM (d) S0, S1; wait status
79. In order to save accumulator value onto the stack, which of the following instructions may
be used
(a) PUSH PSW (b) PUSH A (c) PUSH SP (d) POP PSW
80. A single instruction to clear the lower 4 bits of the accumulator in 8085 assembly
language is
(a) XRI 0F H (b) ANI F0H (c) XRI F0 H (d) ANI 0FH
81. In a vectored interrupt

(a) the branch address is assigned to a fixed location in memory
(b) the interrupting source supplies the branch information to the processor through an
interrupt vector
(c) the branch address is obtained from a register in the processor
(d) none
82. A sequence of two instructions that multiplies the contents of the DE register pair by 2
and stores the result in the HL register pair (in 8085 assembly language) is
(a) XCHG and DAD B (b) XTHL and DAD H
(c) PCHL and DAD D (d) XCHG and DAD H
184
83. Identify key board and display interfacing device from the following
(a) 8255 (b)8253 (c) 8279 (d) 8155
84. Identify the programmable interval timer from the following

(a) 8255 (b) 8253 (c) 8279 (d) 8275
85. Identify the communication interfacing device from the following

(a) 8155 (b) 8255 (c) 8251 (d) 8257
86. Identify the programmable DMA controller from the following

(a) 8257 (b) 8253 (c) 8251 (d) 8279
87. Pick up the programmable interrupt controller from the following

(a) 8279 (b) 8259 (c) 8257 (d) 8275
88. Identify the non-programmable interfacing device from the following

(a) 8295 (b) 8257 (c) 8212 (d) 8255
89. The maximum number of seven segment displays that can be connected to 8279 is
(a) 12 (b) 14 (c) 16 (d) 8
90. Using one 82591C is equivalent to providing _____________ INTR pins on 8085
(a) 16 (b) 12 (c) 8 (d) None
91. Total number of modes the 8253 can work

(a) 4 (b) 6 (c) 8 (d) 12
92. Maximum of how many devices can be connected simultaneously to the microprocessor via
8257 in DMA data transfer mode?
(a) 4 (b) 6 (c) 8 (d) 10
93. A microprocessor with a 12-bit address bus will be able to access

(a) 1K bytes (b) 4K bytes (c) 8K bytes (d) 10 K bytes
94. The frequency of the driving network connected between pins 1 and 2 of 8085 chip is
(a) twice the desired frequency (b) equal to the desired frequency
(c) four times the desired frequency (d) none of the above
95. A high on RESET OUT signifies that

(a) all the registers of the CPU are being reset.
(b) all the registers and counters are being reset,
(c) all the registers and counters are being reset and this signal can be used to reset external
support chip
(d) processing can begin when this signal goes high.
185
96. READY signal in 8085 is useful when the CPU communicates with
(a) a slow peripheral device (b) a fast peripheral device
(c) a DMA chip (d) a PPI
97. Which of the following task is not performed by an assembler

(a) providing storage allocation
(b) creating a table of labels etc.
(c) doing assembly time arithmetic
(d) translate a program written in high level language to machine code program.
98. PSW stand for

(a) accumulator contents (b) flag byte
(c) accumulator and flags register contents (d) none of these
99. During the DMA transfer the processor (check the incorrect answer)
(a) continues its normal operation
(b) suspends its normal operations
(c) needs to initiate read (write) command
(d) needs to check if the input/output device is ready for data transfer
100. In 8085, interrupts except TRAP are disabled (check the incorrect statement) by
(a) a DI instruction (b) a system reset
(c) Acknowledgement of a previous interrupt (d) none of these
Key:
1.d 2.c 3.c 4.d 5.d 6.a 7.b 8.b 9.c 10.a
11.c 12.d 13.d 14.b 15.b 16.d 17.b 18.c 19.d 20.c
21.a 22.a 23.d 24.c 25.a 26.a 27.b 28.d 29.b 30.b
31.a 32.a 33.a 34.b 35.b 36.a 37.b 38.a 39.c 40.d
41.d 42.d 43. a 44.c 45.b 46.b 47.b 48.b 49.c 50.d
51.c 52.d 53.c 54.a 55.a 56.a 57.c 58.c 59.b 60.c
61.d 62.d 63.b 64.b 65.d 66.a 67.d 68.b 69.b 70.C
71.a 72.b 73.c 74.c 75.b 76.b 77.b 78.d 79.a 80.b
81.a 82.d 83.c 84.b 85.c 8 6.a 87.b 88.c 89.c 90.c
91.b 92.a 93.b 94.a 95. c 96.a 97.d 98.c 99.a 100.a
186

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GATE THE Direction

Started by IITian so you become IITian

Electronics & Communication

CHAPTER II BOOLEAN ALGEBRA 19

CHAPTER III NUMBER SYSTEM 35

CHAPTER IV LOGIC FAMILIES 52

CHAPTER V COMBINATIONAL LOGIC CIRCUITS 68

CHAPTER VI SEQUENTIAL LOGIC CIRCUITS 90

CHAPTER VII ADC & DAC 116

CHAPTER VIII SEMICONDUCTOR MEMORY 128

CHAPTER VIII MICROPROCESSOR 140

1 = high= true = yes

Representation of logic ‘1’ & ‘0’:

eg. 1. Logic ‘1’ ------> +5 V and Logic ‘0’ ------> 0 V

2. Logic ‘1’ ------> 0 V and Logic ‘0’ ------> -5 V

b. Negative logic representation:

eg. 1. Logic ‘0’ ------> +5 V and Logic ‘1’ ------> 0 V

2. Logic ‘0’ ------> 0 V and Logic ‘1’ ------> -5 V

Truth table: Symbol: Using NAND Gate

 IC 7404 contains six NOT gates.

 If we provide feedback from output to input between odd number of inverter

Where N: Number of inverters, t p: propagation delay.

 Square wave with time period T = 2tp (2.N.tp ,here N=1 ).

Truth table: Symbol: Using NAND Gate

 AND operation is same as connection of switches in series. In below diagram light is on

 OR operation is same as connection of switches in parallel. In above diagram light is on

Truth table: Symbol:

 Bubble OR gate is NAND gate

Implementation of other gates by using only NAND gate:

Step for representing any function by NAND only:

After step 2 & 3:

Their for 4 NAND gate require.

1. Convert in reduce SOP form: f(A,B,C) = (A+B)(B+C) = B + AC

 AND – OR is analogous to NAND – NAND representation

Truth table: Symbol: Using NAND Gate:

 Bubble AND gate is NOR gate:

Implementation of other gates by using only NOR gate:

Step for representing any function by NOR only:

 OR - AND is analogous to NOR - NOR representation

1) f(A,B,C) = (A+B)(B+C) is in reduce POS form.

Three NOR gate require

Truth table: Symbol: Using NAND Gate:

 Act as inverter if one input is logic 1.

 Act as buffer if one input is logic 0.

 Act as odd parity checker and even parity generator.

Q1 = A’, Q2 = A, Q3 = A’, Q4 = A,…..

Q1 = A’, Q2 = 1, Q3 = A’, Q4 = 1,…..

Truth table: Symbol: Using NAND Gate:

Truth table for three(odd) fan-in XOR and XNOR gates

4) How many NOR gate require to construct XNOR gate

5) If XY = 0 and (X+Y)’ = 0 then find X ʘ Y

A) 0 B) 1 C) X+Y D) Data insufficient

6) If A.B=0 and A B=0 then (A+B)’ is

7) Which logic is generated by following ckt

A) OR B) AND C) NOR D) NAND

A) a NAND or an EX-OR B) an OR or an EX-NOR

C) an AND or an EX-OR D) a NOR or an EX-NOR

12) Minimum number of NAND gates required to implement XNOR gate

A) (ABC)’ B) A’+B’+C’ C) (AB)’+(BC)’+A’+C’ D) both A and B

15) The circuit shown in figure is functionally equivalent to

A) NOR gate B) OR gate C) X-OR gate D) NAND gate

23) Find output Q if B is connected to logic ‘1’

A) 50 MHz B) 25 MHz C) 8.33 MHz D) 16.66 MHz

• Commutative composition laws: A+B=B+A