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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing
Vgs (b) with increasing transistor width (c) considering Channel Length Modulation
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What are the limitations in increasing the power supply to reduce delay?
How does Resistance of the metal lines vary with increasing thickness and increasing
length?
You have three adjacent parallel metal lines. Two out of phase signals pass through the
outer two metal lines. Draw the waveforms in the center metal line due to interference.
Now, draw the signals if the signals in outer metal lines are in phase with each other
What happens if we increase the number of contacts or via from one metal layer to the
next?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for
equal rise and fall times
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later
than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would
you place near the output?
Draw the stick diagram of a NOR gate. Optimize it
For CMOS logic, give the various techniques you know to minimize power consumption
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a
Bus
Why do we gradually increase the size of inverters in buffer design? Why not give the
output of a circuit to one large inverter?
In the design of a large inverter, why do we prefer to connect small transistors in parallel
(thus increasing effective width) rather than lay out one transistor with large width?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2
input Multiplexer. You can expect any simple 2 or 3 input gates)
Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its
stick diagram
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give
the output for a square pulse input going from 0 to VDD
Draw a 6-T SRAM Cell and explain the Read and Write operations
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this
circuit? (Consider Channel Length Modulation)
Approximately, what were the sizes of your transistors in the SRAM cell? How did you
arrive at those sizes?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s
performance?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of
Clock signal?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row
Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines?
Why?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and
Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant
logic)
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you
avoid Latch Up?
ROUND 1
ROUND2
ROUND – 3 (N Aggarwal)
ROUND 4
MEMORY GROUP
ROUND1
Que: Electro migration, & How will u overcome this & at what level u
see it (In
Processing or after a chip is manufactured?)
Que: How will u calculate Electro migration & what r the data u need to
calculate
E.M.? How fingering effects the E.M.?
Que: What is Antenna effect & How metal hopping improves antenna
effects? (Positive
Charge gets collected on the metal, from where this charge comes?)
Que: Explain Latch up? How the Vdd value will come down to 0.9 if it is
5V earlier?
Que: How more substrate contact reduces +ve resistance and also well
contact?
Que: How P tap / Ntap improves latch up?
Que: When does the ESD occurs? In processing or in operation?
Que: when does the Electro migration occurs? In processing or in
Operation?
ROUND2
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VLSI
2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve
changes (a) with increasing Vgs (b) with increasing transistor width (c)
considering Channel Length Modulation
14. What are the limitations in increasing the power supply to reduce
delay?
15. How does Resistance of the metal lines vary with increasing
thickness and increasing length?
16. You have three adjacent parallel metal lines. Two out of phase
signals pass through the outer two metal lines. Draw the waveforms in
the center metal line due to interference. Now, draw the signals if the
signals in outer metal lines are in phase with each other
18. Draw a transistor level two input NAND gate. Explain its sizing (a)
considering Vth (b) for equal rise and fall times
19. Let A & B be two inputs of the NAND gate. Say signal A arrives at
the NAND gate later than signal B. To optimize delay, of the two series
NMOS inputs A & B, which one would you place near the output?
21. For CMOS logic, give the various techniques you know to minimize
power consumption
22. What is Charge Sharing? Explain the Charge Sharing problem while
sampling data from a Bus
25. Given a layout, draw its transistor level circuit. (I was given a 3
input AND gate and a 2 input Multiplexer. You can expect any simple 2
or 3 input gates)
26. Give the logic expression for an AOI gate. Draw its transistor level
equivalent. Draw its stick diagram
28. For a NMOS transistor acting as a pass transistor, say the gate is
connected to VDD, give the output for a square pulse input going from
0 to VDD
29. Draw a 6-T SRAM Cell and explain the Read and Write operations
30. Draw the Differential Sense Amplifier and explain its working. Any
idea how to size this circuit? (Consider Channel Length Modulation)
33. Approximately, what were the sizes of your transistors in the SRAM
cell? How did you arrive at those sizes?
34. How does the size of PMOS Pull Up transistors (for bit & bit- lines)
affect SRAM’s performance?
36. Draw the timing diagram for a SRAM Read. What happens if we
delay the enabling of Clock signal?
37. Give a big picture of the entire SRAM Layout showing your
placements of SRAM Cells, Row Decoders, Column Decoders, Read
Circuit, Write Circuit and Buffers
38. In a SRAM layout, which metal layers would you prefer for Word
Lines and Bit Lines? Why?
41. For an AND-OR implementation of a two input Mux, how do you test
for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can
expect a circuit with some redundant logic)
42. What is Latch Up? Explain Latch Up with cross section of a CMOS
Inverter. How do you avoid Latch Up?
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3. What are set up time & hold time constraints? What do they
signify? Which one is critical for estimating maximum clock
frequency of a circuit?
9. Give the truth table for a Half Adder. Give a gate level
implementation of the same.
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13. What are the total number of lines written by you in C/C+
+? What is the most complicated/valuable program written in
C/C++?
18. What work have you done on full chip Clock and Power
distribution? What process technology and budgets were used?
19. What types of I/O have you designed? What were their
size? Speed? Configuration? Voltage requirements?
20. Process technology? What package was used and how did
you model the package/system? What parasitic effects were
considered?
22. What transistor level design tools are you proficient with?
What types of designs were they used on?
23. What products have you designed which have entered high
volume production?
25. If not into production, how far did you follow the design
and why did not you see it into production?
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16. Can you have constant volatile variable? Yes, you can have
a volatile pointer?
33. How can you define a structure with bit field members?
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1. What is pipelining?
3. For a pipeline with ‘n’ stages, what’s the ideal throughput? What
prevents us from achieving this ideal throughput?
8. What is a cache?
10. Cache Size is 64KB, Block size is 32B and the cache is Two-
Way Set Associative. For a 32-bit physical address, give the
division between Block Offset, Index and Tag.
11. What is Virtual Memory?
19. The CPU is busy but you want to stop and do some other
task. How do you do it?
3. What are set up time & hold time constraints? What do they
signify? Which one is critical for estimating maximum clock
frequency of a circuit?
9. Give the truth table for a Half Adder. Give a gate level
implementation of the same.