Ene KC3810 - V01

KC3810
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Datasheet
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Revision 0.1
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May 2007
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Copyright©2007, ENE Technology Inc. All rights reserved.

Product Name Datasheet
Revision
Revision Description Date
0.1 1. First Release 2007/5/22
Product Serial Number ii All rights reserved.

November 7, 2007
CONTENT
CONTENT................................................................................................................0
1. FEATURES ..........................................................................................................2
1.1 FEATURE SUMMARY ..........................................................................................2
1.2 BLOCK DIAGRAM ..............................................................................................3

1.2.1 System Block Diagram ..........................................................................3
1.2.2 Block Diagram ........................................................................................4
2. PIN ASSIGNMENT AND DESCRIPTION ............................................................5
2.1 24 PIN DIAGRAM TOP VIEW ...............................................................................5
2.2 PIN ASSIGNMENT ..............................................................................................6
2.3 I/O CELL DESCRIPTIONS ....................................................................................7

2.3.1 I/O Buffer Table.......................................................................................7
3. ESB PROTOCOL DESCRIPTIONS.....................................................................8
3.1 ESB HOST (KBX926/KBX925) PACKET FORMAT ...............................................8

3.1.1 Write / Read command...........................................................................8
3.1.2 Interrupt command.................................................................................8
3.1.3 Software Reset function ........................................................................9
3.1.4 Wake up function .................................................................................10
3.1.5 ESB command types............................................................................10
3.2 ESB DEVICE RESPONSE PACKET FORMAT ........................................................11
3.2.1 Device Response Format ....................................................................11
3.2.2 Device Interrupt Response Format.....................................................12
3.2.2.1 Parallel mode ........................................................................................................... 12
3.2.2.2 Cascade mode ......................................................................................................... 12
4. REGISTERS DESCRIPTIONS ..........................................................................13
4.1 REGISTER ADDRESS MAPPING FOR EC/KBC 925/926 ......................................13
4.2 INTERNAL REGISTERS .....................................................................................13

4.2.1 Configuration Register Descriptions..................................................13
4.2.2 EGPIO....................................................................................................13
4.2.2.1 EGPIO Input / Output Control Structure................................................................ 13
4.2.3 EPWM ....................................................................................................13
4.2.3.1 EPWM Functional Descriptions ............................................................................. 13
4.2.3.2 EPWM Registers Descriptions ............................................................................... 13
4.2.4 EGPWU..................................................................................................13
4.2.4.1 EGPWU Functional Descriptions........................................................................... 13
4.2.4.2 EGPWU Registers Descriptions............................................................................. 13
5. ELECTRONIC CHARACTERISTICS.................................................................13
5.1 LA ..................................................................................................................13
5.1.1 lb ............................................................................................................13
5.2 LX ..................................................................................................................13
5.2.1 ly ............................................................................................................13
6. PACKAGING INFORMATION ...........................................................................13
Product Serial Number 1 All rights reserved.

November 7, 2007
1. Features
1.1 Feature Summary
ENE Serial Bus Interface (ESB)
• An ENE serial bus device for KBx925/26 application
• EnE Extension GPIO controller uses this scheme
ENE Peripheral Bus Master (EPBM)
• An EPBM accepts the ESD control signal and generates the control signal for EPB
devices.
General Purpose Input/Output (GPIO)
• All outputs can be optionally tri-stated
• All inputs equipped with pull-up, high/low active, edge/level trigger selection
General Purpose Wake-Up (GPWU)
• All General Purpose Input pins can be configured to generate interrupts or wake-up
events
Pulse Width Modulator (PWM)
• Four built-in PWMs
• Configurable Pre-scale Clock and high period length

November 7, 2007
1.2 Block Diagram
1.2.1 System Block Diagram

a. Parallel mode
The maximum of two devices
b. Cascade mode
The maximum of eight devices

November 7, 2007
1.2.2 Block Diagram
KC3810
Core (The core of ESB device)
REG
(configuration
register
description)
EPBM
GCLK PROT (ENE
(Gate (Protocol Peripheral
Clock) engine) Bus
Master)
CPROT
(Cascade
Protocol
engine)

November 7, 2007
2. Pin Assignment and Description
2.1 24 Pin Diagram Top View
CAS_DAT
TEST_EN
GPIO0C/
GPIO08/
GPIO0B
GPIO0A
GPIO09
PWM0
17
16
15
14
13
18
1
6
ESB_DAT
RST#
ESB_CLK
GPIO00
GPIO01
GPIO02

November 7, 2007
2.2 Pin Assignment

Sunny Pin definition Normal RUN mode Hardware Trap Mode IO / Pin Characteristics
24 No. GPIO Pin Name GPWU IE PU Alt. IN Alt. OUT Reset State IO Cell HI(16mA) Power Buffer Tolerance Pull-Up
1 ESB_CLK IE HiZ / HiZ BQC04HU N/A VCC IN4/4 / O4/4 5V
2 GPIO00 GPIO00 HiZ / HiZ BQC04HU N/A VCC IN4/4 / O4/4 5V 33K/VCC
3 RST# IE HiZ / HiZ BQC04HU N/A VCC IN4/4 / O4/4 5V 33K/VCC
4 ESB_DAT IE PU PH / PH BQC04HU N/A VCC IN4/4 / O4/4 5V 33K/VCC
11 GPIO07 CAS_CLK PU CAS_CLK PH / PH BQC16HU 1 VCC IN16/16 / O16/16 5V 33K/VCC
12 GND GND GND
13 TEST_EN# TEST_EN# PU PH / PH BQC04HU N/A VCC IN4/4 / O4/4 5V 33K/VCC
14 GPIO08 CAS_DAT CAS_DAT CAS_DAT HiZ / HiZ BQC04HU N/A VCC IN4/4 / O4/4 5V 33K/VCC
16 GPIO0A GPIO0A HiZ / HiZ BQC16HU 1 VCC IN16/16 / O16/16 5V 33K/VCC
17 GPIO0B GPIO0B HiZ / HiZ BQC16HU 1 VCC IN16/16 / O16/16 5V 33K/VCC
18 GPIO0C GPIO0C PWM0 HiZ / HiZ BQC16HU 1 VCC IN16/16 / O16/16 5V 33K/VCC
19 GPIO0D GPIO0D PWM1 HiZ / HiZ BQC16HU 1 VCC IN16/16 / O16/16 5V 33K/VCC
20 GPIO0E GPIO0E PWM2 HiZ / HiZ BQC16HU 1 VCC IN16/16 / O16/16 5V 33K/VCC
21 GPIO0F GPIO0F PWM3 HiZ / HiZ BQC16HU 1 VCC IN16/16 / O16/16 5V 33K/VCC
22 GPIO10 ESB_RUN# ESB_RUN#ESB_RUN# HiZ / HiZ BQC04HU N/A VCC IN4/4 / O4/4 5V 33K/VCC
23 GPIO11 GPIO11 PU PH / PH BaseAddOpt. BQC04HU N/A VCC IN4/4 / O4/4 5V 33K/VCC
24 VCC VCC PWR

November 7, 2007
2.3 I/O Cell Descriptions

2.3.1 I/O Buffer Table
IO Name Descriptions Pin Name Direction Pin Descriptions
4mA Output Driving, IO InOut tri-state signal

Output Enable, I Input to Ouput buffer
Input Enable, O Output Input buffer to core
BQC04HU
Pull UP 10Kom Enable, OE Input Output Enable
Schimitter Trigger, IE Input Input Enable
5V Input Tolerance PE Input Pull-up Enable
16mA Output Driving, IO Inout tri-state signal
Output Enable, I Input to Ouput buffer
Input Enable, O Output Input buffer to core
BQC16HU
Pull UP 10Kom Enable, OE Input Output Enable
Schimitter Trigger, IE Input Input Enable
5V Input Tolerance PE Input Pull-up Enable

November 7, 2007
3. ESB Protocol Descriptions

3.1 ESB Host (KBx926/KBx925) Packet Format
3.1.1 Write / Read command
The following figure 3.1 shows the format of Host transfer packet. The ESB host will make up the
correct command before doing the packet transfer according to the receiving command from EPB.
All the transfer for the command packet is MSB first, and also does the data packet respond by the
device.
Figure 3.1
There are several fields in the packet. Not every field used in the specified packet. For example,
there is no data field in the Read/Interrupt command packet. The following table 3.1 explains the
meaning of fields.
Field Description
S Start field, always be bit zero, means the starting of the packet
CMD Host command to device. There are three command available, Interrupt mode,
read and write command. The detailed commands will be described at latter
section.
Address The address to access the external address. Only the length of bank(16 bytes)
can be access in one external device. The address is defined in the external
chip, so there is no definition or setting for the host side.
Data The data to write into the external device. Only the write command will use the
field. The data field should be keep as 8 bit zero if read command is sent.
E End bit is always be bit one. The bit means the ending of the packet.
Table 3.1
3.1.2 Interrupt command

The following figure3.2 shows the Packet type of the interrupt is different from the above
read/write packet. Actually it is similar with the processing of SIRQ except the different header.

November 7, 2007
Figure 3.2
Fields for the interrupt command is different from the fields used in the read/write command.
There is no data field for the interrupt command. There are also some special fields dedicated for
the response packet of interrupt from the device. The following table 3.2 describes fields being
used in the packet of the interrupt command.
Field Description
S Start field, always be bit zero, means the starting of the packet
CMD Host command to device. There are three command available, Interrupt mode,
read and write command. Now it's for interrupt command.
ADDR The field put the identical number for the external chip. For example, if there is
one external chip connected, the address should be keeping 8 bit zero.
E End bit is always be bit one. The bit means the ending of the packet.
Table 3.2
Depending on the spec, since the packet format of interrupt from the host changed during the
transmission, the state machine of the device need to take care this and do corresponding state
changes to judge the correctness of the packet length and format.
3.1.3 Software Reset function

There are two kinds of reset for the ESB device (ESD). One is usually called system reset.
Another one is source of the reset which is coming from the ESB Host. ESD will receive the reset
from the firmware of the Host. The firmware would issue the reset protocol; the protocol will keep
on the ESB data line low for at least 512 cycles of the ESB clock, but it will not be more then 1024
cycles of the ESB clock.
The following figure 3.3 shows the timing relation of reset protocol. The device client needs to
judge if the host sends the interrupt or reset command.

November 7, 2007
Figure 3.3
3.1.4 Wake up function

Wake up function is an optional function. When we want to use this function, it needs to be
enabled first. Host turns high the F4.1 bit that is one of the Configuration Register. After that, device
will pull high this ESB_RUN# pin and input enable at the same time.
In Sleep Mode, when wake up event is happened to the device, the Wake Up pending flag (F4.3)
is high. Then, device will pull the ESB_RUN# bit low. It means the ESB_RUN# pin will be output
enable. Then, Host will wake up.
The following figure 3.4 shows the behavior of Wake Up function.
Figure 3.4
3.1.5 ESB command types

There are four possible command types. The following table 3.3 explains each command
respectively.

November 7, 2007
Command Description
00b Interrupt query. The behavior is the same as SIRQ of LPC in normal mode.
Quiet mode is N/A at current.
01b Read from device
10b Write to device
11b Reserved.
Table 3.3
The host also needs to know which device will be connected. The information of locations of
each external device must be set well to make the correct connection between the host and the
device.
3.2 ESB Device Response Packet Format

3.2.1 Device Response Format
The following figure 3.5 shows the response data packet from the device. The device will send
the response packet after the command packet from the host.
Figure 3.5
If there is a read command received from the host, the device will response with normal format
like the above one. If a write command is received, there is needless for the device to response.
Usually, the host will issue read command to verify whether write command success or not. The
following table 3.4 the field description of the response packet from the device.
Field Description
S Start bit. It is 1 bit zero, means the start of the response packet.
Data Data returned by the previous command.
E End bit, the 1 bit one, indicating the end of the packet.
Table 3.4
If there have two devices connect with ESB bus. When host issue read command to the one

November 7, 2007
device. Another one device will waiting for 14 cycles of the ESB clock. The waiting state is the one
device response packet to host.
3.2.2 Device Interrupt Response Format

3.2.2.1 Parallel mode
The following figure 3.6 shows the data packet returned to the host when interrupt command
received.
Figure 3.6
IRQ0~3 are determined by bits F2.2~F2.0 that are Configuration Register
IRQ should be Low if no interrupt happens, otherwise it should be high. ESB data is high if there
is no device existing. There are turn-around (TR) between IRQ0~IRQ3. However, the master or
slave device should not drive ESB data line during the turn-around time.
3.2.2.2 Cascade mode

From the version 1.0 of ESB protocol (The ESB device and Host should support the cascaded
mode since version 1.0) and when the cascaded mode turns on. The following figure 3.7 shows the
packet format of interrupt query packet.
Figure 3.7

November 7, 2007
4. Registers Descriptions
All registers in KC3810 GPIO Expander Controller can be accessed via ESB (ENE Serial Bus)
bus by EC/KBC 925/926. ENE’s EC/KBC 925/926 access the KC3810’s registers like its own
internal registers.
4.1 Register Address Mapping for EC/KBC 925/926

The EC/KBC 925/926 can access the KC3810 via the ESB (ENE serial bus) bus. And 925/926
accesses the KC3810’s registers like the registers were implemented in the 925/926. This means
that the 925/926 read/write the KC3810’s registers via dedicated addresses just as following
Offset Register Register Full Name Def Bank

HW HW Abbreviation Bit Attr Description
=1 =0
C0 C8 INDEX Index Address 00h FC
7~0 R/W Index register to access all KC3810's
internal registers.
C1 C9 DATA Data Port 00h FC
7~0 R/W Data register to access all KC3810's
internal registers.
C2 CA EGPIODO00 EGPIO 00~07 Data Output 00h FC
7~0 R/W GPIODO00 for GPIO00~07
C3 CB EGPIODO08 EGPIO 08~0F Data Output 00h FC
7~0 R/W GPIODO08 for GPIO08~0F
C4 CC EGPIOIN00 EGPIO 00~07 Input Status 00h FC
7~0 RO GPIOIN00 for GPIO00~07
C5 CD EGPIOIN08 EGPIO 08~0F Input Status 00h FC
7~0 RO GPIOIN08 for GPIO08~0F
C6 CE EGPWUPF00 EGPWU 00~07 Event Pending Flag 00h FC
7~0 R/ GPWUPF00 for GPIO00~07
WC1
C7 CF EGPWUPF08 EGPWU 08~0F Event Pending Flag 00h FC
7~0 R/ GPWUPF08 for GPIO08~0F
WC1

November 7, 2007
4.2 Internal Registers

The following table shows the basic register definition for KC3810. The KC3810 has support
cascade mode. Thus the KC3810 needs to provide the following register definition to support
function.
The KC3810 use the index I/O mode to access the register space. The base address of ESB
related registers will be located on the 0XF0h~0XFFh.
4.2.1 Configuration Register Descriptions

Index Register Register Full Name Def
Addr Abbreviation Bit Attr Description
(FCC0) (FCC1)
F0h ESDVER ESB Device Protocol Version
7~0 RO 10h
The version number of ESB protocol for
the device to support.
For example: 0x10h means the device
support ESB version 1.0 protocol.
The ESB protocol 1.0 supports cascaded
mode.
Any device without supporting new ESB
protocol will return 0x0h.
F1h ESDBA ESB Device Base Address
7~4 R/W Ch
The Base Address of KC3810 in index
I/O mode.
For example, there are following definition
and there may be change in the future
version of different ESB device chip.
0xC0h: The default base address of GPIO
Expander Chip.
3~0 Reserved 00h
F2h ESDIRQ ESB Device IRQ Configuration
7~3 Reserved 00h
2~0 R/W
Setting for occupied IRQ by ESB Device.
The Host will query interrupt in the fixed
period of time (1ms). When the device has
interrupt to emit, the setting of the IRQ
number determine the IRQ seen by the
ESB host.
Note: Although the available of IRQ can be
0~7, but only 0~3 is valid for the normal
parallel link mode of ESB Device. Only
during the cascade mode of ESB device
can use setting for 0~7.
F3h ESDCAC ESB Device Cascade mode Configuration
7~2 Reserved 00h
1 R/W
Cascaded mode enable
Please Note that setting the bit will turn on
the cascade mode of the ESB device. The
related register settings for cascade mode
will be valid once the bit sets to one.
0 R/W
Flag of Last cascaded device.

November 7, 2007
Setting the bit will let the device being

responsible for returning the interrupt
packet to the host when the host is emitting
the interrupt query command.
Note that the bit is valid and useful when
the device is in the cascade
mode(ESDCS0.1=0x1h)
F4h ESDCS ESB Device Control and Status
7~4 Reserved 00h
3 R/
Wake Up pending flag
WC1 When the device asserts wake up signal at
wake up line (ESB_RUN#), the pending
flag will be kept and being cleared after
F/W writing one.
2 Reserved
1 R/W
Wake Up enable
Indicates the device whether notice and
output the wakeup line or not.
0: Ignore the activity of the wake up line.
1: Sense and enable the action of the wake
up line.
0
Reserved

November 7, 2007
4.2.2 EGPIO
4.2.2.1 EGPIO Input / Output Control Structure
GPIOFS
Alt. Output Enable
1
GPIOOD
0
GPIOOE 0
GPIOD 0 OE
OUTPUT PIN
Alt. Output 1
Output Buffer
GPIOFS

November 7, 2007
4.2.2.2 EGPIO Register Descriptions

(FCC0) (FCC1)
01 EGPIOFS01 GPIO 0C~0F Function Selection (0: GPIO, 1: PWM 00h
Output)
7~4 R/W GPIOFS01 for GPIO0C~0F
3~0 Reserved
10 EGPIOOE00 GPIO 00~07 Output Enable (0: Output Disable, 1: 00h
Output Enable)
7~0 R/W GPIOOE00 for GPIO00~07
11 EGPIOOE08 GPIO 08~0F Output Enable (0: Output Disable, 1: 00h
Output Enable)
7~0 R/W GPIOOE08 for GPIO08~0F
12 EGPIOOE10 GPIO 10~11 Output Enable (0: Output Disable, 1: 00h
Output Enable)
7~2 Reserved
1~0 R/W GPIOOE10 for GPIO10~11
20 EGPIODO00 GPIO 00~07 Data Output 00h
21 EGPIODO08 GPIO 08~0F Data Output 00h
7~0 R/W GPIODO08 for GPIO08~0F
22 EGPIODO10 GPIO 10~11 Data Output 00h
7~2 Reserved
30 EGPIOIN00 GPIO 00~07 Input Status 00h
31 EGPIOIN08 GPIO 08~0F Input Status 00h
7~0 RO GPIOIN08 for GPIO08~0F
32 EGPIOIN10 GPIO 10~11 Input Status 00h
7~2 Reserved
40 EGPIOPU00 GPIO 00~07 Pull Up Enable 80h
7~0 R/W GPIOPU00 for GPIO00~07
41 EGPIOPU08 GPIO 08~0F Pull Up Enable 00h
7~0 R/W GPIOPU08 for GPIO08~0F
42 EGPIOPU10 GPIO 10~11 Pull Up Enable 00h
7~2 Reserved
1~0 R/W GPIOPU10 for GPIO10~11
50 EGPIOOD00 GPIO 00~07 Open Drain Enable 00h
7~0 R/W GPIOOD00 for GPIO00~07
51 EGPIOOD08 GPIO 08~0F Open Drain Enable 00h
7~0 R/W GPIOOD08 for GPIO08~0F
52 EGPIOOD10 GPIO 10~11 Open Drain Enable 00h
7~2 Reserved
1~0 R/W GPIOOD10 for GPIO10~11
60 EGPIOIE00 GPIO 00~07 Input Enable 00h
7~0 R/W GPIOIE00 for GPIO00~07
61 EGPIOIE08 GPIO 08~0F Input Enable 00h
7~0 R/W GPIOIE08 for GPIO08~0F
62 EGPIOIE10 GPIO 10~11 Input Enable 00h
7~2 Reserved
1~0 R/W GPIOIE10 for GPIO10~11

November 7, 2007
4.2.3 EPWM
4.2.3.1 EPWM Functional Descriptions
There are four PWM channels with 8-bit resolution.
The PWM Cycle Length defines the PWM cycle time in setting clock source. The length of PWM
pulse high period is defined by PWM High Period Length register and it should be less than Cycle
Length.
The following shows formula of the PWM cycle and high period length.
N
Cycle = PWM Clock x 2 x (FF+1)
N
High Period Length = PWM Clock x 2 x (High Period +1)
The N is determined by bits 82.3~82.0 that is EPWMHPC. The High period is determined by
register 84~87 that are EPWMHIGH0~EPWMHIGH3.
4.2.3.2 EPWM Registers Descriptions

(FCC0) (FCC1)
80 EPWMCFG0 PWM Configuration0 00h
7~4 Reserved
3 R/W PWM3 Enable
2 R/W PWM2 Enable
1 R/W PWM1 Enable
0 R/W PWM0 Enable
81 EPWMCFG1 PWM Configuration1 00h
7~4 Reserved
3 R/W Open drain PWM3 Enable
1: The PWM is special case that high level
will be floating. We only drive Low.
0: The PWM is normal mode.
82 EPWMHPC PWM Prescaler Clock 00h
7~4 Reserved
3~0 R/W This is 4 bit prescaler.
The 2^N prescaler for PWM that include
PWM0~PWM3.
83 Reserved 00h
7~0 Reserved
84 EPWMHIGH0 PWM0 High Period Length 00h
7~0 R/W The high period length of PWM0 should be
small than cycle length (FFh).

November 7, 2007


November 7, 2007
4.2.4 EGPWU
4.2.4.1 EGPWU Functional Descriptions
Each GPIO with GPI pin can generate event (interrupt or wakeup). The GPI input can be set as
Level or Edge trigger or Change trigger. Polarity bit setting will affect Level and Edge trigger, but
no meaning to Change trigger.
4.2.4.2 EGPWU Registers Descriptions

(FCC0) (FCC1)
A0 EGPWUEN00 GPIO 00~07 Event Enable and Asynchronous Wake 00h
Up Enable
7~0 R/W Enable bit to generate event (interrupt, and
wakeup) for a active input. Also Enable bit
for waking up from Deep Sleep mode. This
bit is not cared by GPO-only channel.
A1 EGPWUEN08 GPIO 08~0F Event Enable and Asynchronous Wake 00h
Up Enable
A2 EGPWUEN10 GPIO 10~11 Event Enable and Asynchronous Wake 00h
Up Enable
7~2 Reserved
B0 EGPWUPF00 GPIO 00~07 Event Pending Flag 00h
7~0 R/ GPIO 00~07 Event Pending Flag
WC1
B1 EGPWUPF08 GPIO 08~0F Event Pending Flag 00h
7~0 R/ GPIO 08~0F Event Pending Flag
WC1
B2 EGPWUPF10 GPIO 10~11 Event Pending Flag 00h
7~2 Reserved
1~0 R/ GPIO 10~11 Event Pending Flag
WC1
C0 EGPWUPS00 GPIO 00~07 Polarity Selection 00h
7~0 R/W GPIO 00~07 input active polarity selection.
0: Falling trigger
1: Rising trigger
C1 EGPWUPS08 GPIO 08~0F Polarity Selection 00h
7~0 R/W GPIO 08~0F input active polarity selection.
0: Falling trigger
1: Rising trigger
C2 EGPWUPS10 GPIO 10~11 Polarity Selection 00h
7~2 Reserved
1~0 R/W GPIO 10~11 input active polarity selection.
0: Falling trigger
1: Rising trigger
D0 EGPWUEL00 GPIO 00~07 Edge/Level Trigger Selection 00h

November 7, 2007
7~0 R/W GPIO 00~07 inputs is edge or level trigger

0: Edge trigger
1: Level trigger
D1 EGPWUEL08 GPIO 08~0F Edge/Level Trigger Selection 00h
7~0 R/W GPIO 08~0F inputs is edge or level trigger
0: Edge trigger
1: Level trigger
D2 EGPWUEL10 GPIO 10~11 Edge/Level Trigger Selection 00h
7~2 Reserved
1~0 R/W GPIO 10~11 inputs is edge or level trigger
0: Edge trigger
1: Level trigger
E0 EGPWUCH00 GPIO 00~07 Enable Input Changing Trigger 00h
7~0 R/W GPIO 00~07 inputs will trigger as edge
changing (GPWUEL setting is not cared)
E1 EGPWUCH08 GPIO 08~0F Enable Input Changing Trigger 00h
7~0 R/W GPIO 08~0F inputs will trigger as edge
E2 EGPWUCH10 GPIO 10~11 Enable Input Changing Trigger 00h
7~2 Reserved
1~0 R/W GPIO 10~11 inputs will trigger as edge

November 7, 2007
5. Electronic Characteristics
5.1 la
5.1.1 lb
5.2 lx
5.2.1 ly

November 7, 2007
6. Packaging Information

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Copyright©2007, ENE Technology Inc. All rights reserved.

Product Serial Number ii All rights reserved.

1.1 FEATURE SUMMARY ..........................................................................................2

1.2 BLOCK DIAGRAM ..............................................................................................3

2.1 24 PIN DIAGRAM TOP VIEW ...............................................................................5

2.2 PIN ASSIGNMENT ..............................................................................................6

2.3 I/O CELL DESCRIPTIONS ....................................................................................7

3.1 ESB HOST (KBX926/KBX925) PACKET FORMAT ...............................................8

4. REGISTERS DESCRIPTIONS ..........................................................................13

4.1 REGISTER ADDRESS MAPPING FOR EC/KBC 925/926 ......................................13

4.2 INTERNAL REGISTERS .....................................................................................13

Product Serial Number 1 All rights reserved.

• An ENE serial bus device for KBx925/26 application

• EnE Extension GPIO controller uses this scheme

ENE Peripheral Bus Master (EPBM)

General Purpose Input/Output (GPIO)

• All outputs can be optionally tri-stated

General Purpose Wake-Up (GPWU)

Pulse Width Modulator (PWM)

• Four built-in PWMs

• Configurable Pre-scale Clock and high period length

Product Serial Number 2 All rights reserved.

1.2 Block Diagram

1.2.1 System Block Diagram

Product Serial Number 3 All rights reserved.

1.2.2 Block Diagram

Product Serial Number 4 All rights reserved.

2. Pin Assignment and Description

2.1 24 Pin Diagram Top View

Product Serial Number 5 All rights reserved.

2.2 Pin Assignment

Product Serial Number 6 All rights reserved.

2.3 I/O Cell Descriptions

IO Name Descriptions Pin Name Direction Pin Descriptions

4mA Output Driving, IO InOut tri-state signal

Product Serial Number 7 All rights reserved.

3. ESB Protocol Descriptions

3.1.2 Interrupt command

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3.1.3 Software Reset function

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3.1.4 Wake up function

3.1.5 ESB command types

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01b Read from device

10b Write to device

3.2 ESB Device Response Packet Format

Data Data returned by the previous command.

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3.2.2 Device Interrupt Response Format

3.2.2.2 Cascade mode

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4.1 Register Address Mapping for EC/KBC 925/926

Offset Register Register Full Name Def Bank

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4.2 Internal Registers

4.2.1 Configuration Register Descriptions

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Setting the bit will let the device being

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