Network On-Chip Router Prevention of Fault Tolerant in Fifo Buffers

NETWORK ON-CHIP ROUTER PREVENTION OF FAULT TOLERANT IN FIFO BUFFERS
Abbreviations
VLSI Very Large Scale Integrated Circuits
HDL Hardware Description Language
VHDL VHSIC Hardware Description Language
VHSIC Very High Speed Integrated Circuits
IEEE Institute Of Electrical And Electronic Engineers
VITAL VHDL Initiative Towards Ask Libraries
RTL Register Transfer Level
WAVES Waveform And Vector Exchange to Support Design and Test Verification
PLA Programmable Logic Array
PAL Programmable Array Logic
CPLD Complex Programmable Logic Devices
CLB Configurable Logic Blocks
ISE Integrated Software Environment
EDA Electronic Design Automation
FPGA Field-Programmable Gate Array

INTRODUCTION TO VLSI DESIGN:
VLSI
VLSI stands for "Very Large Scale Integration". this can be the sphere that involves
packing additional and additional logic devices into smaller and smaller areas. VLSI, circuits that
will have taken board furls of house will currently be place into a tiny low house few millimeters
across! VLSI circuits are all over ... your laptop, your car, your current progressive camera, the
cell-phones, and what have you ever. All this involves lots of experience on several fronts among
an equivalent field,that we are going to explore in later sections.
2.1.1 Dealing with VLSI Circuits
The method traditional blocks like latches and gates ar enforced is completely different from what
students have seen to date, however the behavior remains an equivalent. All the mini atomization involves
new things to contemplate. Lots of thought has got to go in actual implementations also as style.
Circuit Delays: giant sophisticated circuits running at terribly high frequencies have one massive
downside to tackle - the matter of delays in propagation of signals through gates and wire even for areas a
couple of micrometers across! The operation speed is therefore giant that because the delays add up, they
will really become equivalent to the clock speeds.
Power: Another impact of high operation frequencies is multiplied consumption of power. This has two-
fold impact - devices consume batteries quicker, and warmth dissipation will increase. as well as the very
fact that surface areas have decreased , heat poses a serious threat to the steadiness of the circuit itself.
Layout: egg laying out the circuit parts is task common to any or all branches of physical science. What’s
therefore special in our case is that there ar several potential ways in which to try and do this; there is
multiple layers of various materials on an equivalent chemical element, there is completely different
arrangements of the smaller components for an equivalent element and shortly. the selection between the
2 is set by the method we tend to selected the layout the circuit parts. Layout can even have an effect on
the fabrication of VLSI chips,creating it either simple or tough to implement the parts on the chemical
element.
The industry has achieved an outstanding growth over the last twenty years, chiefly because of the fast
advances in integration technologies, large-scale systems style - briefly, because of the appearance of
VLSI. the amount of applications of integrated circuits in superior computing, telecommunications, and
client physical science has been rising steady, and at a awfully quick pace. Typically, the specified
procedure power (or, inalternative words, the intelligence) of those applications is that the thrust for the
quick development of this field.offers associate degree over read of the distinguished trends in info
technologies over ensuing few decades. the present leading-edge technologies (such as low bit-rate video
and cellular communications) already offer the end-users a definite quantity of process power and
movability. This trend is predicted to continue, with importantimplications on VLSI and systems style.
one in every of the foremost necessary characteristics of data services is their increasing want for terribly
high process power and information measure (in order to handle period of timevideo, as an example). the
opposite necessary characteristic is that the knowledge services tend to becomeadditional and additional
personalised (as opposition collective services like broadcasting), which suggests that the devices should
be additional intelligent to answer individual demands, and at an equivalent time they have tobe moveable
to permit additional flexibility/mobility.
Very-large-scale integration (VLSI) is that the method of making integrated circuits by combining
thousands of transistor-based circuits into one chip. VLSI began within the Seventies once advanced
semiconductor and communication technologies were being developed. The silicon chip may be a VLSI
device. The term isn't anylonger as common because it once was, as chips have multiplied in complexness
into the many ample transistors. VLSI stands for "Very giant Scale Integration". this can be the sphere
that involves packing additional andadditional logic devices into smaller and smaller areas. due to VLSI,
circuits that will have taken board packed withhouse will currently be place into atiny low house few
millimeters across! This has detached an enormouschance to try and do things that weren't potential
before.
VLSI has been around for a protracted time, there's nothing new concerning it, however as a facet impact
of advances within the world of computers, there has been a dramatic proliferation of tools which will be
accustomed style VLSI circuits. Alongside, obeying Moore's law, the aptitude of associate degree IC has
multiplied exponentially over the years, in terms of computation power, utilization of obtainable space,
yield. The combined impact of those 2 advances is that folks will currently place various practicality into
the IC's, gap up new frontiers. Examples are embedded systems, wherever intelligent devices ar place
within everyday objects, associate degreed present computing wherever tiny computing devices
proliferate to such an extent that even the shoes you wear may very well do one thing helpful like
observance your heartbeats.
Verilog was developed at a time once designers were yearning for tools to mix completely different levels
of simulation. within the early Nineteen Eighties, there have been switch-level simulators, gate-level
simulators,useful simulators (often written ad-hoc in software) and no easy means that to mix them.
Further, the more-widespread, ancient programming languages themselves were/are basically ordered and
therefore "semantically challenged" once modeling the concurrency of digital electronic
equipment.Verilog was created by Phil Moore in 1983-4 at entree style Automation and also the initial
machine was written a year later. It borrowed abundant from the present languages of the time: the
concurrency aspects is also seen in each Modula and (earlier) Simulate; the syntax is deliberately near
that of C; and also the ways for combining completely different levels of abstraction oweabundant to
Hilo.
In 1989, entree style Automation (and rights to Verilog) was purchased by Cadence WHO place Verilog
within theproperty right within the following year. This move did abundant to push the utilization of
Verilog since alternative firms were ready to develop alternatives tools to those of Cadence that, in turn,
allowed users to adopt Verilog while not dependency on one (primarily workstation-tool) provider. In
1992, work began to make associate degree IEEE normal (IEEE-1364) and in December 1995 the
ultimate draft was approved. therefore Verilog has become associate degree n international normal -
which can more increase its business development and use. At present, there's standards activity to
increase Verilog on the far side strictly digital circuits. This includes Verilog-MS for "mixed signal
specification" and Verilog- A for "analog" design; the latter was recently approved (June 1996) by the
board of Open Verilog International and is currently into account by the IEEE. additionally, work is afoot
to change the proof of "equivalence [between] activity and synthesizable specifications" (see the
Cambridge internet site below) to that Verilog without delay lends itself.
While Verilog emerged from developments among personal firms, its main rival came from the Yankee
Department of Defense (DOD). In 1981, a workshop on hardware description languages as a part of its
terribly High Speed Integrated Circuits (VHSIC) program, and also the outcome fashioned a specification
for the VHSIC hardware description language (VHDL) in 1983. There is, of course, the question on that
language is healthier. And this, of course, may be a arduous question to answer while not inflicting
excitement and rebuttals from the selling departments of the less most popular language. However, the
subsequent points featured in a very recent dialogue within the VHDL and Verilog news teams.
The main issue is that the language syntax - since Verilog relies on C and VHDL relies on enzyme.
Verilog less complicated is less complicated} to find out since C may be a way simpler language. It
additionally produces additional compact code: easier each to put in writing and to browse. what is more,
the big variety of engineersWHO already understand C (compared to those that understand ADA) makes
learning and coaching easier. VHDL is incredibly powerfully written, and permits software engineer to
outline their own sorts though, in apply, the most sorts used ar either the fundamental forms of the
language itself, or those outlined by the IEEE. The profit is that sort checking is performed by the
compiler which might cut back errors; the disadvantage is that dynamic sorts should be done expressly.
Verilog has 2 clear blessings over VHDL It permits switch-level modeling that some designers realize
helpful for exploring new circuits. It guarantees that each one signals are initialized to "unknown" that
ensure s that each one American state signers can manufacture the required logic to initialize their de sign
- the bottom sorts in VHDL initialize to zero and also the "hasty" designer might omit a world reset.
2.2 VLSI DESIGNS CLASSIFICATION
There are Three Categories in today`s VLSI domain they are
2.2.1 Analog
Small transistor count precision circuits such as Amplifiers, Data converters, filters,
Phase locked loops, Sensors etc.
2.2.2 ASIC
Progress in the fabrication of IC's has enabled us to create fast and powerful circuits in
smaller and smaller devices. This also means that we can pack a lot more of functionality into the
same area. The biggest application of this ability is found in the design of ASIC's. These are IC's
that are created for specific purposes - each device is created to do a particular job, and do it
well. The most common application area for this is DSP - signal filters, image compression, etc.
To go to extremes, consider the fact that the digital wristwatch normally consists of a single IC
doing all the time-keeping jobs as well as extra features like games, calendar, etc.
2.2.3 SOC
These are highly complex mixed signal circuits (digital and analog all on the same chip).
A network processor chip or a wireless radio chip is an example of a SoC.
2.3 VLSI DESIGN STYLES

Several style designs is thought of for chip implementation of specified algorithms or
logic functions. every stylevogue has its own deserves and shortcomings, and therefore a correct
selection has got to be created by designers so as to supply the practicality at low value.
2.3.1 FPGA
Fully fabricated FPGA chips containing thousands of logic gates or maybe additional,
with programmable interconnects, are offered to users for his or her custom hardware
programming to appreciate desired practicality. This style vogue provides a way for quick
prototyping and additionally for cost-efficient chip style, particularly for low-volume
applications. A typical field programmable gate array (FPGA) chip consists of I/O buffers,
associate degree array of configurable logic blocks (CLBs), and programmable interconnect
structures. The programming of the lay connects is enforced by programming of RAM cells
whose output terminals ar connected to the gates of MOS pass transistors. A general design of
FPGA.A additional careful read showing the locations of switch matrices used for interconnect
routing. an easy CLB (model XC2000 from XILINX) It consists of 4 signal input terminals (A,
B, C, D), a clock signal terminal, user-programmable multiplexers, associate degree SR-latch,
and a look-up table (LUT). The LUT may be a digital memory that stores the reality table of the
Boolean perform. Thus, it will generate any perform of up to four variables or any 2 functions of
3 variables.
CLB is organized specified many various logic functions is completed by programming
its array. Additional refined CLBs have additionally been introduced to map advanced functions.
the everyday style flow of associate degree FPGA chip starts with the activity description of its
practicality, employing a hardware description language like VHDL. The synthesized design is
then technology-mapped (or partitioned) into circuits or logic cells. At this stage, the chip style is
totally delineated in terms of obtainable logic cells. Next, the position and routing step assigns
individual logic cells to FPGA sites (CLBs) and determines the routing patterns among the cells
in accordance with world wide web list. when routing is completed, the on-chip Performance of
the planning is simulated and verified before downloading the planning for programming of the
FPGA chip. The programming of the chip remains valid as long because the chip is powered-on
or till new programming is completed. In most cases, full utilization of the FPGA chip space isn't
potential - several cell sites might stay unused.
The largest advantage of FPGA-based style is that the terribly short turn-around time, i.e.,
the time needed from the beginning of the planning method till a useful chip is obtainable. Since
no physical producing step is important for customizing the FPGA chip, a useful sample is
obtained nearly as before long because the style is mapped into a selected technology. {the
typical|the normal| the everyday} value of FPGA chips ar typically above alternative realization
alternatives (such as gate array or standard cells) of an equivalent style, except for small-volume
production of ASIC chips and for quick prototyping, FPGA offers a awfully valuable choice.
2.3.2 Gate array design
In view of the quick prototyping capability, the gate array (GA) comes when the FPGA. whereas
the planningimplementation of the FPGA chip is completed with user programming, that of the
gate array is completed with metal mask style and process. Gate array implementation needs a
ballroom dance producing process: the primary part, that relies on generic (standard) masks, ends
up in associate degree array of uncommitted transistors on every GA chip. These uncommitted
chips is hold on for later customization, that is completed byprocess the metal interconnects
between the transistors of the array Since the patterning of auriferous interconnectsis completed
at the tip of the chip fabrication, the turn-around time is still short, a couple of days to a couple
ofweeks. a corner of a gate array chip that contains bonding pads on its left and bottom edges,
diodes for I/O protection, nMOS transistors and pMOS transistors for chip output driver circuits
within the neighboring areas of bonding pads, arrays of nMOS transistors and pMOS transistors,
tunnel wire segments, and power and ground busesbeside contact windows.
Magnified portion of the interior array with metal mask style (metal lines highlighted in dark) to
appreciate a poshlogic perform. Typical gate array platforms enable dedicated areas, known as
channels, for intercell routing. the provision of those routing channels simplifies the
interconnections, even victimization one metal layer solely. The interconnection patterns to
appreciate basic logic gates is hold on in a very library, which might then beaccustomed
customise rows of uncommitted transistors in step with world wide web list. whereas most gate
array platforms solely contain rows of uncommitted transistors separated by routing channels,
another platformsadditionally provide dedicated memory (RAM) arrays to permit a better density
wherever memory functions arneeded. The layout views of a traditional gate array and a gate
array platform with 2 dedicated memory banks.
With the utilization of multiple interconnect layers, the routing is achieved over the active cell
areas; therefore, the routing channels is removed as in Sea-of-Gates (SOG) chips. Here, the
complete chip surface is roofed with uncommitted nMOS and pMOS transistors. As within the
gate array case, neighboring transistors is tailor-madeemploying a metal mask to create basic
logic gates. For intercell routing, however, a number of the uncommitted transistors should be
sacrificed. This approach ends up in additional flexibility for interconnections, and frequentlyin a
very higher density. the fundamental platform of a SOG chip is shown in offers a short
comparison between the channeled (GA) vs. the channel less (SOG) approaches.
2.3.3 Standard-cells based design
The standard-cells based mostly style is one in every of the foremost current full custom style
designs that need development of a full custom mask set. the quality cell is additionally known
as the police. during this style vogue, all of the usually used logic cells ar developed,
characterised, and hold on in a very galvanic cell library. A typical library might contain a couple
of hundred cells together with inverters, NAND gates, NOR gates, advanced AOI, OAI gates, D-
latches, and flip-flops. every gate sort will have multiple implementations to supply adequate
driving capability for various fan outs. as an example, the electrical converter gate will have
normal size transistors, double size transistors, and quadruple size transistors in order that the
chip designer will opt for the correct size to attain high circuit speed and layout density. The
characterization of every cell is completed for many completely different classes. It consists of
• delay time vs. load capacitance
• circuit simulation model
• timing simulation model
• fault simulation model
• cell knowledge for place-and-route
• mask knowledge
To change machine-controlled placement of the cells and routing of inter-cell connections,
every cell layout is intended with a set height, in order that variety of cells is abutted side-by-side
to create rows. the ability and ground rails usually run parallel to the higher and lower
boundaries of the cell, thus, neighboring cells share a typical power and ground bus. The input
and output pins ar settled on the higher and lower boundaries of the cell. The layout of a typical
galvanic cell. Notice that the nMOS transistors are settled nearer to the bottom rail where as the
pMOS transistors ar placed nearer to the ability rail.
2.3.4 Full custom design

Although the standard-cells based mostly style is commonly known as full custom style, in a
very strict sense, it's some what but absolutely custom since the cells ar pre-designed for general
use and also the same cells ar utilized in many various chip styles. in a very fuller custom style,
the complete mask style is completed afresh while not use of any library. However, the event
value of such a style vogue is changing into prohibitively high. Thus, the construct of style
utilize is changing into in style so as to scale back style cycle time and development value.the
foremost rigorous full custom style is the planning of a memory cell, be it static or dynamic.
Since an equivalent layout style is replicated, there wouldn't be any different to high density
micro chip style. For logic chipstyle, a decent compromise is achieved by employing a
combination of various style designs on an equivalent chip, like normal cells, data-path cells and
PLAs. In real full-custom layout during which the pure mathematics, orientation and placement
of each junction transistor is completed singly by the designer, style productivity {is usually|is
usually|is sometimes} terribly low - typically ten to twenty transistors per day, per designer.
In digital CMOS VLSI, full-custom style is never used because of the high labor value.
Exceptions to the present embody the planning of high-volume merchandise like memory chips,
high- performance microprocessors and FPGA masters. the total layout of the Intel 486 silicon
chip chip, that may be a exemplar for a hybrid full-custom style.
2.4 Introduction to VHDL

A digital system is delineated at completely different levels of abstraction and from different points of
read. associate degree HDL ought to dependably and accurately model and describe a circuit, whether or
not already engineered or beneath development, from either the structural or activity views, at the
specified level of abstraction. as a result of HDLs ar sculptural when hardware, their linguistics and use
are terribly completely different from those of ancient programming languages.
2.4.1 Limitations of traditional programming languages

There are wide styles of computer programing languages, from Frontend to C to Java. sadly, they're not
equal to model digital hardware. to know their limitations, it's useful to look at the event of a language. A
artificial language is characterised by its syntax and linguistics. The syntax contains the grammatical rules
accustomed write a program, and also the linguistics is that the “meaning” related to language constructs.
once a brand new machine language is developed, the designers initial study the characteristics of the
underlying processes so develop grammar constructs and their associated linguistics to model and
categorical these characteristics.
Most ancient general programming languages, such as C, ar sculptural when a ordered method. during
this method, operations ar performed in ordered order, one operation at a time. Since associate degree
operationof ten times depends on the results of associate degree earlier operation, the order of execution
can't be altered atcan. The ordered method model has 2 major edges. At the abstract level, it helps the
human thinking method to develop associate degree formula step by step. At the implementation level, the
ordered method resembles the operation of a basic laptop model associate degreed therefore permits
economical translation from an formula to machine directions.
The characteristics of digital hardware, on the opposite hand, ar terribly completely different from those
of the ordered model. A typical digital system is generally engineered by smaller components, with tailor-
made wiring that connects the input and output ports of those components. once signal changes, the
components connected to the signal are activated and a collection of latest operations is initiated
consequently. These operations are performed at the same time, and every operation can take a selected
quantity of your time, that represents the propagation delay part, to complete. when completion, every
half updates the worth of the corresponding output port. If the worth is modified, the signaling can
successively activate all the connected components and initiate another spherical of operations. This
description shows many distinctive characteristics of digital systems, together with the connections of
components, coincident operations, and also the construct of propagation delay and temporal order. The
ordered model utilized in ancient programming languages cannot capture the characteristics of digital
hardware, and there's a desire for special languages (i.e., HDLs) that are designed to model digital
hardware.
VHDL includes facilities for describing logical structure and performance of digital systems at variety of
levels of abstraction, from system level right down to the gate level. it's meant, among alternative things,
as a modeling language for specification and simulation. we will additionally use it for hardware
synthesis if we tend to prohibit ourselves to a set which will be mechanically translated into hardware.
VHDL arose out of the u. s. government’s terribly High Speed Integrated Circuits (VHSIC) program.
within the course of this program, it became clear that there was a desire for a customary language for
describing the structure and performance of integrated circuits (ICs). therefore the VHSIC Hardware
Description Language (VHDL) was developed. it had been later developed more beneath the auspices of
the Institute of Electrical and Electronic Engineers (IEEE) and adopted within the kind of the IEEE
normal 1076, normal VHDL Language manual, in 1987. This initial normal version of the language is
commonly mentioned as VHDL-87.
After the initial unharness, varied extensions were developed to facilitate varied style and modeling
necessities. These extensions are documented in many IEEE standards:
i. IEEE normal 1076.1-1999, VHDL Analog and Mixed Signal Extensions (VHDL-AMS): defines the
extension for analog and mixed-signal modeling.
ii. IEEE normal 1076.2-1996, VHDL Mathematical Packages: defines additional mathematical functions
for real and complicated numbers.
iii. IEEE normal 1076.3- 1997, Synthesis Packages: defines arithmetic operations over a set of bits.
iv. IEEE normal 1076.4-1995, VHDL Initiative towards raise Libraries (VITAL): defines a mechanism to
featurecareful temporal order info to ASIC cells.
v. IEEE normal 1076.6-1999, VHDL Register Transfer Level (RTL) Synthesis: defines a set that's
appropriate for synthesis.
vi. IEEE normal one 164- 1993 Multivalve Logic System for VHDL Model ability (std-logicJl64): defines
new knowledge sorts to model multivalve logic.
vii. IEEE normal 1029.1-1998, VHDL wave form and Vector Exchange to Support style and take a look at
Verification (WAVES): defines the way to use VHDL to exchange info in a very simulation setting.
Figure one : outline of VHDL style flow
VHDL is associate degree word form for terribly High Speed Integrated Circuits Hardware description
Language. The language is accustomed model a digital system at several levels of abstraction starting
from the algorithmic level to the gate level. The complexness of the digital system being sculptural may
vary from that of an easy gate to a whole digital electronic system. The VHDL language is thought to be
associate degree integrated uniting of ordered, concurrent, internet list and wave form generation
languages and temporal order specifications.
2.4.2 HISTORY OF VHDL
VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. it had
been developed within the 1980’s as byproduct of a high-speed computer circuit scientific research
funded by the United States department of defense. Through out the VHSIC program, researchers were
confronted with the discouraging task of describing circuits of huge scale (for their time) and of managing
terribly giant circuit style issues that concerned multiple groups of engineers. With solely gate-level tools
offered, it before long became clear that additional structured style ways and tools would be required.
To meet this challenge, groups of engineers from 3 firms - IBM, Lone-Star State Instruments and lay
metrics we are narrowed by the department of defense to complete the specification and implementation
of a brand new language based mostly style description methodology. the primary in public offered
version of VHDL, version 7.2 was discharged in 1985. In 1986, the IEEE was bestowed with a proposal
to standardize the language, that it did in 1987 and educational representatives. The ensuing normal, IEEE
1076—1987 is that the basis for nearly each simulation and synthesis product sold-out these days.
associate degree increased and updated version of the language, IEEE 1076-1993, was discharged in
1994, and VHDL tool vendors are responding by adding these new language options to their merchandise.
Although IEEE normal 1076 defines the whole VHDL language, there ar aspects of the language that
create it tough to put in writing fully moveable style descriptions (description which will be simulated
identically victimization completely different vendor’s tools). the matter stems from the very fact that
VHDL supports several abstract knowledge sorts, however it doesn't address the straightforward
downside of characterizing completely different signal strengths or usually used simulation conditions
like unknowns and high impedances. before long when IEEE 1076-1987 was adopted, machine firms
began enhancing VHDL with new non-standard sorts to permit their customers to accurately simulate
advanced electronic circuits. This caused issues as a result of style descriptions entered into one machine
were typically incompatible with another with alternative environments. VHDL was quickly changing
into a non-standard.
To get round the downside of non-standard knowledge sorts, associate degree IEEE committee adopted
another normal. This normal numbered 1164, defines a customary package (a VHDL feature that permits
usually used declaration to be collected into associate degree external library) containing definition for a
customary nine-value knowledge sort. This normal knowledge sort is named normal logic, and also the
IELL 1164 package is commonly mentioned because the normal logic package. The IEEN 1076-1987 and
IEEE 1164 normals along type the whole VHDL standard in widest use these days (IEEE 1076-1993 is
slowly operating its method into the VHDL thought, however it doesn't add vital variety of options for
synthesis users).
In the rummage around for a customary style and documentation tool for the terribly High Speed
Integrated Circuits (VHSIC) program the u. s. Department of Defense (DOD) within the summer of 1981
sponsored a workshop on HDLs at Woods Hole, Massachusetts. The conclusion of the workshop was the
requirement for a customary language, and also the options which may be needed by such a customary in
1983.DoD established necessities for a customary VHSIC hardware description language(VHDL),
supported the advice of the “Woods Hole” workshop. A contract for the event of the VHDL language, its
setting, and its software package was awarded to IBM, Lone-Star State instruments and Intermetrics.
VHDL 2.0 was discharged solely six months when the project began. The language was considerably
improved hereafter and alternative shortcomings were corrected resulting in the discharge of VHDL half-
dozen.0. In 1985 this vital developments light-emitting diode to the discharge of VHDL half-dozen.0. In
1985 these vital development light-emitting diode to the discharge of VHDL seven.2 language manual.
This was shortly developed as IEEE 1076/A VHDL language manual. Efforts for outlining the restructure
of VHDL explicit in 1990 by a dream of volunteers operating beneath the IEEE DASC (Design
Automation Standards committee). In Oct of 1992, a brand new VHDL’93 was completed and was
discharged for review. when minor modifications, this restructure was approved by the VHDL selection
cluster members and have become the new VHDL language normal. this VHDL normal is formally
referred as VHDL 1076-1993.
2.4.3 LEVELS OF ABSTRACTION (STYLES)
VHDL supports several potential kinds of style description. These designs dissent primarily in however
closely they relate to the underlying hardware. once we speak of the various kinds of VHDL, then, we
tend to are very talking concerning the differing levels of abstraction potential victimization the language.
to present associate degree example, it's potential to explain a counter circuit in a very variety of how. At
rock bottom level of abstraction, you'll use VHDL's hierarchy options to attach a sequence of predefined
logic gates and flip-flips to create a counter circuit.
Fig. Levels of abstraction
In a activity description, the construct of your time is also expressed exactly, with actual delays
betweenconnected events, or might merely be associate degree ordering of operations that ar
expressed consecutive.after you ar writing VHDL for input to synthesis tools, you'll use activity
statements in VHDL to imply that there arregisters in your circuit. it's unlikely, however, that
your synthesis tool are going to be capable of making exactly an equivalent behavior in actual
electronic equipment as you have got outlined within the language.
The highest level of abstraction supported in VHDL is named the activity level of abstraction.
once making a activity description of a circuit, you'll describe your circuit in terms of its
operation over time. The construct of your time is that the vital distinction between activity
descriptions of circuits and lower-level descriptions. If you're acquainted with event-driven
software package programming languages then writing behavior level VHDL won't seem to be
something new. a bit like a artificial language, you'll be writing one or additional tiny programs
that operate consecutive and communicate with each other through their interfaces. the sole
distinction between behavior-level VHDL and a software package artificial language like Visual
Basic is that the underlying execution platform: within the case of Visual Basic, it's the Windows
software system within the case of VHDL, it's a machine. associate degree alternate style
methodology, during which a circuit style downside is divided into registers and combinatory
input logic, is what's typically known as the dataflow level of abstraction. Dataflow is associate
degree intermediate level of abstraction that permits the labor of combinatory logic to be hidden
whereas the additional necessary components of the circuit, the registers, are additional fully
specified . There are some drawbacks to employing a strictly dataflow methodology of style in
VHDL. First, there are not any inherent registers in VHDL the language was designed to be
general, and VHDL’s designers on its activity aspects placed the stress. If you're about to write
VHDL at the dataflow level of abstraction, then you want to initial produce activity descriptions
of the register components that you simply are going to be victimization in your style. These
components should be provided within the kind of parts or within the kind of subprograms.
except for hardware designers, for whom it is tough to relate the ordered descriptions and
operation of activity VHDL with the hardware that's being delineated , victimization the dataflow
level of abstraction will create quite heap of sense.victimization dataflow, it is easier to relate a
style description to actual hardware devices. The dataflow and behavior levels of abstraction ar
accustomed describe circuits in terms of their logical perform. there's a 3rd variety of
VHDLthat's accustomed mix such descriptions along into a bigger, hierarchical circuit
description. Structural VHDLpermits you to encapsulate one a part of a style description as a re-
usable element. Structural VHDL is thought of as being analogous to a matter schematic, or as a
matter diagram for higher-level style.
2.4.4 NEED FOR VHDL
The advanced and backbreaking manual procedures for the planning of the hardware have sealed
the method for the event of languages for prime level description of the digital system. This high-
level description will function documentation for the half also as associate degree entry purpose
into the planning method. The high level description is processed through varied boards, gate
array victimization the synthesis tools of Hardware Description language United States such a
language. VHDL was styled as to supply an integrated style and documentation to speak design
knowledge between varied levels of abstractions.
2.4.5 ADVANTAGES OF VHDL

VHDL permits fast description and synthesis of circuits of five, twenty thousand gates. It
additionally provides the subsequent capabilities. the subsequent are the main blessings of
VHDL over alternative hardware description languages:
• Power and adaptability VHDL has powerful language constructs that permits code description
of advanced management logic.
• Device freelance style VHDL creates style that matches into several device design and it
additionally permits multiple kinds of style description.
• movability VHDL’s movability permits the planning description to be used on completely

different simulators and synthesis tools. therefore VHDL style descriptions is utilized in multiple
comes.
• ASIC migration The potency of VHDL permits style to be synthesized on a CPLD or associate
degree FPGA.typically the code is used with the ASIC.
• pace to promote and low value VHDL and programmable logic try along facilitate speedy style
method. VHDL permits styles to be delineated quickly.
Programmable logic eliminates expenses and facilitates fast style iterations
• The language is used as a communication medium between completely different laptop power-
assisted style(CAD) and laptop power-assisted Engineering (CAE) tools.
• The language supports hierarchy, i.e., a digital system is sculptural as a collection of

interconnected elements; every component, in turn, is sculptural as a collection of interconnected
subcomponents.
•The language supports versatile style methodologies: top-down, Bottom- Up, or Mixed.
• The language is technology freelance and therefore an equivalent behavior model is

synthesized into completely different merchant libraries.
• varied digital modeling techniques like finite-state machine descriptions, algorithmic

descriptions and Boolean equations is sculptural victimization the language.
• It supports each synchronous and asynchronous temporal order models.
• it's associate degree IEEE and ANSI normal, and thus, models delineated victimization these
languages are moveable.
• There are not any limitations that ar obligatory by the language on the dimensions of the
planning.
• The language has components that create large-scale style modeling easier, for e.g.
Components, functions, procedures and packages.
• Take a look at benches is written victimization an equivalent language to check alternative

VHDL models.
• Nominal propagation delays, min-max delays, setup and holding temporal order, temporal order
constraints, and spike detection will all be delineated terribly naturally during this language.
• Activity models that adjust to a definite synthesis description vogue ar capable of being
synthesized to gate-level description.
• The aptitude of process new knowledge sorts provides the ability to explain and simulate a
brand new style technique at a awfully high level of abstraction with none concern concerning
implementation details.
2.4.6 DESIGN METHODOLOGY USING VHDL
There are 3 style methodologies namely: bottom-up, top-down and flat
• The bottom-up approach involves the process and planning the individual parts, then
conveyance the individual parts along to create the general style.
• in a very flat style the useful parts are outlined at an equivalent level because the
interconnection of these useful parts.
• A top-down style method involves a divide-and-conquer approach to implement the planning an

outsized system. Top-down style is mentioned as algorithmic partitioning of a system into its
sub-components till all sub-components become manageable style components. style of a
element is manageable if the element is obtainable as a part of a library, it is enforced by
modifying associate degree already offered half, or it is delineated for a synthesis program or
associate degree automatic hardware generator.
2.4.7 Components OF VHDL
Constructs of the VHDL language ar designed for describing hardware parts, packaging
components and utilities use of libraries and for specifying style libraries and parameters. In its
simplest type, the outline of a element in VHDL consists of associate degree interface
specification associate degreed an subject area specification. The interface description begins
with Entity keyword and contains the input-output ports of the element. associate degree subject
area specification begins with the subject area keyword, that describes the practicality of a
element.
This practicality depends on input-output signals and alternative parameters that ar laid out in the
interface description. many subject area specifications with completely different identifiers will
exist for one element with a given interface description. VHDL permits design to be organized
for a selected technology setting.
in a very hardware style setting it becomes necessary to cluster parts or utilities used for
description of parts.parts and such utilities is classified by use of packages. A package
declaration contains parts and utilities to come into sight by Entities and Architectures. VHDL
permits the utilization of Libraries and binding of sub-components of a style to components of
assorted libraries. Constructs for such applications embody a library statement and
configurations.
2.4.8 VHDL LANGUAGE options
The various building blocks and constructs in VHDL that are used are:
2.4.8.1 ENTITY
Every VHDL style description consists of a minimum of one entity. In VHDL, associate degree
entity declaration describes the circuit because it seems from the "outside", from the angle of its
input and output interfaces.An entity declaration in VHDL provides the whole interface for a
circuit. victimization {the information|the knowledge|theknowledge} provided in associate
degree entity declaration (the port names and also the data sort and direction of every port), you
have got all the knowledge you would like to attach that portion of a circuit into alternative,
higher-level circuits.The entity declaration includes a reputation, compare, and a port statement
process all the inputs and outputs of the entity. every of the ports is given a direction (either in,
out or in out).
• Formal Definition
It is the hardware abstraction of a digital system. Entity declaration describes the external read of
the entity to the skin world.
Simplified syntax:
Entity entity-name is
Port (port-list);
[generic(generic-list);]
end entity-name;
• Description
All styles are expressed in terms of entities. Entity is that the most simple building block in a
very style. The toplevel of the planning is that the ranking entity. If the planning is hierarchical ,
then the ranking description can have lower-level descriptions contained in it. These lower-level
descriptions are going to be lower-level entities contained within the ranking entity description.
2.4.9 DESIGN
Every entity in a very VHDL style description should be sure with a corresponding design. The
design describes the particular perform of the entity to that it's sure. victimization the schematic
as a image, you'll consider the design as being roughly analogous to a lower-level schematic
pointed to by the higher-level useful block image. The second a part of a lowest VHDL supply
file is that the design declaration. each entity declaration you write should be in the middle of a
minimum of one corresponding design. The design declaration begins with a novel name,
followed by the name of the entity to that the design is sure. among the design declaration is
found the particular useful description of our comparator. There ar many ways to explain
combinatory logic functions in VHDL.
A body related to associate degree entity declaration to explain the interior organization or
operation of a style entity. associate degree design body is employed to explain the behavior,
knowledge flow or structure of a style entity:
• Simplified syntax
Architecture architecture-name of entity-name is
Architecture-declarations
Begin
Concurrent-statements
End [architecture] [architecture-name];
• Description
design appointed to associate degree entity describes internal relationship between input and
output ports of the entity. It contains of 2 parts: declarations and coincident statements. initial a
part of design might contain declarations of sorts, signals, constants, subprograms parts and
teams. coincident statements within the designbody outline the connection between inputs and
outputs. This relationship is specified victimization differing kinds of statements: coincident
signal assignment, method statement, element representation, and coincidentprocedure decision,
generate statement, coincident assertion statement, and block statement. It is writing in several
styles: structural, dataflow, activity (functional) or mixed. the outline of a structural body relies
on element representation and generates statements. It permits making hierarchical comes, from
easy gates to terribly advanced parts, describing entire subsystems. The Connections among parts
ar completed through ports.
The Dataflow description is constructed with coincident signal assignment statements. every of
the statements is activated once any of its input signals changes its worth. The design body
describes solely the expected practicality (behavior) of the circuit, with none direct indication on
the arduous ware implementation. Such description consists solely of 1 or additional processes,
every of that contains ordered statements. The design body might contain statements that outline
each behavior and structure of the circuit at an equivalent time. Such design description is named
mixed.
2.4.10 ELEMENT DECLARATION
A element declaration declares a virtual style entity interface that will be utilized in element
representation statement.
Simplified syntax:
Component component-name
[generic(generic-list)];
port(port-list);
end element [component-name];

2.4.11 element representation
A element representation statement defines a subcomponent of the planning entity during which
it seems, associate signals or values with the ports of that subcomponent, and associates values
with generics of that subcomponent.
Label: [component] component-name
Generic map (generic-association-list);
Port map (port-association-list);
2.4.12 CONFIGURATION DECLARATION
A configuration may be a construct that defines however element instances in a very given block
are guaranteed to style entities so as to explain however style entities ar place along to create a
whole style.
Configuration configuration-name of entity-name is

Configuration declarations.
For architecture-name
For instance-label: component-name
Use entity library-name. Entity-name (arch-name);
End for;
end for;
end configuration-name;
2.5 CONFIGURATION representation
A element representation statement defines a subcomponent of the planning entity during which
it seems, associates signals or worth with the ports of that subcomponent
Label: Configuration configuration-name
Generic map (generic-association-list);
Port map (port-association-List);
PACKAGE
A package declaration defines the interface to a package.
Package package-name is
Package –declarations
End [package] package-name;
Package body
A package body defines the bodies of subprograms and also the values of delayed constants
declared within the interface to the package.
Simplified syntax:
Package body package-name is
Package-body-declarations
Subprogram bodies declarations
End [package body] package-name;
2.5.1 ATTRIBUTES
Attributes ar of 2 types: user outlined and predefined.
User outlined
A value, function, type, range, signals, or constant that will be related to one or additional named
entities in a very description.
Attribute attribute-name: type; --attribute declaration
Attribute attribute-name of item: item-class is expression –attribute specification

• Description
Attributes enable retrieving info concerning named entities: sorts, objects, subprograms etc.
Users will outline mew attributes so assign them to named entities by specifying the entity and
also the attribute values for it.
Predefined
A value, function, type, range, signals, or constant that will be related to one or additional named
entities in a very description.
Simplified syntax: object’s attribute-name
2.5.2 STATEMENT
A method statement defines associate degree freelance ordered method representing the behavior
of some portion of the planning
Simplified syntax:
[process-label:] method [(sensitivity-list)];
Process-declarations
begin
Sequential-statements
end method [process-label];
2.5.6 perform
A call may be a package of the shape of associate degree expression that returns a worth.
Function perform name(parameters) come back type -- function declaration
Function perform-name(parameters) come back sort is --- function definition.
Begin
Sequential statements
End [function] function-name;
2.5.7 PORT
A channel for dynamic communication between a block and its setting.
Simplified syntax:
Port (port-declaration, port-declaration,-----);
----port declarations:
Port-signal-name: in port-signal-type: =initial-value
Port-signal-name: out port-signal-type: =initial-value
Port-signal-name: in out port-signal-type: =initial-value
Port-signal-name: buffer port-signal-type: =initial-value
Port-signal-name: linkage port-signal-type: =initial-value

2.5.8 SENSITIVITY LIST
• Formel Definition
A list of signals a method is sensitive to.
Simplified syntax:
(Signal-name, signal-name, ---)
Formal Definition
STANDARD LOGIC
A nine-value resolved logic sort.
Std-logic isn't a region of the VHDL normal. it's outlined in IEEE Std 1164.
Simplified syntax:
Type std-ulogic is (‘U’, -- Uninitialized
‘X’, -- Forcing Unknown
‘0’, -- Forcing zero
‘1’, -- Forcing one
‘Z’ -- High resistance
‘W’--Weak Unknown
‘L’--Weak one
‘-‘--Don’t Care);
Type std-ulogic-vector is array (natural vary <>) of std-ulogic
Function resolved (s: std-ulogic-vector) come back std-ulogic;
2.5.9 knowledge sorts
There are several knowledge sorts offered in VHDL. VHDL permits knowledge to be depicted in
terms of high-level knowledge sorts. These knowledge sorts will represent individual wires in a
very circuit, or will represent collections of wires employing a construct known as associate
degree array. The preceding description of the comparator circuit used the information sorts bit
and bit vector for its inputs and outputs. The bit knowledge sort(bit vector is just associate degree
array of bits) values of '1' and '0' are the sole potential values for the bit knowledge sort. each
knowledge sort in VHDL encompasses a outlined set of values, and an outlined set of valid
operations. sort checking is strict, therefore it's impractical, as an example, to directly assign the
worth of associate degree whole number knowledge sort to to a small degree vector knowledge
sort. (There are ways in which to induce around this restriction, victimization what are known as
sort conversion functions.) VHDL is made language with many various knowledge sorts.
The most common knowledge sorts are listed below:
Bit: a 1-bit worth representing a wire. (Note: IEEE normal 1164 defines a 9-valued replacement
for bit known asstd_logic.)
Bit vector: associate degree array of bits. (Replaced by std_logic_vector in IEEE 1164.)
Boolean: a True/False worth.
Integer: a signed whole number worth, usually enforced as a 32-bit knowledge sort.
Real: a floating-point worth.
Enumerated: accustomed produce custom knowledge sorts.
Record: accustomed append multiple knowledge sorts as a set.
Array: is accustomed produce single or multiple dimension arrays.

Access: like pointers in C or Pascal.
file: accustomed browse and write disk files. helpful for simulation.
Physical: accustomed represent values like time, voltage, etc. victimization symbolic units of live
(such as 'ns' or 'ma').
2.5.10 PACKAGES AND PACKAGE BODIES
A VHDL package declaration is known by the package keyword, and is employed to gather
usually used declarations to be used globally among completely different style units. you'll
consider a package as being a typical cargo area, one accustomed store such things as sort
declarations, constants, and world subprograms.
A package will contains 2 basic parts: a package declaration associate degreed an optional
package body. Package declarations will contain the subsequent forms of statements:
Type and subtype declarations
Constant declarations
Global signal declarations
Function and procedure declarations
Attribute specifications
File declarations
Component declarations
Alias declarations
Disconnect specifications
Use clauses
Items showing among a package declaration is created visible to alternative style units through
the utilization of a use statement. the connection between a package associate degreed package
body is somewhat reminiscent of the connection between an entity and its corresponding design.
Where as the package declaration provides the knowledge required to use the things outlined
among it (the parameter list for a world procedure, or the name ofan outlined sort or subtype),
the particular behavior of such things as procedures and functions should be specified among
package bodies.
2.6 Electronic style Automation
There ar many EDA (Electronic style Automation) tools offered for circuit synthesis,
implementation, and simulationvictimization VHDL. Some tools (place and route, as an
example) ar ordered as a part of a vendor’s style suite (e.g., Altera’s Quartus II, that permits the
synthesis of VHDL code onto Altera’s CPLD/FPGA chips, or Xilinx’s ISE suite, for Xilinx’s
CPLD/FPGA chips). alternative tools (synthesizers, as an example), besides being ordered as a
part of the planning suites, can even be provided by specialised EDA firms (Mentor Graphics,
Synopsis, Simplicity, etc.). samples of the latter cluster ar Leonardo da Vinci Spectrum (a
synthesizer from Mentor Graphics), change(a synthesizer from Simplicity), and Modelsim (a
machine from Model Technology, a Mentor Graphics company). Thestyles bestowed within the
book were synthesized onto CPLD/FPGA devices (appendix A) either from Altera or Xilinx. The
tools used were either ISE combined with ModelSim, MaxPlus II combined with Advanced
Synthesis software package or Quartus II. Leonardo da Vinci Spectrum was additionally used
often. thoughcompletely different EDA tools were accustomed implement and take a look at the
examples bestowed within the style, we tend to determined to standardize the visual presentation
of all simulation graphs. because of its clean look, the wave form editor of MaxPlus II was used.
However, newer simulators like ISE þ ModelSim and Quartus II, over a way broader set of
options, which permit, as an example, a additional refined temporal orderanalysis. For that
reason, those tools were adopted once examining the fine details of every style.
2.6.1 Field-Programmable Gate Array
A field-programmable gate array (FPGA) is a semiconductor device that can be configured by the
customer or designer after manufacturing—hence the name "field-programmable". To program an FPGA
one must specify how they want the chip to work with a logic circuit diagram or a source code in a
hardware description language (HDL). FPGAs can be used to implement any logical function that an
application-specific integrated circuit (ASIC) could perform, but the ability to update the functionality
after shipping offers advantages for many applications.
FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable
interconnects that allow the blocks to be "wired together"—somewhat like a one-chip programmable
breadboard. Logic blocks can be configured to perform complex combinational functions, or merely
simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements,
which may be simple flip-flops or more complete blocks of memory.
For any given semiconductor process, FPGAs are usually slower than their fixed ASIC counterparts. They
also draw more power, and generally achieve less functionality using a given amount of circuit
complexity. But their advantages include a shorter time to market, ability to re-program in the field to fix
bugs, and lower non-recurring engineering costs. Vendors can also take a middle road by developing their
hardware on ordinary FPGAs, but manufacture their final version so it can no longer be modified after the
design has been committed.
Field Programmable Gate Array (FPGA) devices were introduced by Xilinx in the mid-1980s. They differ
from CPLDs in architecture, storage technology, number of built-in features, and cost, and are aimed at
the implementation of high performance, large-size circuits.
A field-programmable gate array (FPGA) may be a semiconductor which will be organized by the client or
designer when manufacturing—hence the name "field-programmable". To program associate degree
FPGA oneshould specify however they require the chip to figure with a logic circuit diagram or a ASCII
text file in a veryhardware description language (HDL). FPGAs is accustomed implement associate
degreey logical perform that an application-specific computer circuit (ASIC) may perform, however the
power to update the practicality whenshipping offers blessings for several applications.
FPGAs contain programmable logic parts known as "logic blocks", and a hierarchy of reconfigurable
interconnects that enable the blocks to be "wired together"—somewhat sort of a one-chip
programmable bread board. Logic blocks is organized to perform advanced combinatory functions, or
simply easy logic gates like AND and XOR. In most FPGAs, the logic blocks additionally embody memory
components, which can be easy flip-flops oradditional complete blocks of memory.
For any given semiconductor method, FPGAs ar typically slower than their fastened ASIC counterparts.
Theyadditionally draw additional power, and usually attain less practicality employing a given quantity of
circuitcomplexness. however their blessings embody a shorter time to promote, ability to re-program
within the field to repair bugs, and lower non-recurring engineering prices. Vendors can even take a
middle road by developing their hardware on standard FPGAs, however manufacture their final version
therefore it will now not be changed whenthe planning has been committed.
Field Programmable Gate Array (FPGA) devices were introduced by Xilinx within the mid-1980s. They
dissent from CPLDs in design, storage technology, variety of inherent options, and cost, and ar aimed
toward the implementation of high performance, large-size circuits.
Figure 2 : FPGA Architecture
The basic design of associate degree FPGA is illustrated in figure two. It consists of a matrix of CLBs
(Configurable Logic Blocks), interconnected by associate degree array of switch matrices.
The internal design of a CLB is completely different from that of a PLD initial, rather than implementing
SOP expressions with AND gates followed by OR gates (like in SPLDs), its operation is generally
supported a LUT (lookup table). Moreover, in a very FPGA the amount of flip-flops is far additional
copious than in a CPLD,therefore permitting the development of additional refined ordered circuits.
Besides JTAG support and interface to various logic levels, alternative extra options are enclosed in
FPGA chips, like SRAM memory, clock multiplication (PLL or DLL), PCI interface, etc. Some chips
additionally embody dedicated blocks, like multipliers, DSPs, and microprocessors.
Another elementary distinction between associate degree FPGA and a CPLD refers to the storage of the
interconnects. whereas CPLDs are non-volatile (that is, they create use of antifuse, EEPROM, Flash, etc.),
most FPGAs use SRAM, and are thus volatile. This approach saves house and lowers the value of the
chip as a result of FPGAs gift a awfully sizable amount of programmable interconnections, however
needs associate degreeexternal memory board. There are, however, non-volatile FPGAs (with antifuse),
which could be advantageousonce reprogramming isn't necessary.
Figure 3 : Examples of FPGA Packages
FPGAs is terribly refined. Chips factory-made with state-of-the-art0.09mmCMOS technology, with 9

copper layers and over one,000 I/O pins, ar presently offered. a couple of samples of FPGA packages ar
eillustrated in figure A6,that shows one in every of the littlest FPGA packages on the left (64 pins), a
medium-size package within the middle (324 pins), and an outsized package (1,152 pins) on the correct.
many firms manufacture FPGAs, like Xilinx, Actel, Altera, and fast Logic.
Notice that each one Xilinx FPGAs use SRAM to store the interconnects, therefore are reprogrammable,
however volatile (thus requiring external ROM). On the opposite hand, Actel FPGAs are non-volatile
(they use antifuse),however ar non-reprogrammable (except one family, that uses Flash memory). Since
every approach has its own blessings and drawbacks, the particular application can dictate that chip
design is most acceptable
3. Project
3.1 Abstract:
This paper proposes an on-line transparent test technique for detection of latent hard faults which develop
in first input first output buffers of routers during field operation of NoC. The proposed transparent test is
utilized to perform online and periodic test of FIFO memory present within the routers of the NoC.
Simulation results show that periodic testing of FIFO buffers do not have much effect on the overall
throughput of the NoC except when buffers are tested too frequently. The proposed architecture of this
paper analysis the logic size, area and power consumption using Xilinx 14.2.
3.2 Literature survey:

The emergence of multi-cores in embedded systems requires a reliable, scalable and efficient
communication infrastructure. The bus-based architectures have advantages in terms of simplicity and
ease of implementation, but they suffer from fundamental limitations such as scalability and bandwidth.
To overcome these limitations, a new communication infrastructure is needed for multicore chips.
Network-on-Chip (NoC) has been introduced as a promising infrastructure which is based on the packet
switching approach. NoC can tackle the scalability challenges faced by the traditional bus architectures.
“Threshold-based mechanisms to discriminate transient from intermittent faults”, Using an on-chip

interconnection network to replace top-level wiring has advantages of structure, performance, and
modularity. A network structures the top-level wires simplifying their layout and giving them well-
controlled electrical parameters. These well controlled electrical parameters in turn enable the use of
high-performance circuits that result in significantly lower power dissipation, higher propagation velocity,
and higher bandwidth that is possible with conventional circuits.
“System level power modeling and simulation of high-end industrial network-on-chip”, Today’s System
on Chip (SoC) technology can achieve unprecedented computing speed that is shifting the IC design
bottleneck from computation capacity to communication bandwidth and flexibility. Also, since
communication buses between the cores are not sufficiently scalable, bus-based SoCs (the common type
of SoCs) cannot handle this high volume of communication between the cores in the SoCs. In addition,
these SoCs cannot be used for high speed serial communications. Moreover, as volume of the data
communication on the chip increases, the power consumption increases. Therefore, a scalable
communication infrastructure that better supports the trend of state-of-the-art SoC integrations is required.
Thus, recent researchers use packet-switched micro-network on a chip, so called NoC, as a scalable
communication media. The basic idea is borrowed from traditional large-scale multi-processors and the
wide-area network domains.
“Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era”,
Successful design of digital integrated circuits (ICs) has often relied on complicated optimization among
various design specifications such as silicon area, speed, testability, design effort, and power dissipation.
Such a traditional design approach inherently assumes that the electrical and physical properties of
transistors are deterministic and hence, predictable over the device lifetime. However, with the silicon
technology entering the sub- 65-nm regime, transistors no longer act deterministically. Fluctuation in
device dimensions due to manufacturing process (sub-wavelength lithography, chemical mechanical
polishing, etc.) is a serious issue in nanometer technologies. Until approximately 0.35-m technology
node, process variation was inconsequential for the IC industry. Circuits were mostly immune to minute
variations because the variations were negligible compared to the nominal device sizes. However, with
the growing disparity between feature size and optical wavelengths of lithographic processes at scaled
dimensions (below 90 nm), the issue of parameter variation is becoming severe. In the following sections,
first we describe the parametric variations and its ill-effect on power dissipation. Then, we provide an
overview of various emerging circuit and micro architectural solutions to resolve these issues.
1. Toward a scalable test methodology for 2D-mesh network-on-chips
K. Petersen and J. Oberg,
During the last ten years, state of the art SoC designs have increased dramatically in complexity and the
prediction is that this will continue also for the years to come. The technical and economical benefit of
this is expected to be enormous, at least if the full potential can be utilised efficiently. Several
improvements have been envisioned. From a functional and implementation point of view, a decrease of
implementation and verification time by increased reusability through IPs is expected. Traditional on-chip
busses are expected to be replaced by Networks-on-chip (NoC), since future generations of SoC designs
require much higher volumes of communication than can be handled efficiently by traditional on chip
busses [9]. From a manufacturing test point of view, a change from external test to BIST is envisioned, a
change that is expected to solve several problems: [12]. 1) Scalability. Usage of external testers is
becoming very difficult and expensive, since test data volumes increase at the same time as the number of
gates hidden behind each package pin also increases. 2) Deep submicron (DSM) processes must be tested
at full clock-speed, which is very expensive [12], if even possible to accomplish with external testers. 3)
A change from production test only to life time test is required, since tomorrows designs are foreseen to
be used in more reliability demanding applications. And from a manufacturing yield point of view, a
change from “go/no-go-test” to “test and repair” is required, since the increased density of designs
increases the probability for physical defects [13] [5]. This paper presents a BIST strategy for testing the
NoC interconnect network, and investigates if the strategy is a suitable approach for the task. The test
method is inline with the vision of a scalable test methodology. The intention is to use the BIST to detect
faults and to be able to pinpoint the location of each defect, and finally autonomously use this information
to reconfigure the architecture in such a way that full functionality, from a user point of view, can be
remained. The efficiency of the method is evaluated in terms of testability and area overhead for the
selected switch type.
A scalable test methodology targeting 2D-mesh type of NoCs has been presented. The test is executed at
full clock-speed and in a functional-like mode. It is carried out as a go/no-go BIST at start-up. On the
NoC level the proposed method can locate physical defects down to the granularity of a switch, with its
surrounding links. At the switch level, the position of a physical defect can be distinguished to be present
either in the controller part or in the datapath/links. We conclude that from test point of view absolute
address mode is better than relative address mode, since test time is constant for a NoC greater or equal to
3*3, and up to large values of n*m. Switches and links in a 2 by 2 NoC can be tested in less than 3000
clock cycles and NoCs up to 26 by 26 switches can be tested within 6000 clock cycles. If the addressing
mode is changed from relative to absolute, the test time can be reduced to a constant of 2000 clock cycles
for a 2 by 2 NoC and 5100 clock cycles for any 2D NoC with size n ≥ 3. The test times can possibly be
reduced further with a more careful selection of patterns instead of using an ATPG tool to generate them.
This will be investigated in the future. The total BIST area overhead, for a centre switch and links is
limited to less than 7%. Optimising the BIST solutions should reduce the area overhead. How to do this
will also be investigated in the future.
2. A cost-effective scheme for network-on-chip router and interconnect testing
D. Xiang,
As the number of IP cores in systems increases, the implementation of a single broadcast or bus-based
communication architecture becomes a time-consuming task in the system design cycle. For systems with
intensive parallel communication requirements, busses may not provide the required bandwidth, latency,
and power consumption [8]. One emerging solution for such a communication bottleneck is the use of an
embedded switching network, called Network-on-Chip (NoC), to interconnect the IP cores in a System-
on-Chip (SoC) [5]. Several authors have presented different aspects regarding the design and
implementation of on-chip networks [5][8][13]. Recently, industrial NoCs have also been proposed [11].
Furthermore, the reuse of the NoC as Test Access Mechanism (TAM) has been presented as a
cost effective strategy for the test of embedded IP cores, with reduced area, pin count, and test time
costs [2][4]. Although one may claim that the network operation is also tested when it is transmitting
test data, for diagnosis purposes and complete fault coverage it is important to define a test scheme for
the network before its reuse as TAM. In effect, test strategies that reuse the NoC assume that it has been
tested by a specific method before being reused. Some test approaches for NoCs have been discussed in
the literature [1][10][11]. Aktouf [1] suggests the use of a boundary scan wrapper. Other approaches [10]
[11] suggest that a wide variety of standard Design-for-Test (DfT) solutions can be used, from BIST for
FIFOs, to functional testing of wrapped routers. However, those proposals have not been applied, to the
best knowledge of the authors, to actual NoCs. In this paper, we firstly verify the efficiency of some of
the previously suggested NoC test approaches, as well as the applicability of standard DfT techniques [3]
[6][12] to NoC testing. Experiments show that existing approaches may lead to considerable area
overhead and test time, making the NoC testing a major bottleneck for the system design. Hence, we
propose a scalable and cost-effective DfT strategy for the routers of the NoC. The proposed method is
based on partial scan and on an IEEE 1500-compliant test wrapper, and it takes advantage of the NoC
regularity. Moreover, the test strategy is scalable and independent of the network functional operation,
which makes it suitable for a large class of network models and implementations. The method is applied
to three versions of a NoC model with different sizes to demonstrate its effectiveness. The results are
analyzed in terms of area overhead, test time, test data volume, fault coverage, and power dissipation.
The contributions of this paper are twofold: firstly, it shows that the application of standard DfT
techniques to the NoC testing is not straightforward, and may lead to excessive costs if applied
deliberately. Secondly, it presents a structured, scalable, and cost-effective test scheme for NoC routers.
The paper is organized as follows: Section 2 presents a brief overview of NoC design and a description of
the network used in the sequel of the paper. Section 3 presents the results of the application of standard
DfT methods in the test of a NoC. Section 4 describes the proposed test strategy, while Section 5
discusses the experimental results. Section 6 concludes the paper.
3. Minimal-path fault-tolerant approach using connection-retaining structure in networks-on-chip
M. Ebrahimi, M. Daneshtalab, J. Plosila, and H. Tenhunen,
With the aggressive device scaling in the semiconductor technology, two salient problems emerge: (1)
efficient connection of the increasing number of on-chip resources, and (2) effective management of the
decreasing reliability [1]. The first problem concerns the limitation of the conventional interconnects
which cannot scale well with the complexity of the chip multiprocessors. The Network-on-Chip (NoC)
paradigm has emerged as a promising solution for such platforms [2]. The second problem arises from the
extreme device scaling which threatens the reliability by low yield and wear-out. Thus, the interconnect
must be able to tolerate partial failure due to its critical role in holding all of the components of the
system together [1, 3, 4]. The failures are generally classified as either permanent or transient. Moreover,
failures can occur in the switches1 or links connecting the switches. Permanent switch failures are
addressed in this paper. The incorporation of fault-tolerance into NoC design mainly revolves around two
intertwined concepts: (1) routing method, and (2) network architecture. While the focus is often slanted
toward the routing methods, the network architecture plays an equally important role in delivering a
reliable system. Realizing the significance of network connectivity in the presence of faulty routers, the
current research was carried out to propose a Traffic-Aware Reconfigurable Architecture, aptly called
TARA, for Fault-tolerant 2D mesh NoCs. The underlying principle of the proposed technique is inspired
by the Minimal-path Connection-retaining Fault-tolerant (MiCoF) approach [4] to maintain the
connectivity of a network by modifying the router architecture. Once a router becomes faulty, its
associated links are normally discarded. However, by connecting the incoming links of a faulty router to
its outgoing links in the desired directions, the packets are able to bypass the faulty switch and reach the
destination through surviving routers. The main features and contributions of the proposed technique are:
(1) Unlike the static MiCoF which is oblivious to the traffic distribution, the network topology in TARA
is dynamically tailored according to the location of faults and the current traffic pattern in the network.
This is especially important for the real-time systems since their dynamically changing requirements can
be met effectively and a high performance communication can be achieved. Moreover, the corner paths
can be survived using TARA. (2) The proposed method supports adaptivity (path diversity) in the
network. Furthermore, rerouting is minimized by sending the packets through the available minimal
(shortest) paths. It does not require routing tables, disable healthy routers, or set exceptional rules for the
borderlines. (3) TARA uses a purely local fault look-ahead information which is the minimum knowledge
required for making reliable routing decisions. Thus, the hardware overhead is kept to a minimum. (4)
Only one and two Virtual Channels (VCs) [2] along the X and Y dimensions are required to ensure
deadlockfreedom for a single faulty router. It is livelock-free, as well. The rest of the paper is organized as
follows. The related works are studied in Section 2 followed by a description of MiCoF in Section 3.
Section 4 details the mechanism of TARA. Section 5 is devoted to the simulation results and discussion.
Finally, the conclusions are drawn in Section 6.
We have proposed a dynamically reconfigurable architecture (TARA) for wormhole-switched 2D mesh

NoCs. The main advantages of TARA over the conventional schemes is its ability to dynamically tailor
the failed switch to the current traffic pattern such that not only the connectivity of the network is
maintained, but also the performance can be improved. Moreover, TARA supports adaptive, fully
distributed, minimal, and algorithmic routing without using routing tables.
4. Methodologies and algorithms for testing switch-based NoC interconnects
C. Grecu, P. Pande, B. Wang, A. Ivanov, and R. Saleh
Recent advances in semiconductor technology raise the challenge of managing the difficulties of
designing complex chips containing billions of transistors. In this context, the reusability concept is an
essential tool that helps when coping with this issue, where large Systems on Chip (SoC) are built using
pre-existing Intellectual Property (IP) cores. Networks on Chip (NoC) [1] [2] interconnect infrastructures
are emerging as the new paradigm to address the on-chip data communication architecture of large scale
SoCs. In general, two trends can be identified with respect to the architectures of the different NoC
implementations: (i) regular interconnection structures derived from parallel computing, and (ii) irregular,
custom-built NoC fabrics. Kumar [3] has proposed a mesh-based interconnect architecture named
CLICHÉ. Dally et al. [4] suggested a torusbased architecture. Both of these architectures consist of an m
x n mesh of switches interconnecting computational resources (IPs) placed along with the switches.
Guerrier and Greiner [5] proposed the use of a tree-based interconnect (SPIN) and addressed system level
design issues. In [6] and [7], the authors describe an interconnect architecture based on the Butterfly Fat
Tree (BFT) topology for a networked SoC, as well as the associated design of the required switches and
addressing mechanisms. Benini et al. [8] have introduced application specific irregular architectures to
build networked SoCs. The common characteristics of all these interconnect fabrics is that the functional
IP blocks communicate with each other through a highly structured switched medium, consisting of
intelligent switches and inter-switch links. A necessary requirement for any new design methodology to
be widely adopted is to be complemented by efficient test mechanisms. So far, the NoC test
methodologies are mainly concerned with the testing of the functional IP cores, using the communication
infrastructure as a Test Access Mechanism (TAM) [9]. Our work complements this approach by
developing the test strategy for the interconnect infrastructure itself. The test strategy of NoC-based
interconnects infrastructures needs to address two problems: (i) testing of the switch blocks; (ii) the
testing of the inter-switch interconnect segments. Here we specifically propose and evaluate the testing
methodology suitable for the NoC switch blocks. The controllability/observability of the NoC
interconnects is relatively reduced, due to the fact that they are deeply embedded and spread across the
chip. Pin-count limitations restrict the use of I/O pins dedicated for the test of the different components of
the data-transport medium; therefore, we propose that the NoC infrastructure be progressively used for
testing its own components in a recursive manner, i.e., that the good, already tested NoC components be
used to transport test patterns to the untested elements. This test strategy minimizes the use of additional
mechanisms for transporting data to the NoC elements under test, while allowing the reduction of test
time through the use of parallel test paths and test data multicast.
In this paper we proposed two methodologies for testing the switch blocks of NoC interconnects. We paid
special attention to the testing procedure of the FIFO components of these blocks. The first method is
based on a single source – single destination test pattern transport strategy, while the second one exploits
the inherent parallelism of NoCs and uses a single source – multiple destination test pattern transport
strategy. These two methodologies have been evaluated with respect to test time for different system
sizes. Our results indicate that the multicast-based test strategy improves the test time significantly,
specifically for large NoC sizes. We are currently working on extending these test strategies to irregular
NoCs infrastructures, characterized by irregular topologies and/or switch blocks having different number
of ports and channel widths.
5. A distributed and topologyagnostic approach for on-line NoC testing
M. R. Kakoee, V. Bertacco, and L. Benini
Network-on-Chips (NoCs) constitute the interconnection infrastructure of today’s massively parallel

many-core architectures. As silicon technologies continuously shrink, NoCs like other hardware devices
become increasingly vulnerable to process and runtime variations [1]. Variability results in complex
structural faults which can lead to unpredictable errors. A single fault in the NoC may cause packets to be
dropped or become corrupted, resulting in incoherent and erroneous traffic, ultimately causing the entire
chip to fail [2]. While structural testing targets certain structural fault models and tries to prove the
absence of these faults, functional testing validates some specified functionalities. Due to complexity
reasons, this is inherently incomplete, and fault simulation shows usually a rather limited fault coverage
obtained by functional test strategies [3, 4]. Yet functional testing has still some benefits over a structural
test as it does not need a separate test mode, it can be applied in system speed and it may even detect
faults not covered otherwise [5–7]. The goal of the paper at hand is to combine the benefits of structural
and functional test of NoCs. It presents an automated approach to generate functional test patterns with
high structural fault coverage. Functional test patterns can be applied during the normal operation of a
switch interleaving the normal traffic. The conditional line flip (CLF), as introduced in [8], is used to
specify any type of structural faults. A formal satisfiability-based (SAT) approach classifies structural
faults into functional failure classes. Fault classification is specially useful to extend the functional failure
classes, so that the structural fault coverage of the corresponding functional test increases. It determines
which structural faults cause a certain functional failure. Besides, it provides a weighted functional failure
classification with respect to the number of structural faults in each class. The method includes four tasks:
1) Definition of functionalities of an NoC switch, and formalization of the corresponding failure modes.
2) Mapping the failure modes to the switch structure in the form of clauses. This allows test generation by
modern satisfiability solvers (SAT). 3) Modeling structural faults (not just stuck-at faults) by clauses and
adding these clauses to the failure mode description. 4) Solving the SAT problem allows now to generate
data input for the functional test and to quantify the structural faults covered by each of the functional
failure modes. The outcome of this method is functional data packets for the switches and links which can
be applied in system mode and form highly effective test sequences. The experimental results show that
functional tests generated this way achieve a significantly higher fault coverage than the ones obtained by
commercial sequential ATPG tools.
This paper presented an automated approach for functional test pattern generation for NoC switches with
high structural fault coverage. The formal definition of functionalities of the switch and the corresponding
failure modes allow mapping of failure modes to the switch structure in the form of clauses. Thus, fault
classification and test generation can be conducted by modern SAT solvers. In addition to the
quantification of structural faults covered by each functional failure mode, the experiments show an
effective classification resulting in high fault coverage of the generated functional test. Moreover, the
classification can be used to select the appropriate fault tolerant technique while trading off the area and
timing constraints.
6. A parametric design of a built-in self-test FIFO embedded memory
S. Barbagallo et al.
FIFO (First In First Out) memories have acquired a larger interest in VLSI design in telecom applications.
Such macrocells provide an efficient way to interface two asynchronous system, buffering data between
subsystems operating at different data rates, thus increasing the flexibility in data transmission. In fact,
data in FIFO memories are read following the same order in which they have been writtenl, without the
need of providing the address of the data. Different approaches have been considered in literature to
design FIFO mmory cells. In this paper w: define an architecture based on a static RAM cell, available in
the Italtel library of components. We aim at defining a parametric architecture whose size can be modified
with slight modifications to the basic structure. In order to obtain such a result, the control logic has been
designed in a modular way, thus defining a flexible structure, whose basic components are described in
VHDL. In particular, the control logic is constituted by two subsystems with two independent clock
signals, managing the read and write operations, respectively. Performance and area constraints have
driven the design optimizations. The off-line Built-In Self Test (BIST) design technique has been chosen
to allow for testing of such a macrocell. Two operation modes are provided: in the normal mode the
wcrocell performs the nominal operations; in the test mode the macrocell is isolated from the main device
into which it is embedded in order to execute the test procedure. The choice for the Built-In Self Test
technique is motivated by the requirement of testing such cells when they are deeply embedded into more
complex devices. without the necessity of driving long test sequences into the device to the macrocell.
Furthermore, such design for testability technique allows testing at the nominal operation frequency also
in the application field with accurate test procedures. The BIST architecture has been defined in order to
be easily interfaced to the TAP controller for Boundary Scan, thus providing the external inputs dedicated
to the test activation following the specific test protocol. in addition to the nominal inputs. A complete
fault model for the RAM cell has been taken into account, togeither with a set of functional faults
representing the possible stuck-at faults in the control logic. An extended Single Order Addressed (SOA)
march test [5] algorithm has been defined to ensure the fault coverage for all classes of faults identified.
The test algorithm has then been efficiently implemented into the test logic, which has beer1 realized as
self-testing, to avoid erroneous fault attributions. The test logic structure has been defined in a parainetric
way in order to be adapted to different memory sizes.
7. Functional tests for arbitration SRAM-type FIFOs
J. van de Goor and Y. Zorian
First-In First-Out ’FIFO’ memories are widely used as a building block to buffer data between subsystems
operating at different data rates. Various telecommunications oriented systems, such as ATMs, require
such memories. Today different types of FIFOs are in use, both as stand-alone chips and as embedded
macros in ASICs. They can be distinguished, based on the way they are implemented as: 1. RAM-type
FIFOs, which use a RAM (usually an SRAM) to contain the data together with a read and a write address
register to access the data. Depending on the way the data can be accessed, the following RAM-type
FIFOs can be recognized: 1) single-port arbitration RAM-type FIFOs (The read and write addresses are
each specified with an N-bit (N = log2n, where n is the number of words in the FIFO) counter accessing a
single-port memory using an arbiter.); and 2) dual-port RAM-type FIFOs (They allow for simultaneous
read and write operations, while the addressing mechanims can be implemented using counters (counter-
address) or shift registers (ring-addres)). 2. Shifting-type FIFOs, based on a self-clocking shift register
which shifts data from the write port into the last unused location of the read port. They allow for
simultaneous read and write operations and have the property that a word written via the write port has to
bubble through the n-word FIFO to the read port requiring a bubble-through time of n1 handshake
signals. The well-known functional tests for SRAMs [2,3,5] often cannot be applied to other types of
memories because of the need for specific fault models and test algorithms. Recently, several studies were
reported on testing Double Buffered Memories [9] and Single-Address Order Memories [7]. FIFOs also
cannot be tested like standard RAMs because of the following built-in addressing restrictions: only a
single address order can be used, and a march element is restricted to a maximum of one write operation
and one read operation. This means that the classical march algorithms for testing RAMs [2,3,5] cannot
be used with FIFOs. In general, the test approach of a FIFO is like any other part, it could consist of the
test sequence: parametric tests, functional tests and asynchronous tests. Algorithms and methods for DC
and AC parametric tests have been described in [10]. Asynchronous tests, consisting of verifying the
correct FIFO operation for different timing relationships (such as partial overlap between the write and
the read clock signals) are reported in [8]; they report failure rates as high as 75% for chips which passed
the parametric and functional tests. Fault models and tests for arbitration SRAM-type FIFOs have been
described in [4], and for Ring-address SRAM-type FIFOs in [6,11]. However, no test algorithms for
shifting-type FIFOs have been reported. Many manufacturers are providing such chips however: Ad
vanced Micro Devices (Am2812 and Am2813), Philips (74HC/HT40105 and 74HC/HT7030), Texas
Instruments (SN74ALS236), and Monolithic Memories (74S225/A, C67401A/B, C67402A/B, and
67413).
ns A functional model of a shifting-type FIFO has been given. Analoguous to traditional SRAM and
DRAM memories, fault models have been derived for the memory array, the addressing mechanism and
the FIFO functionality logic. These fault models have been based on classical SRAM fault models;
however, they are specific for shifting-type FIFOs. The used methodology may be applied to other types
of embedded memories. Traditional march tests cannot be used for testing FIFOs because of the
mandatory use of a single address order and march elements with only one write and/or read operation. In
addition to testing the addressing mechanism and the memory array, a FIFO test also has to cover faults in
the FIFO functionality logic (this is the embedded logic which implements the FIFO behaviour). For each
of the faults a (set of) requirement(s) has been derived for a test to detect the faults and an order O(n) test
has been given. It has been shown that this test covers all faults. Because of the specific nature of shifting-
type FIFOs, this test is unlike any other memory test; while its simplicity makes it well suitable for
application as a B
8.Theory of transparent BIST for RAMs
M. Nicolaidis
Modern computer systems typically contain a variety of embedded memory arrays like caches, branch
prediction tables or priority queues for instruction execution [4, 14]. Fault free memory operations are
crucial for the correct behavior of the complete system, and thus, efficient techniques for production
testing as well as for periodic maintenance testing are mandatory to guarantee the required quality
standards. However, advances in memory technology and in system design turn memory testing into a
more and more challenging problem. Due to the limited accessibility of embedded memories
conventional methods for external testing can no longer provide satisfactory solutions. A number of
theoretical and practical built-in self-test (BIST) approaches, which have been proposed in the past, offer
the basis to overcome this problem in present-day systems-on-a-chip [1 - 3, 5 - 8, 12, 13, 17 - 20, 22].
These approaches range from on-chip random pattern generation and efficient mechanisms for repeated
consistency checking to deterministic test schemes targeting specific fault models. With increasing
memory densities the relative area overhead for the BIST implementation becomes negligible.
A new approach for transparent RAM BIST has been proposed which exploits symmetries in the test
algorithms to implement schemes for output data compression with precomputable signatures.
Compared to traditional transparent BIST schemes this new approach significantly reduces the test time
while preserving the benefits of previous approaches with respect to hardware overhead and fault
coverage. Experimental studies even show an increase in fault coverage in many cases.
9. Design and evaluation of mesh-of-tree based network-on-chip using virtual channel router
S. Kundu, J. Soumya, and S. Chattopadhyay
The silicon industry has used Systems-on-Chip with multiple heterogeneous processing units as means to
deliver the performance required by modern applications. However, the integration of an increasing
number of specialized processing units poses a challenge on the interconnection mechanisms in such
systems. As a solution, the silicon industry has been using Networks-on-Chip to interconnect components
in this kind of SoC [1], [2]. The Communication in NoC can be either unicast or multicast [3]. In unicast
communication, a message is sent from a processor connected to the network to a single destination
processor. In multicast communication, a message is sent from one processor to an arbitrary set of
destination processors in the network. Several SoCs with multiple processors have applications that
employ multicast communication, for example, barrier synchronization, cache coherency in distributed
sharedmemory architectures, or clock synchronization. Despite the multicast communication can be
implemented by multiple unicast communications, it is not a suitable strategy because it degrades the
performance and increases the congestion in the network [4]. This paper presents an overview of research
on NoC with support for multicast communication and delineates the major issues addressed by the
scientific community in this research area over the last decade. It starts with an overview about Network-
on-Chip and Multicast in Section II. Section III introduces an overview of research that has done on
multicast communication for Networks-on-Chip, and Section IV close this paper with our conclusion.
The proposal of this paper was to present an overview of research on NoC with support for multicast
communication and delineated the major issues addressed so far by the scientific community in this
research area. Although it presents just an overview of all NoC research related to NoCs with multicast
communication, it reveals the main issues and how the researchers deal with that. We noticed that 80% of
the research presented so far have focused on routers structure of the networks in terms of algorithms [5]
[7][10][11][13][20], adding parallel links working in the network [18], or extra bits into the flits structure
[19]. Other 20% of research have focused on the design-time network partition [12], and message scheme
was running on the processing cores connected in the network [14]. We also noticed that few papers are
focusing on multicast on NoC have published so far. We understand that it is a quite new research area,
and the interest on it may increase due to the increasing on multicore Systems-on-chip. The reason for
that increase is the continuous advances in the semiconductor device fabrication technology that expected
to reach fourteen nanometres for silicon fabric [21]. The continued downscaling of the silicon technology
increases transistor density and operating frequency, and hence the SoC demands lower supply voltage,
which reduces noise immunity. At this point, Network-on-Chip emerges as a suitable interconnection
mechanism; it is recognized as a solution for electrical issues on SoCs composed by several processing
cores [22], what may expand the research horizon for multicast communication on NoCs. The Future
scope of this research work will be a detailed survey, in which, the technical details of each research
introduced in this paper will be mitigated. It will serve as a base for an evaluation that our team intends to
do with different multicasting techniques on the RTSNoC[23], a Network-on-Chip designed for real-time
communication flows.
3.3 Existing System:

FIFO buffers in NoC infrastructure are large in number and spread all over the chip. Accordingly,
probability of faults is significantly higher for the buffers compared with other components of the router.
Both online and offline test techniques have been proposed for test of FIFO buffers in NoC. The proposal
is an offline test technique (suitable for the detection of manufacturing fault in FIFO buffers) that
proposes a shared BIST controller for FIFO buffers. Online test techniques for the detection of faults in
FIFO buffers of NoC routers have been proposed. However, the technique considers standard cell-based
FIFO buffers, while we consider SRAM-based FIFO designs. Thus, faults considered in this brief are
different from those targeted. To the best of our knowledge, no work has been reported in the literature
that proposes online test of SRAM-based FIFO buffers present within routers of NoC infrastructure. Thus,
we surveyed online test techniques for SRAM-based FIFOs in general. The survey revealed that SRAM
based FIFOs are tested using either of the following two approaches, dedicated BIST approach as
proposed by Barbagallo et al. and or distributed BIST proposed by Grecu et al.. However, both dedicated
and distributed BIST approaches being offline test techniques fail to detect permanent faults, which
develop over time.
3.4 Proposed System:

In proposed system to increase the size of the FIFO buffer to 32bit range.The algorithmic interpretation of
the transparent SOA-MATS++ test is presented in Algorithm 1. It describes the step-by-step procedure to
perform the three phases of the transparent SOA-MATS++ test for each location of the FIFO memory.
For a particular FIFO memory location (present value of i), the first iteration of j (address run1) performs
the invert phase, where the content of the FIFO location is inverted. The invert test phase involves reading
the content of lut into a temporary variable temp and then backing it up in original. Then, the inverted
content of temp is written back to lut. At this point, the content of lut is inversion of content of original.
In the next iteration of j (address run2), the restore phase is performed. The content of lut is reread into
temp and compared with the content of original. The comparison should result in all 1’s pattern. However,
deviation from the all 1’s pattern at any bit position indicates fault at that particular bit position. Next, the
inverted content of temp is written back to lut. Thus, the content of lut, which were inverted after the first
iteration get restored after the second.
The third iteration of j performs only a read operation of lut, where the content of lut is read into temp
and compared with the contents of original. At this stage of the test, all 0’s pattern in the result signifies
fault free location, while deviation at any bit position from all 0’s pattern means fault at that particular bit
position. The last read operation ensures the detection of faults, which remained undetected during the
earlier two test runs. At the end of the three test runs (iterations of j), the loop index i is incremented by
one to mark the start of test for the next location.
3.4.1 Fault Coverage of the Proposed Algorithm:

The transparent SOA-MATS++ algorithm is intended for test of stuck-at fault, transition fault, and read
disturb fault fault tests developed during field operation of FIFO memories. The fault coverage of the
algorithm is shown in Fig. 4. In both the figures, the word size of FIFO memory is assumed to be of 4
bits. The text in italics against the arrows indicates the operation performed, while the text in bold font
corresponds to the variables used in Algorithm 1.
As shown in Fig. 4, assume the data word present in lut be 1010. The test cycles begin with the invert
phase (memory address pointer j with 0 value) during which the content of location addressed is read into
temp and then backed up in the original. The data written back to lut is the complement of content of
temp. Thus, at the end of the cycle, the data present in temp and original is 1010, while lut contains 0101.
Assume a stuck-at-1 fault at the most significant bit (MSB) position of the word stored in lut. Thus,
instead of storing 0101, it actually stores 1101 and as a result, the stuck-at-fault at the MSB gets excited.
Figure 4: Fault detection during invert phase and restore phase of the transparent SOA-MATS++ test
The FIFO buffer present in each input channel of an NoC router consists of a SRAM-based FIFO memory
of certain depth. During normal operation, data flits arrive through a data_in line of the buffer and are
subsequently stored in different locations of the FIFO memory. On request by the neighboring router, the
data flits stored are passed on to the output port through the data_out line. Fig. 5(a) shows the FIFO
memory with data_in and data_out line. To perform the transparent SOA-MATS++ test on the FIFO
buffer, we added a test circuit, few multiplexers and logic gates to the existing hardware, as shown in Fig.
5(a). The read and write operations on the FIFO buffer are controlled by the read enable and write enable
lines, respectively. The multiplexers mu6 and mu7 select the read and write enable during the normal and
test process. During normal operation when the test_ctrl is asserted low, the internal write and read enable
lines, wen_int and ren_int, synchronized with the router clock, provide the write and the read enable,
respectively. However, during test process, the write enable and read enable are synchronized with the test
clock. As mentioned earlier, the read and write operations during test are performed at alternate edges of a
test clock. The read operations are synchronized with the positive edges, while the write_clk is obtained
by inverting the test clock. In test mode (test_ctrl high), the test read and write addresses are generated by
test address generators implemented using gray code counters similar to the normal address generation.
Muxes m4 and m5 are used to select between normal addresses and test addresses.
Figure 5: (a) Hardware implementation of the test process for the FIFO buffers.
(b) Implementation of test circuit.
Consider the situation when the FIFO buffer is in normal mode with flits being transferred from the
memory to the data_out line. After a few normal cycles, the test_ctrl is asserted high, switching the buffer
to test mode. As long as the buffer is in test mode, no external data is allowed to be written to the buffer,
or in other words, the buffer is locked for the test period. As a result, the input data line for the FIFO
memory is switched from the external data_in line to test_data line available from the test circuit. At the
switching instant, the flit which was in the process of being transferred to the data_out line is
simultaneously read into the Test Circuit. However, a one clock cycle delay is created for the flit to move
to the data_out line. This delay ensures that the flit is not lost during the switching instant and is properly
received by the router, which requests for it. The single cycle delay in the path of the traveling flit is
created by the D-type flip-flop and the multiplexer m3, as shown in Fig. 5(a). The flit, which is read in the
test circuit, is stored in a temporary register temp and the test process begins with this flit.
3.4.2 Advantages:
1. utilize to perform online
2. utilize periodic test of FIFO memory

4. Software Requirement
4.1 MODELSIM - ALTRA
4.1.1 Assumptions
I assume that you simply ar acquainted with the utilization of your software system. you ought to
even beacquainted with the window management functions of your graphic interface: Open Windows,
OSF/Motif, CDE, KDE, GNOME, or Microsoft Windows 2000/XP. we tend to additionally assume that
you simply have a operatinginformation of the language during which your style and/or take a look at
bench is written (i.e., VHDL, Verilog, etc.). though ModelSim™ is a wonderful tool to use whereas
learning HDL ideas and practices, this document isn'twritten to support that goal.
4.1.2 Modelsim introduction
ModelSim may be a verification and simulation tool for VHDL, Verilog, System Verilog, and mixed
language styles. This lesson provides a short abstract summary of the ModelSim simulation setting. it's
divided into four topics, thatyou'll learn additional concerning in subsequent lessons.
4.1.3 Basic Simulation Flow

the subsequent diagram shows the fundamental steps for simulating a style in ModelSim.
Basic Simulation Flow
4.1.3.1 Basic Simulation Flow - Overview Lab

In ModelSim, all styles ar compiled into a library. you sometimes begin a brand new simulation
in ModelSim bymaking a operating library known as "work," that is that the default library name utilized
by the compiler because the default destination for compiled style units.
• compilation Your style
when making the operating library, and compile your style units into it. The ModelSim library format is
compatible across all supported platforms. Its will simulate your style on any platform while not having to
recompile your style. Loading the machine together with your style and Running the Simulation with the
planning compiled, load themachine together with your style by invoking the machine on a ranking
module (Verilog) or a configuration or entity/architecture try (VHDL).
Assuming the planning hundreds with success, the simulation time is ready to zero, and you enter a run
command to start simulation.
• Debugging Your Results
If you don’t get the results you expect, you'll use ModelSim’s sturdy debugging setting to trace down the
explanation for the matter.
4.1.4 Project Flow

A project is a collection mechanism for an HDL design under specification or test. Even thoughyou don’t
have to use projects in ModelSim, they may ease interaction with the tool and are useful for organizing
files and specifying simulation settings. The following diagram shows the basic steps for simulating a
design within a ModelSim project.
Project flow
As you'll see, the flow is analogous to the fundamental simulation flow. However, there ar twoimportant
differences:
• Do not ought to produce a operating library within the project flow; it's in hot water you mechanically.
• Projects ar persistent. In alternative words, they're going to open anytime you invoke ModelSim unless
you specifically shut them.
4.1.5 Multiple Library Flow
ModelSim uses libraries in 2 ways: 1) as a neighborhood operating library that contains the compiled
version of your design; 2) as a resource library. The contents of your operating library can modification as
you update your styleand recompile. A resource library is usually static and is a components supply for
your style. It will produce your own resource libraries, or they'll be provided by another style team or a
3rd party (e.g., a chemical elementvendor). It specifies that resource libraries are going to be used once
the planning is compiled, and there ar rules to specify during which order they're searched. a typical
example of victimization each a operating library and a resource library is one wherever your gate-level
style and take a look at bench ar compiled into the operatinglibrary, and also the style references gate-
level models in a very separate resource library. The diagram below shows the fundamental steps for
simulating with multiple libraries.
Figure 8 : Multiple Library flow
4.1.6 Debugging Tools

ModelSim offers numerous tools for debugging and analyzing your design. Several of these tools
are covered in subsequent lessons, including:
• Using projects
• Working with multiple libraries
• Setting breakpoints and stepping through the source code
• Viewing waveforms and measuring time
• Viewing and initializing memories
• Creating stimulus with the Waveform Editor
• Automating simulation
4.1.7 Basic Simulation
4.1.7.1 Introduction
In this lesson you will go step-by-step through the basic simulation flow:
1. Create the Working Design Library
2. Compile the Design Units
3. Load the Design
4. Run the Simulation
4.1.7.2 Design Files for this Lesson
The sample design for this lesson is a simple 8-bit, binary up-counter with an associated
test bench. The pathnames are as follows:
Verilog – <install_dir>/examples/tutorials/verilog/basicSimulation/counter.v and tcounter.v
VHDL – <install_dir>/examples/tutorials/vhdl/basicSimulation/counter.vhd and tcounter.vhd
This lesson uses the Verilog files counter.v and tcounter.v. If you have a VHDL license, use
Counter.vhd and tcounter.vhd instead. Or, if you have a mixed license, feel free to use the
Verilog test bench with the VHDL counter or vice versa.
4.2 Xilinx ISE
The steps required to perform behavioral and post-route simulations using the Xilinx Integrated
Software Environment (ISE) and Mentor Graphics ModelSim simulator. In the past, Xilinx bundled the
ISE with a licensed edition of ModelSim, resulting in little or no issues between the two softwares.
However, in recent years it appears as if the two companies are no longer on level terms. As a result,
Mentor Graphics does not provide Xilinx with licenses for ModelSim and Xilinx for its part do not
provide pre-compiled device libraries for ModelSim. This tutorial will show you how to resolve
compatibility issues, so that you can continue to use the features that these software’s provide.
As with any software tutorial, there is always more than one way of doing things. If you come
across better solutions or typos or have any suggestions for improving this document please email the
author or contact Dr. Grantner.
4.2.1 Pre-requisite
Before reading any further you should have the following softwares installed on your computer
4.2.2 Simulation Libraries
• Simulation Library Compilation Wizard
• Compile HDL Libraries through Project Navigator
4.3 XILINX
4.3.1 XILINX ISE summary
The Integrated software package setting (ISE™) is that the Xilinx® style software
package suite that permitsyou to require your style from style entry through Xilinx
device programming. The ISE Project Navigator manages and processes your style
through the subsequent steps within the ISE style flow.
4.3.1.1 ENTRY
Design entry is that the beginning within the ISE style flow. throughout style entry,
you produce your supplyfiles supported your style objectives. you'll produce your
ranking style file employing a Hardware Description Language (HDL), like
VHDL, Verilog, or ABEL, or employing a schematic. you'll use multiple formats
for the lower-level supply files in your style.
4.3.2 SYNTHESIS
After style entry and optional simulation, you run synthesis. throughout this step,
VHDL, Verilog, or mixed language styles become netlist files that are accepted as
input to the implementation step.
4.3.3 IMPLEMENTATION
After synthesis, you run style implementation, that converts the logical style into a
physical file format which will be downloaded to the chosen target device. From
Project Navigator, you'll run the implementation method in one step,otherwise you
will run every of the implementation processes severally. Implementation
processes vary betting on whether or not you're targeting a Field Programmable
Gate Array (FPGA) or a posh Programmable Logic Device (CPLD).
4.3.4 VERIFICATION
You can verify the practicality of your style at many points within the style flow.
you'll use machine software package to verify the practicality and temporal order
of your style or a little of your style. The machine interprets VHDL or Verilog code
into circuit practicality and displays logical results of the delineated HDL to see
correct circuit operation. Simulation permits you to make and verify advanced
functions in a very comparatively bit of your time.you'll additionally run in-circuit
verification when programming your device.
4.3.5 DEVICE CONFIGURATION
After generating a programming file, you assemble your device. throughout

configuration, you generate configuration files and transfer the programming files
from a bunch laptop to a Xilinx device.
4.4 PROJECT NAVIGATOR summary
Project Navigator organizes your style files and runs processes to maneuver {the
style|the planning|the look} from style entry through implementation to
programming the targeted Xilinx® device. Project Navigator is that the high-level
manager for your Xilinx FPGA and CPLD styles, that permits you to try and do the
following:
• Add and build style supply files, that seem within the Sources window
• Modify your supply files within the space
• Run processes on your supply files within the Processes window
• View output from the processes within the Transcript window
4.4.1 PROJECT NAVIGATOR MAIN WINDOW
The following figure shows the Project Navigator main window, that permits you
to manage your style beginning with style entry through device configuration.
Fig 7.1 project navigator
1. Toolbar
2. Sources window
3. Processes window
4. Workspace
5. Transcript window
4.4.1.1 USING THE SOURCES WINDOW
The first step in implementing your design for a Xilinx® FPGA or CPLD is to assemble
the design source files into a project. The Sources tab in the Sources window shows the source
files you create and add to your project, as shown in the following figure. For information on
creating projects and source files, see Creating a Project and Creating a Source File.
Fig 7.2 SOURCES WINDOW
The Design View ("Sources for") drop-down list at the top of the Sources tab allows you
to view only those source files associated with the selected Design View (for example,
Synthesis/Implementation). For details, see Using the Design Views. The "Number of" drop-
down list, Resources column, and Preserve column are available for designs that use Partitions.
For details, see Using Partitions.
The Sources tab shows the hierarchy of your design. You can collapse and expand the
levels by clicking the plus (+) or minus (-) icons. Each source file appears next to an icon that
shows its file type. The file you select determines the processes available in the Processes
window. You can double-click a source file to open it for editing in the Workspace. For
information on the different file types, see Source File Types.
You can change the project properties, such as the device family to target, the top-level
module type, the synthesis tool, the simulator, and the generated simulation language. For
information, see Changing Project, Source, and Snapshot Properties.
Depending on the source file and tool you are working with, additional tabs are available in
the Sources window:
 Always available: Sources tab, Snapshots tab, Libraries tab
 Constraints Editor: Timing Constraints tab
 Floor plan Editor: Translated Netlist tab, Implemented Objects tab
 iMPACT: Configuration Modes tab
 Schematic Editor: Symbols tab
 RTL and Technology Viewers: Design tab
 Timing Analyzer: Timing tab
4.5.1 USING THE TRANSCRIPT WINDOW
The Console tab of the Transcript window shows output messages from the processes you
run. When the following icons appear next to a message, you can right-click the message and
select Goto Answer Record to open the Xilinx website and show any related Answer
Records. If a line number appears as part of the message, you can right-click the message and
select Goto Source to open the source file with the appropriate line number highlighted.
 Warning
 Error
Depending on the source file and tool you are working with, additional tabs are available in
the Transcript window:
 Always available: Console tab, Errors tab, Warnings tab, Tcl Shell tab, Find in Files tab
 ISE Simulator: Simulation Console tab
 RTL and Technology Viewers: View by Name tab, View by Category tab
4.6 CREATING A PROJECT

Project Navigator allows you to manage your FPGA and CPLD designs using an ISE™
project, which contains all the files related to your design. First, you must create a project and
then add source files. With your project open in Project Navigator, you can view and run
processes on all the files in your design. Project Navigator provides a wizard to help you create a
new project
CHAPTER 5 RESULTS
5. Timing report
5.1 Power report
5.2 Area report
5.3 RTL view
5.3.1 Top view architecture:

5.3.2 overall architecture:
5.4 Test circuit
5.4 FIFO memory

6. Conclusion
we have proposed a transparent SOA-MATS++ test generation algorithm that can detect run-time
permanent faults developed in SRAM-based FIFO memories. The proposed transparent test is
utilized to perform online and periodic test of FIFO memory present within the routers of the
NoC. Periodic testing of buffers prevents accumulation of faults and also allows test of each
location of the buffer. As future work, we would like to modify the proposed FIFO testing
technique that will allow incoming data packets to the router under test without interrupting the
test.
REFERENCE
1. K. Petersen and J. Oberg, “Toward a scalable test methodology for 2D-mesh network-on-chips,”
in Proc. Design, Autom., Test Eur. Conf. Exhibit., Apr. 2007, pp. 1–6.
2. D. Xiang, “A cost-effective scheme for network-on-chip router and interconnect testing,” in Proc.
22nd Asian Test Symp. (ATS), Nov. 2013, pp. 207–212.
3. M. Ebrahimi, M. Daneshtalab, J. Plosila, and H. Tenhunen, “Minimal-path fault-tolerant approach

using connection-retaining structure in networks-on-chip,” in Proc. 7th IEEE/ACM Int. Symp. Netw.
Chip (NoCS), Apr. 2013, pp. 1–8.
4. C. Grecu, P. Pande, B. Wang, A. Ivanov, and R. Saleh, “Methodologies and algorithms for testing
switch-based NoC interconnects,” in Proc. 20th IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., Oct.
2005, pp. 238–246.
5. M. R. Kakoee, V. Bertacco, and L. Benini, “A distributed and topologyagnostic approach for on-
line NoC testing,” in Proc. 5th ACM/IEEE Int. Symp. Netw. Chip, May 2011, pp. 113–120.
6. S. Barbagallo et al., “A parametric design of a built-in self-test FIFO embedded memory,” in

Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., Nov. 1996, pp. 221–229.
7. J. van de Goor and Y. Zorian, “Functional tests for arbitration SRAM-type FIFOs,” in Proc. 1st
Asian Test Symp. (ATS), Nov. 1992, pp. 96–101.
8. M. Nicolaidis, “Theory of transparent BIST for RAMs,” IEEE Trans. Comput., vol. 45, no. 10,
pp. 1141–1156, Oct. 1996.
9. S. Kundu, J. Soumya, and S. Chattopadhyay, “Design and evaluation of mesh-of-tree based

network-on-chip using virtual channel router,” Microprocess. Microsyst., vol. 36, no. 6, pp. 471–488,
Aug. 2012.

Network On-Chip Router Prevention of Fault Tolerant in Fifo Buffers

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VLSI Very Large Scale Integrated Circuits

HDL Hardware Description Language

VHDL VHSIC Hardware Description Language

VHSIC Very High Speed Integrated Circuits

IEEE Institute Of Electrical And Electronic Engineers

VITAL VHDL Initiative Towards Ask Libraries

RTL Register Transfer Level

PLA Programmable Logic Array

PAL Programmable Array Logic

CPLD Complex Programmable Logic Devices

CLB Configurable Logic Blocks

ISE Integrated Software Environment

EDA Electronic Design Automation

FPGA Field-Programmable Gate Array

2.1.1 Dealing with VLSI Circuits

2.3 VLSI DESIGN STYLES

2.3.4 Full custom design

2.4 Introduction to VHDL

2.4.1 Limitations of traditional programming languages

Figure one : outline of VHDL style flow

2.4.2 HISTORY OF VHDL

2.4.3 LEVELS OF ABSTRACTION (STYLES)

Fig. Levels of abstraction

2.4.4 NEED FOR VHDL

2.4.5 ADVANTAGES OF VHDL

• movability VHDL’s movability permits the planning description to be used on completely

Programmable logic eliminates expenses and facilitates fast style iterations

• The language supports hierarchy, i.e., a digital system is sculptural as a collection of

• The language is technology freelance and therefore an equivalent behavior model is

• varied digital modeling techniques like finite-state machine descriptions, algorithmic

• Take a look at benches is written victimization an equivalent language to check alternative

2.4.6 DESIGN METHODOLOGY USING VHDL

There are 3 style methodologies namely: bottom-up, top-down and flat

• A top-down style method involves a divide-and-conquer approach to implement the planning an

2.4.7 Components OF VHDL

2.4.8 VHDL LANGUAGE options

Architecture architecture-name of entity-name is

End [architecture] [architecture-name];

2.4.10 ELEMENT DECLARATION

end element [component-name];

Label: [component] component-name

Generic map (generic-association-list);

Port map (port-association-list);

2.4.12 CONFIGURATION DECLARATION

Configuration configuration-name of entity-name is

For instance-label: component-name

Use entity library-name. Entity-name (arch-name);

2.5 CONFIGURATION representation

Label: Configuration configuration-name

Generic map (generic-association-list);

Port map (port-association-List);

A package declaration defines the interface to a package.

End [package] package-name;

Package body package-name is

Subprogram bodies declarations

End [package body] package-name;

Attributes ar of 2 types: user outlined and predefined.

Attribute attribute-name: type; --attribute declaration

Attribute attribute-name of item: item-class is expression –attribute specification

Simplified syntax: object’s attribute-name

[process-label:] method [(sensitivity-list)];

end method [process-label];