Proceedings of the 7th International Caribbean Conference on Devices, Circuits and Systems, Mexico, Apr.

28-30, 2008

Bending Effect of Si MOSFETs on Flexible Plastic

Substrate
H. L. Kao1, Y. C. Chang1, B. S. Lin1, M. H. Huang1, and C. H. Kao2
1
Department of Electronic Engineering, Chang Gung University, Tao-Yuan 33302, Taiwan
snoopy@mail.cgu.edu.tw
2
Department of Accounting Information, Takming College, Taipei 11451, Taiwan

Abstract—By applying ~0.27% tensile strain to the flexible die
of a 0.16 μm thin-body (100 μm) Si MOSFET mounted on
plastic, the DC characteristics have been improved. The small
DC performance degradation of the Si MOSFET transferred
to plastic shows the potential of integrating electronics onto
plastic. The device performance was improved by flexing the
substrate to create stress, which produced a 10.7%
enhancement of the saturation drain current and only 0.003V
Vth is lower. The approach has the advantages of flexible
electronics on the insulating plastic substrate and low cost.
saturation drain current (Id,sat) with ~0.27% mechanically-
strained is 10.7% higher and the threshold voltage (Vth) is
0.003 V lower for 0.16 μm Si MOSFET. The mobility can be
improved from 187 to 208 cm2/V⋅sec. The improved
performance was confirmed by T-Supreme and Medici
simulations (TMA). The improvements arise from tsub and
high flexibility, since the surface strain increases with 1/tsub2
[13]. We demonstrate a successful bonding process and good
mechanical flexibility performance for the Si MOSFETs.

II. Experimental Procedure

I. INTRODUCTION
Flexible electronics have a lot of attention for portable
electronics product due to their lightness, thinness, shortness,
and minimization properties [1]-[3]. The flexible electronic
device is limited to the performance of low-temperature
amorphous, polycrystalline Si thin-film transistors (TFTs)
and organic TFTs (OTFTs) [4]-[8]. Comparison of single-
crystal Si MOSFETs, they suffer from much lower mobility
(e.g., ≤ 1.5 cm2/V⋅sec). Some reports have proposed nano-
crystalline Si TFT or rubrene-based OTFT to improve the
mobility but still lower than single-crystal Si material. In
order to achieve the high performance on the flexible plastic,
the single crystal Si MOSFET is still a good alternative in
terms of higher performance and mature technology. The
integrating Si IC on light transparent, low cost and small
weight plastic substrate is the key technology for radio
frequency identification tags (RF ID), Display and Flexible
Electronics, since the Si MOSFETs are well out-performance
the polymer/organic transistors [9]-[12]. However, a
challenge for integrating Si MOSFET on plastic is that high
performance transistors are required and needed to be
transferred from their Si substrates and mounted on plastic
with little performance degradation. In this paper, we report
a Si substrate thinning method and successfully transferred
devices onto plastic. The 100 μm thick Si MOSFETs after
thinned-down and transfer on plastic shows a little
degradation. Additionally, due to the high flexibility of the
thin body thickness (tsub) on plastic, a large strain
(proportional to 1/tsub2) can be applied for device
performance improvement. The improvement of the
In this study we used low-cost, highly-insulating 270 µm
thick polyethylene substrates, which had a resistivity of 108-
109 Ω-cm. We designed the n-type MOSFETs using 0.16 μm
technology and then fabricated on 8-in wafer at an IC
foundry. The devices have gate oxide and poly-Si thickness
of 4.4 nm and 100 nm respectively. To achieve integration
onto plastic, we first thinned down the substrate of the Si
MOSFETs from 700 μm to 100 μm, using Chemical
Mechanical Polish (CMP) procedure. The thinned devices
were then glued onto a 270 μm thick light-transparent
polyethylene terephthalate (PET) plastic for DC testing. The
schematic process flow is shown in Fig. 1. The transparency
is useful for integration with displays as shown in Fig. 2(a).
The DC characteristics were measured using an HP4142
measurement system. Figure 2(b) shows the high flexibility
of 100 μm thick Si substrate under a large surface strain
without cracking. Thus, it is possible to apply a large
mechanical strain to the flexible Si substrate devices on
plastic and not crack the Si substrate. We have calculated the
surface strain by using ANSYS 8.0 simulation software and
the device characteristics, under various applied tensile
strains, using TMA process-device simulation software.
Figure 1. The schematic of thinned-down and transfer on platic process.

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 8
Lg=0.16μm W=10.14μm
7

5 measure @ V d=2.1V

ID (mA)
4

3
on VLSI-standard Si substrate
2
on plastic with 100 μm Si
Figure 2. (a) Image of a die with n-type MOSFETs on transparent plastic on plastic with tensile strain
(hand-held). (b) Image showing the flexibility of the ~40 μm-thick Si 1 Line: simulated by TMA
substrate (tsub) under mechanical strain (which is proportional to 1/ tsub 2).
0
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
III. RESULTS AND DISCUSSION VD (V)

A. DC characteristics on plastic:
Figures 3 shows a comparison of Id -Vg characteristic for
0.16 μm n-MOSFET on a VLSI-standard substrate and on
plastic with 100 μm thinned-down Si substrate. There is a
slight Vth shift and little gm degradation at the linear region.
The Id –Vd characteristics is shown in Fig. 4. The measured Id
-Vg and Id –Vd of the 0.16 μm devices, before and after
thinning and mounting on plastic, is almost identical. These
results suggests that the CMP technique of thinning down the
Si substrate to 100 μm, then transferring and bonding it onto
plastic, produced little degradation for the 0.16 μm n-
MOSFETs as expected [14]. The observed shift could be due
to conduction-band reduction from the residual strain [15].
The damage of thinned-down and transfer process can be
neglected. Close agreement between the measured and
simulated Id -Vg, gm -Vg and Id –Vd results were first achieved
for the fresh device to show the accuracy of the TMA
simulation and they are included in Figs. 3 and 4,
respectively.
2.0
Lg=0.16μm W=10.14μm measure @ Vg=0.1V
on VLSI-standard Si substrate
on plastic with 100 μm Si
1.5 on plastic with tensile strain
Line: simulated by TMA
ID (mA)
Figure 4. Measured and simulated Id-Vd characteristics for 0.16 μm
nMOSFETs on a VLSI-standard substrate and on plastic with 100 μm Si,
with or without tensile strain. The solid lines are the TMA-simulated data
for a VLSI-standard Si substrate and on plastic under ~0.27% tensile strain.
B. DC characteristics enhancement by strain:
To further utilize the inherit merit of high flexibility for
thin Si substrate, we have applied a tensile stress to the
MOSFETs die on plastic. The large surface strain ε, is
calculated from ε=3aF/btsub2E [16] where a is the shortest
distance between the bending distance and the test device, F
is the applied force for the die, b is the chip width, tsub is the
wafer thickness, and E is the Young’s modulus of the silicon
(115×109 Pa), as shown in Fig. 5. Figure 6 shows the thin Si
substrate under an applied tensile strain, as calculated using
ANSYS 8.0 simulation software. The bending distance was
0.25 cm when using 0.32 GPa stress on 100 μm thick Si
substrate. This condition gives a tensile strain of ~0.27%
(=0.32GPa/115GPa), assuming that the Young’s Modulus of
3.0 Si is 115GPa [13].
2.5
2.0

gm (mS)

1.0 1.5

1.0
0.5
0.5

0.0 0.0
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
VG (V)

Figure 3. Measured and simulated Id-Vg characteristics for 0.16 μm

Figure 5. The schematic of our measurement system to measure and
nMOSFETs on a VLSI-standard substrate and on plastic with 100 μm Si,
calculate the mechanical strain ε=3aF/btsub2E.
with or without tensile strain. The solid lines are the TMA-simulated data
for a VLSI-standard Si substrate and on plastic under ~0.27% tensile strain.
 100 μm Si-body 0.16 μm nMOSFET is shown in Fig. 8. A
good match between the measured and simulated Id -Vg, Id –
Vd and mobility results were achieved for the strained case
and they are included in Figs. 3, 4 and 7, respectively.

250
Lg=0.16μm W=10.14μm

Effective Mobility (cm /V-sec)

measure @ Vg=0.1V

200

2
150

a =0.25cm
Stress=0.32GPa 100
Bending distance on VLSI-standard Si substrate
50 on plastic with 100 μm Si
on plastic with tensile strain
Line: simulated by TMA

Figure 6. The mechanical stress calculated by using ANSYS 8.0 0

simulation software. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Effective Field (MV/cm)
Under the same conditions, the experimental data of the
effect of strain on the Id -Vg and Id –Vd characteristics for the Figure 7. The measured and simulated effective mobility data for 0.16
μm nMOSFETs on a VLSI-standard substrate and on plastic with 100 μm
0.16 μm n-MOSFET on plastic are also shown in Figs. 3 and Si, with or without tensile strain. The solid lines are the TMA-simulated
4. After applying a ~0.27% tensile strain, the thin-Si body data for a VLSI-standard Si substrate and on plastic under ~0.27% tensile
MOSFETs on plastic showed a 0.003V lower threshold strain.
voltage (Vt) and a 10.7% higher Id,sat. A change in drain
current with strain is due to changes in the effective mobility
and effective channel charge density arising from strain-
induced changes in the energy band structure and interface
charge changes. We consider the effect of strain on the
effective electron mobility (μeff) obtained from the following
equation at Vd =0.1 V [13].

ID
μ eff = (1)
VDS Cox W L (VGS − VT )

The derivation of effective mobility as a function of effective

electric field for 0.16 μm nMOSFET is shown in Fig. 7. For
the unstrained case, a good mobility of 187 cm2/V⋅sec was
observed. Under the applied ~0.27 % tensile strain, a higher
208 cm2/V⋅sec mobility was achieved. The 11% mobility
improvement is obtained and consists with the driving
current. The higher drain current of the Si MOSFETs under
strain condition is due to the higher mobility. The mobility
increases in this field range is due to reducing phonon
scattering and effective mass. The strain induces band
splitting and electron occupies two-fold valleys increases.
The two-fold valleys have the lower effective mass parallel
to the Si/SiO2 interface, which increases mobility [17]. The
improved mobility and DC performance is important for Si
MOSFET in flexible electronics applications.
To further analyze the improvement of Si MOSFET
under the mechanical strain, we have used TMA process-
device simulation software to simulate the effect of strain on
the 0.16 μm nMOSFETs. The simulated stress distribution of
Figure 8. TMA device simulation of a 100 μm Si-body 0.16 μm n-
MOSFETs under applied mechanical strain. The unit of Sxx is dynes/cm2.
C. Strain effect of DC charactersitics:
Figure 9 summarizes the measured and simulated Id,sat
and Vth as a function of strain. The strain effect of Vth (=φMS-
Qox/Cox+2φF+Qdpl/Cox) is only ~0.003V slightly lower. It
indicates that the oxide charge and inversion layer are only a
little changes. However, a significant Id,sat improvement
(10.7%) is obtained under ~0.27% tensile strain. From the
simulation data, the Id,sat can be improved 15.8% under
~0.43% tensile strain. The effect arises from the 1/tb2
dependence of the strain for thin-body Si. In comparison
with the OTFT, our approach can be achieved high mobility
and driving current. Also can be improved the performance
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IV. CONCLUSIONS
[12] H. L. Kao, Albert Chin, B. F. Hung, C. F. Lee, J. M. Lai, S. P.
McAlister, G. S. Samudra, Won Jong Yoo and C. C. Chi, "Low Noise
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mounted on a flexible plastic base. These devices showed Seabaugh, “Partially depleted SOI MOSFETs under uniaxial
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ACKNOWLEDGMENT K. W. Teoh, H. M. Chua, Z. X. Shen, C. K. Cheng, G. Q. Lo, N.
We would like to thank Prof. Albert Chin of NCTU for Balasubramanian, and D.-L. Kwong, "Bendability of single-crystal Si
MOSFETs investigated on flexible substrate," in IEEE Electron
his help. This work was partially supported by an NSC (96- Device Letters (EDL), Vol. 27, no. 7, 2006, pp.538-540.
2218-E-182-002)-Taiwan grant. [16] T. Ghani, M. Armstron, C. Auth, M. Bost, P. Charvat, G. Glass, T.
Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry,
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