A Report on

PHASE LOCKED LOOPS

Ma. del Rocío Ricardez-Trejo, Celso Gutiérrez-Martínez, IEEE Member, J. Alfredo Torres-Fórtiz,
Jacobo Meza-Pérez
Instituto Nacional de Astrofísica Óptica y Electrónica (INAOE)

For the Course

By

SIDHANT YADAV (BT17ECE033)

RANJEET PRAKASH RAI (BT17ECE034)

SHAGUN SHARMA (BT17ECE035)

Under the supervision of

Mr. Vivek Kumar

National Institute of Technology,Uttarakhand

Satellite Campus (M.N.I.T. Campus, Jaipur)

 INTRODUCTION

Fig.1 Simplest Analog Phase Locked Loop

A phase-locked loop or phase lock loop (PLL) is a control system that generates an
output signal whose phase is related to the phase of an input signal. There are several
different types; the simplest is an electronic circuit consisting of a variable frequency
oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal,
and the phase detector compares the phase of that signal with the phase of the input periodic
signal, adjusting the oscillator to keep the phases matched.
Keeping the input and output phase in lock step also implies keeping the input and output
frequencies the same. Consequently, in addition to synchronizing signals, a phase-locked
loop can track an input frequency, or it can generate a frequency that is a multiple of the input
frequency. These properties are used for computer clock synchronization, demodulation,
and frequency synthesis.
Phase-locked loops are widely employed in radio, telecommunications, computers and other
electronic applications. They can be used to demodulate a signal, recover a signal from a
noisy communication channel, generate a stable frequency at multiples of an input frequency
(frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such
as microprocessors. Since a single integrated circuit can provide a complete phase-locked-
loop building block, the technique is widely used in modern electronic devices, with output
frequencies from a fraction of a hertz up to many gigahertz.
 MODELING A PHASE LOCKED LOOP IN MATLAB

Below is the block diagram depicting the overall functioning of the PLL.

Fig.2 Block Diagram

Matlab Code for PLL:

fo=1E6;
pref=0;
fv=1.1E6;
K=0.5E6;
fs=100E6;
Ns=1000;
fc=0.2E6;
filnum=100;
b = fir1(filnum,fc/(fs/2));
Ts=1/fs;
T=[0:Ts:(Ns-1)*Ts];
Vco=zeros(1,Ns);
phi=zeros(1,Ns);
ref=sin(2*pi*fo*T+pref);

for n=2:Ns
t=(n-2)*Ts;
errmul(n)=ref(n)*Vco(n-1);

for m=1:length(b)
if n-m+1>=1
errarr(m)=errmul(n-m+1);
else
errarr(m)=0;
end
end
err(n)=sum(errarr.*(b));

phi(n)=phi(n-1)+2*pi*err(n)*K*Ts;
Vco(n)=sin(2*pi*fv*t+phi(n));
end

figure(1)
plot(T,ref,T,Vco),
title('Plot of input and output signals'),
xlabel('Time'),
legend('Input','Output');
figure(2)
plot(T,err),
title('Error signal'), xlabel('Time ');
 Output collected by running the above code in Matlab can be seen from the plots obtained
below where the PLL along with the Error signal generated can be observed well. The plots
below depicts the input sinusoidal wave provided as an input for modulation and the output
collected by demodulation using Phase Locked Loops.

Fig.3 Plot of Input And Output Signals obtained from

Fig.4 Error Signal generated from PLL demodulation

Variations
There are several variations of PLLs. Some terms that are used are analog phase-locked loop (APLL) also
referred to as a linear phase-locked loop (LPLL), digital phase-locked loop (DPLL), all digital phase-
locked loop (ADPLL), and software phase-locked loop (SPLL).[10]
Analog or linear PLL (APLL)
Phase detector is an analog multiplier. Loop filter is active or passive. Uses a voltage-controlled
oscillator (VCO).
Digital PLL (DPLL)
 An analog PLL with a digital phase detector (such as XOR, edge-trigger JK, phase frequency
detector). May have digital divider in the loop.
All digital PLL (ADPLL)
Phase detector, filter and oscillator are digital. Uses a numerically controlled oscillator (NCO).
Software PLL (SPLL)
Functional blocks are implemented by software rather than specialized hardware.
Neuronal PLL (NPLL)
Phase detector, filter and oscillator are neurons or small neuronal pools. Uses a rate controlled
oscillator (RCO). Used for tracking and decoding low frequency modulations (< 1 kHz), such as
those occurring during mammalian-like active sensing.

Costas loop:-
A Costas loop is a phase-locked loop (PLL) based circuit which is used
for carrier frequency recovery from suppressed-carrier modulation signals (e.g. double-
sideband suppressed carrier signals) and phase modulation signals (e.g. BPSK, QPSK). It was
invented by John P. Costas at General Electric in the 1950s. Its invention was described as
having had "a profound effect on modern digital communications". The primary application of
Costas loops is in wireless receivers.

The analysis of stability and numerical simulation of Costas loop circuits for the high-
frequency signals is a challenging task. The problem lies in the fact that it is necessary to
observe very fast time scale of input signals and slow time scale of signal’s phases
simultaneously. To overcome this difficulty, it is possible to follow the classical ideas of
Gardner and Viterbi to construct a mathematical model of Costas loop, in which only slow time
change of signal’s phases and frequencies is considered. Such an construction, in turn, requires
the computation of phase detector characteristic, depending on the waveforms of the considered
signals. In this paper, the problems of nonlinear analysis of Costas loops and the approaches to
the simulation of the classical Costas loop, the quadrature phase shift keying (QPSK) Costas
loop, and the two-phase Costas loop are discussed. The analytical method for the computation
of phase detector characteristics of Costas loops is described.

Demodulation of DSBSC using costas loop:-

Costas loop is used to make both the carrier signal (used for DSBSC modulation) and the
locally generated signal in phase. Following is the block diagram of Costas loop.
 Fig.5 Block Diagram

Costas loop consists of two product modulators with common input s(t)s(t), which is DSBSC
wave. The other input for both product modulators is taken from Voltage Controlled
Oscillator (VCO) with −90 phase shift to one of the product modulator as shown in figure.
We know that the equation of DSBSC wave is
s(t)=Accos(2πfct)m(t)

Let the output of VCO be

c1(t)=cos(2πfct+ϕ)

This output of VCO is applied as the carrier input of the upper product modulator.

Hence, the output of the upper product modulator is

v1(t)=s(t)c1(t)

Substitute, s(t)s(t) and c1(t)c1(t) values in the above equation.

⇒v1(t)=Accos(2πfct)m(t)cos(2πfct+ϕ)

After simplifying, we will get v1(t)v1(t) as

v1(t)=Ac2cosϕm(t)+Ac2cos(4πfct+ϕ)m(t)

This signal is applied as an input of the upper low pass filter. The output of this low pass filter
is
v01(t)=(Ac/2)cosϕm(t)
Therefore, the output of this low pass filter is the scaled version of the modulating signal.

The output of −90 phase shifter is

c2(t)=cos(2πfct+ϕ−90)=sin(2πfct+ϕ)

This signal is applied as the carrier input of the lower product modulator.

The output of the lower product modulator is

v2(t)=s(t)c2(t)

Substitute, s(t)s(t) and c2(t)c2(t) values in the above equation.

⇒v2(t)=Accos(2πfct)m(t)sin(2πfct+ϕ)

After simplifying, we will get v2(t)v2(t) as

v2(t)=(Ac/2)sinϕm(t)+(Ac/2) sin(4πfct+ϕ)m(t)

This signal is applied as an input of the lower low pass filter. The output of this low pass filter
is
v02(t)=(Ac/2)sinϕm(t)

The output of this Low pass filter has −90 phase difference with the output of the upper low
pass filter.
The outputs of these two low pass filters are applied as inputs of the phase discriminator.
Based on the phase difference between these two signals, the phase discriminator produces a
DC control signal.

This signal is applied as an input of VCO to correct the phase error in VCO output. Therefore,
the carrier signal (used for DSBSC modulation) and the locally generated signal (VCO output)
are in phase.
 MODELING A COSTAS LOOP IN MATLAB

Matlab Code for Costas Loop:

t = 0:16000;
fs = 4e5;
fc = 4000;
m = sin(2*pi*150*t/fs);
c = cos(2*pi*fc*t/fs + pi/3);
st = m.*c;

N = length(st);
t = 0:1:N-1;
phi = zeros(1,N);
s1 = zeros(1,N);
s2 = zeros(1,N);
y1 = zeros(1,N);
y2 = zeros(1,N);
for i = 1:N

if i>1

phi(i) = phi(i-1) - (5*10^-5)*pi*sign(y1(i-1)*y2(i-1));

end

s1(i) = st(i) * cos(2*pi*fc*t(i)/fs + phi(i));

s2(i) = st(i) * sin(2*pi*fc*t(i)/fs + phi(i));

if i<=100

for j=1:i
y1(i) = y1(i) + s1(j);
y2(i) = y2(i) + s2(j);
end

else

for j = i-99:i
y1(i) = y1(i) + s1(j);
y2(i) = y2(i) + s2(j);
end
end
end
figure;
plot(t,y1);title('Output signal');
xlabel('Time');ylabel('Amplitude');
figure;
plot(t,phi);title('phase for Signal vs time');
xlabel('Time');ylabel('Phase');
phase = phi(end);
disp(phase);
 Output collected by running the above code in Matlab can be seen from the plots obtained
below where the Costas Loop Output along with the Phase for signal Vs time generated can
be observed well. The plots below depicts the input sinusoidal wave provided as an input for
modulation and the output collected by demodulation using Costas Loop for Double Side
Band Supressed Carrier.

Fig. 6 Output Signal from Costas Loop Demodulation

Fig.7 Phase for Signal Vs Time

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