Q1 : When MBIST is inserted in your design?

Ans : Mbist is inserted at RTL stage i.e before synthesis.

Q2 : We insert BIST logic to Test Memories ,So how to test that bist logic inserted?

Ans : Bist logic consists of flipflops and combi logic, so this bist logic becomes a part of
scan chain and is tested during scan test mode.

Q3 : What is the difference between Timing and No timing Simulations ?

Ans : No Timing : Basically no timing simulations are done to check the Design(setup)
related errors.In this, we test for zero delay and unit delay conditions , for this we consider
SDC.

Timing : Timing simulations are done to check where our design is able to meet all the timing
constraints properly or not. For this we consider SDF file(delay information file) which is
provided by STA team

Q4 : Consider Two flops and specify where there is chance for delays and what type of
delays?
Ans : A path has a start point and an end point.

 Start point - All input ports/pins or clock ports/pins of sequential cells are considered
as start points.
 End points - All output ports/pins or D pin of sequential cells are considered as end
points.

Based on the above mentioned start point and end point, there are four types of timing
paths based on direction.

1. Input to Register - Start point is an input pin/port and end point is the D pin/port of a
register (flipflop). It might include both combinational and sequential cells.
2. Register to Register - Start point is the CLK pin/port of a register (flipflop) and end point
is the D pin/port of next register (flipflop). Also, this type of path might include
combinational and sequential cells.
3. Register to Output - Start point is the CLK pin/port of a register (flipflop) and end point is
an output pin/port. Both sequential and combinational cells are included here.
4. Input to Output - Start point is an input pin/port and end point is an output pin/port. It
includes combinational cells only.
5. Clock path - The timing path which is fully traversed by clock signals is called as Clock
path. In a clock path, there could only be clock inverters or clock buffers.
Clock paths are further categorized into two types.
 Launch path - The timing path which is traversed by the clock signal from source pin
to launch register (flipflop) CLK pin (FF1 in Figure).
 Capture path - The timing path which is traversed by the clock signal from source pin
to capture register (flipflop) CLK pin (FF2 in Figure).
6. Data path - The timing path which is fully traversed by data signals is called as Data path.
In a data path, there could be combinational cells, data buffers etc.,
7. Cell delay : CMOS transistors inside a standard cell takes finite amount of time to
switch from one logic state to another. This time taken is called as the cell delay or
the propagation delay of a cell which is typically specified in the cell timing library
8. Net delay : Interconnect delay or net delay is due to the physical wire (metal traces
having resistances and capacitances) of a logical net (i.e. between a driver and
load/loads). All net timing arcs are positive unate. This is because there can be either
rise-rise transition from driver to load or fall-fall transition from driver to load.

Q5 : What is PVT ?

Ans : PVT is abbreviation for Process, Voltage and Temperature. In order to make our chip to
work in all possible conditions, like it should work in Siachen Glacier at -40°C and also in
Sahara Desert at 60°C, we simulate it at different corners of process, voltage and temperature
which IC may face after fabrication. These conditions are called as corners. All these three
parameters affect the delay of the cell.
Q6 : Best and worst Conditions for PVT ? / What Specifies Max and Min ?

BEST Condition Worst condition

Hold / Fast Lib / Min Setup / Slow Lib / Max

Process : 1 Process : 1

Voltage : 1.1v Voltage : 0.9v

Temperate : -40c Temperate : 125/-40c

Q7 : Do you know about worst and best conditions in Timing ?

Ans :

Q8 :What are Stuckat(SAF) and Transition Fault(TDF) ?

Ans: In DFT, we test for the manufacturing faults. To detect these manufacturing faults there
are different fault models,Based on algorithms we determine the various faults that can arise
when the chip fabricated in the fabrication labs. SAF and TDF are two such models

Stuck-at Fault model tells us that a particular net/wire is either stuck-at 0 (connected to
ground/VSS) or stuck-at 1 (connected to Power/VDD)

Transition fault model falls under the delay fault model which tells us that a particular node is
able to make a transition from 0->1 or vice-verse at maximum operating frequency of design
. The two possible faults are slow-to-fall and slow-to-rise.

Q9 : consider a gate and explain stuck at faults?

Ans: For a two input AND gate we will have a total of 6 stuck-at faults and two transition
faults.
Stuck-at faults for a and gate can be shown as below
Q10 : What is the Difference btw Verification and DFT ?

Ans : Verification : Verification is done to check the functionality of the design.

DFT : Dft is used to detect the manufacturing defects by adding an extra logic to the design to
attain controllability and observability over the design

Q11: Do verification is done at RTL level for testing functionality or not ?

Ans : Yes ,Functional testing is done after RTL Stage.

Q12 : What is setup and hold ?

Ans: Setup Time: the amount of time the data at the synchronous input (D) must be stable
before the active edge of clock

Setup : Required time – Arrival Time >= 0

Required Time : Tclk + T capture latency – T uncertainity – T setuplib

Arrival Time : Tclk + T launch latency + T c-q + T combi

Hold Time: the amount of time the data at the synchronous input (D) must be stable after the
active edge of clock

Hold : Arrival Time - Required time >0

Required Time : T capture latency + T uncertainity + T Holdlib

Arrival Time : T launch latency + T c-q + T combi
Q13 : Explain Scan Insertion Flow?

Q14 : What are the scan violations you faced and how did you debug them?
Ans: I have faced uncontrolled clock and uncontrolled set/reset violations. When all the flops
in design are not controlled globally then we get these violations because for a design to be
DFT ready we should have global controllability and observability. For debugging these
violations we need to check the dft drc’s using the command check_dft_rules(cadence). Once
you have known that there are internally driven clocks there are two major ways of getting
back the controllability.
a. Auto fixing the issue using the command fix_dft_violations.
b. Inserting a test point so as to bypass the logic while testing.

Q15 : Instead of Adding MUX as testpoint, can we fix it by another method?

Ans : Yes we can fix it using “AND , OR” gates based on design.

Q16 : If we insert Test point by keeping always test enable high then do functionality
verification effect or not?
Ans : Yes it effects functional verification , we cant perform functional verification when test
enable is high.

Q17 : How to insert Testpoint ?

Ans : Using Autofix command ,hacking netlist ,or inserting manually test point.

Q18 : What are the outputs of scan insertion ?

Ans : Scan inserted Netlist , SPF or Pin assignment file , Scan Def ,Scan Sdc.

Q19 : What are the inputs of Atpg ?

Ans : Libraries , Scan Inserted Netlist , SPF or Pin assignment file ,Sdc ,Sdf (Timing).
Q20 : What is clock gating cell with AND gate and why we go for ICG ?
Ans : Clock gating is a common technique for reducing dynamic power dissipation by
regulating the unwanted switching of the clock to modules by a clock enable signal.

There are two commonly used ICG cell types.

 Using AND gate with high EN

The following design uses a negative edge triggered latch to synchronize the EN
signal to the CLK. The GCLK is available only when the latch o/p is high. GCLK is
held low when EN is low.

 Using OR gate with high EN

The following design uses a positive edge triggered latch. GCLK is held high when
EN is low.Note that the latch o/p is inverted at the OR input. Hence, the clock is
passed through when this i/p gets a low.

Q21 : What are the Violations you have seen in Atpg ?

Ans : I have faced S1 violation which is related to scan chain tracing. If the ATPG tool is
unable to trace the scan chain completely then it will throw this error. If the right libraries are
not read then there is a chance of getting this violation. Also if clock pin is not mentioned
properly we get this violation.
I have also faced violations related to black boxes and memories. We should update with
memory libraries and black box libraries to get rid of this violation

Q22 : What does test procedure files have?

Ans: The test procedure file contains all the scan information of your test ready netlist.
1. The number of the scan chains
2. The number of scan cells in each scan chain.
3. The shift clocks.
4. The capture clocks
5. Any test setup procedure required before starting the test pattern generation
6. The timing of the different clocks.
7. The time for forcing the Primary input , bidi inputs , scan inputs etc
8. The time to measure the primary outputs, scan outputs , etc ..
9. The pins which have to be held at some state in the different procedure as load_unload,
shift etc ..

Q23 : what are reasons for low coverage in Atpg ?

Ans : Low coverage occurs due to AU , ND faults and Pin constraints

For AU – Increase Sequential Depth,

For ND – Increase Abort Limit,
For Pincontraints – add/remove pin constraints as per the scenario

Q24 : Rather than blackboxes and unwanted Pin constraints did you notice any other low
coverage issues ?
Ans : AU , ND faults

For AU – Increase Sequential Depth,

For ND – Increase Abort Limit.

Q25 : Do latches present in your design lead to low coverage ?

Ans : we lose coverage, "putting latch on transparent mode by constraining enable signal".
Any logic driving the enable signal will lose some coverage due to this constraint.

If the enable signal is driven by a large cone of logic, you can increase the coverage
by adding a "force transparent on" gate close to the enable of the latch, and add an observe
flip-flop just before the added gate, so that most of the faults in the logic cone can be
recovered.

Without modifying the circuitry, recovering fault coverage in ATPG really depends on how
these latches are used in the functional path.
Q26 : Did you face clock as data violation anytime ? How did you debug it?
Ans : Yes, A clock that affects the data input of a register reduces the fault coverage.
By inserting test point you can avoid this violation.

Q27 : Do there is need of checking Stuck-at even after transition patterns are detected at each
node?
Ans : if you attain 100% coverage for transition faults then no need to do stuck-at or else you
have to check for stuckat fault also.

Q28 : Even though your scan insertion is perfect why scan chain tracing issues will come in
atpg?
Ans : After Scan insertion , the scan inserted netlist will go to P&R team for scan chain re-
ordering ,so due to this we get scan chain tracing issue

Q29 : What is occ ?

Ans : OCC is on chip clock, which is mainly used generate atspeed pulses to detect transition
faults.
Q30 : Explain Architecture of OCC ?

Ans :

Mode of Operations Test Opcg Shift

Enable(TE) enable enable(SE)
Functional Mode 0 X X

Scan shift mode 1 0 or 1 1

Capture mode(static capture) 1 0 0

Non – OPCG mode
Opcg mode / At speed mode 1 1 0

Q31 : Why shift register is used in occ structure ?

Ans : To generate specified number of at-speed pulses

Q32 : Why we perform simulations ?

Ans : To validate the Atpg test patterns

Q33 : Did you face any issues in simulation ?

Ans : yes ,In timing I have faced setup and hold issues.which is a binary mismatch
Debug : First check the design with no timing ,if its passing then send the setup violation
details to STA team for solution

Q34 : what is the complexity of your design?

Ans : 150k flops

Q35 : How many scan chains in your design?

Ans : flops 150k
External scan channels : 5
Compression : 50
Internal scan chains : 250
No. of flipflops in each scanchain : 600
Q36 : How many clock domains ?
Ans : 2

Q37 : Do the clocks are synchronous or asynchronous?

Ans : Synchronous

Q38 : Why opcg and explain it with wave forms how two pulses are generated?
Ans : OCC is on chip clock, which is mainly used generate atspeed pulses to detect
transition faults

Q39 : What is loc and los ?

Ans : Los : Launch happens in the last shift cycle of scan frequency and capture happens at
atspeed frequency.

Loc : Launch and capture both will happen at at-speed (capture).

Q40 : Which is advantage loc/los?

Ans : Based on the design and its complexity loc and los are considered

LOS LOC

Less Patterns More Patterns

Full Scan Design Partial Scan Design

1 atspeed pulse 2 atspeed pulse

Se signal controlling is difficult Se signal is easily controllable

It is necessary that the timing path should be same as the functional path. i.e., clocks should
be the same in both functional & at-speed test mode. Whatever methodology (Launch On
Shift / Launch On Capture) is required to meet this requirement should be implemented.
There are other critical factors that will also drive to LOS / LOC implementation.

1. Whether clocks are generated by internal PLLs.

2. Whether, tester can support multiple waveforms on the same clock pin.

3. How do you handle scan enable to switch between shift & capture modes.
Most of the designs that have internal clock generators implement LOC method for testing.

Below are differences between the LOC and LOS

a) For LOS the scan enable has to closed at functional frequency (which may result in gate
count increase with addition of large buffers), whereas in LOC the timing on scan enable can
relaxed between the last shift and launch cycle.

b) LOS atpg run time is less compared to the LOC for pattern generation.

c) Pattern count in LOS in less than the LOC.

d) Test/fault coverage for LOS is higher than the LOC.

I) Launch on last shift - In this method, during the last shift itself, we will shift in the required
value in to the flop which will create the required transition on the intended node.

Advantages: 1) Tool has the controllability to put the required value in to the flop to cause
transition.

2) We will get good coverage as we are launching the value through SD path.

Disadvantages: 1) Scan-enable need to change at-speed, we have to implement pipeline logic

in order to support this.

II) Launch on capture - In this method, the flop which creates the launch on the intended node
will get the value through D path. Scan-enable will be low during this time.

Advantages: 1) No need to add pipeline logic for Scan-enable.

Disadvantages: 1) We may loose some coverage as the value is launched through D path.

Its always better to go with LOS, The major advantage with LOS is increased coverage and
reduction in number of patterns. When the no of patterns decreases, the test time reduces,
which in turn reduces the cost for test time to a great extend.

Q41 : How will you do compression debug ?

Ans : In Tessent, if you find any violation(F8,F9,F10) when Compression(edt) is enabled for
the scan chains it is difficult to sort the exact location of issue, So EDT Finder is set to off
state and and we will run the file, then you will get T3,T5 etc issues which is easily
addressable by right click and go to schematic view

Q42 : What are clock choppers ?

Ans : Clock choppers is also called as occ and opcg.
Q43 : If you have more than two clocks how many OCC do we need?
Ans : One OCC is enough. (Refer : http://ijrect.com/issues/vol3issue3/ramkumar.pdf)

Q44 : Is there any possibility of using one occ if you have two clocks other than testclock
Ans : Yes, (Refer : http://ijrect.com/issues/vol3issue3/ramkumar.pdf)

Q45 : How to avoid X-Blocking in compression ?

Ans : We use X-Masking logic to avoid X propogation
 Wide 0
 Wide 1
 Wide 2

Q46 : What is Shadow logic ?

Ans : Shadow logic is the technique used to bypass the memories in the design and to
improve atpg coverage.

Q47 : Where do we mention PLL initialization procedures?

Ans : In SPF ,procedures and macro test procedures

Q48 : How clock choppers will be enabled ?

Ans : In scan insertion, you have a switch (True/False) to enable clock chopper in our design

Q49 : What are the signals that we define while we insert opcg ?
Ans : opcg enable,opcg load,opcg load clock.

Q50 : How do we generate more than 2 pulses in occ?

Ans : By controlling the inputs of and gates using shift register output.

Q51 : How you are giving the controlling information for the clock to toggle in atspeed
pulses if two or more clocks are present?
Ans : By defining load-unload,capture procedures in spf

Q52 : Which pin will you enable for static capture?

Ans : SE pin
Q53 : How do parallel and serial test benches differ ?
Ans : In serial test bench data is given at SI and observed at SO.
In parallel test bench, the data is forced at SI and observed at SO, so the flops i/o
configuration differs.

i.e Pin definition differ on basis of loading and unloading of data

Q54 : Do you know P1500 technology?

Ans: P1500 is an IEEE standard for testing embedded cores in a SOC.JTAG is used at PCB
level and P1500 wrapper is used at Core level.

Q55 : What do you have inside wrapper boundary register?

Ans: Wrapper boundary register will have wrapper boundary cells which will test the core.

Q56 : What is your role in project ?

Ans : scan insertion and scan drc’s,atpg pattern generation and analyzing coverage,simulation

Q57 : How many blocks in your Design and how many did you handle ?
Ans : In our Design we have 8 blocks and I have worked on 2blocks

Q58 : What was the flop count in your Design?

Ans : 150k flops

Q59 : How Many clocks ?

Ans : 2

Q60 : How many scan chains(external)?

Ans : 5

Q61 : Is compression there in your Design?

Ans : Yes, Compression is enabled in our Design.

Q62 : What is the compression ratio?

Ans : 50

Q63 : How many internal scan chains ?

Ans : 250

Q64 : Atpg flow?

Ans : ATPG has three modes in it’s operation.
First mode is BUILD mode, wherein it reads all the input files required for setting up the base
for ATPG.Here the inputs are ATPG Libraries, Scan inserted netlist and SPF file.
Second mode is DRC mode where it reads the SPF file generated in the DFT-Compiler and
checks for any Design rule violations in the design and generates the test patterns.
Third mode is Test mode wherein the tool will validate the generated test patterns.
The outputs in ATPG are Test-patterns, Test-benches.

Q65 : What was your coverage for stuck at and transition faults?
Ans : stuck at : 99 , transition : 91
Q66 : How many capture cycles initially?
Ans : 2

Q67 : what are the signals defined in scan?

Ans : SI , SO , SE , TM ,SCAN CLOCK.

Q68 :Why we need compression?

Ans : To reduce Test application time and test data volume

Q69 : Architecture of compression ?

Ans :

Q70 : What is difference between adaptive scan and lfsr ?

Ans : Adaptive scan is the technique used in synopsys Dft max which is combination of mux
and logic gates

Lfsr is the technique used in Mentor Graphics (EDT Architecture) which is designed with
flops and logic gates

Q71 : What is Lockup latch ?

Ans : Lockup latch is basically used to avoid loading and unloading issues by adding a half
cycle delay.It is inserted between two flops for which the clock is taken from first flop

Q72 : What happens if we have positive triggered flops followed by negative triggered flops?
Ans : In single cycle loading and unloading of data happens so to avoid this we use lockup
latch and provide half cycle delay so as to attain good capture of data

Q73 : if serial fails chain test also fails ,what is the reason?
Ans : chain consist of scan flops which are connected in series,so if serial fails chain test
fails.

Q74 : What is clock skew ?

Ans : Capture clock latency – launch clock latency

Q75 : what happens if we go on increasing compression?

Ans : if we increase compression ratio,no. of scan chains increases and coverage decreases

Q76 : Which is same as at-speed frequency, functional or shift frequency ?

Ans : functional frequency

Q77 : What are scan channels ?

Ans : External scan chains are called Scan channels
Q78 :what is contention violation ?
Ans when a signal input is driven by two or more nets it is called contention violation

Q79 : If you have 2 clocks with 55mhz, 1ghz ,which frequency will u use for shifting and
why?
Ans we use low frequency for shifting to avoid power desipation