Basic Elevator Design in VHDL

Basic Elevator Design in VHDL
https://forums.xilinx.com/t5/General-Technical-Discussion/Basic-Elevator-Design-in-VHDL/td-
p/205793
markbadong
Visitor
01-22-2012 06:45 PM - edited 01-22-2012 06:48 PM
31,926 Views
Registered: 01-07-2012
Basic Elevator Design in VHDL
Hi everybody! Taking another challenge problem. This time, a waveform

is given that we are expected to follow for an elevator that has the
following specifications:
1. 7 Floor buttons, from 0(Basement) to 7th floor
2. Two timers, one for the elevator's moving up or down, and the other as
a time delay before opening/closing the door.
3. When you press a floor button (for this code, for simplification, only
one floor at a time is supported) clock 2 counts from 3 to 0 before the
door closes and moves to the desired floor, which increments or
decrements with each clock signal from clock 1. After reaching the desired
floor, counter 2 counts from 3 to 0 again before the door opens.
Attached is the picture of the expected waveform we are supposed to get.
Here is my code so far. Still doesn't give me any values when I try it :(
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:54:43 01/18/12
-- Design Name:
-- Module Name: Elevator - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Elevator is
Port ( Ze : in std_logic;
One : in std_logic;
Tw : in std_logic;
Thr : in std_logic;
Fou : in std_logic;
Fiv : in std_logic;
Six : in std_logic;
Sev : in std_logic;
DoorOpen : out std_logic;
DoorClose : out std_logic;
Up : out std_logic;
Down : out std_logic;
Cnt1 : out std_logic_vector(3 downto 0);
Cnt2 : out std_logic_vector(3 downto 0);
Rst1, Rst2 : in std_logic;
Clk1 : in std_logic;
Clk2 : in std_logic);
end Elevator;
architecture Behavioral of Elevator is
signal count1, count2, df, cf: std_logic_vector(3 downto 0);
begin
process (clk2)
begin
if(rst2 = '1') then

count2 <= "0000";
cf <= "0001";
df <= "0001";
elsif ( ((df < cf) or (df > cf)) and(clk2'event and clk2 = '1')) then
count2 <= "0011";
if (count2 = "0011") then count2 <= "0010";

elsif (count2 = "0010") then count2 <= "0001";
end if;
end if;
end process;
process (clk1)
begin
if(rst1 = '1') then

count1 <= "0001";
elsif ((count2 = "0000") and (clk1'event and clk1 = '1')) then
cf <= count1;
IF (Ze = '1') then df <= "0000";
ELSIF (One = '1')then df <= "0001";
ELSIF (Tw = '1') then df <= "0010";
ELSIF (Thr = '1') then df <= "0011";
ELSIF (Fou = '1') then df <= "0100";
ELSIF (Fiv = '1') then df <= "0101";
ELSIF (Six = '1') then df <= "0110";
ELSIF (Sev = '1') then df <= "0111";
end if;
IF ((count1 = "0000") and (df > cf)) THEN

count1 <= "0001"; up <= '1'; down <= '0';
ELSIF ((count1 = "0001") and (df > cf)) THEN

count1 <= "0000"; up <= '1'; down <= '0';
ELSIF ((count1 = "0001") and (df < cf)) THEN
count1 <= "0010"; up <= '0'; down <= '1';

count1 <= "0001"; up <= '1'; down <= '0';
count1 <= "0011"; up <= '0'; down <= '1';

count1 <= "0010"; up <= '1'; down <= '0';
count1 <= "0100"; up <= '0'; down <= '1';

count1 <= "0011"; up <= '1'; down <= '0';
count1 <= "0101"; up <= '0'; down <= '1';

count1 <= "0100"; up <= '1'; down <= '0';
count1 <= "0111"; up <= '0'; down <= '1';

count1 <= "0110"; up <= '0'; down <= '1';
ELSE
count1 <= count1;
end if;
end if;
end process;
cnt1 <= count1;

cnt2 <= count2;
end Behavioral;
scampbell
Moderator
01-22-2012 08:33 PM
31,918 Views
Re: Basic Elevator Design in VHDL
Without solving it for you ...
Use a state machine instead of the netsted if/elsif structures. I would pick
each state to represent a floor. Send count enable signals from the state
machine to a process for the counter. I would also send a direction signal
to the counter from the state machine to indicate up or down motion.
Good luck , and hope this gets you on the right track ...
eteam00
Teacher
01-22-2012 08:46 PM
31,914 Views
It is much simpler to successfully complete this design if you start with a
state diagram. Do you have a state diagram you can post? This helps
organise and structure your implementation (the lines of code are the
implementation, not the design).
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-
Forum/README-first-Help-for-new-users/td-p/219369
markbadong
Visitor
01-22-2012 09:36 PM
31,908 Views
Thanks for the reply guys. I'll get started making the state machine
design a little later. In the meantime, could you tell me how I can
implement that counter 2 that only counts when a floor is registered, such
that it stays 0 until either a) a command to change floor is given, which
would count 3 clock edges before it closes the elevator door, or b) the
elevator reaches the desired floor, at which it will count 3 clock edges
before it opens the door.
That implementation got me quite confused. Any ideas how to implement
it? Pseudo code would help :)
eteam00
Teacher
01-22-2012 09:46 PM - edited 01-22-2012 09:52 PM
31,906 Views
Have you heard the term "top-down design"? You should look it up, and
you should try it.
You're a student, right? You're trying to learn the right way to design
things, right?
When you want to build a barn, do you start by learning how to hang a 2-
tube fluorescent light fixture?
OK, here's a mini-challenge:
Design and implement a counter 2 that only counts when a floor is

registered, such that it stays 0 until either a) a command to change floor
is given, which would count 3 clock edges before it closes the elevator
door, or b) the elevator reaches the desired floor, at which it will count 3
clock edges before it opens the door.
You can design it with pseudo code, or you can draw a state diagram, to
sort out what the counter does and how it works. Once you have
designed it, you can reduce your state diagram or pseudo code design to
actual lines of VHDL code. The diagram stage is called "design",
the writing VHDL code stage is called "implementation".
-- Bob Elkind
markbadong
Visitor
01-23-2012 11:10 PM
31,871 Views
I was able to make a state diagram but came upon this hurdle: How do I
use 2 different clocks in only one state machine? Like for the time delay
state, I will need to use clock 2...
eteam00
Teacher
01-23-2012 11:33 PM
31,868 Views

Suggest you use a counter for the delay. One clock should be sufficient.
 At the start of the delay, set the counter to 0, then count clock cycles until
the delay is complete.
 When the counter reaches NNNN, the delay is complete.
-- Bob Elkind
markbadong
Visitor
01-24-2012 12:51 AM
31,864 Views

Unfortunately, our professor requires that the waveform I showed you
earlier be the exact output he sees, or close enough - so that means I
need to use two clocks nevertheless :(
Here's the code I was able to make so far.
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:02:27 01/24/12
-- Design Name:
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--
--------------------------------------------------------------------------------
library IEEE;

--library UNISIM;
entity Elevator is
Port ( clk1 : in std_logic;
clk2 : in std_logic;
rst : in std_logic;
rst2 : in std_logic;
zero : in std_logic;
one : in std_logic;
two : in std_logic;
three : in std_logic;
four : in std_logic;
five : in std_logic;
six : in std_logic;
seven : in std_logic;
up : out std_logic;
down : out std_logic;
dooropen : out std_logic;
doorclose : out std_logic;
cnt1 : out std_logic_vector(3 downto 0);
cnt2 : out std_logic_vector(1 downto 0));
end Elevator;
type state_type is (s0,s1,s2,s3,s4);

signal current_s,next_s: state_type;
signal cf, df: std_logic_vector(3 downto 0);
signal count1: std_logic_vector(1 downto 0);
signal count2: std_logic_vector(1 downto 0);
begin
--The following processes clk2, which is the time delay clock used.
process (clk2,rst2)
begin
if (rst2='1') then
count2 <= "00";
elsif (clk2'event and clk2='1') then
if (count2 = "11") then count2 <= "10";

else count2 <= "00";
end if;
end if;
end process;
--The following processes clk1, which registers the cf(current floor) and
df(desired floor).
process (clk1,rst)
begin
if (rst='1') then
current_s <= s3;
df <= "0001";
cf <= "0001";
up <= '0';
down <= '0';
dooropen <= '1';
doorclose <= '0';
if (zero = '1') then df <= "0000";

elsif (one = '1') then df <= "0001";
elsif (two = '1') then df <= "0010";
elsif (three = '1') then df <= "0011";
elsif (four = '1') then df <= "0100";
elsif (five = '1') then df <= "0101";
elsif (six = '1') then df <= "0110";
elsif (seven = '1') then df <= "0111";
end if;
current_s <= next_s;

cnt1 <= cf;
end if;
end process;
process (current_s, cf, df, clk2)

begin
case current_s is
when s0 => --when current state is "s0"
if(cf < df) then
doorclose <= '1';
up <= '1';
next_s <= s0;
if (cf = "0000") then cf <= "0001";
elsif (cf = "0001") then cf <= "0010";
elsif (cf = "0010") then cf <= "0011";
elsif (cf = "0011") then cf <= "0100";
elsif (cf = "0100") then cf <= "0101";
elsif (cf = "0101") then cf <= "0110";
elsif (cf = "0110") then cf <= "0111";
else cf <= cf;
end if;
elsif(cf = df) then
up <= '0';
next_s <= s2;
count2 <= "11";
end if;

if(cf > df) then
doorclose <= '1';
down <= '1';
next_s <= s1;
if (cf = "0111") then cf <= "0110";
elsif (cf = "0001") then cf <= "0000";
elsif (cf = "0010") then cf <= "0001";
elsif (cf = "0011") then cf <= "0010";
elsif (cf = "0100") then cf <= "0011";
elsif (cf = "0101") then cf <= "0100";
elsif (cf = "0110") then cf <= "0101";
else cf <= cf;
end if;
elsif(cf = df) then
down <= '0';
next_s <= s2;
count2 <= "11";
end if;
when s2 =>
if((count2 = "11") or (count2 = "10") or (count2 = "11")) then
next_s <= s2;
elsif(count2 = "00") then
next_s <= s3;
end if;
when s3 =>
if(cf = df) then
dooropen <= '1';
doorclose <= '0';
next_s <= s3;
elsif ((cf<df) or (cf>df)) then
next_s <= s4;
end if;
when s4 =>
if((count2 = "11") or (count2 = "10") or (count2 = "11")) then
next_s <= s2;
elsif((count2 = "00") and (cf<df)) then
dooropen <= '0';
next_s <= s0;
elsif((count2 = "00") and (cf>df)) then
dooropen <= '0';
next_s <= s1;
end if;
end case;
end process;
cnt1 <= cf;
end Behavioral;
markbadong
Visitor
01-24-2012 12:59 AM
31,862 Views
Here's the output of that code :( I hope you can help me figure this out
by today, we're submitting this tomorrow >.< It’s got quite a significant
grade too if I can complete it, so I hope you can help me figure out what
I'm doing wrong. Synthesized and tested in Xilinx ISE 7.1i (Required,
because our school can't afford a later version just yet so this is what we
use)
eteam00
Teacher
01-24-2012 01:21 AM
31,853 Views

I can't promise that you will complete your assigment in time. That is
your job.
The counters cnt1 and cnt2 are not initialised. The simulator cannot
resolve 'U' + 1 to anything other than 'U'.
So here is your first help: initialise each of your registers with a value
(other than 'U').
-- Bob Elkind
markbadong
Visitor
01-24-2012 01:24 AM
11,944 Views

Could you teach me how to initialize? Our prof skipped a lot in our initial
lessons about VHDL, and didn't properly explain initializing values. Could
you at least give me the code for initializing those counters?
Also, instead of handing the solution to me on a silver platter, could you

try out the code for yourself and make it work - then just tell me how
much more I need to edit before I reach the solution, without giving away
the exact code (like, 'you're very close, just remember this - counter is
this and that, etc). This is so I can at least know if my code is close to
working or if I should scrap it and start anew so I won't waste time.
Thanks again!
rcingham
Teacher
01-24-2012 01:28 AM
11,941 Views
"Could you teach me how to initialize?"
signal count1: std_logic_vector(1 downto 0) := "00";

signal count2: std_logic_vector(1 downto 0) := "00";
You need to beg, borrow, or otherwise acquire a VHDL textbook. Or find a

college with a competent professor...
------------------------------------------
eteam00
Teacher
01-24-2012 01:34 AM - edited 01-24-2012 01:35 AM
11,938 Views
help #2
Here's help #2:
once count2 reaches '0', it will stay stuck there. There is no exit from the
'0' state for count2.
-- Bob Elkind
markbadong
Visitor
01-24-2012 01:38 AM
11,934 Views
Re: help #2
Do you mean this line of code from my program:
elsif(cf = df) then
up <= '0';
next_s <= s2;
------------------------------
count2 <= "11";
------------------------------
end if;
Will not affect count2 at all?
markbadong
Visitor
01-24-2012 01:41 AM
11,931 Views
Re: help #2
By the way, here's the synthesis log:
Started process "Synthesize".
==================================================
=======================
* HDL Compilation *
==================================================
=======================
Compiling vhdl file "C:/Documents and
Settings/XPMUser/Desktop/Badong_MT/Elevator.vhd" in Library work.
Entity <elevator> compiled.
Entity <elevator> (Architecture <behavioral>) compiled.
==================================================
=======================
* HDL Analysis *
==================================================
=======================
Analyzing Entity <elevator> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <up> in unit <elevator> never changes
during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <down> in unit <elevator> never changes
during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <dooropen> in unit <elevator> never
changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <doorclose> in unit <elevator> never
changes during circuit operation. The register is replaced by logic.
Entity <elevator> analyzed. Unit <elevator> generated.
==================================================
=======================
* HDL Synthesis *
==================================================
=======================
Synthesizing Unit <elevator>.

Related source file is "C:/Documents and
Settings/XPMUser/Desktop/Badong_MT/Elevator.vhd".
WARNING:Xst:1306 - Output <cnt2> is never assigned.
WARNING:Xst:1780 - Signal <count1> is never used or assigned.
INFO:Xst:1799 - State 10 is never reached in FSM <count2>.
Found finite state machine <FSM_0> for signal <count2>.
-----------------------------------------------------------------------
| States | 1 |
| Transitions | 1 |
| Inputs | 0 |
| Outputs | 1 |
| Clock | clk2 (rising_edge) |
| Reset | rst2 (positive) |
| Reset type | asynchronous |
| Reset State | 00 |
| Power Up State | 00 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
WARNING:Xst:737 - Found 4-bit latch for signal <cf>.
Using one-hot encoding for signal <current_s>.
WARNING:Xst:737 - Found 5-bit latch for signal <next_s>.
WARNING:Xst:737 - Found 1-bit latch for signal <dooropen>.
WARNING:Xst:737 - Found 1-bit latch for signal <down>.
WARNING:Xst:737 - Found 4-bit latch for signal <count2>.
WARNING:Xst:737 - Found 4-bit latch for signal <cf>.
WARNING:Xst:737 - Found 1-bit latch for signal <up>.
WARNING:Xst:737 - Found 1-bit latch for signal <doorclose>.
Found 4-bit register for signal <cnt1>.
Found 4-bit comparator less for signal <$n0050> created at line 117.
Found 4-bit comparator equal for signal <$n0051> created at line 128.
Found 4-bit comparator greater for signal <$n0052> created at line 137.
Found 4-bit comparator greatequal for signal <$n0061> created at line 117.
Found 4-bit comparator not equal for signal <$n0062> created at line 128.
Found 4-bit comparator lessequal for signal <$n0063> created at line 137.
Found 5-bit register for signal <current_s>.
Found 4-bit register for signal <df>.
Summary:
inferred 1 Finite State Machine(s).
inferred 4 D-type flip-flop(s).
inferred 6 Comparator(s).
Unit <elevator> synthesized.
==================================================
=======================
* Advanced HDL Synthesis *
==================================================
=======================
Advanced RAM inference ...

Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
==================================================
=======================
HDL Synthesis Report
Macro Statistics
# FSMs : 1
# Registers : 3
4-bit register : 2
5-bit register : 1
# Latches : 7
1-bit latch : 4
4-bit latch : 2
5-bit latch : 1
# Comparators : 6
4-bit comparator equal : 1
4-bit comparator greatequal : 1
4-bit comparator greater : 1
4-bit comparator less : 1
4-bit comparator lessequal : 1
4-bit comparator not equal : 1
==================================================
=======================
==================================================
=======================
* Low Level Synthesis *
==================================================
=======================
WARNING:Xst:1710 - FF/Latch <cnt1_3> (without init value) has a constant
value of 0 in block <elevator>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cnt1_0>
(without init value) has a constant value of 0 in block <elevator>.
WARNING:Xst:1988 - Unit <elevator>: instances <Mcompar__n0063>,
<Mcompar__n0052> of unit <LPM_COMPARE_6> and unit <LPM_COMPARE_3>
are dual, second instance is removed
ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <dooropen>

Sources are:
Output signal of LD instance <dooropen/0>
Signal <dooropen> in Unit <elevator> is assigned to VCC
ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <doorclose>

Sources are:
Output signal of LD instance <doorclose/0>
Signal <doorclose> in Unit <elevator> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <up>

Sources are:
Output signal of LD instance <up/0>
Signal <up> in Unit <elevator> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <down>

Sources are:
Output signal of LD instance <down/0>
Signal <down> in Unit <elevator> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <cnt1<3>>

Sources are:
Output signal of LD instance <cf/3/0>
Output signal of LD instance <cf_ren/3/0>
Signal <N1> in Unit <elevator> is assigned to GND
CPU : 1.17 / 1.35 s | Elapsed : 1.00 / 1.00 s
-->
Total memory usage is 78064 kilobytes
Number of errors : 0 ( 0 filtered)

Number of warnings : 17 ( 0 filtered)
Number of infos : 7 ( 0 filtered)
ERROR: XST failed

Process "Synthesize" did not complete.
eteam00
Teacher
01-24-2012 01:47 AM
11,926 Views
help #3
Do you mean this line of code from my program:
elsif(cf = df) then

up <= '0';
next_s <= s2;
------------------------------
count2 <= "11";
------------------------------
end if;
Will not affect count2 at all?
Here's help #3:
You can assign a value to a register in one process -- and ONLY one
process.
You have a process for count2 register. If you want to control a register
assigned in process PROCESS_A from another process PROCESS_B, you
will need to send a control signal from the PROCESS_B to PROCESS_A,
and add logic to PROCESS_A to act upon the control signal from
PROCESS_B.
-- Bob Elkind
eteam00
Teacher
01-24-2012 01:54 AM
11,923 Views
help #4
Here's help #4:
Either use variable and signal names which have obvious meaning
(example: elevator_up_command_output)
OR
Sprinkle lots of comments through your code which explain what your
lines of code (especially in state machines) are doing (example: s1 state
checks the elevator stopped signal and opens the elevator door)
OR
do both. Useful and recognisable names AND useful comments.
-- Bob Elkind
eteam00
Teacher
01-24-2012 02:01 AM - edited 01-24-2012 02:03 AM
11,921 Views
help #5
here's help #5...
this is a clocked process

begin
case current_s is
if(cf < df) then
doorclose <= '1';
up <= '1';
next_s <= s0;
if (cf = "0000") then cf <= "0001";
elsif (cf = "0001") then cf <= "0010";
elsif (cf = "0010") then cf <= "0011";
elsif (cf = "0011") then cf <= "0100";
elsif (cf = "0100") then cf <= "0101";
elsif (cf = "0101") then cf <= "0110";
elsif (cf = "0110") then cf <= "0111";
else cf <= cf;
end if;
elsif(cf = df) then
up <= '0';
next_s <= s2;
count2 <= "11";
end if;
...
process continues for several states...
You can tell it is a clocked process because a variable is being changed

based on its present value. This is not possible with combinatorial logic,
so it must be clocked logic. Agreed?
help #5a
the only signals which belong in the sensitivity list of a clocked process
are: the clock and the asynchronous set/reset (if the process has an
async set/reset).
help #5b
the if clk'event clause for the clocked process pasted above is missing.
Correcting this should get rid of some of the 'latched signals' warnings.
-- Bob Elkind
eteam00
Teacher
01-24-2012 02:20 AM
11,917 Views
when you have updated your code and simulation...

when you have updated your code and simulation... suggest you post
your updated code and simulation.
-- Bob Elkind
eteam00
Teacher
01-24-2012 02:33 AM
11,912 Views
help #6
here is help #6:
In the process mentioned in help #5 --

begin
case current_s is
if(cf < df) then
doorclose <= '1';
up <= '1';
next_s <= s0;
if (cf = "0000") then cf <= "0001";
elsif (cf = "0001") then cf <= "0010";
elsif (cf = "0010") then cf <= "0011";
elsif (cf = "0011") then cf <= "0100";
elsif (cf = "0100") then cf <= "0101";
elsif (cf = "0101") then cf <= "0110";
elsif (cf = "0110") then cf <= "0111";
else cf <= cf;
end if;
elsif(cf = df) then
up <= '0';
next_s <= s2;
count2 <= "11";
end if;
...
process continues for several states...
This process in an incomplete clocked process, as mentioned in help

#5. Once you correct this process, you should replace all "next_s"
assignments in this process with "current_s" assignments. This is one
step further toward converting your two-process state machine to a
single-process state machine. This will help remove the confusion
between clocked and combinatorial processes.
Then you must also remove the current_s assignments in the preceding
process (pasted below), because current_s can be assigned values in
only one process.
process (clk1,rst)
begin
if (rst='1') then
current_s <= s3;

df <= "0001";
cf <= "0001";
up <= '0';
down <= '0';
dooropen <= '1';
doorclose <= '0';
if (zero = '1') then df <= "0000";

elsif (one = '1') then df <= "0001";
elsif (two = '1') then df <= "0010";
elsif (six = '1') then df <= "0110";
end if;
current_s <= next_s;

cnt1 <= cf;
end if;
end process;
-- Bob Elkind
markbadong
Visitor
01-24-2012 06:05 AM
12,774 Views
Re: help #6
Thanks for all the info - but this just became too much for me to absorb,
I'm getting bombarded with terms I'm not that familiar with yet - seems I
can't use a state machine right now because I lack the proper knowledge
to implement it....
Should I redo my code without state machines?
rcingham
Teacher
01-24-2012 06:19 AM
12,773 Views
Re: help #6
"Should I redo my code without state machines?"
No.
Control systems such as this are canonical examples of state machine
implementation.
Are the other students on your course having similar problems?
------------------------------------------
eteam00
Teacher
01-24-2012 06:30 AM
12,771 Views
Re: help #6
"Should I redo my code without state machines?"
No.
Control systems such as this are canonical examples of state machine
implementation.
Agreed, 100%. The whole point of the assignment is to confirm (to you
and to your instructor) that the lesson has indeed been learned and the
class is ready to hear the next lesson. If the assignment is a washout,
this is essential information directing the instructor to spend some more
time on this lesson before teaching the next lesson.
-- Bob Elkind
markbadong
Visitor
01-24-2012 06:39 AM
12,769 Views
Re: help #6
I really want to grasp the state machines, but I fear I may be too late for
this one, because our submission is tomorrow and I'm not sure if I can
understand the code in time for tomorrow's submission. That's why I'm
currently confused between deciding to redo the code and risk a fresh
start or keep studying but risk wasting time going nowhere with all the
warnings I have to correct. I can't fully grasp the difference of
combinatorial with clocked or stuff like that :(
I guess C++ has spoiled me..
rcingham
Teacher
01-24-2012 06:46 AM
12,766 Views
Re: help #6
"I guess C++ has spoiled me."
Digital hardware design and object-oriented software programming are 2

completely different paradigms. You need to (temporarily) forget the latter while
learning the former.
------------------------------------------
eteam00
Teacher
01-24-2012 06:51 AM
12,765 Views
instructor time
If you are feeling lost in the dark forest, it's time to seek help and
guidance from your instructor. He gets paid to teach you, not just hand
out assignments. Give him a chance to do his job.
-- Bob Elkind
bassman59
Historian
01-24-2012 08:11 AM
12,757 Views

@markbadong wrote:
Could you teach me how to initialize? Our prof skipped a lot in our initial
lessons about VHDL, and didn't properly explain initializing values. Could
you at least give me the code for initializing those counters?
It's called a reset, and is fundamental to digital design. Without resets,

you have no guarantee that your real hardware will function properly.
There's a boatload of information here and elsewhere on the Interwebs
about resets.
----------------------------Yes, I do this for a living.
markbadong
Visitor
01-24-2012 09:53 AM
12,749 Views

I reworked my code to exclude state diagrams for now and got this.
Only the tIme delay for the first going up to the 5th floor works, however,
I haven't been able to implement door close and open just yet, but there's
no more time so here goes nothing:
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:02:27 01/24/12
-- Design Name:
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--
--------------------------------------------------------------------------------
library IEEE;

--library UNISIM;
entity Elevator is
Port ( clk1 : in std_logic;
clk2 : in std_logic;
rst : in std_logic;
rst2 : in std_logic;
zero : in std_logic;
one : in std_logic;
two : in std_logic;
three : in std_logic;
four : in std_logic;
five : in std_logic;
six : in std_logic;
seven : in std_logic;
up1 : out std_logic;
down1 : out std_logic;
dooropen : out std_logic:='0';
doorclose : out std_logic:='0';
upordown: out std_logic_vector(1 downto 0);
desired: out std_logic_vector(2 downto 0));
end Elevator;
--type state_type is (s0,s1,s2,s3,s4);

--signal current_s,next_s: state_type;
signal cf, df: std_logic_vector(2 downto 0):="001";
signal count2, updown: std_logic_vector(1 downto 0):="00";
signal readytogo: std_logic;
signal gon: std_logic:='0';
begin
process (clk2,rst2)
begin
if (rst2='1') then
count2 <= "00";
if (count2 = "11") then count2 <= "10"; gon <= '1';

elsif (count2 = "00") then
if (gon = '0') then
if (cf=df) then
count2 <= "00";
elsif (clk1='1') then
count2 <= "11";
end if;
elsif (gon = '1') then
if (cf=df) then
count2 <= "00";
else readytogo <= '1';
end if;
end if;
end if;
end if;
end process;
process(df,cf,readytogo)
begin
if (readytogo = '1') then
if (df < cf) then
updown <= "10";
elsif (df > cf) then
updown <= "01";
elsif (df = cf) then
updown <= "00";
else updown <= "11";
end if;
else updown <= updown;
end if;
end process;
process (clk1,rst)
begin
if (rst='1') then
cf <= "001";
dooropen <= '1';
doorclose <= '0';
if (zero = '1') then df <= "000";
elsif (one = '1') then df <= "001";
elsif (two = '1') then df <= "010";
elsif (six = '1') then df <= "110";
end if;
if (updown = "01") then

if (cf = "000") then cf <= "001";
elsif (cf = "001") then cf <= "010";
elsif (cf = "010") then cf <= "011";
elsif (cf = "011") then cf <= "100";
elsif (cf = "100") then cf <= "101";
elsif (cf = "101") then cf <= "110";
elsif (cf = "110") then cf <= "111";
else cf <= cf;
end if;
elsif (updown = "10") then
if (cf = "111") then cf <= "110";
elsif (cf = "001") then cf <= "000";
elsif (cf = "010") then cf <= "001";
elsif (cf = "011") then cf <= "010";
elsif (cf = "100") then cf <= "011";
elsif (cf = "101") then cf <= "100";
elsif (cf = "110") then cf <= "101";
else cf <= cf;
end if;
elsif (updown = "00") then
--readytogo <= '0';
cf <= cf;
else cf <= cf;
end if;
end if;
end process;
cnt1 <= cf;
cnt2 <= count2;
up1 <= updown(0);
down1 <= updown(1);
--doorclose <= updown(0) and updown(1);
--dooropen <= not (updown(0) and updown(1));
desired <= df;
upordown <= updown;
end Behavioral;
markbadong
Visitor
01-24-2012 09:55 AM
12,748 Views

Hey guys, I was wondering if you could give me the ideal solution for this
problem just this once? If you want, I'll just go ahead and submit this
code of mine as is just so I can have some closure. Unfortunately, our
teacher doesn't explain the solution until next week and I would really
love to see just how this really works. If it's OK with you guys.
If not, then it's OK, thanks so much for all the help. I don't have much
time left before we have to submit anyways, but I really wish I could see
how you guys would solve this once and for all. :) Thanks!
eteam00
Teacher
01-24-2012 05:15 PM - edited 01-24-2012 06:36 PM
12,743 Views

but I really wish I could see how you guys would solve this once and for
all.
You're missing the point. The only reason we're involved in your
assignment is to help you learn. Solving the challenge problem is nothing
more than a means to an end. A working solution to the assigned
problem is entirely inconsequential if you do not understand how to arrive
at a solution on your own.
Keep yourself focused on the important objective.
-- Bob Elkind
mcgett
Xilinx Employee
01-24-2012 06:41 PM
11,927 Views

I think that it is great that you want to understand the solution to the
problem, but before going down that path is this:
1. 7 Floor buttons, from 0(Basement) to 7th floor
2. Two timers, one for the elevator's moving up or down, and the other as
a time delay before opening/closing the door.
one floor at a time is supported) clock 2 counts from 3 to 0 before the
door closes and moves to the desired floor, which increments or
decrements with each clock signal from clock 1. After reaching the desired
floor, counter 2 counts from 3 to 0 again before the door opens.
the entire text of the problem that your professor gave you? If so, this is
an incomplete (and confusing) problem description and with just this
information it would not be possible to create the waveform that you were
also given.
If you were just paraphrasing the original problem statement, please post
the full problem that you were given.
------Have you tried typing your question into Google? If not you should before
posting.
Too many results? Try adding site:www.xilinx.com
markbadong
Visitor
01-24-2012 08:23 PM
11,922 Views

Well basically I just defined how I understood what our teacher said. But
there is no problem text - our professor simply gave us this waveform,
explained what it meant (those 3 things you said there) and that's pretty
much it. Our objective is to output that waveform by any means of code
possible. He told us that all we need is to show such a waveform (with
credible evidence that it would work with other floors too, not just 5th and
2nd) and we will get a perfect score.
eteam00
Teacher
01-24-2012 08:41 PM - edited 01-24-2012 08:42 PM
11,920 Views
state machines are your friends

I really want to grasp the state machines
So do we. And you will. State machines are an efficient means of

designing and debugging datapath controls and system controls. And
HDL (i.e. {VHDL | Verilog} ) is a much more efficient design entry
method for state machines than schematics.
An alternative to state machines is an assortment of small counters or

state units which control each other through control signals and
semaphores. Because the control structure is so decentralised and
diffused, managing (understanding, debugging, modifying) the controls is
tedious and error-prone.
Stick with state machines, grab a hold of this design method sooner
rather than later. It will make you more efficient in your work and your
learning, and you will also probably live longer and happier.
-- Bob Elkind
rcingham
Teacher
01-25-2012 01:34 AM
11,906 Views

"I was wondering if you could give me the ideal solution for this problem just
this once?"
I doubt that you can afford my consultancy rate.
------------------------------------------
bassman59
Historian
01-25-2012 09:26 AM
11,899 Views

@mcgett wrote:
one floor at a time is supported)
Oh, what fun is that? If America wants to be great again, our

undergraduate EE students need to learn how to design elevators that can
land on all floors simultaneously! Or else the British the Germans the
Russians the Japanese the Chinese the terrorists have won!
----------------------------Yes, I do this for a living.
mcgett
Xilinx Employee
01-26-2012 01:15 PM
11,890 Views
> But there is no problem text - our professor simply gave us this
waveform,
I really don't like your professor as they are not giving you enough
information to succeed at learning. The two clocks in the design is a
useless design construct that just makes it harder to implement with no
benefit to the education process.
I've looked at the waveform and constructed the following problem

description that should give you a better chance of implementing this
design.
Inputs
 Clk1
o Clock with 300nS period and 50/50 duty cycle
o Rising edge aligned with Clk2
 Clk2
Clock with 150nS period and 50/50 duty cycle
o
 Ze, One, Tw, Thr, Fou, Fiv, Six, Sev
o Indicates which floor the elevator should move to
o Synchronous to Clk1, Initialized to 0
o Asserted high 10nS before the Clk1 rising edge for one clock
period
Outputs
 Up
o Indicates that the elevator is moving up
o Asserted high after a button is de-asserted and at the same
time as DoorClose is asserted if the destination floor is greater
than the current floor (Cnt1)
o Asserted low after Cnt1 is equal to the button that was
pushed
 Down
o Indicates that the elevator is moving down
o Asserted high after a button is de-asserted event and at the
same time as DoorClose is asserted if the destination floor is
lower than the current floor (Cnt1)
pushed
 DoorClose
o Indicates that the elevator door is closed
o Asserted high after a button push event and after Cnt2 has
reached 0
pushed and Cnt2 has reached 0
 DoorOpen
o Indicates that the elevator door is open
o Inverted version of DoorClose
Internal Registers
 Cnt1[3:0]
o Indicates the current floor that the elevator is on
o Range of 0 to 7
o Incremented by 1 for every cycle that Up is asserted
o Decremented by 1 for every cycle that Down is asserted
 Cnt2[3:0]
o General purpose loadable down counter
o Range of 3 to 0
o Loaded to a value of 3 after a button is de-asserted or after
Up is de-asserted or Down is de-asserted
o Decrements each cycle until value is 0
------Have you tried typing your question into Google? If not you should
before posting.
eteam00
Teacher
01-26-2012 10:11 PM - edited 01-26-2012 10:13 PM

11,884 Views

The two clocks in the design is a useless design construct that just makes
it harder to implement with no benefit to the education process.
Agreed, the second clock is useless for any purpose other than indulging
the professor.
On the other hand, perhaps this instructor is one who enjoys planting
seeds of constructive challenges from the students. Perhaps there are
extra-credit points to be gained by providing a well-supported conclusion
that the second clock is superfluous and it should be ignored. This
happens frequently in the movies, and one of my high-school teachers
delighted in such challenges.
I really don't like your professor...
I interpret this to mean: I really don't like your professor's assignment...
Having said that, it seems that complaints and reports and evidence of
dysfunctional, lazy, disinterested, or uninformed instructors are a
(seemingly) daily occurrence in these forums.
One of the newer trends in education is to bypass locally available under-

achieving instructors by providing instruction over the web by the elite of
effective instructors. I have no doubts that interactive web-based courses
on FPGA design and HDL design, led by decent instructors, would be
almost instantly popular and profitable (for both instructor and
students). Much of this material is covered by the Xilinx video tutorials,
missing only the interactive component and the sustaining business model
(i.e. profit incentive for continuing the venture).
Here is my cynical side coming to the surface...
The lawyers and accountants who wrote the nation's arcane and self-
conflicted tax codes and regulations are the same people who profit from
providing tax-preparation services and provding legal representation in
tax court lawsuits. Anyone see a conflict of interest there?
No doubt the official keepers of the VHDL language have similarly built an
intricate web of complexity into the VHDL language, thereby multiplying
the need (and demand) for high-priced VHDL instruction seminars. The
more complicated, obtuse, and intolerant the language becomes, the
greater the business prospects for commercial instruction.
Note: No-one has ever considered paying me for either VHDL instruction
or insightful analysis of the EDA industry -- and perhaps now you know
why! And yes, I use Verilog rather than VHDL in my own design work, so
I am very much commenting on VHDL out of self-gratifying ignorance.
Ed, have you considered collaborating with Austin and a few others on the
possibility of such an entrepreneurial venture (interactive web-based
subscription EDA instruction), after retiring from Xilinx?
-- Bob Elkind
mcgett
Xilinx Employee
01-27-2012 08:59 AM
11,877 Views

> I interpret this to mean: I really don't like your professor's
assignment...
You are right, I have nothing against the professor especially since I
never met the person.
If this is an accurate representation of the professor's teaching methods

(waveform only with a verbal description) then I think it is extremely
lacking for entry level course on HDL design and hinders to
student''s ability to learn and succeed in this subject. Since the students
are also constrained to using an antiquated version of ISE 7.1i (2005) my
assumption is that this course has been around for 5-6 years which
should have been ample time to refine the problem assignment.
IMHO, problem assignments should be a way for a student to better

understand and practice the concepts that were taught in
class and should not be a guessing game. As a course progresses
from basic concepts to advanced concepts there would be less details
given to require more critical thinking of the student to complete the
project.
If the professor plans on using a common testbench to validate the

student's work then the interface must be detailed, while the internals
would have varying degrees of details depending on the course
progession. In this case there, were details that two explicit counters
were required suggesting that this is an early problem assignment
assignment. Later in the course I would expect that this would not be
described and left for the student to determine.
I am also a bit surprised that the professor is holding on to using this

older ISE version instead of using a more modern and free ISE WebPack
version such as 12.4 or 13.4.
------Have you tried typing your question into Google? If not you should before
posting.
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Basic Elevator Design in VHDL

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Basic Elevator Design in VHDL

Hi everybody! Taking another challenge problem. This time, a waveform

1. 7 Floor buttons, from 0(Basement) to 7th floor

Attached is the picture of the expected waveform we are supposed to get.

---- Uncomment the following library declaration if instantiating

signal count1, count2, df, cf: std_logic_vector(3 downto 0);

if(rst2 = '1') then

count2 <= "0011";

if (count2 = "0011") then count2 <= "0010";

if(rst1 = '1') then

elsif ((count2 = "0000") and (clk1'event and clk1 = '1')) then

IF ((count1 = "0000") and (df > cf)) THEN

ELSIF ((count1 = "0001") and (df > cf)) THEN

ELSIF ((count1 = "0010") and (df > cf)) THEN

ELSIF ((count1 = "0011") and (df > cf)) THEN

ELSIF ((count1 = "0100") and (df > cf)) THEN

ELSIF ((count1 = "0101") and (df > cf)) THEN

ELSIF ((count1 = "0111") and (df < cf)) THEN

cnt1 <= count1;

OK, here's a mini-challenge:

Design and implement a counter 2 that only counts when a floor is

Re: Basic Elevator Design in VHDL

Re: Basic Elevator Design in VHDL

Here's the code I was able to make so far.

---- Uncomment the following library declaration if instantiating

architecture Behavioral of Elevator is

type state_type is (s0,s1,s2,s3,s4);

elsif (clk2'event and clk2='1') then

if (count2 = "11") then count2 <= "10";

elsif (clk1'event and clk1='1') then

if (zero = '1') then df <= "0000";

current_s <= next_s;

process (current_s, cf, df, clk2)

when s1 => --when current state is "s0"

cnt1 <= cf;

Re: Basic Elevator Design in VHDL

Re: Basic Elevator Design in VHDL

Also, instead of handing the solution to me on a silver platter, could you

signal count1: std_logic_vector(1 downto 0) := "00";

You need to beg, borrow, or otherwise acquire a VHDL textbook. Or find a

01-24-2012 01:34 AM - edited 01-24-2012 01:35 AM

Will not affect count2 at all?

Started process "Synthesize".

Synthesizing Unit <elevator>.

Advanced RAM inference ...

ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <dooropen>

ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <doorclose>

ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <up>

ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <down>

ERROR:Xst:528 - Multi-source in Unit <elevator> on signal <cnt1<3>>

Total memory usage is 78064 kilobytes

Number of errors : 0 ( 0 filtered)

ERROR: XST failed

elsif(cf = df) then

Will not affect count2 at all?

Here's help #3:

do both. Useful and recognisable names AND useful comments.

01-24-2012 02:01 AM - edited 01-24-2012 02:03 AM

this is a clocked process

process (current_s, cf, df, clk2)

You can tell it is a clocked process because a variable is being changed

when you have updated your code and simulation...

In the process mentioned in help #5 --

process (current_s, cf, df, clk2)