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OP AMPS
What is an Op Amp?
The op amp (operational amplifier) is a high gain, dc coupled amplifier designed to
be used with negative feedback to precisely define a closed loop transfer function.
The basic requirements for an op amp:
• Sufficiently large gain (the accuracy of the signal processing determines this)
• Differential inputs
• Frequency characteristics that permit stable operation when negative feedback is
applied
Other requirements:
• High input impedance
• Low output impedance
• High speed/frequency
Why Op Amps?
The op amp is designed to be used with single-loop, negative feedback to accomplish
precision signal processing as illustrated below.
Single-Loop Negative Feedback Network Op Amp Implementation of a Single-Loop
Negative Feedback Network
Feedback Network
Vf(s) Vf(s)
F(s) F(s)
- Vout(s) Vout(s)
Vin(s) + -
S A(s) Vin(s)
+
Av(s)
Op Amp 060625-01
Vout(s)
The voltage gain, V (s) , can be shown to be equal to,
in
Vout(s) Av(s)
Vin(s) = 1+Av(s)F(s)
If the product of Av(s)F(s) is much greater than 1, then the voltage gain becomes,
Vout(s) 1
The precision of the voltage gain is defined by F(s).
Vin(s) ≈ F(s)
OP AMP CHARACTERIZATION
Linear and Static Characterization of the CMOS Op Amp
A model for a nonideal op amp that includes some of the linear, static nonidealities:
where
Rid = differential input resistance
Cid = differential input capacitance
Ricm = common mode input resistance
Ricm = common mode input capacitance
VOS = input-offset voltage
CMRR = common-mode rejection ratio (when v1=v2 an output results)
en2 = voltage-noise spectral density (mean-square volts/Hertz)
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-5
OP AMP CATEGORIZATION
Classification of CMOS Op Amps
Conversion Hierarchy
Current
Voltage Transconductance Transconductance Stage
to Current Grounded Gate Grounded Source
Second
Voltage
Current Class A (Source Class B Stage
to Voltage or Sink Load) (Push-Pull)
Table 110-01
COMPENSATION OF OP AMPS
Compensation
Objective
Objective of compensation is to achieve stable operation when negative feedback is
applied around the op amp.
Types of Compensation
1. Miller - Use of a capacitor feeding back around a high-gain, inverting stage.
• Miller capacitor only
• Miller capacitor with an unity-gain buffer to block the forward path through the
compensation capacitor. Can eliminate the RHP zero.
• Miller with a nulling resistor. Similar to Miller but with an added series resistance
to gain control over the RHP zero.
2. Self compensating - Load capacitor compensates the op amp (later).
3. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can
be less than unity.
Because compensation plays such a strong role in design, it is considered before design.
-20dB/decade
A measure of stability is given by the phase when |A(j)F(j)| = 1. This phase is called
phase margin.
Phase margin = M = Arg[-A(j0dB)F(j0dB)] = Arg[L(j0dB)]
A “good” step response is one that quickly reaches its final value.
Therefore, we see that phase margin should be at least 45° and preferably 60° or larger.
(A rule of thumb for satisfactory stability is that there should be less than three rings.)
Note that good stability is not necessarily the quickest rise time.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-14
M3 M4 Q3 Q4
M6 Q6
vout vout
- M1 M2 - Q1 Q2
vin vin
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE Fig. 120-04
Small-Signal Model:
Note that this model neglects the base-collector and gate-drain capacitances for purposes
of simplification.
|A(jw)|
GB
0dB log10(w)
Phase Shift -40dB/decade
-45/decade
180°
Arg[-A(jw)]
135°
-45/decade
90°
45°
0° log10(w)
|p1'| |p2'| w0dB 150128-02
If we assume that F(s) = 1 (this is the worst case for stability considerations), then the
above plot is the same as the loop gain.
Note that the phase margin is much less than 45° (≈ 6°).
Therefore, the op amp must be compensated before using it in a closed-loop
configuration.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-17
MILLER COMPENSATION
Miller Compensation of the Two-Stage Op Amp
VDD VCC
M3 M4
Q3 Q4
CM M6 CM Q6
Cc vout Cc vout
M1 M2 Q1 Q2
- -
vin CI CII vin CI CII
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE Fig. 120-08
Cc
v2
+ +
vin gm1vin CI CII vout
rds2||rds4 gm6v2 rds6||rds7
- -
Fig. 120-09
Same circuit holds for the BJT op amp with different component relationships.
-1 -1 gmII
p1 = R (C +C )+R (C +C )+g R R C ≈ g R R C , z= C
I I II II II c mII 1 II c mII 1 II c c
Avd(0) dB Uncompensated
|A(jw)F(jw)| -20dB/decade
F(jw)=1
Compensated
GB
0dB log10(w)
Phase Shift -40dB/decade
Uncompensated
180°
Arg[-A(jw)F(jw)|
-45°/decade
135°
F(jw)=1
90° -45°/decade
Compensated Phase
45°
No phase margin Margin
0° log10(w)
|p1| |p1'| |p2'| |p2|
150128-04
1
|p1| ≈ R (g R C )
I m6 II c
gm6
|p2| ≈ C
II
3.) Right-half plane zero (One source of zeros is from multiple paths from the input to
output): VDD
gm6 RII
-RIIsC - 1 Cc
-gm6RII(1/sCc) RII c vout
vout = R + 1/sC v’ + R + 1/sC v’’ = R + 1/sC v
II c II c II c v''
M6
v'
where v = v’ = v’’. Fig. 120-15
Further Comments on p2
The previous observations on p2 can be proved as follows:
Find the resistance RCc seen by the compensation capacitor, Cc.
Cc VDD
vx
RCc RII
RCc
ix ix
M6 +
RI RI vgs6 RII
- gm6vgs6
060626-02
Thus, at the frequency where CII begins to short the output, Cc is acting as a short.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-24
Cc
A
+ +
Vi gmIIVi CII RII Vout
s + gmII/ACc
- -
Vout(s) ACc Fig.430-09
Self-Compensated Op Amps
Self compensation occurs when the load capacitor is the compensation capacitor (can
never be unstable for resistive feedback)
Voltage gain:
vout
vin = Av(0) = GmRout
Dominant pole: Stability:
-1 Large load capacitors simply reduce
p1 = R GB but the phase is still 90° at GB.
outCL
Unity-gainbandwidth:
Gm
GB = Av(0)·|p1| = C
L
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-29
C2 C2
-A -A
R1 C1 R1 C1 C3(1+A)
RootID01
C2 C2
+A +A
R1 C1 R1 C1 C3(1-A)
RootID02
p1 +1 Cc
RII
vout
2.) Zeros are also created by two paths from the input to the M6
output and one or more of the paths is frequency dependent. v''
v'
3.) Zeros also come from simple RC networks. 070425-01
C1
+ + Vout s + 1/(R1C1)
Vin R1 R2 Vout =
Vin s + 1/(R1||R2)C1
- -
070425-02
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-31
I5 I6-I5-I7 I5 I5 I7-I5 I5
SR = minC , C = C because I6>>I5
+ SR = minC , C = C if I7>>I5.
-
c L c c L c
Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew
rate of the two-stage op amp should be, I5/Cc.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-32
SUMMARY
• Op amps achieve accuracy by using negative feedback
• Compensation is required to insure that the feedback loop is stable
• The degree of stability is measured by phase margin and is necessary to achieve small
settling times
• A compensated op amp will have one dominant pole and all other poles will be greater
than GB
• A two-stage op amp requires some form of Miller compensation
• A high output resistance op amp is compensated by the load capacitor
• Poles of a CMOS circuit are generally equal to the negative reciprocal of the product of
the resistance to ground from a node times the sum of the capacitances connected to
that node.
• The slew rate of the two-stage op amp is equal to the input differential stage current
sink/source divided by the Miller capacitor