PLD4016FT Service Manual PDF

SERVICE MANUAL
6M83B-24E391
Content:
1. 6M83B SPECIFICATION
2. LIST OF KEY PARTS
3. IC SPECIFICATION
4. BLOCK DIAGRAM
5. CIRCUIT DIAGRAM
6. MAIN PCB DRAWING
7. INSTRUCTION MANUAL

1 Outlook
Please refer to the picture

2 Brief Information
2.1 Product Name 24E391
2.2 Chassis Name 6M83B
2.3 Solution MSD6308RTC
2.4 Key functions ISDB-T/PAL M,N
2.5 Target Market Argentina
2.6 Product Category
2.7 Product Positioning LOW END DTV
2.8 Product size \
3 Panel Specification
3.1 Model Number Model Number
3.1.1 Panel Manufacturer SKYWORTH
3.1.2 Model Number SEL240HY(QD0-210)
3.2 Mechanical Mechanical
3.2.1 Panel Size 24"
3.2.2 Dimension TBD
3.2.3 Visible Area (mm) : H x V TBD
3.2.4 Pixel Format (H × V) TBD
3.2.5 Backlight Type LED
3.2.6 Diagonal Screen Size \
3.2.7 Pixel Pitch (mm) TBD
3.3 Electronic Parameter Electronic Parameter
3.3.1 Power consuption \
2
3.3.2 Brightness (cd/m ) \
3.3.3 Contrast Ratio \
3.3.4 Dynamic Contrast Ratio \
3.3.5 Veiwing Angle \
3.3.6 Response Time (ms) \
3.3.7 Back light Time (Hours) \
3.3.8 120Hz(100Hz)/240Hz(200Hz) \
3.3.9 3D No/PR/SG \
4 Signal Receiving System
4.1 ATV Receiving System ATV Receiving System
4.1.1 PAL BG/I/DK/NTSC-M No
4..1.2 PAL/SECAM BG/DK/I SECAM L/L" No
4.1.3 PAL M/N NTSC-M Yes
4.2 DTV Receiving System DTV Receiving System
4.2.1 ATSC No
4.2.2 DVB-T No
4.2.3 DVB-T with CI No
4.2.4 DVB-T2 No
4.2.5 DVB-T2 with CI+ No
4.2.6 ISDB-T/SBTVD-T Yes
4.2.7 DTMB No
4.2.8 DVB-C with CA No
4.2.9 DVB-S No
4.2.10 DVB-S2 No
4.3 Antenna input Antenna input
4.3.1 Antenna Input port: 1 (1 for analogue) No
4.3.2 Antenna Input port: 1 (1 for both analogue and digital) No
4.3.3 Antenna Input port: 2 (1 air + 1 Cable) Yes
4.3.4 Type of Antenna Input Port IEC169-2 Female
4.3.5 Receiving Frequency range (ATV) 54MHz～864MHz
4.3.6 Receiving Frequency range (DTV) VHF 177-213 MHZ, UHF 473-803 MHZ
4.4 External Signal Receiving System
4.4.1 Composite Input PAL 50Hz/60Hz Yes
4.4.2 SECAM Yes
4.4.3 NTSC 3.58 Yes
4.4.4 NTSC4.43 Yes
4.4.5 Component Input 480i /480p/720p/1080i (60Hz) Yes
4.4.6 576i /576p/720p/1080i (50Hz) Yes
4.4.7 1080P 24Hz/25Hz/30Hz/50Hz/60Hz Yes
4.4.8 PC Input VGA (640 x 480) Yes
4.4.9 S-VGA (800 x 600) Yes
4.4.10 XGA (1024 x 768) Yes
4.4.11 W-XGA (1280 x 768) Yes
4.4.12 W-XGA（1360×768） Yes
4.4.13 S-XGA (1280 x 1024) Yes
4.4.14 HDMI Input 480i /480p/720p/1080i (60Hz) (Video Format) Yes/Yes/Yes/Yes
4.4.15 576i /576p/720p/1080i (50Hz) (Video Format) Yes/Yes/Yes/Yes
4.4.16 1080P 24Hz/25Hz/30Hz/50Hz/60Hz (Video Format) Yes/Yes/Yes/Yes/Yes
4.4.17 VGA (640 x 480) (PC Format) Yes
4.4.18 S-VGA (800 x 600) (PC Format) Yes
4.4.19 XGA (1024 x 768) (PC Format) Yes
4.4.20 W-XGA (1280 x 768) (PC Format) Yes
4.4.21 W-XGA（1360×768）(PC Format) Yes
4.4.22 S-XGA (1280 x 1024) (PC Format) Yes
4.4.23 USB Media player formats Please see attached
5 Features
5.1 Picture Picture
5.1.1 Picture Mode Normal/ Movie / Sports / User
5.1.2 Picture Display Size 4:3/16:9/Panorama/Subtitle/Movie/Native
5.1.3 Picture Freeze Yes
5.1.4 Backlight Adjust No
5.1.5 Auto Format No
5.1.6 3:2 Pull Down No
5.1.7 4:3 Stretch No
5.1.8 Comfilter 3D
5.1.9 PIP(Single tuner) No
5.1.10 Noise Reduction Off/Low/Middle/High
5.1.11 MPEG Reduction Off/Low/Middle/High
5.1.12 3D No
5.1.13 Color temperature Cool/ Normal/Warm/ User
5.2 Sound Sound
5.2.1 Sound Mode Standard / Music / Film /News/ User
5.2.2 For personal mode:Treble/Bass/Balance No
5.2.3 Surround Yes
5.2.4 Sound Mode Standard / Music / Film / News/ User
5.2.5 Equalizer Yes
5.2.6 Audio Output Power 2 X 3W
5.2.7 NICAM No
5.2.8 A2 No
5.2.9 BTSC(MTS) Yes
5.3 Teletext Teletext
5.3.1 FLOF/TOP No
5.3.2 Memory Page No
5.3.3 Character Language No
5.3.4 Teletext Level No
5.4 Program Management Program Management
5.4.1 V-Chip No
5.4.2 Parent Control(Child Lock) Yes
5.4.3 Closed Caption Yes
5.4.4 Subtitle Yes
5.4.5 EPG Yes
5.4.6 Channel list Yes
5.4.7 Faivorate Channel List Yes
5.4.8 Channel Editor Yes
5.4.9 On/Off timer Yes
5.4.10 Sleep timer Yes
5.4.11 Channel Swap timer No
5.4.12 Blue Screen Yes
5.5 AC Input AC Input
5.5.1 AC Input Range \
5.5.2 AC Plug Type \
5.5.3 AC Cable Length \
5.5.4 Power Consumption \
5.5.5 Standby Power Consumption <1W
5.6 HDMI HDMI
5.6.1 CEC Yes
5.6.2 ARC No
5.6.3 3D No
5.6.4 MHL Yes
5.7 Software Update Software Update
5.7.1 By USB Yes
5.7.2 By Internet Yes
5.7.3 Internet Auto search No
5.7.4 By Over-Air No
5.7.5 By other Service Port No
5.8 PVR PVR
5.8.1 By External USB or HDD Yes
5.8.2 Built in HDD No
5.8.3 Time Shift Yes
5.9 OSD Lauguage OSD Lauguage
5.9.1 OSD Lauguage English/Spanish/Portuguese
5.1O USB File System USB File System
5.10.1 FAT16 Yes
5.10.2 FAT32 Yes
5.10.3 NTFS Yes
5.11 Middleware Middleware
5.11.1 MHEG5 No
5.11.2 Ginga Yes
5.11.3 MHP No
5.12 Wifi Wifi
5.12.1 Wifi Dongle Optional
5.12.2 Wifl Built in No
6 Terminals Configuration
6.1 Teminal Direction (Side and Bottom & Side and Rear)
6.2 Wifi Wifi
6.2.1 Tuner BackX2
6.2.2 Composite Side X1
6.2.3 S-Video No
6.2.4 Full Scart No
6.2.5 Half Scart No
6.2.6 Component Side X1
6.2.7 PC input with 3.5mm mini jack audio input Side X1(same AV audio)
6.2.8 HDMI Side X1 BackX1
6.2.9 USB Side X1
6.2.10 LAN Back X1
6.2.11 CI Slot No
6.2.12 CA Slot No
6.3 Output Output
6.3.1 Video Output No
6.3.2 Audio Output (Fixed & Variable) Share with earphone
6.3.3 Digital Audio Output (Coaxial & Optical) No
6.3.4 Earphone Back X1
6.4 Diagram of Teminal Configuration Please see attached
7 Mechanical Spec
7.1 Cabinet Cabinet
7.1.1 Cabinet color For front back stand \
7.1.2 Operation Keys / Touch sensor
7.1.3 AC Power Switch Mechanical power switch \
7.1.4 LED Indicator Power on (Green) \
7.1.5 Power on / Standby (Green / Red ) \
7.1.6 Power on / Standby / Recording(Green / Red / Orange) \
7.1.7 Program Timer / Recoding (Green / Red) \
7.1.8 On Timer or Program Timer(Green) \
7.1.9 Logo Style Silk Printing / SUS Badge (inlet type) \
7.1.10 Stand Tilt / Swivel \
7.2 Dimension & Stuffing Dimension & Stuffing
7.2.1 Size (with stand)( mm ) \
7.2.2 Size (without stand) ( mm ) \
7.2.3 Package Size (with stand)(mm) \
7.2.4 Net Weight(Kg) \
7.2.5 Gross Weight \
7.2.6 Loading quantity (20GP/40GP/40GP) with pallet \
7.2.7 Loading quantity (20GP/40GP/40GP) without pallet \
7.2.8 Stand build in Packing Box (together or separately ) \
8 Accessories
8.1 Remote Controller Remote Controller
8.1.1 Type No. TBD
8.1.2 Battery TBD
8.2 Instruction Manual Instruction Manual
8.2.1 Paper size \
8.2.2 Printing Color \
8.2.3 Languages (Refer to Sales Country Sheet) \
8.2.4 Total Pages \
8.2 Others Others
8.2.1 3D Glasses \
8.2.2 Camera \
8.2.3 etc \
9 Requested Certification
9.1 CB Yes
9.2 UL \
9.3 EMC TBD
9.4 FCC \
9.5 HDMI Yes
9.6 USB No
9.7 CI+ No
9.8 Dolby No
9.9 DOLBY + No
9.10 Dvix Hometheatre \
9.11 DviX HD \
9.12 DviX+HD \
9.13 MHL No
9.14 DLNA \
9.15 CTS \
9.16 Wifi \
9.17 MPES \
9.18 Energy Star \
6M83B关键件清单
长周期\关键件分类物料编号单机用量位号

TUNER 5219-06033D-7V00 1 T1
MAIN CHIP 475C-M63085-3690 1 U9
Nand-FLASH 4701-T581G1-0480 1 U23
AMP 4722-T31130-0280 1 U15
DC/DC 5V 476A-M14950-0080 1 U5
DC/DC 1.15V 476A-M14950-0080 1 U4
DC/DC 3.3V 476A-M14940-0080 1 U2
LDO 3.3V 47DG-L11171-0030 1 U6
LDO 1.5V 47B6-A11174-0300 1 U3
P-MOS 47D9-M94350-0080 1 U11
PDF 文件使用 "pdfFactory Pro" 试用版本创建 www.fineprint.cn
TPA3113D2
www.ti.com ........................................................................................................................................... SLOS650B – AUGUST 2009 – REVISED SEPTEMBER 2009
6-W FILTER-FREE STEREO CLASS-D AUDIO POWER AMPLIFIER WITH

SPEAKERGUARD™
1 FEATURES
• 6-W/ch into an 8-Ω Loads at 10% THD+N From
2
DESCRIPTION
a 10-V Supply The TPA3113D2 is a 6-W (per channel) efficient,
• 12-W into a 4-Ω Mono Load at 10% THD+N Class-D audio power amplifier for driving bridged-tied
From a 10-V Supply stereo speakers. Advanced EMI Suppression
Technology enables the use of inexpensive ferrite
• 87% Efficient Class-D Operation Eliminates
bead filters at the outputs while meeting EMC
Need for Heat Sinks requirements. SpeakerGuard™ speaker protection
• Wide Supply Voltage Range Allows Operation circuitry includes an adjustable power limiter and a
from 8 V to 26 V DC detection circuit. The adjustable power limiter
• Filter-Free Operation allows the user to set a "virtual" voltage rail lower
than the chip supply to limit the amount of current
• SpeakerGuard™ Speaker Protection Includes through the speaker. The DC detect circuit measures
Adjustable Power Limiter plus DC Protection the frequency and amplitude of the PWM signal and
• Flow Through Pin Out Facilitates Easy Board shuts off the output stage if the input capacitors are
Layout damaged or shorts exist on the inputs.
• Robust Pin-to-Pin Short Circuit Protection and The TPA3113D2 can drive stereo speakers as low as
Thermal Protection with Auto Recovery Option 4 Ω. The high efficiency of the TPA3113D2, 87%,
• Excellent THD+N / Pop-Free Performance eliminates the need for an external heat sink when
playing music.
• Four Selectable, Fixed Gain Settings
• Differential Inputs The outputs are also fully protected against shorts to
GND, VCC, and output-to-output. The short-circuit
protection and thermal protection includes an
APPLICATIONS auto-recovery feature.
• Televisions
• Consumer Audio Equipment
• Monitors
1mF
OUTL+ LINP TPA3113D2

Audio OUTL- LINN
Source
OUTR+ RINP OUTPL FERRITE
6W
BEAD
OUTNL FILTER 8W
OUTR- RINN
GAIN0
GAIN1
OUTPR FERRITE
6W
BEAD
OUTNR FILTER 8W
PLIMIT
PBTL
Fault
SD PVCC 8 to 26V
Figure 1. TPA3113D2 Simplified Application Schematic
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 SpeakerGuard, PowerPad are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPA3113D2
SLOS650B – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC Supply voltage AVCC, PVCC –0.3 V to 30 V
SD, GAIN0, GAIN1, PBTL, FAULT –0.3 V to VCC + 0.3 V
VI Interface pin voltage PLIMIT –0.3 V to GVDD + 0.3 V
RINN, RINP, LINN, LINP –0.3 V to 6.3 V
Continuous total power dissipation See Dissipation Rating Table
TA Operating free-air temperature range –40°C to 85°C
(2)
TJ Operating junction temperature range –40°C to 150°C
Tstg Storage temperature range –65°C to 150°C
BTL: PVCC > 15 V 4.8
RL Minimum Load Resistance BTL: PVCC ≤ 15 V 3.2
PBTL 3.2
(3)
Human body model (all pins) ±2 kV
ESD Electrostatic discharge (4)
Charged-device model (all pins) ±500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The TPA3113D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
(3) In accordance with JEDEC Standard 22, Test Method A114-B.
(4) In accordance with JEDEC Standard 22, Test Method C101-A
DISSIPATION RATINGS
PACKAGE (1) TA ≤ 25°C DERATING FACTOR (θJA) TA = 85°C θJP ΨJT
28 pin TSSOP (PWP) 4.48 W 27.87 °C/W 2.33 W 0.72 °C/W 0.45 °C/W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC Supply voltage PVCC, AVCC 8 26 V
VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 V
VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 V
VOL Low-level output voltage FAULT, RPULL-UP=100k, VCC=26V 0.8 V
IIH High-level input current SD, GAIN0, GAIN1, PBTL, VI = 2V, VCC = 18 V 50 µA
IIL Low-level input current SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V 5 µA
TA Operating free-air temperature –40 85 °C
2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPA3113D2

TPA3113D2
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
| VOS | VI = 0 V, Gain = 36 dB 1.5 15 mV
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 24V 32 50 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 24V 250 400 µA
VCC = 12 V, IO = 500 mA, High Side 400
rDS(on) Drain-source on-state resistance mΩ
TJ = 25°C Low side 400
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain
GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
ton Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 µs
GVDD Gate Drive Supply IGVDD = 100µA 6.4 6.9 7.4 V
tDCDET DC Detect time V(RINN) = 6V, VRINP = 0V 420 ms
DC CHARACTERISTICS
Class-D output offset voltage (measured
| VOS | VI = 0 V, Gain = 36 dB 1.5 15 mV
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 12V 20 35 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12V 200 µA
VCC = 12 V, IO = 500 mA, High Side 400
rDS(on) Drain-source on-state resistance mΩ
TJ = 25°C Low side 400
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain
GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
tON Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 µs
GVDD Gate Drive Supply IGVDD = 2mA 6.4 6.9 7.4 V
Output Voltage maximum under PLIMIT
VO V(PLIMIT) = 2 V; VI = 1V rms 6.75 7.90 8.75 V
control
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3

TPA3113D2
AC CHARACTERISTICS
200 mVPP ripple at 1 kHz,
KSVR Power Supply ripple rejection –70 dB
Gain = 20 dB, Inputs ac-coupled to AGND
PO Continuous output power THD+N = 10%, f = 1 kHz, VCC = 10 V 6 W
THD+N Total harmonic distortion + noise VCC = 16 V, f = 1 kHz, PO = 3 W (half-power) 0.07 %
65 µV
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dBV
Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz –100 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C
AC CHARACTERISTICS
200 mVPP ripple from 20 Hz–1 kHz,
KSVR Supply ripple rejection –70 dB
Gain = 20 dB, Inputs ac-coupled to AGND
THD+N Total harmonic distortion + noise RL = 8 Ω, f = 1 kHz, PO = 3 W (half-power) 0.06 %
65 µV
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dBV
Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz –100 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C
PWP (TSSOP) PACKAGE

(TOP VIEW)
SD 1 28 PVCCL
FAULT 2 27 PVCCL
LINP 3 26 BSPL
LINN 4 25 OUTPL
GAIN0 5 24 PGND
GAIN1 6 23 OUTNL
AVCC 7 22 BSNL
AGND 8 21 BSNR
GVDD 9 20 OUTNR
PLIMIT 10 19 PGND
RINN 11 18 OUTPR
RINP 12 17 BSPR
NC 13 16 PVCCR
PBTL 14 15 PVCCR

TPA3113D2
PIN FUNCTIONS
PIN
Pin I/O/P DESCRIPTION
NAME
Number
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs
SD 1 I
enabled). TTL logic levels with compliance to AVCC.
Open drain output used to display short circuit or dc detect fault status. Voltage
compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting
FAULT 2 O
FAULT pin to SD pin. Otherwise, both short circuit faults and dc detect faults must
be reset by cycling PVCC.
LINP 3 I Positive audio input for left channel. Biased at 3V.
LINN 4 I Negative audio input for left channel. Biased at 3V.
GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
AVCC 7 P Analog supply
AGND 8 Analog signal ground. Connect to the thermal pad.
High-side FET gate drive supply. Nominal voltage is 7V. Also should be used as
GVDD 9 O
supply for PLIMIT function
Power limit level adjust. Connect a resistor divider from GVDD to GND to set
PLIMIT 10 I
power limit. Connect directly to GVDD for no power limit.
RINN 11 I Negative audio input for right channel. Biased at 3V.
RINP 12 I Positive audio input for right channel. Biased at 3V.
NC 13 Not connected
PBTL 14 I Parallel BTL mode switch
Power supply for right channel H-bridge. Right channel and left channel power
PVCCR 15 P
supply inputs are connect internally.
Power supply for right channel H-bridge. Right channel and left channel power
PVCCR 16 P
BSPR 17 I Bootstrap I/O for right channel, positive high-side FET.
OUTPR 18 O Class-D H-bridge positive output for right channel.
PGND 19 Power ground for the H-bridges.
OUTNR 20 O Class-D H-bridge negative output for right channel.
BSNR 21 I Bootstrap I/O for right channel, negative high-side FET.
BSNL 22 I Bootstrap I/O for left channel, negative high-side FET.
OUTNL 23 O Class-D H-bridge negative output for left channel.
PGND 24 Power ground for the H-bridges.
OUTPL 25 O Class-D H-bridge positive output for left channel.
BSPL 26 I Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge. Right channel and left channel power
PVCCL 27 P
Power supply for left channel H-bridge. Right channel and left channel power
PVCCL 28 P

TPA3113D2
FUNCTIONAL BLOCK DIAGRAM
GVDD
PVCCL
BSPL
PVCCL
PBTL Select OUTPL FB

Gate
Drive OUTPL
OUTPL FB
LINP PGND
PWM
Gain
PLIMIT Logic
Control GVDD
LINN PVCCL
BSNL
PVCCL
OUTNL FB
OUTNL FB
FAULT
Gate
Drive OUTNL
SD
TTL
Buffer
GAIN0 SC Detect
Gain PGND
GAIN1 Control
DC Detect
Ramp Biases and Startup Protection
Generator References Logic Thermal
Detect
PLIMIT
PLIMIT Reference UVLO/OVLO
GVDD
PVCCL
BSNR
AVDD
PVCCL
AVCC LDO
Regulator
GVDD
Gate
Drive OUTNR
GVDD
OUTNN FB OUTNR FB
RINN
PGND
Gain PWM
PLIMIT Logic
Control
GVDD PVCCL
RINP
BSPR
PVCCL
OUTNP FB
Gate
Drive OUTPR
TTL PBTL PBTL Select
PBTL Buffer Select OUTPR FB
AGND
PGND

TPA3113D2
TYPICAL CHARACTERISTICS
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is
available at ti.com.)
TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

vs vs
FREQUENCY (BTL) FREQUENCY (BTL)
10 10
Gain = 20 dB Gain = 20 dB
VCC = 12 V VCC = 18 V
ZL = 8 Ω + 66 µH
THD − Total Harmonic Distortion − %

ZL = 8 W + 66 mH
1 1
0.1 0.1
PO = 5 W
PO = 1 W
0.01 PO = 0.5 W 0.01
PO = 2.5 W PO = 5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G001 G002
Figure 2. Figure 3.

vs vs
10 10
VCC = 24 V VCC = 12 V
ZL = 6 Ω + 47 µH
ZL = 8 W + 66 mH
1 1
0.1 0.1
PO = 5 W
PO = 1 W
PO = 0.5 W
0.01 0.01
PO = 2.5 W
PO = 5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
G003 G004
Figure 4. Figure 5.

TPA3113D2
TYPICAL CHARACTERISTICS (continued)


vs vs
10 10
VCC = 18 V VCC = 12 V

ZL = 6 W + 47 mH ZL = 4 W + 33 mH
1 1
0.1 0.1
PO = 1 W
0.01 0.01
PO = 1 W
PO = 5 W
PO = 5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
G005 G006
Figure 6. Figure 7.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
OUTPUT POWER (BTL) OUTPUT POWER (BTL)
10 10
THD+N − Total Harmonic Distortion + Noise − %
VCC = 12 V VCC = 18 V
ZL = 8 Ω + 66 µH ZL = 8 Ω + 66 µH
1 1
f = 20 Hz f = 1 kHz f = 20 Hz
0.1 f = 1 kHz 0.1
0.01 0.01
f = 10 kHz f = 10 kHz
0.001 0.001
0.01 0.1 1 10 0.01 0.1 1 10
PO − Output Power − W PO − Output Power − W
G007 G008
Figure 8. Figure 9.

TPA3113D2


vs vs
10 10

VCC = 24 V VCC = 12 V
ZL = 8 Ω + 66 µH ZL = 6 Ω + 47 µH
1 1
f = 1 kHz f = 1 kHz
f = 20 Hz
0.1 0.1
0.01 0.01
f = 20 Hz
f = 10 kHz
f = 10 kHz
0.001 0.001
0.01 0.1 1 10 0.01 0.1 1 10
G009 G010
Figure 10. Figure 11.

vs vs
10 10
VCC = 18 V VCC = 12 V
ZL = 6 Ω + 47 µH ZL = 4 Ω + 33 µH
1 1
f = 1 kHz f = 1 kHz
f = 20 Hz
0.1 0.1
0.01 0.01
f = 20 Hz
f = 10 kHz f = 10 kHz
0.001 0.001
0.01 0.1 1 10 0.01 0.1 1 10
G011 G012

TPA3113D2

MAXIMUM OUTPUT POWER OUTPUT POWER

vs vs
PLIMIT VOLTAGE (BTL) PLIMIT VOLTAGE (BTL)
16 35
14 VCC = 24 V VCC = 12 V
30
ZL = 8 Ω + 66 µH ZL = 4 Ω + 33 µH
PO(Max) − Maximum Output Power − W
12
25
PO − Output Power − W
10
20
8
15
6
10
4
5
2
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 3 4 5 6
VPLIMIT − PLIMIT Voltage − V VPLIMIT − PLIMIT Voltage − V
G013 G014
Note: Dashed line represents thermally limited Note: Dashed line represents thermally limited
region. region.
GAIN/PHASE EFFICIENCY
vs vs
FREQUENCY (BTL) OUTPUT POWER (BTL)
40 100 100
35
90 VCC = 12 V
50
Phase 80
30 0
70
25
η − Efficiency − %
−50
60 VCC = 18 V
Gain − dB
Phase − °
Gain
20 −100 VCC = 24 V
50
15 −150 40
CI = 1 µF
Gain = 20 dB 30
10 −200
Filter = Audio Precision AUX-0025
VCC = 12 V 20
5 VI = 0.1 Vrms −250
ZL = 8 Ω + 66 µH Gain = 20 dB
10
0 −300 ZL = 8 Ω + 66 µH
20 100 1k 10k 100k 0
f − Frequency − Hz 0 1 2 3 4 5 6 7 8 9 10
G015
G018
Figure 16.
Note: Dashed lines represent thermally limited
region.
Figure 17.

TPA3113D2

EFFICIENCY EFFICIENCY
vs vs
OUTPUT POWER (BTL with LC FILTER) OUTPUT POWER (BTL)
100 100
90 VCC = 12 V 90
VCC = 12 V
80 80
70 VCC = 18 V 70 VCC = 18 V
VCC = 24 V
60 60
50 50
40 40
30 30
20 20
Gain = 20 dB
10 LC Filter = 22 µH + 0.68 µF 10 Gain = 20 dB
RL = 8 Ω ZL = 6 Ω + 47 µH
0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
G032 G019
Note: Dashed lines represent thermally limited Note: Dashed lines represent thermally limited
region. region.
EFFICIENCY EFFICIENCY
vs vs
OUTPUT POWER (BTL with LC FILTER) OUTPUT POWER (BTL)
100 100
Gain = 20 dB
90 VCC = 12 V 90 VCC = 12 V
ZL = 4 Ω + 33 µH
80 80
70 VCC = 18 V 70
60 60
50 50
40 40
30 30
20 20
Gain = 20 dB
10 LC Filter = 22 µH + 0.68 µF 10
RL = 6 Ω
0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
G033 G020
Note: Dashed lines represent thermally limited Note: Dashed line represents thermally limited
region. region.

TPA3113D2

EFFICIENCY SUPPLY CURRENT

vs vs
OUTPUT POWER (BTL with LC FILTER) TOTAL OUTPUT POWER (BTL)
100 1.2
Gain = 20 dB
90 ZL = 8 Ω + 66 µH
1.0
80
ICC − Supply Current − A

70 VCC = 12 V
0.8
60
50 0.6 VCC = 18 V
40
0.4
30 VCC = 24 V
20
Gain = 20 dB 0.2
10 LC Filter = 22 µH + 0.68 µF
RL = 4 Ω
0 0.0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
PO − Output Power − W PO(Tot) − Total Output Power − W
G034 G021
Note: Dashed line represents thermally limited Note: Dashed lines represent thermally limited
region. region.
CROSSTALK SUPPLY RIPPLE REJECTION RATIO

vs vs
−20 0
−30
VCC = 12 V Vripple = 200 mVpp
KSVR − Supply Ripple Rejection Ratio − dB
−40 VO = 1 Vrms −20 ZL = 8 Ω + 66 µH

ZL = 8 Ω + 66 µH
−50
−40
−60
Crosstalk − dB
−70
−60 VCC = 12 V
−80
Right to Left
−90
−80
−100
−110 Left to Right

−100
−120
−130 −120
20 100 1k 10k 20k 20 100 1k 10k 20k
G023 G024

TPA3113D2

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY (PBTL) OUTPUT POWER (PBTL)
10 10

VCC = 12 V VCC = 12 V
ZL = 4 W + 33 mH ZL = 4 W + 33 mH
1 1
PO = 5 W f = 1 kHz
0.1 0.1
PO = 0.5 W
0.01 0.01
PO = 2.5 W f = 20 Hz
f = 10 kHz
0.001 0.001
20 100 1k 10k 20k 0.01 0.1 1 10 50
f − Frequency − Hz PO − Output Power − W
G025 G026
GAIN/PHASE EFFICIENCY
vs vs
FREQUENCY (PBTL) OUTPUT POWER (PBTL)
40 100 100
VCC = 12 V
35 90
50
Phase 80 VCC = 18 V
30 0
70
25 −50
Gain − dB
60
Phase − °
Gain
20 −100
50
15 −150 40
CI = 1 µF
10 Gain = 20 dB 30
−200
Filter = Audio Precision AUX-0025
VCC = 24 V
5 −250
20
VI = 0.1 Vrms
ZL = 8 Ω + 66 µH Gain = 20 dB
10
0 −300 ZL = 4 Ω + 33 µH
20 100 1k 10k 100k
0
f − Frequency − Hz 0 1 2 3 4 5 6 7 8 9 10
G027
G029

TPA3113D2

SUPPLY CURRENT SUPPLY RIPPLE REJECTION RATIO

vs vs
OUTPUT POWER (PBTL) FREQUENCY (PBTL)
1.0 0
0.9 ZL = 4 Ω + 33 µH Vripple = 200 mVpp
KSVR − Supply Ripple Rejection Ratio − dB

−20 ZL = 8 Ω + 66 µH
0.8
ICC − Supply Current − A
0.7
−40
0.6 VCC = 12 V
0.5 −60 VCC = 12 V
0.4
VCC = 18 V −80
0.3
0.2
−100
0.1
0.0 −120
0 1 2 3 4 5 6 7 8 9 10 20 100 1k 10k 20k
PO − Output Power − W f − Frequency − Hz
G030 G031

TPA3113D2
DEVICE INFORMATION
Gain Setting Via GAIN0 and GAIN1 Inputs

The gain of the TPA3113D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 7.2 kΩ, which is the absolute minimum input impedance of the TPA3113D2. At the lower gain
settings, the input impedance could increase as high as 72 kΩ
Table 1. Gain Setting

INPUT IMPEDANCE
AMPLIFIER GAIN (dB)
GAIN1 GAIN0 (kΩ)
TYP TYP
0 0 20 60
0 1 26 30
1 0 32 15
1 1 36 9
SD Operation
The TPA3113D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see
specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the
outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier
operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage.
PLIMIT
The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail.
Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also
be used if tighter tolerance is required. Also add a 1µF capacitor from pin 10 to ground.
Vinput
PLIMIT = 6.96V Pout = 11.8W
PLIMIT = 3V Pout = 10W
PLIMIT = 1.8V Pout = 5W
TPA3110D1 Power Limit Function

Vin=1.13VPP Freq=1kHz RLoad=8W
Figure 32. PLIMIT Circuit Operation

TPA3113D2
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to fixed maximum value. This limit can be thought of as a "virtual" voltage rail which is lower than the supply
connected to PVCC. This "virtual" rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to
calculate the maximum output power for a given maximum input voltage and speaker impedance.
2
ææ RL ö ö
çç ç ÷ x VP ÷÷
è RL + 2 x RS ø
POUT = è ø for unclipped power
2 x RL (1)
Where:
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
POUT (10%THD) = 1.25 × POUT (unclipped)
Table 2. PLIMIT Typical Operation

OUTPUT POWER OUTPUT VOLTAGE AMPLITUDE
TEST CONDITIONS () PLIMIT VOLTAGE
(W) (VP-P)
PVCC=24V, Vin=1Vrms, 1.62 5 14
RL=8Ω, Gain=26dB
PVCC=24V, Vin=1Vrms, 1.86 5 14.8
RL=8Ω, Gain=20dB
PVCC=12V, Vin=1Vrms, 1.76 5 15
RL=8Ω, Gain=20dB
GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply
the PLIMIT voltage divider circuit. Add a 1µF capacitor to ground at this pin.
DC Detect
TPA3113D2 has circuitry which will protect the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on
the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the
state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling SD will
NOT clear a DC detect fault.
A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example,
+57%, -43%) for more than 420 msec at the same polarity. This feature protects the speaker from large DC
currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low
at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive
and negative inputs to avoid nuisance DC detect faults.
The minimum differential input voltages required to trigger the DC detect are show in table 2. The inputs must
remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.

TPA3113D2
Table 3. DC Detect Threshold

AV(dB) Vin (mV, differential)
20 112
26 56
32 28
36 17
PBTL Select
TPA3113D2 offers the feature of parallel BTL operation with two outputs of each channel connected directly. If
the PBTL pin (pin 14) is tied high, the positive and negative outputs of each channel (left and right) are
synchronized and in phase. To operate in this PBTL (mono) mode, apply the input signal to the RIGHT input and
place the speaker between the LEFT and RIGHT outputs. Connect the positive and negative output together for
best efficiency. For an example of the PBTL connection, see the schematic in the APPLICATION INFORMATION
section.
For normal BTL operation, connect the PBTL pin to local ground.
Short-Circuit Protection and Automatic Recovery Feature

TPA3113D2 has protection from overcurrent conditions caused by a short circuit on the output stage. The short
circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z
state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through
the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit
protection latch.
Thermal Protection
Thermal protection on the TPA3113D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
Thermal protection faults are NOT reported on the FAULT terminal.

TPA3113D2
APPLICATION INFORMATION
PVCC
100 μF 0.1 μF 1000 pF
100 kΩ
Control 1 28
SD PVCCL
System 1 kΩ
2 27
FAULT PVCCL
1 mF 3 26 0.22 μF
LINP BSPL FB
1 mF 4 25
LINN OUTPL 1000 pF
5 24
GAIN0 PGND
6 23
PVCC 10 Ω
GAIN1 OUTNL 1000 pF
7 22
AVCC BSNL FB
1 mF 0.22 μF
TPA3113D2
8 21 0.22 μF
AGND BSNR FB
1 mF 9 20 1000 pF
GVDD OUTNR
1 mF
10 kΩ 10 19
PLIMIT PGND
10 kΩ
1 mF 11 18
RINN OUTPR 1000 pF
Audio 12 17 FB
RINP BSPR
Source 1 mF
0.22 μF
13 16
NC PVCCR
100 μF 0.1 μF 1000 pF
14 15
PBTL PVCCR
GND
29
PowerPAD
PVCC
Figure 33. Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs

TPA3113D2
PVCC
100 μF 0.1 μF 1000 pF
100 kΩ
Control 1 28
SD PVCCL
System 1 kΩ
2 27
FAULT PVCCL
3 26
LINP BSPL
0.47 μF
4 25
LINN OUTPL
5 24
GAIN0 PGND
6 23 FB
GAIN1 OUTNL
7 22 1000 pF
PVCC AVCC BSNL
10 Ω TPA3113D
1 mF 8 21
AGND BSNR
1000 pF
1 mF
9 20
GVDD OUTNR
FB
10 19
PLIMIT PGND
0.47 μF
1 mF 11 18
RINN OUTPR
Audio 12
BSPR
17
RINP
Source 1 mF
13 16
NC PVCCR
100 μF 0.1 μF 1000 pF
14 15
AVCC PBTL
GND
PVCCR
29
PowerPAD
PVCC
Figure 34. Stereo Class-D Amplifier with PBTL Output and Single-Ended Input

TPA3113D2
TPA3113D2 Modulation Scheme

The TPA3113D2 uses a modulation scheme that allows operation without the classic LC reconstruction filter
when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP
and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty
cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of
OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load
sits at 0V throughout most of the switching period, reducing the switching current, which reduces any I2R losses
in the load.
OUTP
OUTN
No Output
OUTP
OUTP-OUTN 0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN 0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP-OUTN 0V
-PVCC
Speaker 0A
Current
Figure 35. The TPA3113D2 Output Voltage and Current Waveforms Into an Inductive Load
Ferrite Bead Filter Considerations

Using the Advanced Emissions Suppression Technology in the TPA3113D2 amplifier it is possible to design a
high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to
the operation of the Class D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.

TPA3113D2
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case, it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current of the amplifier. If these specifications are not available, it is also possible to estimate the bead current
handling capability by measuring the resonant frequency of the filter output at low power and at maximum power.
A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite
beads which have been tested and work well with the TPA3113D2 include 28L0138-80R-10 and
HI1812V101R-10 from Steward and the 742792510 from Wurth Electronics.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to
ground. Suggested values for a simple RC series snubber network would be 10 Ω in series with a 330 pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the PGND or the PowerPad™ beneath the
chip.
70
FCC Class B (3m)
60
50
Limit Level - dBmV/m
40
30
20
10
0
30M 230M 430M 630M 830M
f - Frequency - Hz
Figure 36. TPA3113D2 EMC spectrum with FCC Class B Limits
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme

The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3113D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.

TPA3113D2
When to Use an Output Filter for EMI Suppression

The TPA3113D2 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 125 cm and high power. The TPA3113D2 EVM passes FCC Class B specifications under
these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases, a classic
second order Butterworth filter similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, it LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
33 mH
OUTP
C2
L1
1 mF
33 mH
OUTN
C3
L2
1 mF
Figure 37. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
L1 C2
2.2 mF
15 mH
OUTN
L2 C3
2.2 mF
Figure 38. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 39. Typical Ferrite Chip Bead Filter (Chip Bead Example)

TPA3113D2
Input Resistance
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the
largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or
cutoff frequency may change when changing gain steps.
Zf
Ci
Zi
Input IN
Signal
The -3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 1.
1
f =
2p Zi Ci (2)
Input Capacitor, CI
In the typical application, an input capacitor CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in Equation 3.
-3 dB
1
fc =
2p Zi Ci
fc (3)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
1
Ci =
2p Zi fc (4)
In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 µF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network CI) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.

TPA3113D2
Power Supply Decoupling, CS

The TPA3113D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum decoupling is
achieved by using a network of capacitors of different types that target specific types of noise on the power
supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper
trace inductances as well as lead frame capacitance, a good quality low equivalent-series-resistance (ESR)
ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as close to
the device PVCC pins and system ground (either PGND pins or PowerPad) as possible. For mid-frequency noise
due to filter resonances or PWM switching transients as well as digital hash on the line, another good quality
capacitor typically 0.1 µF to 1 µF placed as close as possible to the device PVCC leads works best For filtering
lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µF or greater placed near the
audio power amplifier is recommended. The 220 µF capacitor also serves as a local storage capacitor for
supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 220 µF or larger capacitor should be placed on each PVCC terminal. A 10 µF
capacitor on the AVCC terminal is adequate. Also, a small decoupling resistor between AVCC and PVCC can be
used to keep high frequency class D noise from entering the linear input amplifiers.
BSN and BSP Capacitors

The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22 µF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22 µF capacitor must be
connected from OUTPx to BSPx, and one 0.22 µF capacitor must be connected from OUTNx to BSNx. (See the
application circuit diagram in Figure 1.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3113D2 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3113D2 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac grounded at
the audio source instead of at the device input for best noise performance. For good transient performance, the
impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 14 ms power-up time. If the input
capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching
which can result in pop if the input components are not well matched.
Using LOW-ESR Capacitors

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.

TPA3113D2
Printed-Circuit Board (PCB) Layout

The TPA3113D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed
circuit board. The following suggestions will help to meet EMC requirements.
• Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (220 µF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3113D2 on the PVCCL and PVCCR supplies. Local, high-frequency bypass
capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the
thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR
ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1µF and
1µF also of good quality to the PVCC connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
• Grounding—The AVCC (pin 7) decoupling capacitor should be grounded to analog ground (AGND). The
PVCC decoupling capacitors should connect to PGND. Analog ground and power ground should be
connected at the thermal pad, which should be used as a central ground connection or star ground for the
TPA3113D2.
• Output filter—The ferrite EMI filter (Figure 39) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter (Figure 37 and Figure 38) should be placed close to the outputs.
The capacitors used in both the ferrite and LC filters should be grounded to power ground.
• Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35mm. Seven rows of
solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application
Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB
footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3113D2 Evaluation Module (TPA3113D2EVM) User Manual. Both the EVM
user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.
Revision History
Changes from Original (August 2009) to Revision A ..................................................................................................... Page
• Changed Feature From: 90% Efficient Class-D Operation Eliminates Need for Heat Sinks To: 87% Efficient Class-D
Operation Eliminates Need for Heat Sinks ............................................................................................................................ 1
• Changed the Drain Source TYP value From: 240 to 400 mΩ. .............................................................................................. 3
• Changed the Drain Source TYP value From: 240 to 400 mΩ. .............................................................................................. 3
• Changed AC Char 24V - PO From: THD+N = 10%, f = 1 kHz, VCC = 16 V (TYP = 15W) To: THD+N = 10%, f = 1
kHz, VCC = 10 V (TYP = 6W) ................................................................................................................................................. 4
• Changed AC Char 24V - THD+N From: VCC = 16 V, f = 1 kHz, PO = 7.5 W (half-power) To: VCC = 16 V, f = 1 kHz,
PO = 3 W (half-power) TYP From: 0.1 To: 0.07..................................................................................................................... 4
• Deleted AC Char 12V -, PO - Continuous output power ...................................................................................................... 4
• Changed AC Char 12V - THD+N From: VCC = 16 V, f = 1 kHz, PO = 5 W (half-power) To: VCC = 16 V, f = 1 kHz, PO
= 3 W (half-power) ................................................................................................................................................................. 4
• Changed multiple graphs in theTYPICAL CHARACTERISTICS. .......................................................................................... 7
Changes from Revision A (August 2009) to Revision B ................................................................................................ Page
• Added the Pin out illustration. ................................................................................................................................................ 4

• Changed the Stereo Class-D Amplifier with BTL Output and Single-Ended Input illustration Figure 33 - Corrected
the pin names. ..................................................................................................................................................................... 18
• Changed the Stereo Class-D Amplifier with PBTL Output and Single-Ended Input Figure 34 - Corrected the pin
names. ................................................................................................................................................................................. 19

Headphone Amplifiers
Standard
Headphone Amplifiers
BH3541F,BH3544F,BH3547F,BH3548F No.10102EAT02
Description
BH3541F, BH3544F, BH3547F, BH3548F is headphone amplifiers suitable for portable products.
BH3541F has a fixed gain of 0 dB and BH3544F, BH3547F, BH3548F has a fixed gain of 6 dB.
External resistors for gain setting are not needed. Package of BH3541F, BH3544F, BH3547F, BH3548F is pin-to-pin
compatible (SOP8), enable to replace each other easily.
BH3541F, BH3544F, BH3547F, BH3548F also has mute functions that make it easy to prevent pop noise when power
supply turns on/off. Moreover, thermal shutdown function is built-in.
BH3541F, BH3544F, BH3547F can drive 16/32 load, BH3548F can drive 8/16/32 . So, BH3548F is suitable for 8
receiver.
Features
1) Built-in mute function for preventing pop noise when power supply turns on/off
2) Built-in thermal shutdown function
3) BH3541F, BH3544F, BH3547F, BH3548F are pin-to-pin compatible
4) SOP8 small package
Applications
TV, Desktop PC, Notebook PC, Camcorder and other equipment having headphone output
Line up
Part No. BH3541F BH3544F BH3547F BH3548F Unit
Supply voltage +2.8 +6.5 +4.5 +5.5 +4.0 +5.5 V

Quiescent current 7.0 3.7 6.5 mA
Amplifier gain 0 6 dB
Output [RL=16 ] 62 77 62 mW
load impedance 16 / 32 8/16/32
Operating temperature range -25 +75 -40 +85
Absolute maximum ratings(Ta=25°C)

Ratings
Parameter Symbol Unit
BH3541F,BH3544F,BH3547F,BH3548F
Applied voltage VCC 7.0 V
*1
Power dissipation Pd 550 mW
Storage temperature Tstg -55 +125 °C
*1 Derating is done at 5.5mW/°C above Ta=25°C. (When mounted on a 70mm×70mm×1.6mm PCB board, FR4)
Operating conditions (Ta=25°C)

Limits
Parameter Symbol Unit
BH3541F,BH3544F BH3547F BH3548F
Supply voltage VCC +2.8 +6.5 +4.5 +6.5 +4.0 +5.5 V
Temperature Range Topr -25 +75 -40 +85
* These product are not designed for protection against radioactive rays.
www.rohm.com
1/8 2010.05 - Rev.A
© 2010 ROHM Co., Ltd. All rights reserved.
PDF 文件使用 "pdfFactory Pro" 试用版本创建 www.fineprint.com.cn

BH3541F,BH3544F,BH3547F,BH3548F Technical Note
Electrical characteristics (Unless otherwise noted, Ta=25°C,VCC=5V,RL=32 ,f=1kHz,BW=400 30kHz

BH3541F : VIN=0dBV, BH3544F, BH3547F, BH3548F : VIN =-6dBV)
Limits(TYP.)
Parameter Symbol Unit Conditions
BH3541F BH3544F BH3547F BH3548F
Quiescent current IQ 7 3.7 6.5 mA VIN=0Vrms
Mute pin control voltage H VTMH 1.6< V Mute OFF
Mute pin control voltage L VTML <0.3 V Mute ON
Gain GVC 0 6 dB -
Gain difference between
GVC 0 dB -
channels
Total harmonic distortion THD 0.02 0.05 0.02 % BW=20 20kHz
RL=32 ,THD<0.1%
(BH3541F,BH3544F,BH3548F)
Rated output 1 PO1 31 46 31 mW
RL=32 ,THD 0.3%
(BH3547F)
RL=16 ,THD<0.1%
(BH3541F,BH3544F,BH3548F)
Rated output 2 PO2 62 77 62 mW
RL=16 ,THD 0.5%
(BH3547F)
RL=8 ,THD 0.25%
Rated output 3 PO3 - 120 mW
(BH3548F)
Output noise voltage VNO -93 dBV BW=20 20kHz,Rg=0
Channel separation CS -90 -87 -90 dB Rg=0
Mute attenuation ATT -80 dB Rg=0
Ripple rejection RR -57 dB fRR=100Hz,VRR=-20dBV
Input resistance Rin 180 90 k -
Reference data
BH3541F/BH3544F BH3541F/BH3544F BH3541F/BH3544F
Fig. 1 Quiescent current vs. Fig. 2 in DC current vs. Fig. 3 Output voltage vs.
power supply voltage power supply voltage Mute control voltage
www.rohm.com
2/8 2010.05 - Rev.A

Reference data (Continued)

10 10
Ta 25 C
Ta 25 C
RL 32 RL 32
VCC 5V
VCC 3V
1 1
f 10kHZ f 10kHZ
0.1 0.1
f 1kHZ f 1kHZ
0.01 0.01
f 100HZ
f 100HZ
0.001 0.001
40 30 20 10 0 10 40 30 20 10 0 10
OUTPUT VOLTAGE :VO (dBV) OUTPUT VOLTAGE: VO (dBV)
Fig. 4 Voltage gain vs. frequency Fig. 5 Total harmonic distortion vs. Fig. 6 Total harmonic distortion vs.
output voltage (1) output voltage (2)
Fig. 7 Total harmonic distortion vs. Fig. 8 Total harmonic distortion vs. Fig. 9 Channel separation vs.
output voltage (3) output voltage (4) frequency
Fig. 10 MUTE attenuation vs. frequency Fig. 11 Ripple rejection vs. frequency Fig. 12 Ripple rejection vs.
power supply voltage
www.rohm.com
3/8 2010.05 - Rev.A

Block diagram
V CC OUT2 BIA S IN2
8 7 6 5
B IAS
180 k
0d B (90 k)
(6d B)
TS D 180 k
(9 0k)
0 dB
(6d B)
MUTE
1 2 3 4
OU T1 MUTE IN1 GND
( ) are BH3544F, BH3547F, BH3548F values.
Fig. 13
Measurement circuit
Fig. 14
www.rohm.com
4/8 2010.05 - Rev.A

Terminal Equivalent Circuit / Description
Pin Pin Equivalent circuit

I /O Pin voltage Function
No. Name BH3544F,BH3547F,BH3548F BH3547F
VCC VCC
1 OUT1
2.1V
O Output pin
(VCC=5V)
7 OUT2 1 1
7 10k 7 10k
VCC VCC
0.1V Mute control pin

2 2
2 MUTE I (When open) Mute on:Hi
190k 200k
Mute off:Lo (open)
VCC VCC
3 IN1
2.1V 3 3
I Input pin
(VCC=5V)
5 IN2 5 180k 5 90k
BIAS BIAS
VCC VCC Bias pin
(Since the 47 µF
externally attached
60k 70k
2.1V capacitor also serves
6 BIAS I/O
(VCC=5V) 6 6 BIAS as the time constant for
BIAS
60k
64k pop noise
countermeasures,
evaluate adequately
when changing it.)
4 GND I - - - GND pin
8 VCC I - - - Power supply pin
The figure in the pin explanation and input/output equivalent circuit is reference value, it doesnt guarantee the value.
www.rohm.com
5/8 2010.05 - Rev.A

Application circuit
C7
330 µ
+ C5
C6 R5 1µ
47µ VIN2
VCC +
C8 VCC OUT2 BIAS IN2
+
10µ
8 7 6 5
BIAS
180k
0dB (90k)
(6dB)
TSD 180k
(90k)
0dB
(6dB)
MUTE
C1 1 2 3 4
330µ
OUT1 MUTE IN1 GND
+ C3
1µ
VMUTE C2 VIN 1
R2 100k 1µ
H : Active R3
L : Mute
Fig. 15
Description of external components.

1) Input coupling capacitors (C3, C5)
These are determined according to the lower cutoff frequency fc. Moreover, since lowering the capacitance can cause
the occurrence of pop noise, when changing this, determine it after adequate checking.
Since the input impedance of the BH3541F is 180k and that of the BH3544F,BH3547F,BH3548F is 90k , these are
found by the expressions below, although drift, temperature characteristics, and other considerations are necessary.
(Layered ceramic capacitors are recommended.)
C3(C5)=1/(2 ×180k ×fc) [BH3541F]
C3(C5)=1/(2 × 90k ×fc) [BH3544 ,BH3547F,BH3548F]
2) Bias capacitor (C6)
When VCC=5V, 47 F is recommended. Since lowering the capacitance too much can cause worsening of electrical
characteristics or the occurrence of pop noise, when changing this, determine it after checking this adequately.
3) Mute pin pop noise countermeasures (R2, C2)
Since the BH3541F,BH3544F,BH3548F has an impedance of 190k against GND and the BH3547F has 200k , it may
be impossible to cancel mute mode if R2 is made too large.
4) Output coupling capacitors (C1, C7)
These are determined by the lower cutoff frequency. If RL is the output load resistance (assuming a resistance RX is
put in for output protection or current restriction), these are found by the expression below.
C1(C7)=1/(2 ×(RL+R )× fc)
5) Input gain adjustment resistances (R3, R5) (BH3544F,BH3547F)
Externally attached resistances (R3, R5) make input gain adjustment possible. The gain found by the expression
below can be set.
GVC=6+20log(90k /(90k +R3[R5])) [dB]
When input gain is not accommodated, these resistors have no use.
Notes for use

1) Numbers and data in entries are representative design values and are not guaranteed values of the items.
2) Although we are confident in recommending the sample application circuits, carefully check their characteristics further
when using them. When modifying externally attached component constants before use, determine them so that they
have sufficient margins by taking into account variations in externally attached components and the Rohm LSI, not only
for static characteristics but also including transient characteristics.
3) Absolute maximum ratings
If applied voltage, operating temperature range, or other absolute maximum ratings are exceeded, the LSI may be
damaged. Do not apply voltages or temperatures that exceed the absolute maximum ratings. If you think of a case in
which absolute maximum ratings are exceeded, enforce fuses or other physical safety measures and investigate how
not to apply the conditions under which absolute maximum ratings are exceeded to the LSI.
www.rohm.com
6/8 2010.05 - Rev.A
PDF 文件使用 "pdfFactory Pro" 试用版本创建 ÿwww.fineprint.com.cn

4) GND potential
Make the GND pin voltage such that it is the lowest voltage even when operating below it. Actually confirm that the
voltage of each pin does not become a lower voltage than the GND pin, including transient phenomena.
5) Thermal design
Perform thermal design in which there are adequate margins by taking into account the allowable power dissipation in
actual states of use.
6) Shorts between pins and misinstallation
When mounting the LSI on a board, pay adequate attention to orientation and placement discrepancies of the LSI.
If it is misinstalled and the power is turned on, the LSI may be damaged. It also may be damaged if it is shorted by a
foreign substance coming between pins of the LSI or between a pin and a power supply or a pin and a GND.
7) Operation in strong magnetic fields
Adequately evaluate use in a strong magnetic field, since there is a possibility of malfunction.
8) Pop noise countermeasures
In order to prevent the pop noise that occurs when the power supply turns ON or OFF, make the rise and fall with
reference to the timing diagram shown below.
1)BH3541F/ BH3544F/ BH3548F
Rise time
Rise time
A PLAY period
A
VCC
B C
OUT
MUTE
Fig. 16
(A):Mute period (Use as pop noise countermeasure when power supply turns ON/OFF by makingVMUTE=Lo.)
(B):Mute cancellation period (This has a time constant because it is used by the externally attached C2 and R2 as
a pop noise countermeasure on mute cancellation, so be careful of the timing.)
(C):Mute start time (As on cancellation, this has a time constant.)
2)BH3547F (MUTE period)
(Rise time) (Fall period)

(PLAY period)
VCC (B)
(A)
Vmute
SG
(Input Signal)
OUT
Fig. 17
(A):Before VCC rise (or at the same time as VCC) make mute cancelled (VMUTE=Hi).
(B):Soft mute period (This time can be set by externally attached R2 and C2)
www.rohm.com
7/8 2010.05 - Rev.A

Ordering part number
B H 3 5 4 1 F - E 2
Part No. Part No. Package Packaging and forming specification

3541 F: SOP8 E2: Embossed tape and reel
3544
3547
3548
ÍÑÐè
äÌ¿°» ¿²¼ Î»»´ ·²º±®³¿¬·±²â
ëòðoðòî
øÓßÈ ëòíë ·²½´«¼» ÞËÎÎ÷ Ì¿°» Û³¾±--»¼ ½¿®®·»® ¬¿°»
õêp
ìp –ìp
è é ê ë Ï«¿²¬·¬§ îëðð°½-
Ûî
Ü·®»½¬·±²
Ì¸» ¼·®»½¬·±² ·- ¬¸» ï°·² ±º °®±¼«½¬ ·- ¿¬ ¬¸» «°°»® ´»º¬ ©¸»² §±« ¸±´¼
±º º»»¼
ø ®»»´ ±² ¬¸» ´»º¬ ¸¿²¼ ¿²¼ §±« °«´´ ±«¬ ¬¸» ¬¿°» ±² ¬¸» ®·¹¸¬ ¸¿²¼ ÷
ï î í ì
ðòëçë
õðòï
ðòïé óðòðë
ðòï Í
ïòîé
Ü·®»½¬·±² ±º º»»¼
ðòìîoðòï ï°·²
øË²·¬ æ ³³÷ Î»»´ Ñ®¼»® ¯«¿²¬·¬§ ²»»¼- ¬± ¾» ³«´¬·°´» ±º ¬¸» ³·²·³«³ ¯«¿²¬·¬§ò
www.rohm.com
8/8 2010.05 - Rev.A

TC58NVG0S3HTA00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
1G BIT (128M  8 BIT) CMOS NAND E PROM
DESCRIPTION
The TC58NVG0S3HTA00 is a single 3.3V 1Gbit (1,140,850,688bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048  128) bytes  64 pages  1024blocks.
The device has a 2176-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes  8 Kbytes: 2176 bytes  64 pages).
The TC58NVG0S3HTA00 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
 Organization
x8
Memory cell array 2176  64K  8
Register 2176  8
Page size 2176 bytes
Block size (128K  8K) bytes
 Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy
 Mode control
Serial input/output
Command control
 Number of valid blocks

Min 1004 blocks
Max 1024 blocks
 Power supply
VCC  2.7V to 3.6V
 Access time
Cell array to register 25 s max
Serial Read Cycle 25 ns min (CL=50pF)
 Program/Erase time
Auto Page Program 300 s/page typ.
Auto Block Erase 2.5 ms/block typ.
 Operating current
Read (25 ns cycle) 30 mA max.
Program (avg.) 30 mA max
Erase (avg.) 30 mA max
Standby 50 A max
 Package
TSOP I 48-P-1220-0.50 (Weight: TBD g typ.)
 8 bit ECC for each 512Byte is required.
1 2012-07-06C
TC58NVG0S3HTA00
PIN ASSIGNMENT (TOP VIEW)
TC58NVG0S3HTA00
8 8
NC 1 48 NC
NC 2 47 NC
NC 3 46 NC
NC 4 45 NC
NC 5 44 I/O8
NC 6 43 I/O7
RY / BY 7 42 I/O6
RE 8 41 I/O5
CE 9 40 NC
NC 10 39 NC
NC 11 38 NC
VCC 12 37 VCC
VSS 13 36 VSS
NC 14 35 NC
NC 15 34 NC
CLE 16 33 NC
ALE 17 32 I/O4
WE 18 31 I/O3
WP 19 30 I/O2
NC 20 29 I/O1
NC 21 28 NC
NC 22 27 NC
NC 23 26 NC
NC 24 25 NC
PIN NAMES
I/O1 to I/O8 I/O port
CE Chip enable
WE Write enable
RE Read enable
CLE Command latch enable
ALE Address latch enable
WP Write protect
RY /BY Ready/Busy
VCC Power supply
VSS Ground
NC No Connection
2 2012-07-06C
TC58NVG0S3HTA00
BLOCK DIAGRAM
VCC VSS
Status register
I/O1 Address register Column buffer

I/O
to Column decoder
Control circuit
I/O8 Command register Data register
Sense amp
CE
Row address decoder

Row address buffer
CLE
decoder
ALE
Logic control Control circuit Memory cell array
WE
RE
WP
RY / BY
RY / BY HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VCC Power Supply Voltage 0.6 to 4.6 V
VIN Input Voltage 0.6 to 4.6 V
VI/O Input /Output Voltage 0.6 to VCC  0.3 ( 4.6 V) V
PD Power Dissipation 0.3 W
TSOLDER Soldering Temperature (10 s) 260 °C
TSTG Storage Temperature 55 to 150 °C
TOPR Operating Temperature 0 to 70 °C
CAPACITANCE *(Ta  25°C, f  1 MHz)
SYMB0L PARAMETER CONDITION MIN MAX UNIT
CIN Input VIN  0 V  10 pF
COUT Output VOUT  0 V  10 pF
* This parameter is periodically sampled and is not tested for every device.
3 2012-07-06C
TC58NVG0S3HTA00
VALID BLOCKS
SYMBOL PARAMETER MIN TYP. MAX UNIT
NVB Number of Valid Blocks 1004  1024 Blocks
NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL PARAMETER MIN TYP. MAX UNIT
VCC Power Supply Voltage 2.7  3.6 V
VIH High Level input Voltage Vcc x 0.8  VCC  0.3 V
VIL Low Level Input Voltage 0.3*  Vcc x 0.2 V
* 2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS (Ta  0 to 70℃, VCC  2.7 to 3.6V)
SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT
IIL Input Leakage Current VIN  0 V to VCC   10 A
ILO Output Leakage Current VOUT  0 V to VCC   10 A
ICCO1 Serial Read Current CE  VIL, IOUT  0 mA, tcycle  25 ns   30 mA
ICCO2 Programming Current    30 mA
ICCO3 Erasing Current    30 mA
ICCS Standby Current CE  VCC  0.2 V, WP  0 V/VCC   50 A
VOH High Level Output Voltage IOH  0.1 mA Vcc – 0.2   V
VOL Low Level Output Voltage IOL  0.1 mA   0.2 V
IOL Output current of RY / BY

VOL  0.2 V  4  mA
( RY / BY ) pin
4 2012-07-06C
TC58NVG0S3HTA00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta  0 to 70℃, VCC  2.7 to 3.6V)
SYMBOL PARAMETER MIN MAX UNIT
tCLS CLE Setup Time 12  ns
tCLH CLE Hold Time 5  ns
tCS CE Setup Time 20  ns
tCH CE Hold Time 5  ns
tWP Write Pulse Width 12  ns
tALS ALE Setup Time 12  ns
tALH ALE Hold Time 5  ns
tDS Data Setup Time 12  ns
tDH Data Hold Time 5  ns
tWC Write Cycle Time 25  ns
tWH WE High Hold Time 10  ns
tWW WP High to WE Low 100  ns
tRR Ready to RE Falling Edge 20  ns
tRW Ready to WE Falling Edge 20  ns
tRP Read Pulse Width 12  ns
tRC Read Cycle Time 25  ns
tREA RE Access Time  20 ns
tCEA CE Access Time  25 ns
tCLR CLE Low to RE Low 10  ns
tAR ALE Low to RE Low 10  ns
tRHOH RE High to Output Hold Time 25  ns
tRLOH RE Low to Output Hold Time 5  ns
tRHZ RE High to Output High Impedance  60 ns
tCHZ CE High to Output High Impedance  20 ns
tCSD CE High to ALE or CLE Don’t Care 0  ns
tREH RE High Hold Time 10  ns
tIR Output-High-impedance-to- RE Falling Edge 0  ns
tRHW RE High to WE Low 30  ns
tWHC WE High to CE Low 30  ns
tWHR WE High to RE Low 60  ns
tR Memory Cell Array to Starting Address  25 s
Data Cache Busy in Read Cache (following 31h and

tDCBSYR1  25 s
3Fh)
tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah)  30 s
tWB WE High to Busy  100 ns
tRST Device Reset Time (Ready/Read/Program/Erase)  5/5/10/500 s
*1: tCLS and tALS can not be shorter than tWP

*2: tCS should be longer than tWP + 8ns.
5 2012-07-06C
TC58NVG0S3HTA00
AC TEST CONDITIONS
CONDITION
PARAMETER
VCC: 2.7 to 3.6V
Input level VCC  0.2 V, 0.2 V
Input pulse rise and fall time 3 ns
Input comparison level Vcc / 2
Output data comparison level Vcc / 2
Output load CL (50 pF)  1 TTL
Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTERISTICS

(Ta  0 to 70℃, VCC  2.7 to 3.6V)
SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES
tPROG Average Programming Time  300 700 s
tDCBSYW2 Data Cache Busy Time in Write Cache (following 15h)   700 s (2)
N Number of Partial Program Cycles in the Same Page   4 (1)
tBERASE Block Erasing Time  2.5 5 ms
(1) Refer to Application Note (12) toward the end of this document.
(2) tDCBSYW2 depends on the timing between internal programming time and data in time.
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH
(25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.
6 2012-07-06C
TC58NVG0S3HTA00
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
CLE
ALE
CE
RE Setup Time Hold Time
WE
tDS tDH
I/O
: VIH or VIL
Command Input Cycle Timing Diagram
CLE
tCLS tCLH
tCS tCH
CE
tWP
WE
tALS tALH
ALE
tDS tDH
I/O
: VIH or VIL
7 2012-07-06C
TC58NVG0S3HTA00
Address Input Cycle Timing Diagram
tCLS tCLH
CLE
tCH tCS tWC tCH

tCS
CE
tWP tWH tWP tWH tWP tWH tWP
WE
tALS tALH
ALE
tDS tDH tDS tDH tDS tDH tDS tDH
I/O CA0 to 7 CA8 to 11 PA0 to 7 PA8 to 15
: VIH or VIL
Data Input Cycle Timing Diagram
tCLS tCLH
CLE
tCS tCH tCS tCH
CE
tALS tALH
tWC
ALE
tWP tWH tWP tWP
WE
tDS tDH tDS tDH tDS tDH
I/O DIN0 DIN1 DIN2175
8 2012-07-06C
TC58NVG0S3HTA00
Serial Read Cycle Timing Diagram
tRC
CE
tRP tREH tRP tRP tCHZ
RE
tRHZ tRHZ tRHZ
tREA tRHOH tREA tRHOH tREA tRHOH
tCEA tCEA
I/O Colu Colu
mn mn
addr
tRR addr
ess ess
A A
RY / BY
: VIH or VIL
Status Read Cycle Timing Diagram
tCLR
CLE
tCLS tCLH
tCS
CE
tWP tCH tCEA
WE tCHZ
tWHC
tWHR
RE
tRHOH
tDS tDH tIR
tREA tRHZ
Status
I/O 70h*
output
RY / BY
: VIH or VIL
*: 70h represents the hexadecimal number
9 2012-07-06C
TC58NVG0S3HTA00
Read Cycle Timing Diagram
tCLR
CLE
tCLS tCLH tCLS tCLH
tCS tCH tCS tCH
CE
tWC
WE
tALH tALS tALH tALS
ALE
tR tRC
RE tWB
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tCEA
tRR
CA0 CA8 PA0 PA8 tREA D DOUT

I/O 00h 30h OUT
to 7 to 11 to 7 to 15 N N1
Data out from

Col. Add. N Col. Add. N
RY / BY
Read Cycle Timing Diagram: When Interrupted by CE

tCLR
CLE
tCLS tCLH tCLS tCLH
tCS tCH tCS tCH
CE
tWC tCSD
WE
tALH tALS tALH tALS
ALE
tR tRC tCHZ
RE tWB
tRHZ
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tCEA
tRR tRHOH
CA0 CA8 PA0 PA8 tREA D DOUT

I/O 00h 30h OUT
to 7 to 11 to 7 to 15 N N1
Col. Add. N Col. Add. N
RY / BY
10 2012-07-06C
TC58NVG0S3HTA00
Read Cycle with Data Cache Timing Diagram (1/2)
tCLR tCLR
CLE
tCLH tCLH tCLH tCLH
tCLS tCLS tCLS tCLS
tCH tCH tCH tCH
tCS tCS tCS tCS
CE
tWC
WE
tALH tALS tALH tALS tRW tCEA tCEA
ALE
tR tDCBSYR1 tRC tDCBSYR1
RE tWB tWB tWB
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tRR tDS tDH tRR tREA
tREA
CA0 CA8 PA0 PA8 DOUT DOUT DOUT

I/O 00h 30h 31h DOUT 31h
to 7 to 11 to 7 to 15 0 1 0
Column address Page address Page address

N* M Page address M M1
RY / BY Col. Add. 0 Col. Add. 0
* The column address will be reset to 0 by the 31h command input. 1
Continues to 1 of next page
11 2012-07-06C
TC58NVG0S3HTA00
Read Cycle with Data Cache Timing Diagram (2/2)
tCLR tCLR tCLR

CLE
tCLH tCLH tCLH
tCLS tCLS tCLS
tCH tCH tCH
tCS tCS tCS
CE
WE
tCEA tCEA tCEA
ALE
tDCBSYR1 tRC tDCBSYR1 tRC tDCBSYR1 tRC
tWB tWB tWB

RE
tDS tDH tDS tDH tDS tDH
tRR tREA tRR tREA tRR tREA
DOUT DOUT DOUT DOUT DOUT DOUT

I/O DOUT 31h DOUT 31h DOUT 3Fh DOUT
0 1 0 1 0 1
Page address Page address M  x
Page address M  1 M2
RY / BY
Col. Add. 0
Col. Add. 0 Col. Add. 0
1 Make sure to terminate the operation with 3Fh command.
Continues from 1 of last page
12 2012-07-06C
TC58NVG0S3HTA00
Column Address Change in Read Cycle Timing Diagram (1/2)
tCLR
CLE
tCLS tCLH tCLS tCLH
tCS tCH tCS tCH

CE
tWC
tCEA
WE
tALH tALS tALH tALS
ALE
tR tRC
tWB
RE
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tRR tREA
CA0 CA8 PA0 PA8 DOUT DOUT DOUT

I/O 00h 30h
to 7 to 11 to 7 to 15 A A1 AN
Page address Page address

P P
RY / BY
Column address
A
Continues from 1 of next page
13 2012-07-06C
TC58NVG0S3HTA00
Column Address Change in Read Cycle Timing Diagram (2/2)
tCLR
CLE
tCLS tCLH tCLS tCLH
tCS tCH tCS tCH
CE
tRHW tWC tCEA
WE
tALH tALS tALH tALS
ALE
tWHR tRC
RE
tDS tDH tDS tDH tDS tDH tDS tDH tREA
tIR
DOUT CA0 CA8 DOUT DOUT DOUT
I/O 05h E0h
AN to 7 to 11 B B1 B  N’
Column address Page address
B P
RY / BY
Column address
B
Continues from 1 of last page
14 2012-07-06C
TC58NVG0S3HTA00
Data Output Timing Diagram
CLE
tCLS tCLH
tCS tCH
CE
WE
tALH
ALE
tRC tCHZ
tRP tREH tRP tRP tRHZ
RE
tREA tREA
tCEA tDS tDH
tREA tRLOH tRLOH
I/O Dout Dout Command
tRR
tRHOH tRHOH
RY / BY
15 2012-07-06C
TC58NVG0S3HTA00
Auto-Program Operation Timing Diagram
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tPROG
tALS
tWB
ALE
RE tDS
tDS
tDS tDH tDS tDH tDH tDH
CA0 CA8 PA0 PA8 DIN Status

I/O 80h DINN DINM* 10h 70h
to 7 to 11 to 7 to 15 N+1 output
Column address
N
RY / BY
: Do not input data while data is being output.
: VIH or VIL
*) M: up to 2175 (byte input data for 8 device).
16 2012-07-06C
TC58NVG0S3HTA00
Auto-Program Operation with Data Cache Timing Diagram (1/3)
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tDCBSYW2
tALS tWB
ALE
RE
tDS tDS
CA0 CA8 PA0 PA8 DIN CA0

I/O 80h DINN 15h 80h
to 7 to 11 to 7 to 15 N+1 to 7
DIN2175
RY / BY
: VIH or VIL
CA0 to CA11 is 0 in this diagram. 1
Continues to 1 of next page
17 2012-07-06C
TC58NVG0S3HTA00
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tALS tDCBSYW2
tWB
ALE
RE
tDS tDS
I/O CA0 CA8 PA0 PA8 DIN CA0

80h DINN 15h 80h
to 7 to 11 to 7 to 15 N+1 to 7
DIN2175
RY / BY
Repeat a max of 62 times (in order to program pages 1 to 62 of a block).

1 2
Continued from 1 of last page
: VIH or VIL
18 2012-07-06C
TC58NVG0S3HTA00
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tALS tPROG (*1)
tWB
ALE
RE
tDS tDS
CA0 CA8 PA0 PA8 DIN

I/O 80h DINN 10h 70h Status
to 7 to 11 to 7 to 15 N+1
DIN2175
RY / BY
: VIH or VIL
2
(*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache
Continued from 2 of last page program, the tPROG during cache programming is given by the following equation.
tPROG  tPROG of the last page  tPROG of the previous page  A

A  (command input cycle  address input cycle  data input cycle time of the last page)
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
(Note) Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by
issuing Status Read command (70h) and make sure the previous page program operation is
completed. If the page program operation is completed issue FFh reset before next operation.
19 2012-07-06C
TC58NVG0S3HTA00
Auto Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
CE
WE
tALH
tALS tWB tBERASE
ALE
RE
tDS tDH
PA0 PA8 Status

I/O 60h D0h 70h
to 7 to 15 output
Busy
RY / BY Auto Block Erase Start Status Read
Erase Setup command command
command
: VIH or VIL : Do not input data while data is being output.
20 2012-07-06C
TC58NVG0S3HTA00
ID Read Operation Timing Diagram
tCLS
CLE
tCLS
tCS tCS tCH tCEA
CE
tCH
WE
tALS tALH
tALH tAR
ALE
RE
tDH
tDS
tREA tREA tREA tREA tREA
If Fail
See See See
I/O 90h 00h 98h F1h Table 5 Table 5 Table 5
ID Read Address Maker code Device code
command 00 コード
: VIH or VIL
21 2012-07-06C
TC58NVG0S3HTA00
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE

The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE

The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.
Chip Enable: CE
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
CE signal is ignored when device is in Busy state ( RY / BY  L), such as during a Program or Erase or Read
operation, and will not enter Standby mode even if the CE input goes High.
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8

The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy: RY / BY
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is
in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
If RY / BY signal is not pulled-up to Vccq( “Open” state ), device operation can not guarantee.
22 2012-07-06C
TC58NVG0S3HTA00
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1
Data Cache 2048 128 I/O8

A page consists of 2176 bytes in which 2048 bytes are
used for main memory storage and 128 bytes are for
redundancy or for other uses.
Page Buffer 2048 128 1 page  2176 bytes
1 block  2176 bytes  64 pages  (128K  8K) bytes
Capacity  2176 bytes  64pages  1024 blocks
64 Pages1 block
65536
pages
1024 blocks
8I/O
2176
An address is read in via the I/O port over four
consecutive clock cycles, as shown in Table 1.
Table 1. Addressing
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

CA0 to CA11: Column address
PA0 to PA15: Page address
First cycle CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second cycle L L L L CA11 CA10 CA9 CA8 PA6 to PA15: Block address
PA0 to PA5: NAND address in block
Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth cycle PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8
23 2012-07-06C
TC58NVG0S3HTA00
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE ,
RE and WP signals, as shown in Table 2.
Table 2. Logic Table

*1
CLE ALE CE WE RE WP
Command Input H L L H *
Data Input L L L H H
Address input L H L H *
Serial Data Output L L L H *
During Program (Busy) * * * * * H
During Erase (Busy) * * * * * H
* * H * * *
During Read (Busy)
* * L H (*2) H (*2) *
Program, Erase Inhibit * * * * * L
Standby * * H * * 0 V/VCC
H: VIH, L: VIL, *: VIH or VIL

*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or
read to device. Reset or Status Read command can be input during Read Busy.
24 2012-07-06C
TC58NVG0S3HTA00
Table 3. Command table (HEX)
First Cycle Second Cycle Acceptable while Busy
Serial Data Input 80 
Read 00 30
Column Address Change in Serial Data Output 05 E0
Read with Data Cache 31 
Read Start for Last Page in Read Cycle with Data Cache 3F 
Auto Page Program 80 10
Column Address Change in Serial Data Input 85 
Auto Program with Data Cache 80 15
Read for Page Copy (2) with Data Out 00 3A
Auto Program with Data Cache during Page Copy (2) 8C 15
Auto Program for last page during Page Copy (2) 8C 10
Auto Block Erase 60 D0
ID Read 90 
Status Read 70  
Reset FF  
HEX data bit assignment

(Example) Serial Data Input: 80h
1 0 0 0 0 0 0 0
8 7 6 5 4 3 2 I/O1
Table 4. Read mode operation states
CLE ALE CE WE RE I/O1 to I/O8 Power
Output select L L L H L Data output Active
Output Deselect L L L H H High impedance Active
H: VIH, L: VIL
25 2012-07-06C
TC58NVG0S3HTA00
DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two
commands, a start address for the Read mode needs to be issued. After initial power on sequence, “00h”
command is latched into the internal command register. Therefore read operation after power on sequence is
excuted by the setting of only five address cycles and “30h” command. Refer to the figures below for the
sequence and the block diagram (Refer to the detailed timing chart.).
CLE
CE
WE
ALE
RE
RY / BY Column Address M Page Address N Busy tR
I/O 00h 30h M M+1 M+2

Page Address N
Start-address input
A data transfer operation from the cell array to the Data
M m
Data Cache Cache via Page Buffer starts on the rising edge of WE in the
30h command input cycle (after the address information has
Page Buffer been latched). The device will be in the Busy state during this
Select page transfer period.
N After the transfer period, the device returns to Ready state.
Cell array
Serial data can be output synchronously with the RE clock
from the start address designated in the address input cycle.
I/O1 to 8: m  2175
Random Column Address Change in Read Cycle
CLE
CE
WE
ALE
RE
RY / BY
Busy
2 tR
Busy Col. M
00h 30h M M1 M2 M3 05h E0h M’ M’1 M’2 M’3 M’4
I/O
Col. M Page N Col. M’

Page N Page N
Start-address input Start from Col. M Start from Col. M’
M M’ During the serial data output from the Data Cache, the column
address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
Select page page.
N
26 2012-07-06C
TC58NVG0S3HTA00
Read Operation with Read Cache
The device has a Read operation with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be
started from the beginning.
CLE
CE
WE
ALE
RE
RY / BY
tR tDCBSYR1 tDCBSYR1 tDCBSYR1
2 3 5 7
Busy Column buffer
1 2 4 6
I/O 00h 30h 31h 0 1 2 3 2175 31h 0 1 2 3 2175 3Fh 0 1 2 3 2175
Col. M Page N Column 0 Page Address N Page Address N  1 Page Address N  2

Data Cache Page N Page N  1 Page N  2
Page Buffer 1 2 Page N Page N  1 Page N  2
3 5 7
4 6
Page N
Cell Array 1 Page N  1
3 Page N  2
5
30h 31h & RE clock 31h & RE clock 3Fh & RE clock
If the 31h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out from the Data Cache, and therefore the tR (Data transfer from memory
cell to data register) will be reduced.
1 Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time period, the device outputs Busy state for tR max.
2 After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again. This data transfer takes tDCBSYR1 max and the completion of this time
period can be detected by Ready/Busy signal.
3 Data of Page N  1 is transferred to Page Buffer from cell while the data of Page N in Data cache can be read out by /RE clock simultaneously.
4 The 31h command makes data of Page N  1 transfer to Data Cache from Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max..
This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
5 Data of Page N  2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data cache can be read out by /RE clock simultaneously
6 The 3Fh command makes the data of Page N  2 transfer to the Data Cache from the Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for
tDCBSYR1 max.. This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
7 Data of Page N  2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page Buffer, the device can accept new command input immediately
after the completion of serial data out.
27 2012-07-06C
TC58NVG0S3HTA00
Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
CLE
CE
WE
ALE
RE
RY /BY
Status
I/O 80h Din Din Din Din 10h 70h Out
Col. M Page P Data
Data input The data is transferred (programmed) from the register to the
Program Read& verification selected page on the rising edge of WE following input of the
“10h” command. After programming, the programmed data is
Selected
transferred back to the register to be automatically verified by the
page
device. If the programming does not succeed, the Program/Verify
operation is repeated by the device until success is achieved or until
the maximum loop number set in the device is reached.
Random Column Address Change in Auto Page Program Operation

The column address can be changed by the 85h command during the data input sequence of the Auto Page Program
operation.
Two address input cycles after the 85h command are recognized as a new column address for the data input. After
the new data is input to the new column address, the 10h command initiates the actual data program into the
selected page automatically. The Random Column Address Change operation can be repeated multiple times within
the same page.
80h Din Din Din Din 85h Din Din Din Din 10h 70h Status
Col. M Page N Col. M’

BUSY
90h
Col. M Col. M’
Data input
Program Reading & verification

Selected
page
28 2012-07-06C
TC58NVG0S3HTA00
Auto Page Program Operation with Data Cache
The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes this
sequenced has to be started from the beginning.
CLE
CE
WE
ALE
RE
RY / BY
tDCBSYW2 tDCBSYW2 tPROG (NOTE)
I/O 80h Add Add Add Din Din Din 15h 70h 80h Add Add Add Add Din Din Din 15h 70h 80h Add Add Add Add Din Din Din 10h 70h
Page N Status Output Page N  1 Status Output Page N  P 5 6 Status Output

1 2 3 4
Data for Page N 2 3 Data for Page N  1 5 Data for Page N  P

Data Cache
4
Page Buffer 1 Data for Page N Data for Page N  1
3
Cell Array Page N 5 6

Page N  1
Page N  P  1 Page N  P
Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache
1 Data for Page N is input to Data Cache.
2 Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs Busy State (t DCBSYW2).
3 Data is programmed to the selected page while the data for page N  1 is input to the Data Cache.
4 By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the programming of page N is completed. The device output busy state from the 15h command
until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of page N and serial data input for Page N  1 (tDCBSYW2).
5 Data for Page N  P is input to the Data Cache while the data of the Page N  P  1 is being programmed.
6 The programming with Data Cache is terminated by the 10h command. When the device becomes Ready, it shows that the internal programming of the Page  P is completed.
NOTE: Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following;
tPROG  tPROG for the last page  tPROG of the previous page  ( command input cycle  address input cycle  data input cycle time of the previous page)
29 2012-07-06C
TC58NVG0S3HTA00
Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation can be detected by the Status Read operation.
 I/O1 : Pass/fail of the current page program operation.
 I/O2 : Pass/fail of the previous page program operation.
The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions.
 Status on I/O1: Page Buffer Ready/Busy is Ready State.
The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or RY / BY pin after the 10h command
 Status on I/O2: Data Cache Read/Busy is Ready State.
The Data Cache Ready/Busy is output on I/O7 by Status Read operation or RY / BY pin after the 15h command.
Example)
I/O2 => Invalid Page 1 Page 1 Page N  2 invalid Page N  1
I/O1 => Invalid Invalid Page 2 Invalid invalid Page N
Status Status Status 80h…15h Status Status Status

80h…15h 70h Out 80h…15h 70h Out 70h Out 70h Out 80h…10h 70h Out 70h Out
Page 1 Page 2 Page N  1 Page N
RY/BY pin
Data Cache Busy
Page 1
Page Buffer Busy
Page 2
Page N  1
Page N
If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during
this Ready period, the Status Read provides pass/fail for Page 2 on I/O1 and pass/fail result for Page1 on I/O2
30 2012-07-06C
TC58NVG0S3HTA00
Page Copy (2)
By using Page Copy (2), data in a page can be copied to another page after the data has been read out.
When the block address changes (increments) this sequenced has to be started from the beginning.
Command 2 3
input
00 Address input 30 Data output 8C Address input Data input 15 00 Address input 3A Data output A
Address Col = 0 start Address When changing data,
Address Col = 0 start
CA0 to CA11, PA0 to PA15 CA0 to CA11, PA0 to PA15 changed data is input. CA0 to CA11, PA0 to PA15
(Page N) (Page M) (Page N+P1)
1 4 5
A
RY/BY tR tDCBSYW2 tDCBSYR2
1 Data for Page N 2 Data for Page N 3 Data for Page M 4 5 Data for Page N + P1
Data Cache
Page Buffer
Cell Array
Page M
Page N Page N + P1
Page Copy (2) operation is as following.

1 Data for Page N is transferred to the Data Cache.
2 Data for Page N is read out.
3 Copy Page address M is input and if the data needs to be changed, changed data is input.
4 Data Cache for Page M is transferred to the Page Buffer.
5 After the Ready state, Data for Page N  P1 is output from the Data Cache while the data of Page M is being programmed.
31 2012-07-06C
TC58NVG0S3HTA00
Command 6
input
A 8C Address input Data input 15 00 Address input 3A Data output 00 Address input 3A Data output B
Address When changing data,
Address Col = 0 start Address Col = 0 start
CA0 to CA11, PA0 to PA15 changed data is input. CA0 to CA11, PA0 to PA15 CA0 to CA11, PA0 to PA15
(Page M+R1) (Page N+P2) (Page N+Pn)
7 8 9
RY / BY A B
tDCBSYW2 tDCBSYR2 tDCBSYR2
6 7 8 9
Data for Page M  R1 Data for Page M  R1 Data for Page N  P2 Data for Page N  Pn
Data Cache
Page Buffer
Page M  Rn  1 Page M + Rn  1
Cell Array Page M  R1
Page M
Page N  Pn
Page N + P2
Page N  P1
6 Copy Page address (M  R1) is input and if the data needs to be changed, changed data is input.
7 After programming of page M is completed, Data Cache for Page M  R1 is transferred to the Page Buffer.
8 By the 15h command, the data in the Page Buffer is programmed to Page M  R1. Data for Page N  P2 is transferred to the Data cache.
9 The data in the Page Buffer is programmed to Page M  Rn  1. Data for Page N  Pn is transferred to the Data Cache.
32 2012-07-06C
TC58NVG0S3HTA00
Command 10
input
B 8C Address input Data input 10 70 Status output
Address
CA0 to CA11, PA0 to PA15
(Page M+Rn)
11
RY / BY B
tPROG (*1)
Data for Page M  Rn Data for Page M  Rn

10 11
Data Cache
Page Buffer
Page M + Rn
Page M  Rn  1
Cell Array
10 Copy Page address (M  Rn) is input and if the data needs to be changed, changed data is input.
11 By issuing the 10h command, the data in the Page Buffer is programmed to Page M  Rn.
(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG here will be expected as the following,
tPROG  tPROG of the last page  tPROG of the previous page  ( command input cycle  address input cycle + data output/input cycle time of the last page)
NOTE)
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
Make sure WP is held to High level when Page Copy (2) operation is performed.
Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence
33 2012-07-06C
TC58NVG0S3HTA00
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Pass
60 D0 70 I/O
Block Address Erase Start Status Read Fail
input: 2 cycles command command
RY / BY Busy
34 2012-07-06C
TC58NVG0S3HTA00
ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:
CLE
tCEA
CE
WE
tAR
ALE
RE
tREA
See See See
I/O 90h 00h 98h F1h
table 5 table 5 table 5
ID Read Address 00 Maker code Device code 3rd Data 4th Data 5th Data
command
Table 5. Code table
Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data
1st Data Maker Code 1 0 0 1 1 0 0 0 98h
2nd Data Device Code 1 1 1 1 0 0 0 1 F1h
3rd Data Chip Number, Cell Type 1 0 0 0 0 0 0 0 80h
4th Data Page Size, Block Size, 0 0 0 1 0 1 0 1 15h
5th Data Plane Number 0 1 1 1 0 0 1 0 72h
3rd Data
Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
1 0 0
2 0 1
Internal Chip Number
4 1 0
8 1 1
2 level cell 0 0
4 level cell 0 1
Cell Type
8 level cell 1 0
16 level cell 1 1
Reserved 1 0 0 0
35 2012-07-06C
TC58NVG0S3HTA00
4th Data
1 KB 0 0
Page Size 2 KB 0 1
(without redundant area) 4 KB 1 0
8 KB 1 1
64 KB 0 0
Block Size 128 KB 0 1
(without redundant area) 256 KB 1 0
512 KB 1 1
x8 0
I/O Width
x16 1
Reserved 0 0 1
5th Data
1 Plane 0 0
2 Plane 0 1
Plane Number
4 Plane 1 0
8 Plane 1 1
Reserved 0 1 1 1 1 0
36 2012-07-06C
TC58NVG0S3HTA00
Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass
/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is
output via the I/O port using RE after a “70h” command input. The Status Read can also be used during a
Read operation to find out the Ready/Busy status.
The resulting information is outlined in Table 6.
Table 6. Status output table
Page Program Read

Definition Cache Program
Block Erase Cache Read
Chip Status1
I/O1 Pass/Fail Pass/Fail Invalid
Pass: 0 Fail: 1
Chip Status 2
I/O2 Invalid Pass/Fail Invalid
Pass: 0 Fail: 1
I/O3 Not Used 0 0 0
I/O4 Not Used 0 0 0
I/O5 Not Used 0 0 0
Page Buffer Ready/Busy

I/O6 Ready/Busy Ready/Busy Ready/Busy
Ready: 1 Busy: 0
Data Cache Ready/Busy

I/O7 Ready/Busy Ready/Busy Ready/Busy
Ready: 1 Busy: 0
Write Protect
I/O8 Write Protect Write Protect Write Protect
Not Protected :1 Protected: 0
The Pass/Fail status on I/O1 and I/O2 is only valid during a Program/Erase operation when the device is in the Ready state.
Chip Status 1:
During a Auto Page Program or Auto Block Erase operation this bit indicates the pass/fail result.
During a Auto Page Programming with Data Cache operation, this bit shows the pass/fail results of the
current page program operation, and therefore this bit is only valid when I/O6 shows the Ready state.
Chip Status 2:
This bit shows the pass/fail result of the previous page program operation during Auto Page Programming
with Data Cache. This status is valid when I/O7 shows the Ready State.
The status output on the I/O6 is the same as that of I/O7 if the command input just before the 70h is not
15h or 31h.
37 2012-07-06C
TC58NVG0S3HTA00
An application example with multiple devices is shown in the figure below.
CE1 CE 2 CE 3 CEN CEN  1
CLE
ALE Device Device Device Device Device
WE 1 2 3 N N1
RE
I/O1
to I/O8
RY / BY
RY / BY Busy
CLE
ALE
WE
CE1
CEN
RE
I/O 70h 70h
Status on Device 1 Status on Device N
System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.
Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
Reset during a Cache Program/Page Copy may not just stop the most recent page program but it may also
stop the previous program to a page depending on when the FF reset is input.
The response to a “FFh” Reset command input during the various device operations is as follows:
When a Reset (FFh) command is input during programming
80 10 FF 00
Internal VPP
RY / BY
tRST (max 10 s)
38 2012-07-06C
TC58NVG0S3HTA00
When a Reset (FFh) command is input during erasing
D0 FF 00
Internal erase
voltage
RY / BY
tRST (max 500 s)
When a Reset (FFh) command is input during Read operation
00 30 FF 00
RY / BY
tRST (max 5 s)
When a Reset (FFh) command is input during Ready
FF 00
RY / BY
tRST (max 5 s)
When a Status Read command (70h) is input after a Reset
FF 70
I/O status: Pass/Fail  Pass
: Ready/Busy  Ready
RY / BY
When two or more Reset commands are input in succession
(1) (2) (3)
10 FF FF FF
RY / BY
The second FF command is invalid, but the third FF command is valid.
39 2012-07-06C
TC58NVG0S3HTA00
APPLICATION NOTES AND COMMENTS
(1) Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h.
The WP signal is useful for protecting against data corruption at power-on/off.
2.7 V 2.7 V
2.5 V 2.5 V
≥ 1ms
VCC 0.5 V 0.5 V
0 V
Don’t Don’t Don’t
care care care
CE , WE , RE
CLE, ALE
VIH
VIL VIL
WP 1 ms max 1 ms max
100 s max Operation 100 s max
Invalid Invalid Invalid
Ready/Busy
(2) Power-on Reset

The following sequence is necessary because some input signals may not be stable at power-on.
Power on FF
Reset
(3) Prohibition of unspecified commands

The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4) Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h and FFh.
40 2012-07-06C
TC58NVG0S3HTA00
(5) Acceptable commands after Serial Input command “80h”
Once the Serial Input command “80h” has been input, do not input any command other than the Column
Address Change in Serial Data Input command “85h”, Auto Program command “10h”, Auto Program with
Data Cache Command “15h”, or the Reset command “FFh”.
80 FF
WE
Address input
RY / BY
If a command other than “85h” , “10h”, “15h” or “FFh” is input, the Program operation is not performed
and the device operation is set to the mode which the input command specifies.
80 XX 10
Mode specified by the command. Programming cannot be executed.
Command other than

“85h”, “10h”, “15h” or “FFh”
(6) Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page Ex.) Random page program (Prohibition)
DATA IN: Data (1) Data (64) DATA IN: Data (1) Data (64)
Data register Data register
Page 0 (1) Page 0 (2)

Page 1 (2) Page 1 (32)
Page 2 (3) Page 2 (3)
Page 31 (32) Page 31 (1)
Page 63 (64) Page 63 (64)
41 2012-07-06C
TC58NVG0S3HTA00
(7) Status Read during a Read operation
00
[A]
Command 00 30 70
CE
WE
RY /BY
RE
Address N Status Read
command input Status output
Status Read
.
The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the
device has been set to Status Read mode by a “70h” command, the device will not return to Read mode
unless the Read command “00h” is inputted during [A]. If the Read command “00h” is inputted during [A],
Status Read mode is reset, and the device returns to Read mode. In this case, data output starts
automatically from address N and address input is unnecessary
(8) Auto programming failure
Fail
80 10 70 I/O 80 10
Address Data Address Data
M input N input
80
If the programming result for page address M is Fail, do not try to program the
10 page to address N in another block without the data input sequence.
Because the previous input data has been lost, the same input sequence of 80h
M command, address and data is necessary.
(9) RY / BY : termination for the Ready/Busy pin ( RY / BY )

A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain
circuit.
VCC
Ready
VCC
VCC
R
Device Busy
RY / BY
CL tf tr
VSS VCC  3.3 V

Ta  25°C
1.5 s CL  50 pF 15 ns
tf
tr 1.0 s 10 ns tf
tr
This data may vary from device to device. 0.5 s 5 ns
We recommend that you use this data as a
reference when selecting a resistor value. 0 1 K 2 K 3 K 4 K
R
42 2012-07-06C
TC58NVG0S3HTA00
(10) Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:
Enable Programming
WE
DIN 80 10
WP
RY / BY
tWW (100 ns MIN)
Disable Programming
WE
DIN 80 10
WP
RY / BY
tWW (100 ns MIN)
Enable Erasing
WE
DIN 60 D0
WP
RY / BY
tWW (100 ns MIN)
Disable Erasing
WE
DIN 60 D0
WP
RY / BY
tWW (100 ns MIN)
43 2012-07-06C
TC58NVG0S3HTA00
(11) When five address cycles are input
Although the device may read in a fifth address, it is ignored inside the chip.
Read operation
CLE
CE
WE
ALE
I/O 00h 30h

Ignored
Address input
RY / BY
Program operation
CLE
CE
WE
ALE
I/O 80h
Ignored
Address input Data input
44 2012-07-06C
TC58NVG0S3HTA00
(12) Several programming cycles on the same page (Partial Page Program)
Each segment can be programmed individually as follows:
1st programming Data Pattern 1 All 1 s
2nd programming All 1 s Data Pattern 2 All 1 s
4th programming All 1 s Data Pattern 4
Result Data Pattern 1 Data Pattern 2 Data Pattern 4
45 2012-07-06C
TC58NVG0S3HTA00
(13) Invalid blocks (bad blocks)
The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:
Please do not perform an erase operation to bad blocks. It may be

impossible to recover the bad block information if the information is
erased.
Bad Block
Check if the device has any bad blocks after installation into the system.
Refer to the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
Bad Block
isolated from the bit lines by select gates.
The number of valid blocks over the device lifetime is as follows:
MIN TYP. MAX UNIT
Valid (Good) Block Number 1004  1024 Block
Bad Block Test Flow
Regarding invalid blocks, bad block mark is in whole pages.

Please read one column of any page in each block. If the data of the column is 00 (Hex), define the block as a bad
block.
Start
Block No  1
Fail
Read Check
Pass
Block No.  Block No.  1 Bad Block *1
No
Last Block
Yes
End
*1: No erase operation is allowed to detected bad blocks
46 2012-07-06C
TC58NVG0S3HTA00
(14) Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.

The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE
Block Erase Failure Status Read after Erase  Block Replacement
Page Programming Failure Status Read after Program  Block Replacement
Read Bit Error ECC Correction / Block Refresh
 ECC: Error Correction Code. 8 bit correction per 512 Bytes is necessary.
 Block Replacement
Program
Error occurs When an error happens in Block A, try to reprogram the

Buffer data into another Block (Block B) by loading from an
memory external buffer. Then, prevent further system accesses
Block A
to Block A ( by creating a bad block table or by using
another appropriate scheme).
Block B
Erase
When an error occurs during an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).
(15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.
47 2012-07-06C
TC58NVG0S3HTA00
(16) Reliability Guidance
This reliability guidance is intended to notify some guidance related to using NAND flash with
TBD bit ECC for each 512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.
Although random bit errors may occur during use, it does not necessarily mean that a block is bad.
Generally, a block should be marked as bad when a program status failure or erase status failure is detected.
The other failure modes may be recovered by a block erase.
ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.
 Write/Erase Endurance
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read
after either an auto program or auto block erase operation. The cumulative bad block count will increase
along with the number of write/erase cycles.
 Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge
gain. After block erasure and reprogramming, the block may become usable again.
Here is the combined characteristics image of Write/Erase Endurance and Data Retention.
Data
Retention
[Years]
Write/Erase Endurance [Cycles]
 Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit
errors occur on other pages in the block, not the page being read. After a large number of read cycles
(between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another
state. After block erasure and reprogramming, the block may become usable again.
48 2012-07-06C
TC58NVG0S3HTA00
Package Dimensions
Weight: TBDg (typ.)
49 2012-07-06C
TC58NVG0S3HTA00
Revision History
Date Rev. Description

2012-02-17 0.10 Initial Release
2012-07-06 0.20 Described ECC bit number: 8, Changed tBERASE, Revised ID Table, Corrected typo.
50 2012-07-06C
TC58NVG0S3HTA00
RESTRICTIONS ON PRODUCT USE
 Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
 This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
 Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
 PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH
MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without
limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for
automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions,
safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. IF YOU USE
PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your
TOSHIBA sales representative.
 Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
 Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
 The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
 ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO
SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
 Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the
U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited
except in compliance with all applicable export laws and regulations.
 Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES
OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
51 2012-07-06C
HDMI1
HDMI输入X2
MHL HDMI2 NAND_FLASH
2GBITS
SPI FLASH
16MBITS
VGA输入X1 VGA I2C EEPROM

32KBITS
YUV
MSDXXX
YUVI输入X1 LVDS PANLE
AV输入X1 AV1
L L_OUT
USB1 MSD9010
USB输入 R R_OUT
L
EARPHONE
R
AV_L/R
YUV_L/R
VGA_L/R
SCART_L/R
AV_OUT
L/R_OUT
IF1
IF2
TUNE输入遥控接收、键控板
IF 音频输入X2 AV音视频光感接收、指示板
输出
5 4 3 2 1
+3.3V_Standby
H :Power on
L :Power off
R2
1.5V Power for DDR3(OK)
4.7KΩ
+12V_PWR
STANDBY
PWR_ON/OFF 本页网络其他页网络
电阻参数更改，位置更改。 Vout=1.25x(1+(R1/R2)) AS1117L/TR-HF
PWR_ON/OFF
D0S1 +3.3V_Standby
7.5V VBL_CTRL
+5V_Normal R1 R2 Vout
+5V_Normal
330Ω 200Ω 3.3V BL-ON/OFF
BL-ON/OFF
4
+12V_PWR
330Ω 330Ω 2.5V BL-ADJUST
+3.3V_Standby BL-ADJUST
OUT
R5 * 22R1 100Ω 1.5V U3
R1S3
10KΩ NC/1KΩ R1=R2P13 R14
100Ω
OUT
ADJ
BL-ON/OFF R4
IN
BL-ON/OFF 10KΩ R2=R3P2 +1.15V_VDDC
3
BL-ON/OFF +1.5V_DDR
3
1 VBL_CTRL +3.3V_Normal
D D
R17 R6 +3.3V_Normal +1.5V_DDR

1KΩ
2
KMBT3904
NC/10KΩ 改LG PANEL
Q3 掉电屏闪 C13 C76 C16
R15
22Ω PWR_ON/OFF
10uF 10uF 100nF
VBL_CTRL
BL-ON/OFF
Inverter controler 反馈电阻参数更改。
BL-ADJUST
BL-ON/OFF
2、PCB排版时输入电容和输出电容尽量靠近IC BL-ADJUST
+5V_Normal
3.3V_Normal(ok)
R133
1KΩ
+5V_Normal
4
U6
OUT
BL/ADJUST
BL/ADJUST
R129 +3.3V_Normal
OUT
ADJ
1KΩ
3
IN
ON/OFF
1 +3.3V_TU
R266 LD1117-3.3 EN
C126 R169 Q10 4.7KΩ CN15
3
3
ADJ
12KΩ KMBT3904 1 R131 BL-ADJUST
2.2uF
2
BL-ADJUST 1 BL-ON/OFF
Q20 10KΩ 2 R104 BL/ADJUST
KMBT3904 3 0Ω
2
+5V_Normal 4 STANDBY
5
C32 C33 C34 C35 6
7
10uF
1.15V 2A for VDDC 2.2uF 100nF 100nF 8
9
10 +12V_PWR
11
2、PCB排版时输入电容和输出电容尽量靠近IC 12
反馈电阻参数更改。 POW-GND
PWR_12V
功率电感用优选料。 CN_M
+12V_PWR FB2 60Ω/100MHz
1.15V MAX 3A
C +1.15V_VDDC C
U4 C17
R16 L2 10uH
4 5
3 GND BST 6
2 SW EN/SYNC 7 22Ω 100nF C219
R18
1 IN VCC 8
5、+12V_PWR转+5V_NOR（2A） AAM FB 47pF
1.05KΩ
STANDBY
C18 C20 C22 C23
MHL做待机充电时，选用1495，无待机充电时，选用1494. MP1495DJ-LF-Z R103
604Ω
C21
10uF 100nF R20 10uF 22uF 100nF
+12V_PWR FB3 60Ω/100MHz R19 100KΩ
82KΩ
+5V_Normal C24
U5 C25
L3 10uH 100nF R21
R23 22Ω
4 5 3.65KΩ
3 GND BST 6
SW EN/SYNC R51
2 7 100nF C220 NC/10KΩ
IN VCC R25
1 8
AAM FB 47pF 20KΩ
STANDBY MP1494DJ-LF-Z
C28 470uF C30
C26
+
C121
10uF R27
100nF CE2 100nF
10uF Rt R1 R2 Vout 2、PCB排版时输入电容和输出电容尽量靠近IC
82KΩ R26 33KΩ 33K 20K 3.6K 5.0V PCB排版时储能电感要尽量靠近IC
C31
100nF
R28 33K 11.25K 3.6K 3.3V
3、通过增大输入和输出电容的容量可以减小纹波的大小
3.65KΩ
R29
NC/10KΩ 100K
33K 3.15K 3.6K
1.65K 3.65K 1.15V

1.5V
选择小ESR值的电容也可以减小纹波的大小 5、+12V_NOR转+3.3V_STB（3A）
（DC-DC价格0.13USD 规格标称最大3A　500KHZ 输入电压范围4.5V-16V 轻载高效　优选）
Vout=0.8x(1+(R1/R2)) 考虑到DC-DC的温升问题.，输出为5V时，最大负载不能超过2.4A
R1=R2P8 Rt=R3P3
Rt R1 R2 Vout
R2=R3P8 R3P2 C3P2 +3.3V_Standby
U2 22Ω 100nF L0P5 10uH
33K 20K 3.6K 5.0V 说明：1、该电路当前的参数是输出+5V_NOR. +12V_PWR 4 5
60Ω/100MHz 3 GND BST 6
33K 11.25K 3.6K 3.3V
如果要输出其他电压，如3.3V;1.5V;1.2V可以 FB0P5
2 SW EN/SYNC 7 R3P4 C3P5 CE1P0
33K 3.15K 3.6K 1.5V 1 IN VCC 8 FB2 1.3KΩ C3P3 C3P4
按照表格里的参数调整R1和R2的大小就可以了
+
C2P9 C3P0 AAM FB R3P1
33K 1.8K 3.6K 1.2V CE0P9
MP1495DJ-LF-Z R3P0 10KΩ C3P1 10uF 100nF 100uF
2、PCB排版时输入电容和输出电容尽量靠近IC 5V NORMAL SW(OK) C218 10uF
+
R3P5
Vout=0.8x(1+(R1/R2)) 100uF
10uF 100nF R2P8
100KΩ
82KΩ 100nF
30KΩ 47pF
PCB排版时储能电感要尽量靠近IC
R1=R2P8 FB2
R2=R3P8 3、通过增大输入和输出电容的容量可以减小纹波的大小 R2P9 R3P3 R3P6
B Rt=R3P3 选择小ESR值的电容也可以减小纹波的大小 +3.3V_Standby
NC/100KΩ 75KΩ 10KΩ
B
U8
3 2 说明：1、该电路当前的参数是输出+5V_NOR. 如果要输出其他电压，如3.3V;2.5V;1.5V可以按照表格里的参数调整R1和R2的大小就可以了
+3.3V_Normal
C36 AO3401A 2、PCB排版时输入电容和输出电容尽量靠近IC PCB排版时储能电感要尽量靠近IC
R30
3、通过增大输入和输出电容的容量可以减小纹波的大小选择小ESR值的电容也可以减小纹波的大小
1
10KΩ 220nF
R31
4、输入输出电容的材质推荐使用X5R或者X7R,不能使用Y5V材质,注意耐压值.
3
R32 100KΩ
STANDBY 1 Q5 5、模块成本仅供参考,受元器件价格及汇率影响会有变化(成本统计时间20140103)
10KΩ KMBT3904
6、EN端的电压根据实际使用的需要可以进行调整
2
Vout=0.807x(1+(R1/R2))
If power input has change,
this part will do option R1=R3P4+R3P5 R2=R3P6 Rt=R3P3 L=L0P5
R1(推荐编号) R2(推荐编号) RT(推荐编号) Vout L(推荐编号) 最大负载模块成本
4100-CA5130-2200(51KΩ)+4100-CA1820-2200((1.8KΩ) 4100-CA1030-2200(10KΩ) 4100-CA7530-2200(75KΩ) 5.07V 4800-S11000-AS80(10uH) 2.4A
Test Point & MARK(OK) 4100-CA3030-2200(30KΩ)+4100-CA1320-2200(1.3KΩ)

4100-CA2030-2200(20KΩ)+4100-CA1020-2200(1KΩ)
4100-CA1030-2200(10KΩ)
4100-CA1030-2200(10KΩ)
4100-CA7530-2200(75KΩ)
4100-CA7530-2200(75KΩ)
3.33V 4800-S11000-AS80(10uH)
2.5V 4800-S123A0-DS00(2.3uH)
2.5A
2.6A
1.3653RMB
4100-CA1030-2200(10KΩ)+4100-CA2720-2200(2.7KΩ) 4100-CA1030-2200(10KΩ) 4100-CA7530-2200(75KΩ) 1.83V 4800-S123A0-DS00(2.3uH) 2.7A

4100-CA7520-2200(7.5KΩ)+4100-CA1320-2200((1.3KΩ) 4100-CA1030-2200(10KΩ) 4100-CA7530-2200(75KΩ) 1.52V 4800-S123A0-DS00(2.3uH) 2.8A 1.39RMB
4100-CA5120-2200(5.1KΩ)+4100-CA0000-2200(0Ω) 4100-CA1030-2200(10KΩ) 4100-CA7530-2200(75KΩ) 1.22V 4800-S123A0-DS00(2.3uH) 2.9A
MK8 MK5
MK1 MK2 H1 H2 H3 H4 H5
8
2
9
7
8
2
9
8
2
9
8
2
9
8
2
9
7 7 7 7 MARK MARK
MARK MARK 3 1 3 1 3 1 3 1 3 1 MK7 MK6
MK3 MK4 6 6 6 6 6
5
4
5
4
5
4
5
4
5
4
Screw Hole Screw Hole Screw Hole Screw Hole Screw Hole
MARK
MARK MARK
MARK
A A
Title
SYSTEM POWER
Size Document Number Rev

D 1.0
Date: Wednesday, September 17, 2014 Sheet 1 of 13

5 4 3 2 1
5 4 3 2 1
D
RESET 本页网络其他页网络
System_RST
System_RST D
System_RST
System_RST
+3.3V_Standby
3
R88
D5
1MΩ BAV99
C109
1
1uF
2
R90 Q8
C 1 C
MMBT3906
100KΩ
R91 1KΩ
3
C111 System_RST
1uF System_RST
R94 C112
100KΩ 1nF
C109，C111更改为1uF
复位脉宽240mS
B B
A A
Title
<Title>

A <Doc> <RevCode>
Date: Tuesday, May 06, 2014 Sheet 1 of 1

5 4 3 2 1
5 4 3 2 1
video Close to MST IC

NAND & CI & TS & Front End POWER&GND
RGB Interface with wide trace
VGA-R
R33
R34
33Ω
68Ω
C41
C42
47nF
47nF
RIN0
GIN0N U9B 本页网络其他页网络
R35 33Ω C43 47nF GIN0
VGA-G BIN0 T19 W14 VGA-R
VGA R36 33Ω C44 47nF
VGA-B T21 PCM_D0 TS0_D0 U16 VGA-G
U9F +1.5V_DDR +1.15V_VDDC
HSYNC0 T20 PCM_D1 TS0_D1 T16 HSYNC0 VGA-B
VGA-HSYNC PCM_D2 TS0_D2 +3.3V_Normal VGA-HSYNC
VSYNC0 Y18 Y13 A14 B16 VSYNC0
TS IN
VGA-VSYNC PCM_D3 TS0_D3 VDDC AVDD_DDR_CMD0 +3.3V_Standby VGA-VSYNC
AA18 AA15 B14 J10 VIDEO_IN
PCM_D4 TS0_D4 +1.15V_VDDC VDDC AVDD_DDR_CMD0 VIDEO_IN
W19 Y15 C13 HD-LIN
PCM_D5 TS0_D5 VDDC +1.5V_DDR HD-LIN
Y17 Y14 C14 A16 HD-RIN
PCM_D6 TS0_D6 VDDC AVDD_DDR_DATA0 +3.3V_TU HD-RIN
AA19 V15 E14 J11
PCM_D7 TS0_D7 W15 F13 VDDC AVDD_DDR_DATA0 J12 EARPHONE-OUTL
U9E V19 TS0_CLK W16 G9 VDDC AVDD_DDR_DATA0 K12 VGA-R PM_CONFIG0 EARPHONE-OUTR
U20 PCM_A0 TS0_VLD V16 G10 VDDC AVDD_DDR_DATA0 VGA-G PM_CONFIG0
RIN0 H3 B9 MDI_RN W20 PCM_A1 TS0_SYNC G11 VDDC A17 HSYNC0 VGA-B UART-TX
R37 33Ω C47 47nF RIN1 GIN0N G2 RIN0P RN C9 MDI_RP MDI_RN Y16 PCM_A2 AA13 G12 VDDC AVDD_DRAM B17 VSYNC0 VGA-HSYNC M-SCL UART-RX
YPBPR-R
PHY
GIN0M RP MDI_RP PCM_A3 TS1_D0 VDDC AVDD_DRAM VGA-VSYNC M-SCL
GIN0 G1 B8 MDI_TN P19 W13 H9 VIDEO_IN M-SDA
VGA
GIN1N BIN0 G3 GIN0P TN C8 MDI_TP MDI_TN R20 PCM_A4 TS1_D1 U13 J9 VDDC HD-LIN VIDEO_IN M-SDA
R40 68Ω C45 47nF
HSYNC0 G4 BIN0P TP MDI_TP T18 PCM_A5 TS1_D2 V13 VDDC M8 HD-RIN HD-LIN DIFP
TS OUT
YPBPR-G R41 33Ω C48 47nF GIN1 HSYNC0 PCM_A6 TS1_D3 VDDP VDDP HD-RIN DIFM
YPBPR-G VSYNC0 G5 U19 T12 B13 N8
VSYNC0 PCM_A7 TS1_D4 DVDD_DDR VDDP EARPHONE-OUTL IF-AGC-T
R38 33Ω C46 47nF BIN1 Y19 T15 H10 ANT_P_DET ANT_P_DET
YPBPR YPBPR-B W21 PCM_A8 TS1_D5 U15 DVDD_DDR N9 PM_CONFIG0 EARPHONE-OUTR HP_DET
PCM
PCM_A9 TS1_D6 AVDD_PLL AVDD_PLL PM_CONFIG0 HP_DET
RIN1 K3 W17 U14
YPBPR
R39 0Ω C49 47nF SOG1 MODE
GIN1N J1 RIN1P Y20 PCM_A10 TS1_D7 T13 A13 M10 UART-TX
GIN1M PCM_A11 TS1_CLK DVDD_RX_0 AVDD_MOD AVDD_MOD UART-RX System_RST
GIN1 J2 A12 USB0_DM U18 U12 H11 N10 M-SCL
BIN1 H2 GIN1P DM_P0 B12 USB0_DP USB0_DM V21 PCM_A12 TS1_VLD T14 DVDD_RX_0 AVDD_MOD M-SDA M-SCL AMP_MUTE CVBS_OUT
USB
SOG1 J3 BIN1P DP_P0 AA7 USB1_DM USB0_DP U17 PCM_A13 TS1_SYNC M-SDA BL-ADJUST AMP_MUTE
SOGIN1 DM_P1 Y7 USB1_DP USB1_DM PCM_A14 K9 V3 DIFP PM_TX BL-ADJUST
DP_P1 USB1_DP AVDDL_MOD AVDDL_MOD AVDD5V_MHL_C AVDD5V_MHL_C DIFM PANEL_ON/OFF
D T17 D4 PM_RX D
PCM_CD_N AVDD5V_MHL_D IF-AGC-T VBL_CTRL
Close to MST IC L2 W18 ANT_P_DET ANT_P_DET EEPROM_WP
L3 RIN2P AA20 PCM_CE_N HP_DET PWR_ON/OFF EEPROM_WP
SCART
AV Interface with wide trace K2
K1
GIN2M
GIN2P
Y21
V18
PCM_IORD_N
PCM_IOWR_N VIFP
V1
W1
VIFP
VIFM
DVDD_NODIE
H7
DVDD_NODIE VSENSE_VDD
R15 HP_DET
MODE
LVA0N
PWR_ON/OFF
H5 BIN2P M1 AA16 PCM_IRQA_N VIFM J6 R13 System_RST LVA0P LVA0N
CVBS
AVDD_NODIE
VIF
H4 HSYNC2 CVBS1P N1 CVBS0 V20 PCM_OE_N AVDD_NODIE GND_EFUSE AMP_MUTE CVBS_OUT LVA1N LVA0P
VIDEO_IN R42 33Ω C50 47nF CVBS0 VSYNC2 CVBS0P N2 VCOM0 R21 PCM_REG_N Y1 IFAGC K5 BL-ADJUST AMP_MUTE LVA1P LVA1N
VIDEO_IN VCOM PCM_RESET IFAGC AVDD_AU AVDD_AU33 BL-ADJUST LVA1P
M2 P20 R6 PM_TX LVA2N
CVBS_OUT1 1 CVBS_OUT PCM_WAIT_N MCP_VDDC PANEL_ON/OFF LVA2N
R44 68Ω C51 47nF VCOM0 R19 L5 R7 PM_RX LVA2P
R43 NC/0Ω PCM_WE_N AVDD_DMPLL AVDD3P3_DMPLL MCP_VDDC VBL_CTRL LVA2P
AA3 RF_SW EEPROM_WP LVACLKN
TGPIO0 V2 P9 PWR_ON/OFF EEPROM_WP LVACLKP LVACLKN
TGPIO1 MCP_VDD33 PWR_ON/OFF LVACLKP
MCP
MSD6308RT NAND_ALE T10 Y3 R45 100Ω T_SCL K4 LVA3N
NAND_ALE NAND_ALE TUNER_I2C_SCL T_SCL AVDD_DVI AVDD_DVI_USB_MPLL LVA3N
NAND_CEZ V8 W2 T_SDA L4 R8 LVA0N LVA3P
NAND_CEZ NAND_CEZ1 U8 NAND_CEZ TUNER_I2C_SDA T_SDA AVDD_DVI_USB_MPLL MCP_AVDD LVA0P LVA0N LVA3P
NAND_CEZ1 NAND_CLE U9 NAND_CEZ1 R46 100Ω R12 LVA1N LVA0P LVB0N
NAND_CLE NAND_DQS U11 NAND_CLE MCP_TESTPIN LVA1P LVA1N LVB0P LVB0N
NAND_DQS NAND_RBZ U7 NAND_DQS LVA2N LVA1P LVB1N LVB0P
NAND_RBZ NAND_REZ V7 NAND_RBZ +3.3V_TU LVA2P LVA2N LVB1P LVB1N
NAND_REZ NAND_REZ C52 C53 LVA2P LVB1P
NAND_WEZ T11 LVACLKN LVB2N
NAND
NAND_WEZ NAND_WPZ T7 NAND_WEZ 22pF 22pF A15 LVACLKP LVACLKN LVB2P LVB2N
NAND_WPZ NAND_WPZ A18 GND M4 LVA3N LVACLKP LVBCLKN LVB2P
NAND_D[7:0] NAND_D0 Y8 B15 GND GND M6 LVA3P LVA3N LVBCLKP LVBCLKN
HDMI & Audio Audio Line IN

NAND_D1
NAND_D2
NAND_D3
NAND_D4
NAND_D5
W9
AA9
W10
Y10
W11
NAND_AD0
NAND_AD1
NAND_AD2
NAND_AD3
NAND_AD4
NAND_AD5
T_SDA
R47
4.7KΩ
R48
4.7KΩ
T_SCL
B18
C15
C18
D15
D18
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M9
M11
M12
M13
M14
LVB0N
LVB0P
LVB1N
LVB1P
LVA3P
LVB0N
LVB0P
LVB1N
LVB1P
LVB3N
LVB3P
MDI_RN
MDI_RP
MDI_TN
LVBCLKP
LVB3N
LVB3P
MDI_RN
MDI_RP
MDI_TN
NAND_D6 W12 E15 M15 LVB2N MDI_TP
NAND_D7 Y12 NAND_AD6 E18 GND GND N4 LVB2P LVB2N MDI_TP
NAND_AD7 F15 GND GND N6 LVBCLKN LVB2P
GND GND LVBCLKN USB0_DM
F18 N11 LVBCLKP USB0_DM
GND GND LVBCLKP USB0_DP
G7 N12 LVB3N USB0_DP
G8 GND GND N13 LVB3P LVB3N USB1_DM
G15 GND GND N14 3D_EN LVB3P USB1_DP USB1_DM
MSD6308RT GND GND 3D_EN USB1_DP
G18 N15 LOCAL_DIMMING_EN
H6 GND GND P5 3D_LR_IN LOCAL_DIMMING_EN
H8 GND GND P10 MDI_RN 3D_LR_IN NAND_ALE
HD-LIN
HD-RIN
HD-LIN
HD-RIN
C56
C57
1uF
1uF
LINE_IN_1L
LINE_IN_1R
GPIO & LVDS U9D
H18
J4
J8
J16
J17
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P11
P12
P13
P14
P15
MDI_RP
MDI_TN
MDI_TP
USB1_DM
USB1_DP
MDI_RN
MDI_RP
MDI_TN
MDI_TP
USB1_DM
USB1_DP
NAND_CEZ
NAND_CEZ1
NAND_CLE
NAND_DQS
NAND_RBZ
NAND_REZ
layout 方便否 K8 R5 USB0_DM
K15 GND GND R9 USB0_DP USB0_DM NAND_WEZ
K16 GND GND R10 USB0_DP NAND_WPZ
L6 GND GND R11 NAND_ALE NAND_D[7:0]
R49 100Ω GND GND NAND_CEZ
靠近mstar IC 3D_EN
3D_EN PCM_PWR_ENK17
3D_EN/PCM_PWR_EN LVA0N
K21 LVA0N
LVA0N
L7
GND GND
T6
NAND_CEZ1
T_SCL
T_SCL
AMP_MUTE K18 J19 LVA0P L8 T8 T_SDA
PWM
AMP_MUTE BL-ADJUST BRI_ADJ J18 AMP_MUTE LVA0P K19 LVA1N LVA0P L9 GND GND T9 NAND_CLE T_SDA
RF_SW
BL-ADJUST PWM_PM D9 BRI_ADJ LVA1N K20 LVA1P LVA1N L10 GND GND U6 NAND_DQS RF_SW
R50 100Ω PWM_PM LVA1P GND GND MHL_CABLE-DET
L19 LVA2N LVA1P L11 U10 NAND_RBZ MHL_CABLE-DET
LVA2N LVA2N GND GND NAND_REZ MHL_VBUS-EN
L20 LVA2P L12 V6 MHL_VBUS-EN
LVA2P M21 LVACLKN LVA2P L13 GND GND V10 NAND_WEZ
Audio Line Out U9C
LED_R R52
KEY0_IN E4
100Ω E5 KEY0_IN
LVACKN
LVACKP
M20
N21
LVACLKP
LVA3N
LVACLKN
LVACLKP
L14
L15
GND
GND
GND
GND
V12
W8
NAND_WPZ
NAND_D[7:0]
SAR
P3 C2 HDMI0_RX0N ARC_DET F7 LED_R LVA3N M19 LVA3P LVA3N L16 GND GND Y9 T_SCL
LINE_IN_0L A_RX0N HDMI0_RX0N ARC_DET LVA3P LVA3P GND GND T_SCL
R2 C1 HDMI0_RX0P KEY1_IN F6 N19 LVA4N Y11 T_SDA
LINE_IN_0R A_RX0P HDMI0_RX0P KEY1_IN LVA4N LVA4N GND T_SDA
LINE_IN_1L U2 D3 HDMI0_RX1N POWER_DET F8 N20 LVA4P AA10 RF_SW
HDMI0_RX1N
LVDS
LINE_IN_1R T3 LINE_IN_1L A_RX1N D1 HDMI0_RX1P POWER_DET LVA4P LVA4P GND AA12 RF_SW
HDMI A
LINE_IN_1R A_RX1P HDMI0_RX1P GND MHL_CABLE-DET
T2 D2 HDMI0_RX2N E19 LVB0N MHL_CABLE-DET
Analog Audio
LINE_IN_2L A_RX2N HDMI0_RX2N LVB0N LVB0N MHL_VBUS-EN

T1 E3 HDMI0_RX2P A10 E20 LVB0P MHL_VBUS-EN
LINE_IN_2R A_RX2P HDMI0_RX2P PM_SPI_CK LVB0P LVB0P
R1 C3 HDMI0_CLKN SPI_SDI B10 F21 LVB1N
SPI
LINE_IN_3L A_RXCN HDMI0_CLKN PM_SPI_DI LVB1N LVB1N
R3 B1 HDMI0_CLKP C11 F20 LVB1P
LINE_IN_3R A_RXCP HDMI0_CLKP PM_SPI_DO LVB1P LVB1P
B2 HDMI0_HPDIN B11 G21 LVB2N
HOTPLUGA HDMI0_HPDIN PM_SPI-CSN LVB2N LVB2N
F1 HDMI0_SCL F19 LVB2P
DDCDA_CK HDMI0_SCL LVB2P LVB2P
F2 HDMI0_SDA G19 LVBCLKN
DDCDA_DA HDMI0_SDA LVBCKN LVBCLKN
EARPHONE_OUTL U5 E2 HDMI_ARC G20 LVBCLKP
EARPHONE_OUTL PAD_ARC HDMI_ARC LVBCKP LVBCLKP
EARPHONE_OUTR V5 F3 HDMI_CEC H19 LVB3N
EARPHONE_OUTR CEC HDMI_CEC LVB3N LVB3N MSD6308RT
AMP-INL R53 150Ω LINE_OUTL1 R58 100Ω H20 LVB3P
AMP-INL AMP-INR LINE_OUTR1 T4 LOCAL_DIMMING_EN C21 LVB3P J21 LVB4N LVB3P
AMP-INR LINE_OUT_0L LOCAL_DIMMING_EN UART_RX2 LVB4N LVB4N
150Ω T5 W5 HDMI2_RX0N MODE C20 J20 LVB4P
LINE_OUT_0R C_RX0N HDMI2_RX0N MODE UART_TX2 LVB4P LVB4P
R54 Y5 HDMI2_RX0P C58 22pF
C_RX0P HDMI2_RX0P R60 NC/100Ω
R311 C59 C60 LINE_OUTL1 U3 W6 HDMI2_RX1N R55 D20
R312 LINE_OUT_2L C_RX1N HDMI2_RX1N LDE
LINE_OUTR1 U4 Y6 HDMI2_RX1P UART_RX E7 D19
HDMI C
200KΩ HDMI2_RX1P 100Ω

200KΩ LINE_OUT_2R C_RX1P AA6 HDMI2_RX2N M-SCL M_I2C_SCL UART_TX D7 M_UART0_RX LCK D21
2.2nF
2.2nF
C_RX2N HDMI2_RX2N M_UART0_TX LVSYNC

W7 HDMI2_RX2P M_I2C_SCL B21 C19
C_RX2P HDMI2_RX2P M_I2C_SCL LHSYNC
AA4 HDMI2_CLKN M-SDAR56 M_I2C_SDA M_I2C_SDA B20
C_RXCN HDMI2_CLKN M_I2C_SDA
AUVAG N3 Y4 HDMI2_CLKP
VAG C_RXCP HDMI2_CLKP C61
AUVRM P2 V4 HDMI2_HPDIN R18
GPIO
100Ω
C VRM HOTPLUGC
DDCDC_CK
W4 HDMI2_SCL
HDMI2_HPDIN
HDMI2_SCL 22pF
TCON0
TCON1
P17 CORE POWER C
W3 HDMI2_SDA N18 +1.15V_VDDC
HDMI2_SDA
TCON
R57 1.5KΩ EARPHONE_OUTL F12 DDCDC_DA L17 TCON2 N17
LOCAL DIMMING
AVDDL_MOD
EARPHONE-OUTL E12 I2S_IN_BCK C6 HDMI3_RX0N L18 SPI1_CK TCON3 P16
I2S_IN_WS D_RX0N HDMI3_RX0N SPI1_DI TCON4
EARPHONE_OUTR D12 B5 HDMI3_RX0P M18 N16 100Ω R61
EARPHONE-OUTR I2S_IN_SD D_RX0P HDMI3_RX0P SPI2_CK TCON5
C5 HDMI3_RX1N M16 R17 HP_DET
R59 1.5KΩ D_RX1N HDMI3_RX1N SPI2_DI TCON6 HP_DET
B4 HDMI3_RX1P M17 R16 ANT_P_DET
HDMI D
I2S
D_RX1P HDMI3_RX1P VSYNC_LIKE TCON7 ANT_P_DET

F10 A4 HDMI3_RX2N C62 C63 C64 C65 C66 C67 C68 C69 C70
I2S_OUT_BCK D_RX2N HDMI3_RX2N
E11 C4 HDMI3_RX2P
I2S_OUT_MCK D_RX2P HDMI3_RX2P 100nF 100nF 100nF 100nF 100nF NC/100nF NC/100nF
F11 A6 HDMI3_CLKN E9 2.2uF NC/10uF
I2S_OUT_WS D_RXCN HDMI3_CLKN LAN_LED0
C71 C72 D11 B6 HDMI3_CLKP F9
R310 R309 I2S_OUT_SD D_RXCP HDMI3_CLKP LAN_LED1
A2 HDMI3_HPDIN
150KΩ 150KΩ HOTPLUGD HDMI3_HPDIN
2.2nF
2.2nF
A3 HDMI3_SCL D6 PM_TX
DDCDD_CK HDMI3_SCL PM_TX/PANEL_ON/OFF PANEL_ON/OFF
B3 HDMI3_SDA E6 PM_RX
靠近mstar IC HDMI3_SDA VBL_CTRL
GPIO_PM
DDCDD_DA PM_RX/VBL_CTRL
FLASH_WP
A7 nodie DDR3 POWER
E10 C10 EEPROM_WP
SPDIF MHL
IRIN B7 SPDIF_IN/3D_FLAG D10 E2PROM_WP C7 100Ω 3D_LR_IN EEPROM_WP

IRIN SPDIF_OUT 3D_LR_IN C12 R62 PWR_ON/OFF 3D_LR_IN DVDD_NODIE
PWR_ON/OFF +1.5V_DDR AVDD_DRAM
System_RST E8 Close to MSTAR IC PWR_ON/OFF A9 R63 100Ω
AUVRM System_RST RESET PM_CONFIG0 PM_CONFIG0
AUVAG R14 G6 PM_CONFIG1
FB4 C74 TESTPIN F4 MHL_CABLE-DET PM_CONFIG1
C73 MHL_CABLE_DET MHL_CABLE-DET
1KΩ/100MHz 4.7uF XTALI AA2 F5 MHL_VBUS-EN C75 C78 C79 C81 C82
XTALIN MHL_VBUS_EN MHL_VBUS-EN
100nF XTALO Y2 1uF
XTALOUT 100nF 100nF NC/100nF
NC/100nF
Close to MSTAR IC
MSD6308RT Close to MST IC
with width trace
MSD6308RT
Standby Power 3.3V

AVDD_DMPLL +3.3V_Standby AVDD_AU
+3.3V_Standby AVDD_DVI AVDD_NODIE
FB5 FB6
Mode Selection detect NAND Flash Power

+3.3V_Standby
IR&Key_CONNECT
+3.3V_Standby
RF
VIFP C94 100nF
DIFP
C85
100nF
C86 C87
NC/100nF NC/100nF 100nF
C88 C89 600Ω/100MHz
100nF
C90
100nF
600Ω/100MHz
C91 C92
NC/100nF100nF
+3.3V_Standby // CHIP Config {PM_CONFIG0, SPI_DI, PM_CONFIG1, PWM_PM} +3.3V_Standby VIFM

使用物料5400-99112S-0800，请注意封装是否相同 R65 C93 100nF
DIFM
//SB51_EXT spi 4'b1000 Boot from 51 EXT SPI flash// +3.3V_Standby 4.7KΩ
HEMCU_EXT spi 4'b1001 Boot from MIPS EXT SPI flash R64 560Ω R66 +3.3V_TU
R67 4.7KΩ PM_CONFIG0 4'b1011 Boot from ROM 100KΩ
R68
R108 IFAGC
R69 Normal Power 3.3V
330Ω LED-R IF-AGC-T
C95
R70
3
SPI_SDI R72 R LED1 G 0Ω 0Ω 22nF
POWER_DET +3.3V_Standby 4.7KΩ R73 4.7KΩ
R71 4.7KΩ 1
3
LED-R 2 1 LED-G
1
1KΩ R Q6
R74 4.7KΩ 4 3 LED_R 1 R76 KMBT3904 +3.3V_Normal AVDD_MOD VDDP AVDD_PLL
R75
2
PM_CONFIG1 47KΩ G Q7 0Ω
PM_CONFIG0 KMBT3904
R77 NC/4.7KΩ PM_CONFIG0 R79
2
R80 LED-G
R78 4.7KΩ PWM_PM RED/GREEN 10KΩ
+3.3V_Standby 47KΩ
C99 C100 C101
when detect source is from 5V,

1
SW3
3
1
CH+ Other NC/100nF100nF
1uF
R106 30KΩ IR R81 IRIN
ch+ 2
change resistance ,make sure 4
R82 R83
100Ω
detect power 1VPP. SWITCH KEY1 10KΩ 10KΩ R84
5
ARC_DET
SW1 R105 KEY0-IN 100Ω KEY0_IN ARC_DET
1 3 KEY1-IN D2
1
KEY1-IN KEY1_IN
ch- D3 D4
2 4 10KΩ R85
1 CH- SW2 C105 100Ω
SWITCH 1 3KEY0-IN
C106 C107
5
KEY0 NC/ESD
Crystal stb 2 4
SWITCH
1
33pF
NC/ESD NC/ESD 100nF
100nF
5
+3.3V_Normal
IR1 IR_GND
4
IR
B B
4
1 IR
1
+3.3V_Standby
Vout 2
GND 3 R86 R87
Vcc 4.7KΩ 4.7KΩ
1
5
C104
M-SDA M-SCL
IR_VCC 100nF
5
SENSOR
XT1
C108
XTALO 27pF
1
DEBUG
2
R89
1MΩ
X1 C110
1
XTALI 24MHz 27pF +3.3V_Standby

XT2
1
MUST pull high to 5VSTB

ISP AND VGA EDID
NOTE:晶体频偏需要小于30PPM
R92 R93
C1=C2=2*CL-5
C1 4.7KΩ 4.7KΩ
R95 100Ω UART_TX

UART-TX R96 UART_RX
UART-RX
100Ω
heat sink
HS1
1
1
2
2
Heat Sink
PART NO:1505-M0420400-2302
A A
Title
CONTROLER

E 1.0

5 4 3 2 1
5 4 3 2 1
D D
MSD MIU AVDD_DRAM
U9A
R100
1KΩ
A19 DDR3_RESETB
MIU0
C DDR3_RESETB A20 DDR3_CKE C

DDR3_CKE B19
ZQ
R101 R102
240Ω 1KΩ
MSD6308RT
B B
Title
A D RAM A

Custom 1.0

5 4 3 2 1
5 4 3 2 1
CN5 其他页网络
41
+12V_Panel
1 2
SZ LVDS Connector 3
5
4
6
本页网络 LVA4N
LVA3N LVA4N
+12V_Panel LVACLKN LVA3N
7 8 +3.3V_Normal LVACLKN
0Ω X 4 0Ω X 4 LVA4P1 9 10 LVA4N1 LVA2N
LVA1N LVA2N
LVB1N RM16 LVB1N1 LVA1N RM11 LVA1N1 LVA3P1 11 12 LVA3N1
2 1 2 1 +12V_PWR LVA0N LVA1N
LVB1P LVB1P1 LVA1P LVA1P1 LVACLKP1 13 14 LVACLKN1 LVA0N
4 3 4 3 +3.3V_Standby
D LVB0N LVB0N1 LVA0N LVA0N1 LVA2P1 15 16 LVA2N1 D
LVB0P 6 5 LVB0P1 LVA0P 6 5 LVA0P1 LVB4N
8 7 8 7 LVA1P1 17 18 LVA1N1 LVB4N
LVA0P1 19 20 LVA0N1 LVB3N
LVBCLKN LVB3N
0Ω X 4 0Ω X 4 3D_EN_1 21 22 3D_LR_IN_1 LVBCLKN
LOCAL_DIMMING_EN_1 23 24 MODE LVA4N LVB2N
LVBCLKN RM15 LVBCLKN1 LVACLKN RM12 LVACLKN1 LVA4N LVB1N LVB2N
2 1 LVACLKP 2 1 LVACLKP1 BL_ADJUST_1 25 26 LVA3N LVB1N
LVBCLKP LVBCLKP1 4 3 27 28 LVA3N LVB0N
4 3 LVA2N LVA2N1 LVACLKN LVB0N
LVB2N LVB2N1 6 5 LVB4P1 29 30 LVB4N1 LVACLKN LVA4P
6 5 LVA2P LVA2P1 LVA2N LVA4P
LVB2P LVB2P1 8 7 LVB3P1 31 32 LVB3N1 LVA2N LVA3P
8 7 LVA1N LVA3P
LVBCLKP1 33 34 LVBCLKN1 LVA1N LVACLKP
LVA0N LVACLKP
LVB2P1 35 36 LVB2N1 LVA0N LVA2P
LVA1P LVA2P
0Ω X 4 0Ω X 4 LVB1P1 37 38 LVB1N1 LVB4N LVA1P
LVB0P1 39 40 LVB0N1 LVB4N LVA0P
RM14 LVA4N RM13 LVA4N1 LVB3N LVA0P
LVB4N LVB4N1 2 1 LVB3N
2 1 LVA4P LVA4P1 LVBCLKN
LVB4P LVB4P1 4 3 Panel-GND LVBCLKN LVB4P
4 3 LVA3N LVA3N1 LVB2N LVB4P
LVB3N LVB3N1 LVB2N LVB3P
42
6 5 LVA3P 6 5 LVA3P1 CN_M 5400-99121S-4020
LVB1N LVB3P
LVB3P LVB3P1 8 7 LVB1N LVBCLKP
8 7 LVB0N LVBCLKP
LVB0N LVB2P
LVA4P LVB1P LVB2P
LVA3P LVA4P
LVB0P LVB1P
LVACLKP LVA3P
LVB0P
LVA2P LVACLKP
LVA1P LVA2P
LVA1P BL-ADJUST
LVA0P BL-ADJUST
LVA0P MODE
C
LVB4P PANEL_ON/OFF C
PANEL_ON/OFF
LVB4P LOCAL_DIMMING_EN
LVB3P LOCAL_DIMMING_EN
LVB3P 3D_EN
LVBCLKP 3D_EN
LVBCLKP 3D_LR_IN
LVB2P 3D_LR_IN
LVB1P LVB2P
LVB0P LVB1P
LVB0P
LOCAL_DIMMING_EN R304 LOCAL_DIMMING_EN_1
+3.3V_Normal BL-ADJUST LVA4N1
+3.3V_Normal 100Ω BL-ADJUST A4N
LVA3N1
R296 MODE A3N
PANEL_ON/OFF LVACLKN1
0Ω PANEL_ON/OFF ACLKN
LVA2N1
R305 R307 A2N
NC/4.7KΩ LVA1N1
R292 0Ω NC/4.7KΩ A1N
LVA0N1
A0N
3D_LR_IN_1
3D_LR
+3.3V_Normal MODE
MODE
3D_EN 3D_EN R298 100Ω 3D_EN_1 LVB4N1
B4N
3D_LR_IN 3D_LR_IN_1 LVB3N1
3D_LR_IN B3N
R297 100Ω LVBCLKN1
BCLKN
R112 LVB2N1
B2N
NC/4.7KΩ LVB1N1
MODE B1N
MODE LVB0N1
R293 0Ω B0N
LVA4P1
A4P
R113 LVA3P1
B A3P B
NC/4.7KΩ LVACLKP1
ACLKP
LVA2P1
A2P
LVA1P1
NC/60Ω/100MHz A1P
LVA0P1
FB8 A0P
Power for panel 3D_EN_1
LOCAL_DIMMING_EN_1
3D_EN
DIM
12V常供 BL_ADJUST_1
ME9435A +12V_Panel BL-ADJUST BL_ADJUST_1 BL-ADJ
BL-ADJUST LVB4P1
R300 0Ω VB4P
100Ω/100MHz LVB3P1
FB9 3 B3P
+5V_Normal LVBCLKP1
2 S
BCLKP
R123 C117 +3.3V_Normal LVB2P1
1 8 B2P
R124 LVB1P1
+12V_PWR FB10 4 G 7 C118 B1P
C215 LVB0P1
6 B0P
100Ω/100MHz 220nF R308 +12V_Panel
10KΩ 5 Panel-VCC
100nF 10uF NC/4.7KΩ
LOCAL_DIMMING_EN
D
+3.3V_Standby
100KΩ U11
R128
Note:靠近J452Panel端子
3
+5V_Normal
L :Power on 10KΩ R125
H :Power off 1 Q9
KMBT3904
3
10KΩ
PANEL_ON/OFF 1 Q17
2
A PANEL_ON/OFF A
R1271KΩ KMBT3904
2
ROL1,R0L9根据实际情况选取阻值
Title
LVDS

B 1.0

5 4 3 2 1
5 4 3 2 1
VGA
其他页网络
VGA-SDA
VGA-SCL
本页网络
VGA-HS
VGA-VS
VGA-B +12V_PWR VGA_RX UART-RX
R174 100Ω VGA-B VGA_TX
VGA_SCL VGA_RX VGA-G HDMI2/5V UART-TX
VGA-G
VGA-G
VGA-R
VGA-B
UART-RX
VGA-R VGA-VSYNC
R175 100Ω
17
1
1
CN12 AVDD5V_MHL_C VGA-HSYNC
NC/ESD
VGA_SDA VGA_TX UART-TX
VGA_SCL 15 5 VGA-B
R176 D9 D10 R177 +12V_INV VGA-G
1
10 D11
VGA_VS 14 4 VGA-R
VGA_VS
R179 100Ω 9
75Ω
75Ω 75Ω NC/ESD VGA_RX UART-RX
HDMI2_RX2P
HDMI2_RX2N
HDMI2_RX2P
HDMI2_RX2N
YPBPR GND_YPbPr Y PR PB
NC/ESD
VGA-VSYNC VGA_HS 13 3 VGA-B VGA_TX HDMI2_RX1P
VGA_HS R178 UART-TX HDMI2_RX1P CN20
VGA-HSYNC 8 HDMI2_RX1N
1
1
1
VGA-VSYNC HDMI2_RX1N
R180 100Ω VGA_SDA 12 2 VGA-G HDMI2_RX0P YPBPR-G
VGA-HSYNC HDMI2_RX0P 1 YPBPR-G YPBPR-G
7 HDMI2_RX0N
R181 R182 VGA-B HDMI2_RX0N 2 YPBPR-R
11 1 VGA-R HDMI2_CLKP
10KΩ VGA-G HDMI2_CLKP 5 YPBPR-R
10KΩ 6 HDMI2_CLKN YPBPR-R
VGA-R HDMI2_CLKN 3 YPBPR-B
HDMI2_RX2P
VGA SOCKET HDMI2_RX2P HDMI2_SCL 4 YPBPR-B
HDMI2_RX2N YPBPR-B
HDMI2_RX2N HDMI2_SDA
16
HDMI2_RX1P HDMI2_HPDIN
D
HDMI2_RX1P HDMI2_HPDIN
HDMI2_RX1N HDMI_ARC D
HDMI2_RX1N HDMI_ARC EPHONE SOCKET
HDMI2_RX0P HDMI_CEC
HDMI2_RX0P HDMI_CEC
HDMI2_RX0N
HDMI2_RX0N MHL_CABLE-DET
HDMI2_CLKP
HDMI2_CLKP
HDMI2_CLKN MHL_VBUS-EN
HDMI2_CLKN
HDMI2_SCL
YPBPR-R
ARC_DET
YPBPR-G
YPBPR-B
HDMI2_SDA CVBS_OUT
HDMI2_HPDIN YPBPR-G
HDMI2_HPDIN YPBPR-G
HDMI_ARC HD-LIN
HDMI_ARC ESD ESD
HDMI_CEC HD-RIN ESD D13
HDMI_CEC MDI_TP D12
MHL_CABLE-DET MDI_TP D8
MDI_TN R167 R168
MDI_TN R165
MDI_RP 75Ω 75Ω 75Ω
MHL_VBUS-EN MDI_RP
MDI_RN
ARC_DET MDI_RN
CVBS_OUT HDMI3_RX0N
YPBPR-G HDMI3_RX0N
YPBPR-G HDMI3_RX0P
HD-LIN HDMI3_RX0P
HDMI3_RX1N HDMI3_RX1N
HD-RIN HDMI3_RX1P
MDI_TP HDMI3_RX1P
MDI_TN MDI_TP HDMI3_RX2N
MDI_TN HDMI3_RX2N
MDI_RP HDMI3_RX2P HDMI3_RX2P
MDI_RN MDI_RP HDMI3_CLKN
MDI_RN HDMI3_CLKN
HDMI3_CLKP HDMI3_CLKP
HDMI3_HPDIN HDMI3_HPDIN
HDMI3_SCL HDMI3_SCL
HDMI3_SDA HDMI3_SDA
HDMI0_RX0P HDMI0_RX0P
HDMI0_CLKN HDMI0_CLKN
HDMI0_CLKP HDMI0_CLKP
HDMI0_HPDIN HDMI0_HPDIN
HDMI0_SCL HDMI0_SCL
HDMI0_SDA
MHL HDMI0_SDA
HDMI3(背出)
CN8
HDMI1 DATA2+
DATA2 SHIELD
1
2
3
HDMI3-RX2P
HDMI3-RX2N 10Ω X 4
DATA2- 4 HDMI3-RX1P RM5
HDMI3-RX2P HDMI3_RX2P
DATA1+ 5 7 8 HDMI3_RX2P
HDMI3-RX2N HDMI3_RX2N
DATA1 SHIELD 6 HDMI3-RX1N 5 6 HDMI3_RX2N
HDMI3-RX1P HDMI3_RX1P
CN7 DAT1A- 7 HDMI3-RX0P 3 4 HDMI3_RX1P
HDMI3-RX1N HDMI3_RX1N
1 HDMI2-RX2P
靠近IC放置(OK) DATA0+
DATA0 SHIELD
8 1 2 HDMI3_RX1N
DATA2+ 2 MHL-CD-SENSE1 9 HDMI3-RX0N
C DATA2 SHIELD DATA0- 10 HDMI3-CLKP
3 HDMI2-RX2N RM4 5.1ΩX4 +5V_Normal 10Ω X 4 C
DATA2- CLK+ 11
4 HDMI2-RX1P HDMI2-RX2P HDMI2_RX2P CLK SHIELD HDMI3-RX0P RM6 HDMI3_RX0P
DATA1+ 7 8 HDMI2_RX2P 12 HDMI3-CLKN 7 8 HDMI3_RX0P
5 HDMI2-RX2N HDMI2_RX2N CLK- HDMI3-RX0N HDMI3_RX0N
DATA1 SHIELD 5 6 HDMI2_RX2N 20 13 CEC 5 6 HDMI3_RX0N
6 HDMI2-RX1N HDMI2-RX1P HDMI2_RX1P GND1 CEC HDMI3-CLKP HDMI3_CLKP
DAT1A- 3 4 HDMI2_RX1P 21 14 HDMI-ARC 3 4 HDMI3_CLKP
7 HDMI2-RX0P HDMI2-RX1N HDMI2_RX1N GND2 NC HDMI3-CLKN HDMI3_CLKN
DATA0+ 1 2 HDMI2_RX1N R138 R139 22 15 HDMI3-SCL 1 2 HDMI3_CLKN
8 GND3 SCL
DATA0 SHIELD 9 HDMI2-RX0N 10KΩ 10KΩ 16 HDMI3-SDA
DATA0- SDA 17
20 10 HDMI2-CLKP DDC/CEC GND
GND CLK+ HDMI2-RX0P R140 5.1Ω HDMI2_RX0P HDMI2-SCL R141 22Ω 18
11 HDMI2_RX0P HDMI2_SCL +5V POWER HDMI3/5V
CLK SHIELD HDMI2-SDA HDMI2-HPD R144 33Ω HDMI2_HPDIN 19 HDMI3-HPD
21 12 HDMI2-CLKN HDMI2-RX0N R143 5.1Ω HDMI2_RX0N HDMI2_SDA HDMI2_HPDIN HOT PLUG
GND CLK- HDMI2_RX0N R142 22Ω
13 CEC
22 CEC 14 HDMI2-CLKP R145 5.1Ω HDMI2_CLKP 此HDMI port IC内置hotplug HDMI SOCKET
GND NC HDMI2_CLKP
15 HDMI2-SCL HDMI2-CLKN R146 5.1Ω HDMI2_CLKN
23 SCL 16 HDMI2-SDA HDMI2_CLKN
GND SDA 17
DDC/CEC GND 18 HDMI3/5V
+5V POWER HDMI2/5V
19 HDMI2-HPD
HOT PLUG
HDMI SOCKET HDMI3/5V

R149 R150
10KΩ 10KΩ
HDMI3-SCL R151 22Ω

HDMI3_SCL
HDMI3-SDA R147
HDMI3_SDA
CEC & ARC MHL MHL SWITCH(OK)

R152 22Ω 1KΩ R148
10KΩ
ARC DET(OK) HDMI3-HPD
3
Q11 R153
C119 HDMI2/5V AVDD5V_MHL_C 1 HDMI3_HPDIN
+5V_MHL KMBT3904 HDMI3_HPDIN
HDMI-ARC HDMI_ARC +5V_VBUS HDMI2/5V R154 4.7KΩ
HDMI_ARC ARC_DET
NC/2.2uF MHL-CD-SENSE1 R155 100Ω HDMI3/5V
2
MHL_CABLE-DET +5V_Normal ARC_DET
R156 5.1Ω NC/4.7KΩ
CEC R157HDMI_CEC
HDMI_CEC U12
200Ω
R158
5
IN OUT
1 根据ARC所放的HDMI定 R159
C122 NC/10KΩ
+
300KΩ C120
2 100nF R160
47nF GND CE10 10KΩ
R183 NC/100Ω 4 3
300K电阻，47nF电容 MHL_VBUS-EN EN FLG NC/100uF
R162 R163 AP2171WG-7

MHL_CABLE-DET
1KΩ NC/10KΩ
C123
NC/100nF
B B
HDMI2 10Ω X 4
1 HDMI0-RX2P HDMI0-RX2P RM2 HDMI0_RX2P
DATA2+ 2 7 8 HDMI0_RX2P
DATA2 SHIELD HDMI0-RX2N HDMI0_RX2N
3 HDMI0-RX2N 5 6 HDMI0_RX2N
DATA2- HDMI0-RX1P HDMI0_RX1P
4 HDMI0-RX1P 3 4 HDMI0_RX1P
DATA1+ HDMI0-RX1N HDMI0_RX1N
5 1 2 HDMI0_RX1N
DATA1 SHIELD 6 HDMI0-RX1N
DAT1A- 7 HDMI0-RX0P
DATA0+ 8 10Ω X 4
DATA0 SHIELD 9 HDMI0-RX0N HDMI0-RX0P RM3 HDMI0_RX0P
DATA0- 7 8 HDMI0_RX0P
20 10 HDMI0-CLKP HDMI0-RX0N HDMI0_RX0N
GND CLK+ 5 6 HDMI0_RX0N
11 HDMI0-CLKP HDMI0_CLKP
CLK SHIELD 3 4 HDMI0_CLKP
AV-IN(OK) 21
GND CLK-
CEC
12
13
HDMI0-CLKN
CEC
HDMI0-CLKN
1 2
HDMI0_CLKN
HDMI0_CLKN
22 14
Ethernet
NET_TX+
NET_TX-
NET_RX+
NET_RX-
GND NC
NET_GND
15 HDMI0-SCL
23 SCL 16 HDMI0-SDA
TRANSFORMER
1
1
GND SDA 17
CN21 DDC/CEC GND
AV-GND AV-R AV AV-L VIDEO_IN 18 HDMI0/5V
VIDEO_IN 8 9 1 +5V POWER 19 HDMI0-HPD
RM17 7 10 R253 75Ω TX+ HOT PLUG
CN4 2
TX-
1
1
1
1
MDI_TP 6 11 3
MDI_TP 8 7 RX+ CN6
MDI_TN 5 12
RD RX
1 AV2_AUL MDI_TN 6 5 4 9 HDMI SOCKET
2 MDI_RP 4 13 R254 75Ω 5 4 GND 10
VIDEO_IN MDI_RP 4 3 TX
MDI_RN 3
TD
14 6 5GND1
5 MDI_RN 2 1 2 15 R255 75Ω 7 RX- HDMI0/5V
3 AV2_AUR
Close to MST IC 1 16 8 7
4 5.1ΩX4
8
with wide trace R256 75Ω
SG5 SG6 RJ45 SOCKET
EPHONE SOCKET TN1
C204 SG1 SG2 SG3 SG4
C202 C203 R132
HDMI0/5V 1KΩ
SPARK SPARK 1nF R164
100nF 100nF SPARK 10KΩ
R170 C205 1nF
HDMI0-HPD
AV2_AUL HD-LIN SPARK
SPARK SPARK
10KΩ
3
R135 R134
10KΩ 10KΩ Q21 1 R161 HDMI0_HPDIN
+3.3V_Standby HDMI0_HPDIN
R171 KMBT3904
4.7KΩ
VIDEO_IN
A 12KΩ AZ1013-04S HDMI0-SCL R136 22Ω A

HDMI0_SCL
2
HDMI0-SDA
FB1 HDMI0_SDA
NC/ESD 4 3 R137 22Ω
5 I/O3 I/O2 2
D7 R172 VDD GND
0Ω 6 1
R166 AV2_AUR I/O4 I/O1
HD-RIN
75Ω C206 U22
10KΩ FB7
R173 100nF
0Ω
12KΩ
Title
HDMI

D 1.0
5 4 3 2 1
5 4 3 2 1
其他页网络
USB POWER 本页网络
+5V_Normal +5V_USB
USB1_DM
USB1_DP USB1_DM
USB1_DP
USB1_DM
USB1_DP USB1_DM USB0_DM
USB1_DP USB0_DP USB0_DM
D USB0_DP D
USB0_DM
USB0_DP USB0_DM
USB0_DP
USB2.0 INTERFACE
+5V_USB
+5V-USB
R199
1
C124 C125 270mΩ Note:电容靠近USB端子,提供usb读写稳定性

10uF
100nF
CN14
USB-DM
1
VBUS 2 5.1Ω USB1_DM
1
R187
D- 3 R188 USB1_DP
D+ 4
1
GND 5.1Ω +3.3V_Normal
5
SHELL 6 USB-DP Note:5.1R电阻靠近端子,减小ESD.
SHELL NC/ESD NC/ESD
C USB2.0 SOCKET R191 C
R190
USB-GND
+3.3V_Normal
270mΩ
C130 C131 R197

3_3V
CN16 DM DP WiFi-GND Note:电容靠近USB端子,提供usb读写稳定性
100nF 10uF
USB ESD分布电容要求<2pF
1
1
VBUS 2
D- 3
D+ R196 5.1Ω USB0_DM
4 R198 5.1Ω USB0_DP
GND 5
SHELL 6
B B
SHELL
R200 R201 Note:5.1R电阻靠近端子,减小ESD.
USB SOCKET
NC/ESD NC/ESD
A A
Title
USB

C 1.0

5 4 3 2 1
5 4 3 2 1
MUTE CONTROL HeadPhone Out
+5V_Normal
AMP_RST=0 MUTE L :Normal H :Normal FB15

H :Mute L :Mute 22uF 22uF 60Ω/100MHz
D
AMP_MUTE=0 MUTE AMP_MUTE AMP_MUTE
C209 C208 D
R209 2
静音电路 +3.3V_Standby
4.7KΩ 1
3
R211 1KΩ
SD
EARPHONE-OUTL
C138
2.2uF OP_VCC1
HP_OUTL
R212
3
10KΩ Q12
D14 R210 150Ω
PWD_MT 1
5
6
7
8
BAV70 KMBT3904 C139
+12V_PWR
3 2.2nF C140 C141
BIAS
IN2
OUT2
VCC
2
R213 R214 U14
D6 PWD_MT_HP 47KΩ
470KΩ 100nF 10uF
BAV99
MUTE
OUT1
3
GND
IN1
R215 Q13
1
2
MMBT3906 BH3544F-E2
C142 470KΩ
4
3
2
1
2
2.2uF
HP_MUTE
HP_OUTR
C143
R216 CE5 2.2uF
EARPHONE-OUTR
+
NC/100KΩ 100uF
R217150Ω
C144
2.2nF
OP_VCC1
R218
HP_MT 100KΩ
3
C PM_CONFIG0 R219 1 KMBT3904 C
PM_CONFIG0 HP_MT R220 HP_MUTE
EARPHONE OUT 47KΩ
3
1KΩ
Q14 KMBT3904 C145
PWD_MT_HP R221 1
2
10KΩ 1uF
Q15
H: MUTE, L: UN-MUTE
2
R263
47KΩ
R261 R262
10KΩ 10KΩ HP-L CN17
HP-GND
CE6 220uF HP-R 4
HP_OUTL 1 2
1
R224
+ 22Ω
1
HP_OUTR R225 1
+ 22Ω 3
CE7 220uF
1
R223 HP_DET HP-DET EPHONE_4_02

+3.3V_Normal
本页网络其他页网络
10KΩ
+3.3V_Standby
AMP_MUTE AMP_MUTE
+12V_PWR
HP_DET
HP_DET
+3.3V_Normal
AMP_MUTE AMP_MUTE EARPHONE-OUTL
HP_DET
HP_DET EARPHONE-OUTR
PM_CONFIG0
B EARPHONE-OUTL B
AMP-INL
EARPHONE-OUTR
AMP-INR
PM_CONFIG0
AUDIO AMP AMP-INL
AMP-INR
+12V_AMP
功放输出端增益放大倍数表
GAIN1 GAIN0 AMP Input阻抗 R226 +12V_AMP SPK_L+

100KΩ
SD +12V_AMP +12V_PWR
1
R650_低 R649_低 20db 60 C146 SPK_L-
R227 C147 220nF
220nF CN-M
R650_低 R648_高 26db 30 33KΩ C149 CE8
1
+
C148
1uF 100nF 100uF SPK_L+
R651_高 R649_低 32db 15 L4 22UH 6
U15
SPK_L- 5
R651_高 R648_高 36db 9 AV_L_OUT# C150 0.047UF C151 29 SPK_R- 4
100nF 1 EP 28 3
/SD PVCCL C152
2
1
2 27 L5 22UH
R230 R231 3 /FAULT PVCCL 26 1
LINP BSPL 220nF
22KΩ NC/22KΩ 4 25
R228 R229 5 LINN OUTPL 24
+12V_AMP NC/22KΩ 22KΩ GAIN0 PGND CN18
6 23 C153
R232 10Ω 7 GAIN1 OUTNL 22 220nF C156
8 AVCC BSNL 21 C155 220nF
C154 1uF
9 AGND BSNR 20 220nF SPK_R-
C157 1uF
10 GVDD OUTNR 19
11 PLIMIT PGND 18 L6 22UH SPK_R+
R234 R233 4.7KΩ
12 RINN OUTPR 17 SPK_R+
3KΩ C158 1uF C159 220nF
13 RINP BSPR 16 1
A AMP-INL R235 AV_L_OUT# C160 14 NC13 PVCCR 15 L7 22UH A
AMP-INL PBTL PVCCR +12V_AMP
150Ω 100nF
AMP-INR R236 AV_R_OUT# AV_R_OUT# C162
AMP-INR C161 0.047UF TPA3113D2
150Ω C163 CE9 220nF
+
100nF 100uF
C164 C165
2.2nF 2.2nF
Title
AMPLIFY

C 1.0

5 4 3 2 1
5 4 3 2 1
D D
1 TU-GND
T1
TUN_VA4N1BD1219 T2
12
13
14
15
TUN_MT-11A55WL
12
13
14
15
GND
GND
GND
GND
GND
GND
GND
GND
ISDB-T
ISDB-T
B1(3.3V)
IF-AGC
RF-SW
IF AGC
SDA
NC1
NC4
NC8
NC9
SCL
IF+
GND
GND
GND
GND
IF-
SDA
SDA
+B1
IFN
IFP
1
2
3
4
5
6
7
8
9
10
11
1
2
4
5
6
7
8
9
10
11
1 T-SCL
1
1 T-SDA
T_SDA
T_SCL
T_SDA
T_SCL
RF-SW
C167
22uF 1 IF-
IF-IN+
IF-IN-
1 1 IF+
IF-IN+
IF-IN-
C T-VCC C
+3.3V_TU
RF_SW TR6 IF-AGC 1

RF_SW C128 4.7KΩ +3.3V_TU
4.7nF C216
R107 470nF
100Ω
IF-AGC-T
本页网络其他页网络
T_SCL
T_SCL
T_SDA
T_SDA
+3.3V_TU IF-IN- DIFM DIFM

T_SCL IF-IN+ DIFP DIFP
T_SCL
T_SDA IF-AGC-T IF-AGC-T
T_SDA
IF-IN- DIFM DIFM RF_SW
RF_SW
B B
IF-IN+ DIFP DIFP
IF-AGC-T IF-AGC-T
RF_SW
RF_SW
A A
Title
TUNER

C 1.0

5 4 3 2 1
5 4 3 2 1
NAND FLASH
NAND-DQS
NAND-WPZ
R250 NC/22Ω
NAND_DQS
NAND_WPZ
NAND_DQS
EEPROM
+3.3V_Nand +3.3V_Nand +3.3V_Nand 8 7 NAND_WPZ
NAND-WEZ NAND_WEZ
6 5 NAND_WEZ
NAND-ALE NAND_ALE +3.3V_Normal
1
U23
48
NAND-CLE 4
2
3
1
NAND_CLE
NAND_ALE
NAND_CLE
EEPROM R97
D NC1 NC48 3V3 D
2 47 AGND 4.7KΩ
NC2 NC47 RM7 22Ω X 4 C195
R251 3 46 需靠近主IC SCL SDA WP
NC/33pF
1
4 NC3 NC46 45 U10
1
10KΩ NC4 NC45
5 44 NAND-D7 1 8
1
6 NC5 I/O8 43 NAND-D6 2 NC1 VCC 7 EEPROM_WP
1
NC6 I/O7 NAND-CEZ1 NAND_CEZ1 NC2 WP EEPROM_WP
NAND-RBZ 7 42 NAND-D5 8 7 NAND_CEZ1 3 6 R98 100Ω M-SCL
R//B I/O6 NAND-CEZ NAND_CEZ A2 SCL M-SCL
NAND-REZ 8 41 NAND-D4 6 5 NAND_CEZ 4 5 R99 100ΩM-SDA
/RE I/O5 NAND-REZ NAND_REZ VSS SDA M-SDA
NAND-CEZ 9 40 4 3 NAND_REZ
/CE NC40 NAND-RBZ NAND_RBZ
NAND-CEZ1 10 39 2 1 NAND_RBZ CAT24C08WI-GT3 C114 C115 C116
NC10 NC39 R252
11 38 NC/0Ω
NC11 NC38 RM8 22Ω X 4 C196
12 37 需靠近主IC 100nF 22pF 22pF
VCC VCC NC/33pF
13 36 Micron Nand需要NC
14 VSS
NC14
VSS
NC35
35 NAND-DQS WP:
NAND-CLE
15
16 NC15 NC34
34
33 NAND_D[7:0] 0:READ AND WRITE
NAND-ALE 17 CLE NC33 32 NAND-D3 RM9
22Ω X 4 1::WRITE PROTECT
NAND-WEZ 18 ALE
/WE
I/O4
I/O3
31 NAND-D2 NAND-D0
8 7
NAND_D0 4707-C24021-08
19 30 NAND-D1 NAND_D1
NAND-WPZ
20 /WP I/O2 29
NAND-D1
NAND-D0 NAND-D2 6 5 NAND_D2
4707-M24C32-08
21 NC20
NC21
I/O1
NC28
28 NAND-D3 4
2
3
1
NAND_D3 4707-24C640-08
22
23 NC22 NC27
27
26
4752-C24320-0080
NC23 NC26 NAND-D4 NAND_D4
24 25 8 7 47CJ-K24040-0080
NC24 NC25 NAND-D5 NAND_D5
6 5
C
C197 TC58NVG0S3HTA00 C198
NAND-D6
NAND-D7 4 3
NAND_D6
NAND_D7
47CJ-K24162-0080 C
100nF 100nF 2 1 47CJ-K24640-0080

RM10 22Ω X 4 47CJ-K24120-0080
+3.3V_Normal +3.3V_Nand
C199 C200 本页网络其他页网络

C201
2.2uF 100nF 100nF
+3.3V_Normal
NAND_DQS
NAND_DQS
NAND_DQS NAND_WPZ
NAND_DQS NAND_WPZ
NAND_WEZ
NAND_WEZ
NAND_WPZ NAND_ALE
NAND_WPZ NAND_ALE
NAND_WEZ NAND_CLE
B
NAND Power NAND_ALE
NAND_CLE
NAND_WEZ
NAND_ALE
NAND_CEZ1
NAND_CEZ
NAND_CLE
NAND_CEZ1
B
NAND_CLE NAND_CEZ
NAND_CEZ1 NAND_REZ
NAND_CEZ1 NAND_REZ
NAND_CEZ NAND_RBZ
NAND_CEZ NAND_RBZ
NAND_REZ
NAND_REZ
NAND_RBZ NAND_D[7:0]
NAND_RBZ
NAND_D[7:0] EEPROM_WP
EEPROM_WP
M-SCL
M-SCL
EEPROM_WP M-SDA
EEPROM_WP M-SDA
M-SCL
M-SCL
M-SDA
M-SDA
A A
Title
NAND FLASH

B 1.0

5 4 3 2 1
MK2x1
MK2
CN18x6 CN18x5 CN5x40 CN5x38 CN5x36 CN5x34 CN5x32 CN5x30 CN5x28 CN5x26 CN5x24 CN5x2 CN5x20 CN5x18 CN5x16 CN5x14 CN5x12 CN5x10 CN5x8 CN5x6 CN5x4 CN5x2
H1x5
CN15x12 CN15x1 H1x8 H1x7
CN5x42 CN5x41 H1x4 H1x3
C162x1 CN5x39 CN5x37 CN5x35 CN5x3 CN5x31 CN5x29 CN5x27 CN5x25 CN5x23 CN5x21 CN5x19 CN5x17 CN5x15 CN5x13 CN5x1 CN5x9 CN5x7 CN5x5 CN5x3 CN5x1 H1x2 H1x9
H1x6
CN5
CN18x4 CN18x3 CN18x2 CN18x1 R300x2 R296x2 R293x2
H1x1
H1
C162x2
C162
R300x1 R296x1 R293x1 C215x2 C215x1 MK4x1
R300
R296
MK4
C118x2 C118x1
R292x2
C215C118
CN15x10 CN15x9 CN15x8 CN15x7 CN15x6 CN15x5 CN15x4 CN15x3 CN15x2 CN15x1 C156x1 CN16x5 CN16x6
R292x1
R293 R292
D0S1x1 D0S1x2 C146x2 C146x1 C152x2 C152x1 C156x2
C146
C152
C156
CN18 D0S1
H2x5 R1S3x2 R1S3x1 R5x2 R5x1 H5x5
CN21x9 FB7x2 H2x8 H2x7 R104x2 R104x1 R17x1 R17x2
H5x8 H5x7
R169x1 R169x2 L5x1
H2x4 H2x3 C126x2 H5x4 H5x3
R133x2 R133x1
FB7x1 R131x1
L6x1
H2x2 H2x9 R129x2 R129x1 H5x2 H5x9
C126x1 R131x2
R131
CN21x1 C204x2
H2x1 H2x6
H5x1 H5x6
H2
H5
CN21x2 Q10x3 Q20x2 Q20x1 L5x2
CN21x3
CN21x4 C153x1 C155x1 L6x2
C204x1
R1S3R104R169R133 R129 Q10

R5R17 C126 Q20
CN21x5 Q10x1 Q10x2 Q20x3
CN21x6 C153x2 C155x2
CN21x7 R254x1 R254x2 R253x2 R253x1 L4x1
CN21x8 SG2x1 SG2x2 SG6x2 SG6x1 TN1x9 TN1x8 C202x1
L7x1
R253SG6
C147x1 C159x1
TN1x10 TN1x7 C202x2
C202
SG1x1 SG1x2
FB7C204 R254SG2SG1
TN1x11 TN1x6 C147x2 C159x2
C153 C147
L4x2
C155 C159
TN1x12 TN1x5 L7x2
CN15 CN21
CN21x10 TN1x13 TN1x4 C163x1 C163x2
C163
SG4x1 SG4x2 TN1x14 TN1x3 C149x1
FB1x1 FB1x2 C205x1 C205x2 C149x2
C149
SG3x1 SG3x2 SG5x2 SG5x1 TN1x15 TN1x2 C203x2 CE8x1 U15x28 U15x27 U15x26 U15x25 U15x24 U15x23 U15x2 U15x21 U15x20 U15x19 U15x18 U15x17 U15x16 U15x15
Q11x1 TN1x16 TN1x1 C203x1
C203
R256x2 R256x1 R255x2 R255x1
CE9x1
CN16
Q11x3 R153x2
CN16x1 CN16x2 CN16x3 CN16x4
SG4SG3 R256
SG5 R255
CN8x22 R212x1 R212x2
TN1
Q11x2 R153x1
U15x29
R153
CN8x19 R209x1 R209x2 R214x2 R214x1 R201x2 R200x2
R147x2 R147x1 R148x2 R148x1 R307x1
CN8x18 C131x1 C130x1
CN8x17 R307x2
R201x1 R200x1 R197x1
C130x2
R307
U15
CN8x16 R150x2 R150x1 R152x1 R152x2 D14x1 U15x1 U15x2 U15x3 U15x4 U15x U15x6 U15x7 U15x8 U15x9 U15x10 U15x1 U15x12 U15x13 U15x14
C130
L5 L4 CE8
CN8x15 R4x1 R6x1
CN8x14 D14x3 R211x2 R211x1
CE8x2 R198x1 R196x1 C131x2
R211
L6 L7CE9
R149x2 R149x1 R151x1 R151x2 C206x2
CN8x13
CE9x2
C131
R4x2 R6x2
R148 R152 R151

CN8x12 D14x2 R198x2 R196x2
R201 R198
R200 R196
CN8x11
C206x1 Q3x1 Q12x3 C148x2 C151x2
R197x2
R197
RM6x1 RM6x2 U22x6 U22x5 U22x4 R232x1 R232x2
CN8x10 C154x1 C154x2
R67x1 R219x2
R232
RM6x3 RM6x4 Q3x3
C154
CN8x9 Q13x1
RM6x5 RM6x6
R88x1 C151x1
CN8x8 C148x1
CN8x21 Q3x2 R67x2 R219x1
RM6x7 RM6x8
R4 R67
R6 R219
CN8x7
C148
R88x2 Q13x3 Q12x1 Q12x2
CN8x6 C157x2 C161x1 C160x2
C158x2
U22
CN8x5
U22x1 U22x2 U22x3 Q13x2 C150x2
RM5x1 RM5x2 R227x1 C161x2 C160x1
CN8x4 D5x1 Q14x1
C160
RM5x3 RM5x4 C111x1 D6x3 C150x1
CN8x3 C157x1 C219x2
RM5x5 RM5x6
R227x2 C158x1 R51x2 R51x1 R18x1 R18x2
CN8x2 D5x3 Q14x3 R216x2 R215x1
C165x2
CN8x1 RM5x7 RM5x8 C219x1
C111x2 FB2x2 FB2x1
C205 Q11 R147R150R149 RM6RM5

D5x2 Q14x2 R216x1 R215x2 R226x1 C164x2 R20x1 R20x2 R103x2 R103x1
C165x1
FB2
R209 D14 Q13 R216

R215
R51R20
Q14
R228x2 R233x2 R234x1
C161 C165
R212 R214 Q12 D6

D6x1 D6x2 R226x2 C164x1 R21x2
R90x1 R19x2 R19x1
R228x1 R233x1 R234x2 U4x1 U4x8
R90x2
Q8x1 R305x1 R21x1
RM17x7 RM17x5 RM17x3 RM17x1 C20x1 U4x2 U4x7 C24x1 C24x2
Q8x3 R94x1 C18x2
R305x2 U4x3 U4x6
R213x2 R235x2 R230x1 R231x2 R229x2 R297x1
R305
CN8x20 RM17x8 RM17x6 RM17x4 RM17x2 C142x1 C20x2 U4x4 U4x5 C17x1
C13x1
R94x2
C20
C109x1 Q8x2
FB1 CN8
RM17
Q3 D5 Q8
R213x1 R235x1 R230x2 R231x1 R229x1 R297x2
CE5x1 C18x1 R16x2 R16x1 C17x2
R18R103R19C24 R16
C219R21 C17
R91x1
R154x2 R159x1 C109x2 C142x2 R54x2 R236x2
U3x3 C13x2
C206 R88 C111R90C109

C142
R91x2 R75x1 R62x2
R154x1 R159x2 R53x1 C59x2 R311x1
R94 R91
R54x1 R236x1 R14x1
R154
R159
R75x2 R62x1
R53x2 C59x1 R311x2
R62
C60x2 R312x1
U3x2 R14x2
C151 C150 C164 R235 C59

C157 R228 R230 R311
C22x2 L2x2
C60x1 R312x2 R64x2 R63x2
U3x4 R15x1
R233 R231R54C60
C158 R234 R229R236R312
C119x1 C119x2 C100x2
C119
R64x1 R63x1 C23x2 U3x1 R15x2
R63
CE5
CE5x2 C100x1
C23x1
R227 R226 R213 R53 C100

C23
C22x1 R128x1
C18 C22
R72x2 R78x1
R95x2 R96x2 L2x1 Q9x2 R128x2
R72x1 R78x2
R72
R297 R75 R64 R78
R95x1 R96x1
U4 L2
R74x1 C21x1 C21x2 C76x2 C76x1 Q9x3
R127x1
C21
R157x1 R157x2 Q9x1
R93x2 R92x2 R74x2 R127x2
C16x1 C16x2
C13R14 R15 R128 R127

CN12x16 R93x1 R92x1 R218x1 R218x2 C112x1
R77x2
C62x2 C62x1 R87x1 R308x2 R112x2 R266x2
R266x1
Q17x2
C112x2 C66x2 C66x1 R87x2 R308x1 R112x1
R266
R77x1
C112
R175x2 R174x2 Q17x3
C64x2 C64x1 R124x2 R124x1 R123x2 R123x1 R125x2
R175x1 R174x1 C208x1 C209x1 R86x1 R56x1 R55x1 R304x1 R113x2 Q17x1
R124
C16 R123
Q9 Q17
FB5x2 FB5x1 FB6x1 FB6x2 R125x1
FB5
FB6
R71x1
R125
C63x2 C63x1 C78x1 C78x2 R86x2 R56x2 R55x2 R304x2 R113x1
R182x2 R179x1 C90x1 C88x1 C85x1 R71x2
R220x1 R221x2 R263x1 C117x2 C117x1
R74 R77 R71

R182x1 R179x2 C90x2 C88x2 C85x2 C65x2 C65x1 C79x1 C79x2
R102x2 C61x1 C58x1 R101x2 R60x1
C90
C88
C85
C208x2 C209x2 R220x2 R221x1 R263x2
R220
R221
R263
C209
CN12x15 CN12x5 C68x2 C68x1 R100x1 R100x2 R102x1 C61x2 C58x2 R101x1 R60x2
R86 R102
R56 C61
R87 R55 C58
R308 R304 R101
C62C66 C64 C63 C65 C68

C78 C79 R100
CN12x10 R181x2
R181x1
R180x1
R180x2
C140x1
HS1x2 R58x1
U1 x4 U1 x3 U1 x2 U1 x1 FB9x2
CN12x14 CN12x4 C140x2 U14x8 U14x7 U14x6 U14x5 R58x2
R112 R113 R60 R58

CN12x9 D11x1 R178x1 Q15x1 C89x2 C89x1
CN12x13 CN12x3 D11x2 R178x2 C141x2 Q15x3

Q15x2 C92x2 C92x1
FB8x2 FB9x1
Q15
C89 C92
CN12x8 D10x1 R177x1 C141x1 U9xA2 U9xA3 U9xA4 U9xA6 U9xA7 U9xA9 U9xA10 U9xA12 U9xA13 U9xA14 U9xA15 U9xA16 U9xA17 U9xA18 U9xA19 U9xA20
FB8x1
FB8
CN12x12 CN12x2 D10x2 R177x2 U9xB1 U9xB2 U9xB3 U9xB4 U9xB5 U9xB6 U9xB7 U9xB8 U9xB9 U9xB10 U9xB11 U9xB12 U9xB13 U9xB14 U9xB15 U9xB16 U9xB17 U9xB18 U9xB19 U9xB20 U9xB21 RM16x7 RM16x5 RM16x3 RM16x1 RM15x7 RM15x5 RM15x3 RM15x1
U1 x5 U1 x6 U1 x7 U1 x8 FB10x1
CN12x7 U9xC1 U9xC2 U9xC3 U9xC4 U9xC5 U9xC6 U9xC7 U9xC8 U9xC9 U9xC10 U9xC11 U9xC12 U9xC13 U9xC14 U9xC15 U9xC18 U9xC19 U9xC20 U9xC21
U14
U14x1 U14x2 U14x3 U14x4 RM16x8 RM16x6 RM16x4 RM16x2 RM15x8 RM15x6 RM15x4 RM15x2
FB15x1 U9xD1 U9xD2 U9xD3 U9xD4 U9xD6 U9xD7 U9xD9 U9xD10 U9xD11 U9xD12 U9xD15 U9xD18 U9xD19 U9xD20 U9xD21
RM16
CN12x11 CN12x1 D9x2 R176x2 U9xE2 U9xE3 U9xE4 U9xE5 U9xE6 U9xE7 U9xE8 U9xE9 U9xE10 U9xE11 U9xE12 U9xE14 U9xE15 U9xE18 U9xE19 U9xE20
C144x2
CN12x6 D9x1 R176x1 FB15x2 C145x1 U9xF1 U9xF2 U9xF3 U9xF4 U9xF5 U9xF6 U9xF7 U9xF8 U9xF9 U9xF10 U9xF11 U9xF12 U9xF13 U9xF15 U9xF18 U9xF19 U9xF20 U9xF21
R96 R92 R174 R179 R180 R178 R177 R176

R157 R218 C208 C140 C141 FB15
C144x1
U9xG1 U9xG2 U9xG3 U9xG4 U9xG5 U9xG6 U9xG7 U9xG8 U9xG9 U9xG10 U9xG11 U9xG12 U9xG15 U9xG18 U9xG19 U9xG20 U9xG21
FB10x2
R95 R93 R175 R182 R181D11D10 D9

C75x1 C75x2
C75
C145x2 R36x1 R36x2 C44x1 C44x2 U9xH2 U9xH3 U9xH4 U9xH5 U9xH6 U9xH7 U9xH8 U9xH9 U9xH10 U9xH11 U9xH18 U9xH19 U9xH20
C145
R217x2 RM14x8 RM14x7 FB0P5x1
U9xJ1 U9xJ2 U9xJ3 U9xJ4 U9xJ6 U9xJ8 U9xJ9 U9xJ10 U9xJ11 U9xJ12 U9xJ16 U9xJ17 U9xJ18 U9xJ19 U9xJ20 U9xJ21
181.0mm
R35x1 R35x2 C43x1 C43x2 RM14x6 RM14x5
165.0mm
R217x1 RM14x4 RM14x3
CE0P9x2 CE0P9x1
U9xK1 U9xK2 U9xK3 U9xK4 U9xK5 U9xK8 U9xK9 U9xK12 U9xK15 U9xK16 U9xK17 U9xK18 U9xK19 U9xK20 U9xK21
C144 R217
R34x1 R34x2 C42x1 C42x2 FB0P5x2
U9xL2 U9xL3 U9xL4 U9xL5 U9xL6 U9xL7 U9xL8 U9xL9 U9xL10 U9xL11 U9xL12 U9xL13 U9xL14 U9xL15 U9xL16 U9xL17 U9xL18 U9xL19 U9xL20 RM14x2 RM14x1
FB9 FB10 FB0P5

R33x1 R33x2 C41x1 C41x2 RM11x8 RM11x7
U9xM1 U9xM2 U9xM4 U9xM6 U9xM8 U9xM9 U9xM10 U9xM11 U9xM12 U9xM13 U9xM14 U9xM15 U9xM16 U9xM17 U9xM18 U9xM19 U9xM20 U9xM21
C44C43C42C41
C143x1 RM11x6 RM11x5
U9xN1 U9xN2 U9xN3 U9xN4 U9xN6 U9xN8 U9xN9 U9xN10 U9xN11 U9xN12 U9xN13 U9xN14 U9xN15 U9xN16 U9xN17 U9xN18 U9xN19 U9xN20 U9xN21 RM11x4 RM11x3
C46x1 C46x2
U3 C76 C117 U11 CE0P9

U9xP2 U9xP3 U9xP5 U9xP9 U9xP10 U9xP11 U9xP12 U9xP13 U9xP14 U9xP15 U9xP16 U9xP17 U9xP19 U9xP20 RM11x2 RM11x1
C143x2 R38x1 R38x2
U9xR1 U9xR2 U9xR3 U9xR5 U9xR6 U9xR7 U9xR8 U9xR9 U9xR10 U9xR11 U9xR12 U9xR13 U9xR14 U9xR15 U9xR16 U9xR17 U9xR18 U9xR19 U9xR20 U9xR21 RM12x8 RM12x7
C73x1 RM12x6 RM12x5
C45x1 C45x2 FB4x2 C74x1 U9xT1 U9xT2 U9xT3 U9xT4 U9xT5 U9xT6 U9xT7 U9xT8 U9xT9 U9xT10 U9xT11 U9xT12 U9xT13 U9xT14 U9xT15 U9xT16 U9xT17 U9xT18 U9xT19 U9xT20 U9xT21 R3P1x2
RM12x4 RM12x3 C2P9x1 C2P9x2
C73x2
CN12x17 CE7x1 C139x1 U9xU2 U9xU3 U9xU4 U9xU5 U9xU6 U9xU7 U9xU8 U9xU9 U9xU10 U9xU11 U9xU12 U9xU13 U9xU14 U9xU15 U9xU16 U9xU17 U9xU18 U9xU19 U9xU20 RM12x2 RM12x1 R3P1x1
C73
R40x2 R40x1
RM15 RM14 RM12
R36R35R34R33 C46R38 C45R40

C139x2 FB4x1 C74x2 U9xV1 U9xV2 U9xV3 U9xV4 U9xV5 U9xV6 U9xV7 U9xV8 U9xV10 U9xV12 U9xV13 U9xV15 U9xV16 U9xV18 U9xV19 U9xV20 U9xV21 RM13x8 RM13x7 C3P0x2 C3P0x1
C74
U9xW1 U9xW2 U9xW3 U9xW4 U9xW5 U9xW6 U9xW7 U9xW8 U9xW9 U9xW10 U9xW11 U9xW12 U9xW13 U9xW14 U9xW15 U9xW16 U9xW17 U9xW18 U9xW19 U9xW20 U9xW21 RM13x6 RM13x5 C3P3x2 C3P3x1 R2P9x1 R2P8x1
R210x2 C48x2 C49x2 C50x2 C51x2 RM13x4 RM13x3
C3P3
U9xY1 U9xY2 U9xY3 U9xY4 U9xY5 U9xY6 U9xY7 U9xY8 U9xY9 U9xY10 U9xY11 U9xY12 U9xY13 U9xY14 U9xY15 U9xY16 U9xY17 U9xY18 U9xY19 U9xY20 U9xY21 R2P9x2 R2P8x2
RM13x2 RM13x1 U2x4 U2x3 U2x2 U2x1
RM11 RM13
R210x1 C48x1 C49x1 C50x1 C51x1 U9xAA2 U9xAA3 U9xAA4 U9xAA6 U9xAA7 U9xAA9 U9xAA10 U9xAA12 U9xAA13 U9xAA15 U9xAA16 U9xAA18 U9xAA19 U9xAA20
R50x2 R50x1 R3P3x1 R3P5x2

R41x2 R39x2 R42x2 R44x2
C138x1 R3P3x2 R3P5x1
CN17x2 CE7x2
C2P9C3P0 U2
R41x1 R39x1 R42x1 R44x1 R61x2 R61x1 U2x5 U2x6 U2x7 U2x8
C50 R42
R262x2 R262x1
R49x2 R49x1 R298x2 R298x1 R3P2x2 C3P1x1 R3P0x1 C218x2 R3P4x2
C138x2
R50 R61 R49

R298
C47x2 R43x1
C143 C139 R210 C138

R225x2 R225x1 C57x1 R3P2x1 C3P1x2 R3P0x2 C218x1 R3P4x1
C3P1
R3P0
R3P1 R2P9 R3P3 C218
R2P8 R3P5 R3P4
C47x1 R43x2
C49 R39 R43

C3P2x1
R261x2 R261x1 C57x2 C93x1 C94x1
C3P2x2 R3P6x2 R3P6x1
CE6x1 R37x2
R3P6
L0P5x1 L0P5x2
R3P2C3P2
C93x2 C94x2
C93
C94
R224x2 R224x1 R37x1
C48 R41 C47 R37

CN17x4 CN17x1
R262 R225 R261 R224

R173x1
C56x1 C3P4x1 C3P4x2
C3P4
R173x2 C3P5x2 C3P5x1
U9 R173
L0P5C3P5
C56x2
HS1x1
FB4 C51 R44 C57 C56

RM10x1 RM10x2
R66x1 R69x1 RM10x3 RM10x4 R223x1 R223x2 C201x1 C201x2 CE1P0x1 CE1P0x2
R171x2 C52x1 C53x1 RM10x5 RM10x6
CE7 CE6
CN17x3 CE6x2 R66x2 R69x2 RM10x7 RM10x8
HS1
R252x2 R252x1 C101x1 C101x2 C199x2 C199x1
R66
CN12 CN17
RM10
R171x1 C52x2 C53x2
C199
R223 R252
C201 C101
R171
R45x1 R46x1
C95x1 R57x2 R59x2
CE1P0
R45x2 R46x2 C195x2 U23x48 U23x47 U23x46 U23x45 U23x4 U23x4 U23x42 U23x41 U23x40 U23x 9 U23x 8 U23x 7 U23x 6 U23x 5 U23x 4 U23x U23x 2 U23x 1 U23x 0 U23x 9 U23x 8 U23x 7 U23x 6 U23x 5
C52R45
C95x2 R57x1 R59x1
R69 C95
C195x1 R250x2
R47x1 R48x1 R250x1 C36x2 U8x1

C71x2 C72x2 C110x2 C196x1
R250
R47x2 R48x2 C36x1 U8x2
T2x12T1x12 T2x13 C71x1 C72x1 C110x1 C196x2
C53R46 R47
R48
C195C196
X1x1 U8x3
R310x2 R309x2 R89x2
RM8x7 RM8x5 RM8x3 RM8x1 RM9x7 RM9x5 RM9x3 RM9x1 R30x1
R310x1 R309x1 R89x1 R2x2 R2x1 R32x1 R32x2
R30x2
R57 C71 R310

R59 C72 R309
RM8x8 RM8x6 RM8x4 RM8x2 RM9x8 RM9x6 RM9x4 RM9x2
RM9
C108x1
R31x2
Q5x1
C108x2
R31x1
Q5x3
C110 R89 C108

C36 R30 R31
RM7x7 RM7x5 RM7x3 RM7x1 Q5x2
T1x15
U8 R32R2 Q5
RM7x8 RM7x6 RM7x4 RM7x2
RM8 RM7
R98x2 R99x2
R98x1 R99x1
C114x2 R97x2 C115x2 C116x2

X1x2
X1
C114x1 R97x1 C115x1 C116x1
C114
R97
R98 C115
R99 C116
U10x8 U10x7 U10x6 U10x5
R156x1 R183x1 U23x1 U23x2 U23x U23x4 U23x5 U23x6 U23x7 U23x8 U23x9 U23x10 U23x1 U23x12 U23x1 U23x14 U23x15 U23x16 U23x17 U23x18 U23x19 U23x 0 U23x 1 U23x 2 U23x U23x 4
U23
C32x2 C32x1
C32
R156x2 R183x2
R156
R183
C33x1 C33x2 C198x2 C198x1 R251x1 R251x2 C200x1 C200x2 C197x2 C197x1
C198
R251
C200
C197
C33
U12x5 U12x4 R163x2
R163x1 U10x1 U10x2 U10x3 U10x4
U10
U6x3 U6x2 U6x1 U12x1 U12x2 U12x3 C123x1
C107x2 C107x1 R84x2 R84x1
T1x14 C123x2
R163 C123
R160x1 R160x2 D3x2 D3x1 R83x2 R83x1
U12 R160
R84 R83
C107 D3
C106x2
SW3x1 SW3x2 C106x1 SW1x1 SW1x2 SW2x1 SW2x2

D4x2 R82x1
U6x4 SW3x5 D4x1 SW1x5 SW2x5 R82x2
R106x2 R105x2 R85x2

C34x2 C34x1
U6 C34
R106x1 R105x1 R85x1
T1x1 T1x2 T1x3 T1x4 T1x5 T1x6 T1x7 T1x8 T1x9 T1x10 T1x11 SW3x3 SW3x4 SW1x3 SW1x4 SW2x3 SW2x4
IR1x1 IR1x2 IR1x3
C106 D4R106
R82 R105
R85
SW1
SW2
C35x2 C35x1 C105x2 R81x2 D2x1 R79x1 C104x2
C35
R29x1 R29x2 R28x1 R28x2 C220x2 C220x1
R29
C105x1 R81x1 D2x2 R79x2 C104x1

R188x2 R188x1 R191x1 R191x2
C105
R81
R79
C104
D2
T2x15 T1x13 T2x14 U5x1 U5x8

R26x2 R26x1 R25x1 R25x2
T1
R187x2 R187x1 R190x1 R190x2 C28x1 U5x2 U5x7 C31x1 C31x2 R27x1 R27x2
FB3x2
R188 R187
R191 R190
C26x2 U5x3 U5x6
C122x2 R143x2 R140x2 C125x2 C28x2
R164x2 R137x2 R136x2 U5x4 U5x5
C28
U5
C122x1 R144x2 R142x2 R141x2 C124x1 C124x2 FB3x1
C124
R164x1 R137x1 R136x1 R143x1 R140x1 R23x2 R23x1 C25x1 C25x2
C122
FB3
R143
R140
C26x1
R28 R26 C31 R23
C220 R25 R27 C25
T2x2 T2x4 T2x5 T2x6 T2x7 T2x8 T2x9 T2x10 T2x11 R166x1 R170x2
C26
Q21x2 Q21x1 R144x1 R142x1 R141x1 C125x1 C30x2
R144
T2
R166x2 R170x1 R161x1 R134x1 R135x1 RM3x2 RM3x4 RM3x6 RM3x8 RM2x2 RM2x4 RM2x6 RM2x8
CE10x1 C121x1
R155x2 R162x1 C30x1
C30
C128x2 C216x2 C216x1 R107x2 R107x1 R161x2 R134x2 R135x2 RM3x1 RM3x3 RM3x5 RM3x7 RM2x1 RM2x3 RM2x5 RM2x7 MK1x1
R107
R155x1 R162x2 R139x1 R138x1 R146x2 R145x2
R164 R161
R137 R134
R136 R135
C216
R155
R162
RM3
RM2
Q21x3
MK1
C128x1 C167x2 C167x1 D7x1 R172x2 R199x1 C121x2 L3x2

C121
R139x2 R138x2 R146x1 R145x1
C128
C167
R132x1 R132x2
R142 R139
R141 R138
R146
R145
IR1x5 IR1x4
Q21 R132
RM4
D7x2 R172x1
CE2x2
R170 R172
R166D7
TR6x1 TR6x2 CN20x2 CN4x2 CN14x1 CN14x2 CN14x3 CN14x
TR6
R52x2 R80x1 R70x1
MK3x1 R199x2 R52x1 R80x2 R70x2
MK3
R52
R80
R70
C125 R199
SW3 CE10
H3x5
CN20x5 CN4x5 CN6x19 CN6x18 CN6x17 CN6x1 CN6x15 CN6x14 CN6x13 CN6x12 CN6x1 CN6x10 CN6x9 CN6x8 CN6x7 CN6x CN6x5 CN6x4 CN6x3 CN6x2 CN6x1 CE10x2 C120x2 R158x1
CN7x19 CN7x18 CN7x1 CN7x16 CN7x15 CN7x14 CN7x13 CN7x12 CN7x1 CN7x10 CN7x9 CN7x8 CN7x CN7x6 CN7x5 CN7x4 CN7x3 CN7x2 CN7x1 H4x5 L3x1 R68x2 R65x2 R108x1
R68x1 R65x1 R108x2 LED1x2 LED1x4
L3
H3x8 H3x7 H4x8 H4x7 Q7x3

R108
C120x1 R158x2 Q6x3
C120
R158
D8x1 D8x2 R165x1 R165x2
CN6x20 CN6x21 CN7x20 CN7x21 CN14x5 CN14x6 R76x2 R73x1
H3x4 H3x3 H4x4 H4x3
Q7
Q7x1 Q7x2 R76x1 R73x2

CE2x1
CE2
Q6
Q6x1 Q6x2
R68 R76
R65 R73
CN20x3 D13x1 D13x2 R168x1 R168x2 CN4x3 LED1x1 LED1x3

IR1 LED1
H3x2 H3x9 D12x1 D12x2 R167x2 R167x1

H4x2 H4x9
R165 R168 R167

D8D13D12
H3x6 H4x6
H3x1 H4x1
H3
H4
CN20x4 CN20x1 CN4x4 CN4x1 CN6x22 CN6x23 CN7x22 CN7x23
CN6
CN7
CN14
CN20
CN4
256.0mm
H1x5
PANEL-GNDx1 H1x8 H1x7
PANEL-VCCx1
PANEL-GND
PANEL-VCC
BCLKNx1
BCLKN
MK6x1 PWR_12Vx1 3D_LRx1 H1x4 H1x3
MK6
PWR_12V
B1Nx1 A3Nx1
A3N
BL-ADJx1 A3Px1 H1x2 H1x9
BL-ADJ
A3P
SPK_L+x1 SPK_L-x1 SPK_R-x1 SPK_R+x1 H1x6
SPK_L+
SPK_L-
SPK_R-
SPK_R+
H1x1
H1
ENx1
ON/OFF
EN
ON/OFFx1 POW-GNDx1
3D_LR DIM
MODEx1 DIMx1
POW-GND
B1Px1 BCLKPx1
MODE
BCLKP
B1N B1P
3D_ENx1
3D_EN
H2x5 H5x5 MK5x1
H2x8 H2x7 H5x8 H5x7
MK5
CN21x9
H2x4 H2x3 H5x4 H5x3
NET_TX+x1
NET_TX+
CN21x1 H2x2 H2x9 H5x2 H5x9
H2x6 ADJx1 H5x6
ADJ
H2x1 H5x1
H2
H5
NET_TX-x1 CN21x2
CN21x3
NET_RX+x1 CN21x4
NET_RX+
CN21x5
NET_RX-x1 CN21x6
NET_TX- NET_RX-
CN21x7
CN21x8
NET_GNDx1
NET_GND
CN21x10
CN8x22 DPx1 DMx1
DP
DM
WIFI-GNDx1
WIFI-GND
3_3Vx1
3_3V
CN8x21
CN8x20
CN12x16
VGA-VSx1
VGA-VS
VGA-SCLx1 CN12x15 CN12x5
VGA-SCL
CN12x10
HS1x2
CN12x14 CN12x4
CN12x9
VGA-HSx1 CN12x13 CN12x3 VGA-Bx1
CN12x8 B0Nx1
CN12x12 CN12x2 VGA-Gx1 C67x2 C67x1
VGA-SDAx1 CN12x7 B0Px1
B0P
C86x1 C86x2 B2Nx1
VGA-HS VGA-SDA
C69x1 C69x2
CN12x11 CN12x1 VGA-Rx1 B2Px1
B0N B2P
VGA-BVGA-GVGA-R
C87x1 C87x2 C70x1 C70x2
C67 C69 C70
C86 C87
CN12x6 B3Px1 VB4Px1
C91x2
C91x1
C91
B3Nx1 B4Nx1
B4N
C82x1 C81x1
C82x2 C81x2 A0Nx1
C82
C81
C99x1
A1Px1 A0Px1
A1P
C99x2
C99
A2Nx1 A2Px1 A1Nx1
CN12x17
ACLKP
ACLKPx1 A4Px1
A0N A1N A4P

A4Nx1
B2N B3P B3N A2N A4N

ACLKNx1
VB4P A0P A2P ACLKN

HP-Rx1
HP-R
HP-GNDx1 CN17x2
HP-GND
HP-Lx1
HP-L
CN17x4 CN17x1 IR17x1
IR17
HP-DETx1
HP-DET
HS1x1
CN17x3
HS1
CN21 CN8 CN12 CN17
T2x12T1x12 T2x13
XT2x1
T1x15
XT1x1
XT2 XT1
WPx1
WP
3V3x1 SCLx1
3V3
SCL
SDAx1
SDA
AGNDx1
AGND
T1x14
RF-SWx1
RF-SW
T-SCLx1 T-SDAx1
T-SCL
T-SDA
T-VCCx1 IF-AGCx1 IF-x1 IF+x1
IF-AGC
IF-
IF+
T-VCC
T1x1 T1x2 T1x3 T1x4 T1x5 T1x6 T1x7 T1x8 T1x9 T1x10 T1x11 KEY0x1
KEY1x1
KEY0
KEY1
CH+x1 CH-x1
CH-
CH+
T2x15 IRx1
IR
TU-GND
T1x13 T2x14 TU-GNDx1
T1
USB-GNDx1
USB-GND
T2x2 T2x4 T2x5 T2x6 T2x7 T2x8 T2x9 T2x10 T2x11
T2
IR_GNDx1
IR_GND
+5V-USBx1
+5V-USB
PRx1 AVx1 USB-DMx1
PR
AV
USB-DM
MK7x1 AV-GNDx1
MK7
AV-GND
H3x5 USB-DPx1 H4x5
USB-DP
GND_YPBPRx1 Rx1
GND_YPBPR
H3x8 H3x7 H4x8 H4x7 IR_VCCx1
IR_VCC
CN6x20 CN6x21 CN7x20 CN7x21 CN14x5 CN14x6

H3x4 H3x3 Yx1 H4x4 H4x3
AV-Rx1
Y
PB
AV-R
CN20x3 PBx1 CN4x3 AV-Lx1
AV-L
H3x2 H3x9 H4x2 H4x9 MK8x1 Gx1
R G
H3x6 H4x6
MK8
H3x1 H4x1
H3
H4
CN20x4 CN20x1 CN4x4 CN4x1 CN6x22 CN6x23 CN7x22 CN7x23
CN6
CN7
CN14
CN20
CN4
LED1
Q6
C104
IR1 R79
R108R65
R68 R73R76
MK1
D2
R81
C105
Q7
C25
R23
R70
C220
R80R52
R25
R27
L3
R28R26
C31
256.0mm
R29
U5
C28
C26
FB3
CE2
C30
C121
CN14
H4
R3P4 CE1P0 C116
R3P6
C115
R32
C218 R99 R97

R2
R3P5
R3P0 R98 C114
R2P8 C3P1 R3P2 U8 Q5
H1 R128 R127
R125 FB9
FB10 FB0P5 R2P9R3P3
C130 C13 R3P1 R85
R14 R15 R82
C131 R105
R188 C124
C197
FB8 U2
R123
C3P0
Q9 Q17
CN5 C3P2 C36
U23 R30
R31 SW2
R191
R190
R197
R187
MK4
C107R84
R83
C199
C3P4
R196
C2P9
R124
C117
R200 R198
C201
C101
C76
D3
U3 R199
C3P5
C3P3
C16
R201 R266 U11

CN16 C125 CN7
R251 C200
R307 CE0P9
C215
C118
R223R252
L0P5 RM4
C198
SW1 R140
R143
HS1
RM16 RM15
R298
RM10
RM9
RM11
R292 RM13 R250 R145
R146
R50
R61
R49
R112 R113
C195
R308 R141
RM8
RM12 C196
R304 R142
RM7
R18 R103
R293 R21 R87 R55 R60 R58 RM14 C106

D4 R106
CE9 C17 R144
R19
R296
R16
L6
R300
L7 R101
U9 R138
U9
R139
C219 SW3
C24
C122
R51
L2 C58
R56 C61 R102
FB2 R20
C62
R86 CE10 R158C120

R100
C21
C78
C79
R163
U4 C123
U15
C66
C64
C63
C65
C68
C149
C20C18
R62
C23
C22
R183
R156
CN6
R74
R160
C160 R305 R162R155

C159 R63 U12
C155 C165
C161C158 R78
C162
C147 C157
R234R233 R64 R77R71 X1
C163
R297 R75
RM3 RM2
CN18 C156 L5 L4 R228

R229 R236 C112
R232 C154
C153 R59 C110R89

R312
R231R54 C60 R72 C108
C72 R309
C152
C71 R310
C151 R136
C148 R230 R311 C85 R69 R57 R135
R211
C150 C164 R235C59 R137

C146
C88
R132
R66 R134
C100 R164
C95 U6
C89
C92
Q21
R213 C73 C94 C53 R161

R227 R226 R53 C93 R46
R214
C52 R171
R169R133
R129
C142 C51 R44

FB6
FB5
R131C126 C90
R5
C34
C74 C50 R42 R45

R1S3
R48
C75
R104
R17
FB4 C57 C56

R212
CE8 R47
D0S1
C202
C32
C203 R170 R172

C35
D14
D6
Q20 TN1
Q12
C44
C43
C42
C41
R209
R43
C33
R215R216 R173 R166 D7 CN4

Q13
C45R40
C47 R37
R6 CE5 C49 R39
Q14
R36
R35
R34
R33
C46
R38
R4 C48 R41
Q10
R219 R94 R91
T2
R67 Q15
T1
Q3 D5 R263R221 U14 C144 R217 R210

R253
H2 Q8
SG3 R256 R255
C143 C139 C138

R167
SG5
SG6
RM17
C206 R220 CE6

R88 C209
C111 R90 C109
R165
D13 R168
C208 C145
U22
C216 R107
R254
R147R148
FB7 C204
D12
C140 FB15
D8
R157
R218
SG2
SG1
SG4
R152
R151
R150
R149
R262
R225
R261
R224
R153 C141
C205 R96 R92 R174 R176
R179 R180 R178 R177 D9
R95 R93 R175 R182 R181
D11 D10
CE7
Q11 RM6 RM5
CN20 H3
CN12 C119
R159R154
C167
TR6
FB1
CN21 CN8 C128

MK2
CN15 CN17 MK3
165.0mm
181.0mm
8KM
5KM
76C
96C
07C
18C
28C
99C
19C
78C
68C
7KM
6KM
Q_3_S_SOT-23_1H40
IR1 LED1
4
LED1
Q_3_S_SOT-23_1H40
3
LED_4_S_3P50_3L20_1W60_1H10 4 3
2
2 1
Q6 G R G
5
1 R
RQ6G
2
M_5_S_2P54_7L40_7W00_5H90
C_2_S_1L00_0W50_0H50 3
05D1_00D0_S_1_PT1
C104 1
IR1RI
R_2_S_1L00_0W50_0H30
05D1_00D0_S_1_R108 1
PT R65 2 1 1 2
R
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30
R79 R_2_S_1L00_0W50_0H30
C_2_S_1L00_0W50_0H50
R73R76
05D1_00D0_S_1_P-T 1 D2
1 2 2 1 1 2
R_2_S_1L00_0W50_0H35 MK1 R68
D20D_2_S_1L00_0W60_0H39
R_2_S_1L00_0W50_0H35
_00D0_SR_2_S_1L00_0W50_0H30
2
_1_PT 1
2 1 2 1
5D1R81
M
C_2_S_1L00_0W50_0H61
C_2_S_1L00_0W50_0H50
Q7M
2 1
C1051 8R
KIM2
MK_1_S_1D50
CCV_
05D1_S_13_KM 1 2 1
R_2_S_1L00_0W50_0H35 1 2
R_2_S_1L00_0W50_0H30 1 2 1
Q7
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H32
DR_2_S_1L00_0W50_0H35
NG_RI 2 1
C25
R23
R70
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H32
R_2_S_1L00_0W50_0H30
05D1_00D0_S_1_PT 1
C220
R80R52
R25
R27
L3
R_2_S_1L00_0W50_0H30
C_2_S_1L00_0W50_0H61
1 2 2 2
L3x2
L3x1
R28R26
L3
2 1 1 1
C31
2 1 2 1
1
1 2 1 2
256.0mm
5
U5
R29
2
1
IC_8_S_TSOT23-8_0P65_3L00_1W70_1H00
4
U5
L_2_S_6L00_6W00_4H20
IC_5_S_SOT-25_0P95_3L10_1W70_1H45
C_2_S_2L00_1W25_1H25
C28 1 2
C26
C_2_S_1L00_0W50_0H50
C26
CE_2_S_8L40_8W40_10H0
CE2
2
1
FB_2_S_1L60_0W80_0H80
FB3
2 B 1
2 1
C_2_S_1L00_0W50_0H50 CE2
JA_6_S_USB_1R_9H40
C30
2 1
C121 C
H4x1 H4x3
C_2_S_2L00_1W25_1H25
H4
3
C_2_S_1L00_0W50_0H55 CE_2_S_6L60_6W60_5H50
H4x7
H4x9
7 9
H4x5
H4x6
5
8 1 2
1 6
SW_5_S_2P25_6L50_6W50_3H10
CN14
H4x8
H4x2
H4x4
4
05D1_00D0_S_1_PT
H4
C_2_S_1L00_0W50_0H50
C_2_S_2L00_1W25_1H25
CN14x6
R_2_S_1L00_0W50_0H35
8188EUS
R3P4 CE1P0 C116

66
D
R_2_S_1L00_0W50_0H35
R3P6
C115
H1x1
CN14
H1x3
R32
R_2_S_1L00_0W50_0H30
C_2_S_1L00_0W50_0H50
R99 R97
H1
3 C218
H1x7
H1x9
IC_8_S_SOIC_1P27_5L00_4W00_1H75
R2
7 9 R3P5
R3P0 R98 C114 U10
TP_1_S_0D00_1D50 4
CN16
R_2_S_1L00_0W50_0H35
C_2_S_1L00_0W50_0H50
TP_1_S_0D00_1D50 R2P8
C_2_S_1L00_0W50_0H50
IC_8_S_SOIC_1P27_5L00_4W00_1H75 V3_3 C3P1 R3P2 U8

H1x5
H1x6
Q5
H1 5 R125 FB9 R_2_S_1L00_0W50_0H35 R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H35
1 1 6 R_2_S_1L00_0W50_0H35 C_2_S_1L00_0W50_0H50
TP_1_S_0D00_1D50 R2P9R3P3
RP_8_S_0P50_2L00_1W00_0H45
1 05D1_00D0_S_1_PT 1
2
FB10 FB0P5
3
2 1 2 1 5 4
R128 R127 1
U8 Q5 W
2
U10
SW_5_S_2P25_6L50_6W50_3H10
CE1P0
FB_2_S_3L20_1W60_0H80
C_2_S_1L00_0W50_0H50
05D1_00D0_S_1_4PT 1 LCS 1_00D0_S_31_PT 1

R_2_S_1L00_0W50_0H50
R_2_S_1L00_0W50_0H50
R_2_S_1L00_0W50_0H30 TP_1_S_0D00_1D50D0N5GD-B
C_2_S_1L00_0W50_0H61 PD-BSU
R_2_S_1L00_0W50_0H35
C13
R_2_S_1L00_0W50_0H35
H1x8
H1x2
5KM
M ADS
R_2_S_1L00_0W50_0H35
C130 R3P1 1 2 2 1 2 1 1
1
1 2
8
IC_48_S_TSOPI_0P50_18L4_12W4_1H20 IC_4_S_SOT-223_2P30_6L50_3W50_1H65 2 C13 1 2 1 2 1 2 1 2 2 1
Q_3_S_SOT-23_1H40
1 R85SU 1
2 1 2 1 6 3
FB9 FB10
H1x4
Q_3_S_SSOT-3_1H38
C_2_S_1L00_0W50_0H50
05D1_S_16_KM 1 3 1 C_2_S_1L00_0W50_0H50 R14 R15

MC 2 R_2_S_1L00_0W50_0H35
2
PW
C_2_S_1L00_0W50_0H50 R_2_S_1L00_0W50_0H35
2
4 MD R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
1
1
0_S_1_PT2 1 MD-BSU
2 1 1 2 1 2 2 1
1 1
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
FB_2_S_1L60_0W80_0H80 R82 05D1_00D 2 2 1 7 2

1
2 1
C_2_S_2L00_1W25_1H25 R_2_S_1L00_0W50_0H35 R105
2
R123 2
1
1
C131 C_2_S_1L00_0W50_0H50
Q9 Q
Q_3_S_SOT-23_1H40
Q_3_S_SOT-23_1H40
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H32
R_2_S_1L00_0W50_0H32
R188 C124
D N G A
C197
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
U2
U2
FB8 FB_2_S_3L20_1W60_0H80
FB_2_S_1L60_0W80_0H80 2
3
1 2
TP_1_S_0D00_1D50 2 1 8 1 2
C3P0
1 2 2 1
U3
DPR197 Q9 Q17 R_2_S_1L00_0W50_0H35 1 8
C_2_S_1L00_0W50_0H50
CN5 2
PC_2_S_2L00_1W25_1H25
2 1 2 R_2_S_1L00_0W50_0H32 SW2 2 1 1 2 2 1
U11 CE0P9
05D1_00D0_S_1_PT 1 D C3P2 C36 R31 R_2_S_1L00_0W50_0H35
05D1_00D0_S_1_PT 11 BSU-V5+ 1 2 7
1 2 1
3
1
1
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H50 3 6
C_2_S_1L00_0W50_0H50 1
2
R30
R191
R190
R197 2
2
U23 4 5 2 1 1 2
R187
MK4 5 1 1 3V3
CN14x5
R84
R83
SW2
1 8
1
C199
2 2
R_2_S_3L20_1W60_0H55 C_2_S_1L00_0W50_0H50
C3P4
R_2_S_1L00_0W50_0H50
C_2_S_2L00_1W25_1H25
1
R196 2 1 1 2 1
IC_8_S_TSOT23-8_0P65_3L00_1W70_1H00
C_2_S_2L00_1W25_0H85
C
1 1
1
DNG-IFIW 2 7 5
5
C107
M
C_2_S_1L00_0W50_0H50
C2P9
2 2
R_2_S_1L00_0W50_0H35
05D1_00D0_S_1_R_2_S_1L00_0W50_0H32
R_2_S_1L00_0W50_0H35
L0P5
41 PT 1
R124
C117
C_2_S_1L60_0W80_0H90
1 1 1
R200 R198
25 24
2 1 1 2
1 3 6
C201
C101
MK_1_S_1D50 R_2_S_1L00_0W50_0H30 2 1 1
2 1 26 23 1 1
C76
R_2_S_1L00_0W50_0H35
2 2 2 2
R_2_S_1L00_0W50_0H32
27 22
-
2
C_2_S_2L00_1W25_1H25
U23
4 C_2_S_2L00_1W25_1H25
D3
2 2 28 21 2 2
C_2_S_1L00_0W50_0H50
4 5
U3 L_2_S_6L00_6W00_4H20 R199
C3P5
C3P3
2 29 20
CN5
2 1 1 1
C16
1 2 1
R201 R266
30 19
2 1
U11
C R199 CN7
31 18
05D1_00D0_S_1_PT 1 CN16
R_2_S_1L00_0W50_0H30 2 2 2
C_2_S_1L00_0W50_0H50
CE_2_S_6L60_6W60_5H50
SW_5_S_2P25_6L50_6W50_3H10
2 2 32 17
2
1
C_2_S_2L00_1W25_1H25
4 3 1
C_2_S_2L00_1W25_1H25
1
IC_8_S_SOP_1P27_5L00_4W00_1H75 1 33 16
D_2_S_1L00_0W60_0H39
05D1_00D0_S_1_PT 1 C125
R251 C200
R307 CE0P9 1 1 1
C215
C118
34 15
1
CCV-6LENAP 2
5
2 35 14
CN7x21
CN7x23
5
R_2_S_3L20_1W60_0H55
R223R252
36 13
2 2 1 1
0YEK
L_2_S_6L00_6W00_4H20
2 37 12
05D1_00D0_S_1N_3PAT 1
L_2_S_6L00_6W00_4H20
21
21 23
23
8 7 38 11
B
L0P5 1 2
RM4
TUN_15_H_VA4N1BD1219_7H50
39 10
2
P4A
R_2_S_1L00_0W50_0H35
CN7
TUN_14_H_MT-11A55WL_9H30
40 9
10 9
C198
SW1
05D1_00D0_S_1P_3PAT 1 N0A N1A
41 8
1
R140
C_2_S_1L00_0W50_0H50
42 7
C_2_S_1L00_0W50_0H50
12 11
2
43 6 1
DIP05D10_50D0D10_050_D0SD1__10N0_40PSBDT_10__1PST_1_1PT 1 R143
2
44 5 8 7 2
4
HS1
SW1
RM16 RM15
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
14 13 45 R_2_S_1L00_0W50_0H32 4 3
05D1_00D0_SN_E1__DP3T 1 RP_8_S_0P50_2L00_1W00_0H45
6 5
R298
2
1
46 3 4
3
4 3
RM10 47 2 5
16 15
P4BV PKLCA R_2_S_1L00_0W50_0H32 2 1
E
48 1 6
05D1_00D0_S_1_PT 1
R_2_S_1L00_0W50_0H32
RM9
2 1
HS1x1
RM11 R_2_S_1L00_0W50_0H35 7
18 17
R292 05D1_00D0_S_1_PT 1 P0A RM13
RP_8_S_0P50_2L00_1W00_0H45
RP_8_S_0P50_2L00_1W00_0H45
R250
8
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35 R_2_S_1L00_0W50_0H32 R145 9
7
1
5
2 1
05D1_00D0_0SN5_2D 1B_1P_0T005DD101__S0_01D_0P_TS_11_PP2TA 1 NKLCA 12

10
2 1
11
20 19
R_2_S_1L00_0W50_0H35 2 1 1 2
R146
R50
R61
R49
11
R112 R113
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
2
R_2_S_1L00_0W50_0H35
05D1_00D0_S_1_PT 1
1 2 3 4
22 R_2_S_1L00_0W50_0H35 21 2 1 2 1 3 4
C195 5 6
R_2_S_1L00_0W50_0H35 2 1
12
13
IC-369P-P08
0R308 R141
05D1_00D0_S_1-_HPCT 1
C_2_S_1L00_0W50_0H61
RM8
RP_8_S_0P50_2L00_1W00_0H45
RP_8_S_0P50_2L00_1W00_0H45 N_01B
_01_1SP0_T51D
5 6
5D10_50D 0D RM12
10_050_D0SD 1_00__0PSDT C196 7 8 R_2_S_1L00_0W50_0H35 14
C_2_S_2L00_1W25_1H25
RL_D3 _1P1T_00_0S1D_10__1P
7
RP_8_S_0P50_2L00_1W00_0H45
5
2 1
R304 _1_1PT 1
7 8 15
0_1S__010_DP0T_S_11_PT 1 ST R142
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H32
05RP_8_S_0P50_2L00_1W00_0H45
05H0_05W0_00L916_CS_20_5CH0_05W0_00L1_S_2_C 68C
1 1 1
05D1_000D 24 23
MID
RM7
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30 2 1 1 2 16
RP_8_S_0P50_2L00_1W00_0H45
R87 R55 R60 R58 05D10_50D 1_00_0SD

1
0 D _ 1 P T
5
5D
R18 R103
2
6
2 1
R293 R21 RM14 2 2 2
2 1 1 2 R_2_S_1L00_0W50_0H35 R106 C106
D4
17
R_2_S_1L00_0W50_0H35
1 2
R_2_S_1L00_0W50_0H30 R_2_S_1L00_0W50_0H30
HS1
C_2_S_1L00_0W50_0H61 1 2
H0_0RP_8_S_0P50_2L00_1W00_0H45
_0P2 _TS_11_PT 1 P3B N3B P1A N2A N4A

2 1 1 2
05D1_00D0_JSD_A 1_-LPBT 1
18
26 25 R_2_S_1L00_0W50_0H32
CE9
R_2_S_1L00_0W50_0H35 C17 052 D1 1_02 0051DD011__S20_01D C_2_S_1L00_0W50_0H61 3 4 C_2_S_1L00_0W50_0H50 R144
R19
3 4
R296
19
R16
L6
U9 05D1_00D02_S1 _1_PT2 11 R_2_S_1L00_0W50_0H35
R138
L7 1
R101
5 6
5 6
1 2 D_2_S_1L00_0W60_0H39
R_2_S_1L00_0W50_0H30
L2x2
L2x1
28 27 7 8 -
RP_8_S_0P50_2L00_1W00_0H45
3 4
2 1
R300
EDOM 7 8
SW3D4 1YEK
L2
U9
05D1_00D0_S_1_PT 1
2 1 2 1 1 2
R_2_S_1L00_0W50_0H35
1R_2_S_1L00_0W50_0H35 R139
2
5 6 C_2_S_1L00_0W50_0H50
0_S_1_PT 1 P2B
CN7x20
CN7x22
C219 2
051D21_02 0D 1
C24
2 C_2_S_1L00_0W50_0H50
L6 L7CE9
RP_8_S_0P50_2L00_1W00_0H45
30 29 7 8
C122
5W0_706C
R51
2 1 1 1
R_2_S_1L00_0W50_0H35
L2 1 2 1 2 1 2 C58
05D1_00D0_SN_K1L_CPBT 1 20
20 22
22
2
4
L6x1
L6x2
RP_8_S_0P50_2L00_1W00_0H45
32 31
P0B 2 1
L7x1
L7x2
1 2 2 1 2
R_2_S_1L00_0W50_0H35
2
R56 1 2 C_2_S_1L00_0W50_0H50
SW3 CE10
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H35 C61 R102
FB2 R20
C62
1 2
34 33 PKLCB 1 2
1 2 C_2_S_1L00_0W50_0H50
05D1_00D0_S_1_PT 1
R_2_S_1L00_0W50_0H35
L_2_S_6L00_6W00_4H20
L_2_S_6L00_6W00_4H20
U4 R86 1 2 C_2_S_1L00_0W50_0H50
R_2_S_1L00_0W50_0H35
2 1 CE10 1 2 R158C120
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
JA_23_S_HDMI_H_8H40
2 1
R100
B21 C21 D21 F21 G21 J21 K21 M21 N21 R21 T21 V21 W21 Y21
36 35
0L1_S_2_0C5H0_05W0_00L1_S_2_C
1
2
SMT
C21
R_2_S_1L00_0W50_0H32
C78
C79
1
C_2_S_1L60_0W80_0H80
R_2_S_1L00_0W50_0H30 R163 2 1
0_1S__010N_D1P0BT_S_11_PT 1 CE_2_S_6L60_6W60_5H50 Serial No.

A20 B20 C20 D20 E20 F20 G20 H20 J20 K20 L20 M20 N20 P20 R20 T20 U20 V20 W20 Y20 AA20
05D1_000D IC_8_S_TSOT23-8_0P65_3L00_1W70_1H00
07C
FB_2_S_1L60_0W80_0H80
2 2 2 R_2_S_1L00_0W50_0H35
38 37
P1B C_2_S_1L00_0W50_0H50 U4 1 C123
5D A19 B19 C19 D19 E19 F19 G19 H19 J19 K19 L19 M19 N19 P19 R19 T19 U19 V19 W19 Y19 AA19
1
4
C_2_S_1L00_0W50_0H50
40 39 U15 C_2_S_2L00_1W25_1H25
C_2_S_3L20_1W60_1H35
1 2
1 1 1
A18 B18 C18 D18 E18 F18 G18 H18 J18 K18 L18 M18 N18 R18 T18 U18 V18 W18 Y18 AA18
05D1_00D0_S_1_PT 1 1 2
L_2_S_6L00_6W00_4H20
C_2_S_1L60_0W80_0H90
1 2 2 2 1
2 A17 B17 J17 K17 L17 M17 N17 P17 R17 T17 U17 W17 Y17 2 1 1 2
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
+HC
52H1_52W1_00L2_S_2_C
C66
C64
C63
C65
C68
1 1
C_2_S_1L00_0W50_0H50 C_2_S_1L00_0W50_0H50 C_2_S_1L00_0W50_0H50 C_2_S_1L00_0W50_0H50
C18
1 1 1 1 1
C22 C23
A16 B16 J16 K16 L16 M16 N16 P16 R16 T16 U16 V16 W16 Y16 AA16
C149 2 2
CE_2_S_6L60_6W60_5H50
2
U12
C20C18 A15 B15 C15 D15 E15 F15 G15 K15 L15 M15 N15 P15 R15 T15 U15 V15 W15 Y15 AA15
CN6
1
2 2 2 2 2 4 3
118C C_2_S_1L00_0W50_0H50 R183
5
15 14
1 2 1 2 2
H5x1 H5x3
C
1
42
U15
A14 B14 C14 E14 L14 M14 N14 P14 R14 T14 U14 W14 Y14
2
IC_29_S_HTSSOP_0P65_9L70_4W C
16 13 2
H5
3
1
R_2_S_1L00_0W50_0H35 1 2
R_2_S_1L00_0W50_0H35 1
H5x7
H5x9
R_2_S_1L00_0W50_0H30 C22
CN6x21
CN6x23
R62
A13 B13 C13
28C F13 L13 M13 N13 P13 R13 T13 U13 V13 W13 Y13 AA13
HEATSINK40.2X41.5 R156
1
17 12 1 2 R_2_S_1L00_0W50_0H35
X1 X1
7 9 R_2_S_1L00_0W50_0H35 R74
R160
FB_2_S_16L0_0W80_0H80
18 11
C160 R305 A12 B12 C12 D12 E12 F12 G12 J12 K12 L12 M12 N12 P12 R12 T12 U12 V12 W12 Y12 AA12
5 1
R162R155 1 2
39
1 2
R_2_S_1L00_0W50_0H32
40
C159
C_2_S_2L00_1W25_0H85 U12
21
21 23
23
CN_42_S_2R_1P25_W_F_2H80
DNG-LENAP
19 10
R63
05D1_00D0_S_1_PT 1
2 1 B11 C11 D11 E11 F11 G11 H11 J11 L11 M11 N11 P11 R11 T11 U11 W11 Y11
C155
C_2_S_2L00_1W25_0H85 R_2_S_1L00_0W50_0H35 R_2_S_1L00_0W50_0H30
D_3_S_3L10_1W65_1H40
C165
H5x5
H5x6
1 2 2 1 1 2
05D1_0005DD01__S01_01D_0P_TS_1_PT 1 2 2 1
29
20 9
C161C158 1 2 R78
CN6
2 1
5
11
C162 6 21 8
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30
A10 B10 C10 D10 E10 F10 G10 H10 J10 L10 M10 N10 P10 R10 T10 U10 V10 W10 Y10 AA10
R77R71
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30 1 2
R_2_S_1L00_0W50_0H30
Q_3_S_SOT-23_1H40
C_2_S_1L00_0W50_0H50
A9 B9 C9 D9 E9 F9 G9 H9 J9 K9 L9 M9 N9 P9 R9 T9 U9 W9 Y9 AA9
C147
22
C_2_S_1L00_0W50_0H50 7
C157 R641 2
R_2_S_1L00_0W50_0H30
C_2_S_1L00_0W50_0H50 1TX
C
1 2 1 2 2 1
R234R233 C_2_S_1L00_0W50_0H55 2TX
H5x8
H5x2
1
23 6 B8 C8 E8 F8 G8 H8 J8 K8 L8 M8 N8 R8 T8 U8 V8 W8 Y8
CN18 C
1
C163
C_2_S_1L60_0W80_0H80
R297 R75
RM3 RM2
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
2
8 2 R228 99C 8 7
C
H5x4
1
24 5
C156 L4 2 1 A7 B7 C7 D7 E7 F7 G7 H7 L7 R7 T7 U7 V7 W7 Y7 AA7 3
U
L5
C_2_S_1L00_0W50_0H50 R229 R236 C112 6 5
1
R232 C154
4 C153
25 4
2
2 1 A6 B6 C6 D6 E6 F6 G6 H6 J6 L6 M6 1 N6 2 R6 T6 U6 V6 W6 Y6 AA6
R_2_S_1L00_0W50_0H32
R_2_S_1L00_0W50_0H32 R59
2 1
C110
2 1
R89
1 2 4 3
4
C_2_S_2L00_1W25_0H85 26 3
R312
R231R54 C60 R72 2 1 C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
5
C108
P0 NO.
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H32 2 1
C_2_S_2L00_1W25_0H85
C
C_2_S_1L60_0W80_0H80 B5 C5 E5 F5 G5 H5 K5 L5 P5 R5 T5 U5 V5 W5 Y5
C72 R309
6
27 2
05H0_05W0_00L1_S_129_CC
A
C_2_S_2L00_1W25_0H85
C152
1
1 2 2 1 7
2 R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H32 28 1 1 A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 T4 U4 V4 W4 Y4 AA4 R_2_S_1L00_0W50_0H32
R_2_S_1L00_0W50_0H32
C_2_S_1L00_0W50_0H50 8
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50 8 7
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
2 1 2 1 2 1
L5x1
L5x2
L4x1
L4x2
C_2_S_1L00_0W50_0H50
C71 R310
+R_KPSTP_1_S_0D00_1D50
A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 N3 P3 R3 T3 U3 V3 W3 Y3 AA3
L5 L4 CE8
IC_6_S_SOT-23-6_0P95_3L12_1W80_1H45
1 2 2 1 2 1 1 2 6 5
5 C_2_S_2L00_1W25_0H85 1 C_2_S_1L60_0W80_0H80 10
2 1
CN18
4 3
2 R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 R_2_S_1L00_0W50_0H35 11
R_2_S_1L00_0W50_0H32
R_2_S_1L00_0W50_0H32
2 2 1 2 1 2 1 2 1
C_2_S_2L00_1W25_0H85
12
2 1 2 1 2 1 2 1
1 C151 B1 C1 D1 F1 G1 J1 K1 M1 N1 R1 T1 V1 W1 Y1
R136
1
R38 C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
1 TP_1_S_0D00_1D50
13
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H32
C_2_S_1L00_0W50_0H50 1 2 R_2_S_1L00_0W50_0H35
R230 R311 C85 R69 R135 2 1 1 2
14
W
C1482 1
A
Y
AA
C
G
B
N
P
R
T
U
E
F
L
J
1
1 C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50 2 1 1 2 1 2 1 2 2 1 2
R57
D_2_S_2L85_1W75_1H15
1 2
R211
15
-R_KPS C150 C164 R235C59

5800-A6M83B-0P00 R137
C146
1
Q_3_S_SOT-23_1H40
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
C88 C_2_S_1L00_0W50_0H50
16
2 R_2_S_1L00_0W50_0H32 C_2_S_1L60_0W80_0H80
C_2_S_1L00_0W50_0H50 R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H32C100 1 2 1
R_2_S_1L00_0W50_0H35
C_2_S_1L00_0W50_0H50 R_2_S_1L00_0W50_0H35 R_2_S_1L00_0W50_0H35
R132
R66
78C
R134 2 1 1 2
17
2 1 2 1 1 2
1
1 TP_1_S_0D00_1D50
2
2 1 2 1 2 1
C_2_S_1L00_0W50_0H50 R164 18
2
R_2_S_1L00_0W50_0H35 C95 U6 R_2_S_1L00_0W50_0H35
19
C89
C92
Q21
-L_KPS 1 2 R213 C94 C53 R161 2 1 1 2

C_2_S_2L00_1W25_0H85
2 1 1 2 2 1 1 2
1 C73
R_2_S_1L00_0W50_0H30
2 1 1 2 1 2
1 TP_1_S_0D00_1D50 R227 R226

R_2_S_1L00_0W50_0H32 R53 1 C_2_S_1L00_0W50_0H50
VER00.00 C93 R_2_S_1L00_0W50_0H30
CN6x20
CN6x22
C
1 2 1 2
R46
C_2_S_1L00_0W50_0H50
C_2_S_1L00_0W50_0H50
3
R214
C52 R171
R169R133
R129
R_2_S_1L00_0W50_0H32
R_2_S_1L00_0W50_0H35
U6 Q
1 2
C51 R44 1 2
1
CE_2_S_6L60_6W60_5H50C142 C_2_S_1L00_0W50_0H50 C_2_S_1L00_0W50_0H50 1

FB6
1 1
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
FB5
2
FB_2_S_16L0_0W80_0H80
+L_KPS R131C126 C90

R5
Q D6
C34
C_2_S_1L00_0W50_0H50
C 20
20 22
22
2 2 1 2 FB_2_S_1L60_0W80_0H80 C74 C50 R42 R45
R1S3
3 1
R48
C75
R104
1 2 2 1 2 1 2
R17
4
R_2_S_1L00_0W50_0H35
C_2_S_1L00_0W50_0H50 FB4 C57
1 3 3 C_2_S_2L00_1W25_1H45 C56
4
R212
2
CE8
2014-09-02
R_2_S_1L00_0W50_0H30 R47 R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
C_2_S_1L00_0W50_0H50 C_2_S_1L60_0W80_0H80
B
D0S1
2 2 1 1 2 1 2 1 2
2
C202
CE5
C32
2 1
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H32
1 1 R_2_S_1L00_0W50_0H35
C C
C_2_S_1L00_0W50_0H50
HHS1x2
C203 R_2_S_1L00_0W50_0H32 2 1 R170 R172

C35
D14 C_2_S_1L00_0W50_0H50
Q_3_S_SOT-23_1H40
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
JA_23_S_HDMI_H_7H35
2 1 2 1 1 2
71RI 1 2
D6
C_2_S_2L00_1W25_1H25
1 2 1 2 1 2
Q20
R_2_S_1L00_0W50_0H35 1
6 TN1
Q12
1 2 2 1 2 1 2 1
3
C44
C43
C42
C41
R_2_S_1L00_0W50_0H35
C_2_S_1L60_0W80_0H90
C_2_S_1L60_0W80_0H80
C_2_S_1L60_0W80_0H80
R209
R43 C_2_S_1L00_0W50_0H50
D Q
1 2 C_2_S_1L00_0W50_0H50
R_2_S_1L00_0W50_0H35
C33
C_2_S_1L00_0W50_0H50
2 2 2 2 2 1 2 1
C_2_S_2L00_1W25_1H45 3
CN4
1 2
C_2_S_1L00_0W50_0H50 R_2_S_1L00_0W50_0H32
1 2 2 R_2_S_1L00_0W50_0H35
C_2_S_1L00_0W50_0H50 1 2 2 1
2 2
1
Q
D_2_S_1L00_0W60_0H39
D_2_S_1L00_0W60_0H39
D_2_S_1L00_0W60_0H39
Q_3_S_SOT-23_1H40 R215R216
D_3_S_3L10_1W65_1H40
1 2
1 2 1 R_2_S_1L00_0W50_0H35
C_2_S_1L00_0W50_0H50 1 1 1 1
S_12_P1 T 2 11R173
1 2
2 R166 - VA D_2_S_1L00_0W60_0H39
D7
8
02 51D1_2 001 D02 _R_2_S_1L00_0W50_0H32 1

D7
1
1 2
2
IC_4_S_SOT-223_2P30_6L70_3W65_1H75
1 1 2
R_2_S_1L00_0W50_0H35 R_2_S_1L00_0W50_0H35
CN_6_S_1R_2P00_T_M_5H10
C
3
TN1
R_2_S_1L00_0W50_0H35
1
2 2 2 2 2 2
Q13 R_2_S_1L00_0W50_0H30
C45R40
1 2
C47 R37
2
CE_2_S_6L60_6W60_5H50
Q F
2 2 1 2 1
DNG-UT
C49 R39
AV
T1x15
T1x14
05D1_00D0_S_1_PT 1 JDA 2
1 1 1 1 1 1 1 2
11 R6 R CE5 2 1
5
1 2 2 1
Q_3_S_SOT-23_1H40
Q14 05D1_00D0_S_1_PT 1
CN4
Q_3_S_SOT-23_1H40
R36
R35
R34
R33
C46
CN4x1
Q L-VA
R_2_S_1L60_0W80_0H40
C48 R41
15
15 14
14
1 1 2 1 1
R_2_S_1L00_0W50_0H30
R4 R R219 T_16_S_S16013LF_12L8_6W90_5H65
05D1_00D0_S_1_PT 1 1
T2
1
1 2 1 2
R94 R91
1
1 2 1 2
3
1
EN
2 2 1 2 2
05D1_00D0_S_1_PT
SPARK_2_S_1P72_GAP
SPARK_2_S_1P72_GAP
SPARK_2_S_1P72_GAP
SPARK_2_S_1P72_GAP
NE R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
3
05D1_00D0_S_1_PT 1 1
Q ADS-T
3
Q3 D5 Q8
T1x1 T1x2 T1x3 T1x4 T1x5 T1x6 T1x7 T1x8 T1x9 T1x10 T1x11
Q10
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30
CN15 CN21
R67 JA_5_S_EPHONE_H_8H00
T2x14
Q15 IC_8_S_SOP_1P27_5L00_4W40_1H61 05D1_00D0_S_1_PT 1 11
T1
Q_3_S_SOT-23_1H40
H2x1
14
H2x3
Q_3_S_SOT-23_1H40
D_3_S_3L10_1W65_1H40
Q_3_S_SOT-23_1H40 R263 R-VA
T1
05DD1N_G0-0VDA0_S_1_PT 1
H2
3 U14
H2x7
H2x9
Q3 D5 C144 R217 R210

R253
R221
H2
1
2 7 9
C_2_S_1L00_0W50_0H50 Q8 LCS-T
R256 R255
10
QC PASS R_2_S_1L00_0W50_0H32
R_2_S_1L00_0W50_0H32 C143 C139 C138 05D1_00D0_S_1_PT 1
R167
C_2_S_1L00_0W50_0H50
CN4x3
CN4x4
10
11
12
13
14
15
16
SG5
R_2_S_1L00_0W50_0H35
SG69
3 4
RM17
C206 05D1_00D0_S_1_PT 1
H2x5
H2x6
R_2_S_1L00_0W50_0H35
CE6
R_2_S_1L00_0W50_0H30
R220
U14
C C
C_2_S_3L20_1W60_1H60
2 1 1 2 1 2 1 2 1 2 5 4
T2x4 T2x5 T2x6 T2x7 T2x8 T2x9 T2x10 T2x11
1 2
T2
5
1 1 6
05D1_00D0D_NSG_-1W_O P 13 9
1
R88 C_2_S_1L60_0W80_0H80 SDA

PT R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H35
2 1 2 1 1 2 2 1
11
C_2_S_2L00_1W25_1H45
C_2_S_1L60_0W80_0H80
C111 R90 C109 C209
R_2_S_1L00_0W50_0H35 2 1 6 3
R165
C_2_S_1L00_0W50_0H50
R_2_S_1L60_0W80_0H40
D13 R168
SPARK_2_S_1P72_GAP
R_2_S_1L60_0W80_0H40
H2x8
H2x2
1
SPARK_2_S_1P72_GAP
C208
CE7 CE6
1
U22
8 2 1
1
U22
1 2
1 2 C145C_2_S_2L00_1W25_1H45
C_2_S_2L00_1W25_1H45 2 2 1
C216 R107
8
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
4 3
H2x4
7 2
10
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
05D1_00D0_SF_F1O_/N
PO
1 2 SCL
R254
T 14 R_2_S_1L00_0W50_0H30
R147 R148
4
C209
1 1 2
2
2 2 5 2 3 4
C_2_S_1L60_0W80_0H80
1
FB7 C204
2 5 6 C_2_S_2L00_1W25_1H25 8 1
D12
R_2_S_3L20_1W60_0H55
SG3
C_2_S_3L20_1W60_1H60
05D1_00D0_S_1+_FPIT 1
T2x13
R_2_S_1L00_0W50_0H35
6 1 7 8
FB15 1 2 7 9
2 2 2
R_2_S_1L60_0W80_0H40
C140 NC
D8
R157
R218
1
R_2_S_3L20_1W60_0H55
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
13
2 2 2 2 2 1
C_2_S_3L20_1W60_1H35
C208 C
SG2
SG1
SG4
1 1 1
R152
R151
5
RP_8_S_0P50_2L00_1W00_0H45
R150
R149
FB7C204 F
1
2 2
-FI
2
-
-
-
R262
R225
R261
R224
1 2 1 2
R153 CE_2_S_6L60_6W60_7H70 6 NC
2
IFP
1 1 1
R_2_S_1L00_0W50_0H30 1 1 2 R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30R_2_S_1L00_0W50_0H35 1 1
C_2_S_1L00_0W50_0H50
FB_2_S_1L60_0W80_0H80
C141 1 2 05D1_00D0_S_1_PT 1 8
2
5
C205 C_2_S_3L20_1W60_1H35 R96 R92 R174

Y
CN20
R176
CN20x1
6 R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
R_2_S_1L00_0W50_0H35
P_S_1_PYT 1
IF-
05D1_00DC0G_A
S-_F1I_PT 1
R177 L-PH R179 R180 R178 5 R0 1
IFN
2 1
D9 CE_2_S_6L60_6W60_7H70
1 2 2 2 1 2 1 2 1 1 2 1 2 1 2 1 2 2 1
057D1_00D
R_2_S_1L60_0W80_0H45
R_2_S_1L60_0W80_0H45
1 1 R95 R93 R175 R182 R181 - D_2_S_1L00_0W60_0H39 1 1
R_2_S_1L00_0W50_0H35 -
D
R_2_S_1L00_0W50_0H35 -G
D
R_2_S_1L00_0W50_0H30
R_2_S_1L00_0W50_0H30D9 D10
-AGVD_2_S_1L00_0W60_0H39 2 1 1
D11
PR
1
2 1 2 1 2 1 2 1 2 1 2 2
D_2_S_1L00_0W60_0H39
3
CN21x1
CN21x3
CN21x5
CN21x7
054D1_00D0_S6_1_PT 1
Q
R_2_S_1L00_0W50_0H30
7 2 05D1_0CE7
0D0_S_1_PT
2 1 2 JA_5_S_EPHONE_H_8H00 1 IF+ GND
1 3 5 7
M M
2
8
4
1 1 1
JA_10_H_RJ45_V_15H9 Q_3_S_SOT-23_1H40
RP_8_S_0P50_2L00_1W00_0H45
RP_8_S_0P50_2L00_1W00_0H45
2
SV_1_PT 1 R-AGV R-PH CCV-T 055D1_100D0_S_1_PT 1
2
PB BP
CN21x2
CN21x4
CN21x6
CN21x8
05D1_00D B0 -A_G
1
7
3
2 2 2
CN17x4 CN17x1
05D1_00D0_S_1_PT 1 3 GND
1
C_2_S_1L60_0W80_0H80
CN12 CN17
2 4 6 8 R_2_S_1L00_0W50_0H30 IF AGC
+8XT_TEN 05D1_00D 1
050D
_S1__10_0PDT0_S_1_PT 1
12 T1x12
T1x13
CN20x3
CN20x4
RM6 RM5
05D1_00D0_S_1_PT 1 1 1 2
Q11 1 05D1_00D0_S_1_PT 1 1 05D1_00D0_W
S_S1-_FPRT 1 05D1_040D0_2 S_1_PT 1 3 4
12
13
-XR_TEN DNG_TEN R_2_S_1L00_0W50_0H35 2 SDA

CN12x5
CN12x4
CN12x3
CN12x2
CN12x1
12
13
CN12x16
CN12x17
NC
CN20 H3
2 1
0_1S__010_DP0T_0S5_1D 00D10_S_1_PT 1
1_1P_T
CN12 C119
-X09
T5_D
T1E_N000D
5D 55 44 33 22 11 RPBPY_DNG
19
18
17
16
15
14
13
12
11
10
05D1_00D0_S_1_PT 1
9
CN17x2
CN17x3
CN8
2 R159R154
16
16 17
17
C167
TR6
1 SCL
CN12x10
CN12x9
CN12x8
CN12x7
CN12x6
B1
7K1M
2
H3x1
05D1_00D0_S_1_PT 1
H3x3
05D1JA_17_H_VGA_V_17H6
22
33
JA_4_H_EPHONE_V_10H0
TED-PH
M
CN8x22
CN8x20
+XR_TEN
C_2_S_3L20_1W60_1H35
V21_RWP SV-AGV 10
10 99 88 77 66 _00D0_S_1_PT 1
H3
CN21x9
CN21x10
3
T2x12
0_S_1_PT 1
JA_22_S_HDMI_V_16H0
H3x7
H3x9
05D1_00D 1
CN21x
22 20 1
T2x2
10
M
10
6KM 05D1_S2_1_KM 7 9 RF
CN12x15
CN12x14
CN12x13
CN12x12
CN12x11
9
GND
1 1
05D1_S_1_KM 15 14
15 14 13
13 12
12 11
11
H3x5
H3x6
C_2_S_1L00_0W50_0H50 2
M
-
T2x1
CN8x21
5
11
6 NC IF AGC
4
FB1
1 MK_1_S_1D5012 CN21 21 DVT01_S01_01D_0P_TS_11_PT 1

CN8 05D1_00D
050LD
_CS1S_-10A_05GP 2 1
T2x15
ADS-AG
0V5D1_00D0_S_1_PT
H3x8
H3x2
1
M 8 2
15
H3x4
C128
CN_12_S_1R_2P50_W_M_6H00
MK2 SH-AGV 4
1
CN15 DNG-PH
CN17 MK_1_S_1D50
MK3
+ B1
GND
10
165.0mm
181.0mm
6M83B Troubleshooting
Q7"C"
Q7 Ｕ２
Q17"C"
Q17
U11
Q17

PLD4016FT Service Manual PDF

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

PLD4016FT Service Manual PDF

Încărcat de

Drepturi de autor:

Formate disponibile

Please refer to the picture

长周期\关键件分类 物料编号 单机用量 位号

6-W FILTER-FREE STEREO CLASS-D AUDIO POWER AMPLIFIER WITH

OUTL+ LINP TPA3113D2

Figure 1. TPA3113D2 Simplified Application Schematic

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s) :TPA3113D2

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3

PWP (TSSOP) PACKAGE

4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s) :TPA3113D2

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5

FUNCTIONAL BLOCK DIAGRAM

PBTL Select OUTPL FB

6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s) :TPA3113D2

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

THD − Total Harmonic Distortion − %

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7

TYPICAL CHARACTERISTICS (continued)

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

THD − Total Harmonic Distortion − %

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

THD+N − Total Harmonic Distortion + Noise − %

8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s) :TPA3113D2

TYPICAL CHARACTERISTICS (continued)

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

THD+N − Total Harmonic Distortion + Noise − %

Figure 10. Figure 11.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

THD+N − Total Harmonic Distortion + Noise − %

Figure 12. Figure 13.

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9

TYPICAL CHARACTERISTICS (continued)

MAXIMUM OUTPUT POWER OUTPUT POWER

10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s) :TPA3113D2

TYPICAL CHARACTERISTICS (continued)

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11

TYPICAL CHARACTERISTICS (continued)

EFFICIENCY SUPPLY CURRENT

ICC − Supply Current − A

CROSSTALK SUPPLY RIPPLE REJECTION RATIO

−40 VO = 1 Vrms −20 ZL = 8 Ω + 66 µH

−110 Left to Right

Figure 24. Figure 25.

12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s) :TPA3113D2

TYPICAL CHARACTERISTICS (continued)

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION + NOISE

THD+N − Total Harmonic Distortion + Noise − %

Figure 28. Figure 29.

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 13

TYPICAL CHARACTERISTICS (continued)

SUPPLY CURRENT SUPPLY RIPPLE REJECTION RATIO

KSVR − Supply Ripple Rejection Ratio − dB

0.5 −60 VCC = 12 V

Figure 30. Figure 31.

14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

长周期\关键件分类物料编号单机用量位号