A

Project Report

On

“LOW POWER DESIGN FOR A WORD –LEVEL

NORMAL BASIS FINITE FIELD MULTIPLIER USING
FACTORING TECHNIQUE”

Submitted in partial fulfilment of requirements for

the award of the degree of
MASTER OF TECHNOLOGY
In

VLSI SYSTEM DESIGN

By

B.PRASANNALAXMI

(168R1D5703)

Under the esteemed guidance of

G.SWATHI Asst.Prof

Department of Electronics and Communication Engineering

CMR ENGINEERING COLLEGE

(Approved by AICTE & Affiliated by JNTU, Hyderabad)

Kandlakoya (V), Medchal (M), Hyderabad-501401

2016-2018
 CMR ENGINEERING COLLEGE
(Approved by AICTE New Delhi, Affiliated to JNTU, Hyderabad)

KANDLAKOYA, MEDCHAL ROAD, HYDERABAD – 501401 2015-2017

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

CERTIFICATE

This is to certify that the dissertation entitled “Low Power Design for a Word –
Level Normal Basis Finite Field Multiplier Using Factoring Technique” is being
carried out by Ms. B.PRASANNALAXMI bearing Roll Number 168R1D5703 in partial
fulfilment of the academic requirements for the award of the degree of MASTER OF
TECHNOLOGY in VLSI SYSTEM DESIGN, submitted to the Department of
ELECTRONICS AND COMMUNICATION ENGINEERING, CMR
ENGINEERING COLLEGE, HYDERABAD.

INTERNAL GUIDE HOD

(Mrs.G.SWATHI) (Dr.D.BHASKAR)

Asst.Professor Professor, Dept of ECE

EXTERNAL EXAMINER
 DECLARATION
I hereby declare that the Project entitled “LOW POWER DESIGN FOR
A WORD –LEVEL NORMAL BASIS FINITE FIELD MULTIPLIER
USING FACTORING TECHNIQUE” is done by me, submitted in partial
fulfilment of the requirements for the award of the degree in MASTER OF
TECHNOLOGY in VLSI SYSTEM DESIGN, for the year 2016-18.

This is a record of bonafide work carried out by me and the results obtained
have not been reproduced or copied from any source. The results of this
dissertation have not been submitted to any other University or Institute for the
award of any Degree.

DATE: B.PRASANNALAXMI
PLACE: (168R1D5703)
 ACKNOWLEDGEMENTS
A part from the efforts of me, the success of this project depends largely
on the encouragement and guidelines of many others. I take this opportunity to
express my gratitude to the people who have been instrumental in the successful
completion of this project.

I render my thanks to Sri. CH. NARASIMHA REDDY, Chairman CMR

Engineering College, for his encouragement.

I express my sincere gratitude to Dr. A.S REDDY, Principal, CMR

Engineering College, for providing excellent academic environment in the
college.

I thank and express my gratitude to Dr.D.BHASKAR, Professor, Head of

the Department, ECE for providing with both time and amenities to make this
project a success within schedule.

I take unique privilege to express my thanks to Dr. B. HARI KRISHNA,

Professor, Department of ECE, Project Coordinator for his valuable guidance and
encouragement given to me throughout this project.

I am grateful to internal guide Mrs.G. SWATHI, Asst.Professor, for his

valuable suggestions and guidance during the execution of this project work.

I extend my thanks to all the people, who have helped me a lot directly or
indirectly in the completion of this project

B.PRASANNALAXMI

(168R1D5703)
 CONTENTS
CHAPTER 1 INTRODUCTION .....................................Error! Bookmark not defined.
1.1 FINITE FIELD .............................................................Error! Bookmark not defined.
1.2 REPRESENTATION ...................................................Error! Bookmark not defined.
1.2.1 Polynomial Basis ..........................................................Error! Bookmark not defined.
1.2.2 Normal Basis ................................................................Error! Bookmark not defined.
1.2.3 Dual Basis .....................................................................Error! Bookmark not defined.
1.3 POLYNOMIALS..........................................................Error! Bookmark not defined.
1.6 FINITE FIELD ARITHMETIC....................................Error! Bookmark not defined.
1.7 TYPES OF FAULTS ....................................................Error! Bookmark not defined.
1.8 ERROR DETECTION METHODS .............................Error! Bookmark not defined.
1.8.1 Concurrent Error Detection ..........................................Error! Bookmark not defined.
1.9 MAIN OBJECTIVES OF THE THESIS ......................Error! Bookmark not defined.
CHAPTER 2 LITERATURE SURVEY .......................Error! Bookmark not defined.
2.1 Survey on Various Finite Field Multipliers ..................Error! Bookmark not defined.
2.2 Survey on Various Error Detection Methods for Finite FieldMultipliers ............ Error!
Bookmark not defined.
CHAPTER 3................................................................. Error! Bookmark not defined.
HYBRID ERROR DETECTION TECHNIQUES FOR CLASSICAL
FINITE FIELD MULTIPLICATION ..................... Error! Bookmark not defined.
3.1 INTRODUCTION ........................................................Error! Bookmark not defined.
3.2 CLASSICAL FINITE FIELD MULTIPLICATION ALGORITHM Error! Bookmark
not defined.
3.3.1 Hardware Redundancy Techniques ..............................Error! Bookmark not defined.
3.3.3.1 Shifting technique .....................................................Error! Bookmark not defined.
3.3.3.2 Swapping strategy.....................................................Error! Bookmark not defined.
3.3.3.3 Duplication technique ...............................................Error! Bookmark not defined.
CHAPTER 4 ................................................................................Error! Bookmark not defined.
METHODS TO IMPROVE THE EFFICIENCY OF FINITE FIELD
MULTIPLIERS IN POLYNOMIAL AND NORMAL BASIS Error! Bookmark
not defined.
4.2 POLYNOMIAL BASIS BIT-PARALLEL SYSTOLIC ARRAY FINITE FIELD
MULTIPLIER ..............................................................Error! Bookmark not defined.
 4.2.1 Multiplication Algorithm and Architecture ..................Error! Bookmark not defined.
CHAPTER 5 ..............................................................................Error! Bookmark not defined.
METHODS TO IMPROVE THE EFFICIENCY OF FINITE FIELD
MULTIPLIERS IN WORD LEVELNORMAL BASIS ...... Error! Bookmark not
defined.
5.1 Multiplication Algorithm and Architecture ..................Error! Bookmark not defined.
CHAPTER-6 ...................................................................................Error! Bookmark not defined.
VERILOG PROGRAMMING LANGUAGE ............................Error! Bookmark not defined.
6.1 Introduction ..................................................................Error! Bookmark not defined.
6.2 History ..........................................................................Error! Bookmark not defined.
6.3 Verilog Code Structure .................................................Error! Bookmark not defined.
6.4 Verilog Design Issues ...................................................Error! Bookmark not defined.
CHAPTER-7 XILINX SOFTWARE .........................................Error! Bookmark not defined.
7.1 XILINX ISE OVERVIEW ...........................................Error! Bookmark not defined.
7.1.1 DESIGN ENTRY .........................................................Error! Bookmark not defined.
7.1.2 SYNTHESIS .................................................................Error! Bookmark not defined.
7.1.3 IMPLEMENTATION ..................................................Error! Bookmark not defined.
7.1.4 VERIFICATION ..........................................................Error! Bookmark not defined.
7.1.5 DEVICE CONFIGURATION ......................................Error! Bookmark not defined.
CHAPTER 8 SIMULATION RESULTS ...................................Error! Bookmark not defined.
CHAPTER 9 CONCLUSION AND FUTURE SCOPE .............Error! Bookmark not defined.
FUTURE SCOPE....................................................................Error! Bookmark not defined.
REFERENCES ...........................................................................Error! Bookmark not defined.
REFERRED IEEE PAPER
PUBLISHED PAPER
 LIST OF FIGURES

S.NO NAME OF THE FIGURE PAGE No.

Figure 1. General architecture of CED Error! Bookmark

not defined.

Figure 2. Block diagram of classical finite field multiplication 30

Figure 3. Flowchart for classical finite field multiplication algorithm 31

Figure 4. DWC for finite field multiplier 33

Figure 5. Time redundancy technique for multiplier 34

Figure 6. Dataflow in the first step 35

Figure 7. Dataflow in the second step 36

Figure 8. General structure of proposed technique 38

Figure 9. Block diagram for shifting method 39

Figure 10. Block diagram for swapping method 40

Figure 11. Block diagram for duplication method 42

Figure 12. SFG for multiplication over GF (2m) 50

Figure 13. Circuit of (i,k)th cell 52

Figure 14. Schematic diagram of polynomial basis multiplier 55

Figure 15. WL-NB multiplier over GF (2m) 58

Figure 16. Xk module 59

Figure 18: Simulation waveform for polynomial basis multiplier 66

Figure 19: Simulation waveform for word level normal basis multiplier 67

LIST OF TABLES

S.NO NAME OF THE TABLE PAGE No.

Table 1. Possible values of ‘m’ for irreducible AOP 5

Table 2. Contents of R3 register at every clock cycle 60

Table 3: Logic utilization for polynomial basis multiplier 66

Table 4: Logic utilization for polynomial basis multiplier 67

 Abstract

In CMOS based for the most part application-particular microcircuit

(ASIC) styles, add up to control utilization is overwhelmed by unique
power, wherever powerful power comprises of 2 noteworthy components,
to be specific, move control and inner power. Amid this venture a low-
control style for a digit-serial limited field number in GF (2m) is given.
Inside the arranged style, factorization method is utilized to lessen move
control. To the least complex of our data, factorization strategy has not been
reportable inside the writing getting utilized inside the style of limited field
number at relate field level. PC circuit substitution is furthermore used to
downsize inner power. The arranged style nearby many existing
comparative works are acknowledged for GF (28) on ASIC stage and a
correlation is made between them. The blend results demonstrate that the
arranged number style expends thirty seven the entire power.