FACULTY OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

COURSE PLAN
Course Code : CS01003
Course Title : DIGITAL COMPUTER FUNDAMENTALS
Semester : III
Course Time : Jun 2014 to Nov 2014

Period Timing
1 8.45 – 9.35 AM
2 9.35 – 10.25 AM
3 10.35 – 11.25 AM
4 11.25 AM – 12.15 PM
5 1.30 – 2.20 PM
6 2.20 – 3.10 PM

Location : SRM University, Kattankulathur (Annexure) – Technology Park

Faculty Details
Sec. Name Day Period Mail id
3 3
4 1
A MRS.G.SIVAGAMI 5 3 sivagami.g@ktr.srmuniv.ac.in
1 1
3 2
B MS.TYN.NAGAMALLISWARI 4 3 nagamalleswari.t@ktr.srmuniv.ac.in
2 1,5
C MR.S.JAGADEESAN 5 3 jagadeesan.s@ktr.srmuniv.ac.in
1 2
3 4
D MS.JV.VIDHYA 5 5 vidhya.j@ktr.srmuniv.ac.in
1 1
3 1
E MS.C.SINDHU 5 4 sindhu.c@ktr.srmuniv.ac.in
F MRS.S.SARANYA 3 2,4 saranya.s@ktr.srmuniv.ac.in
 5 6
1 6
2 4
G MS.KIRUTHIKA DEVI 4 1 kiruthikadevi.s@ktr.srmuniv.ac.in
1 1
2 6
H MS.D.VANUSHA 5 3 vanusha.d@ktr.srmuniv.ac.in
2 1
3 4
I MRS.KANMANI SIVAGAR 5 3 kanmani.s@ktr.srmuniv.ac.in
1 1
J Mrs.A.JACKULIN MAHARIBA 4 2,6 jackulin.a@ktr.srmuniv.ac.in
1 3
K Mrs.C.JAYAVARTHINI 3 1,3 jayavarthini.c@ktr.srmuniv.ac.in
2 4
3 4
L MRS.G.ABIRAMI 4 6 abirami.g@ktr.srmuniv.ac.in
2 2
3 4
M MR.T.SENTHIL KUMAR 4 3 senthilkumar.t@ktr.srmuniv.ac.in

Required Text Books:

1. Morris M. Mano and Michael Ciletti D., “Digital Design: With an Introduction to the Verilog HDL”, Pearson
Education, 5/e, 2013. [UNIT 5 - Chapter 3 & 4 ]
2. Morris Mano M., “Digital Logic and Computer Design”, Pearson Education, 1/e, 2010. [ UNIT 1
- Chapter 1 , UNIT 2 – Chapter 2 & 3 , UNIT 3 – Chapter 4 & 5, UNIT 4 – Chapter 6 & 7 ]
Web resources
http://www.elec.gla.ac.uk/coursedb/7ltv.pdf

Prerequisite : NIL

Objectives
1. To identify various number systems and work with Boolean Algebra.
2. To understand various logic gates.
3. To simplify the Boolean expression using K-Map and Tabulation techniques.
4. To analyze various types of flip flops used for designing registers and counters and understand
about the fundamental concepts of Hardware Description Language.
Assessment Details
Cycle Test – I : 10 Marks
Surprise Test – I : 5 Marks
Cycle Test – II : 10 Marks
Model Exam : 20 Marks
Attendance : 5 Marks

Test Schedule
 S.No. DATE TEST TOPICS DURATION
1 Cycle Test - I Unit I & II 2 periods
2 Cycle Test - II Unit III & IV 2 periods
3 Model Exam All 5 units 3 Hrs

Course Objective

1. Students use mathematical symbols to represent different bases and will communicate concepts
using different number systems.
2. Students will apply logic to design and create, using gates, solutions to a problem
3. Students will apply the rules of Boolean algebra to logic diagrams and truth tables to minimize the
circuit size necessary to solve a design problem
4. Students will design, construct, build, troubleshoot, and evaluate a solution to a design problem
5. Students will gain knowledge in analyzing and designing Combinational and Sequential Circuits

Course Outcomes
Students who have successfully completed this course will have full understanding of the
following concepts

Course outcomes Program outcome

1. Basics of Digital Fundamentals
2. Analysis and design of Combinational 1. To be able to design and implement digital
circuits electronics concepts in engineering field.
3. Analysis and design of Synchronous and
asynchronous Sequential circuits
4. Hardware Description Language

Detailed Session Plan

NUMBER SYSTEMS AND CODES

Digital Computers and digital systems – Review of binary number systems –Number Base conversions- Complements – Signed
Binary Numbers – Binary Arithmetic – Binary codes – Error Detection codes – Binary Logic – Logic Gates.
Sessi
Time Teaching
on Topics to be covered Ref Testing Method
(min) Method
No.
Quiz
1 Digital Computers and digital systems 50 2 BB
Objective type test
2 Review of binary number systems 50 2 BB
Quiz
3 Number conversion , Complements 50 2 BB Quiz
4 Signed Binary Numbers 50 2 BB Quiz
5 Binary Arithmetic 50 2 BB,PPT Quiz
Quiz
6 Binary codes 50 2 BB
Objective type test
7 Error Detection codes 50 2 BB Quiz, Assignment
 Quiz
8 Binary Logic, Logic Gates 50 2 BB
Objective type test

BOOLEAN ALGEBRA & SIMPLIFICATION

Boolean Algebra – Basic Theorems and properties – Boolean Functions –Canonical and Standard Forms – Karnaugh Map
Simplification – Two, Three,Four and Five Variables – NAND and NOR Implementation – Don’t Care Conditions
– Quine McCluskey Method
9 Boolean Algebra ,Basic Theorems and Properties 50 2 BB Quiz
Quiz
10 Boolean Functions 50 2 BB
Brain storming
Quiz
11 Canonical and Standard Forms 50 2 BB
Surprise Test
Group discussion
12 Karnaugh Map Simplification – Two Variables 50 2 BB, PPT
Quiz
Group discussion
13 Karnaugh Map Simplification–Three Variables 50 2 BB
Quiz
14 Karnaugh Map Simplification – Four Variables 50 2 BB Quiz, Assignment
15 Karnaugh Map Simplification – Five Variables 50 2 BB, PPT
Quiz, Assignment
16 NAND and NOR Implementation 50 2 BB
Quiz
Group discussion
17 Don’t Care Conditions 50 2 BB
Quiz
18 Quine McCluskey Method 50 2 BB Quiz, Assignment
COMBINATIONAL LOGIC CIRCUITS
Combinational Circuits – Adder - Subtractor – Design and Analysis procedures – Binary Parallel Adder – Decimal Adder –
Encoder – Decoder – Multiplexer – Demultiplexer – Magnitude comparators – Read Only Memory (ROM) –
Programmable Logic Array(PLA).
Quiz
19 Combinational Circuits,Adder,Subtractor 50 2 BB, PPT Group discussion
Objective type test
Quiz
20 Design and Analysis procedures 50 2 BB
Group discussion
Quiz, Comparative
21 Binary Parallel Adder 50 2 BB, PPT
study
Quiz
22 Decimal Adder 50 2 BB
Surprise Test
Quiz
23 Encoder 50 2 BB
Group discussion
Quiz
24 Decoder 50 2 BB, PPT
Comparative study
Quiz
25 Multiplexer 50 2 BB
Group discussion
26 Demultiplexer,Magnitude Comparators 50 2 BB, PPT Quiz
Quiz
27 Read Only Memory (ROM) 50 2 BB

28 Programmable Logic Array(PLA). 50 2 BB, PPT Quiz

SEQUENTIAL LOGIC CIRCUITS

Sequential circuits – Latches – Flip-flops – Triggering of Flip-Flops – Analysis of clocked sequential circuits – State reduction
and state assignment – Design procedure of clocked sequential circuits – Design of counters – Registers – Shift registers – Ripple
counter and Synchronous counter
 Group discussion
29 Sequential circuits,Latches 50 2 BB
Assignment
Group discussion
30 Flip-flops 50 2 BB, PPT
Assignment
Objective type test
31 Triggering of Flip-Flops 50 2 BB
Group discussion
Group discussion
32 Analysis of clocked sequential circuits 50 2 BB, PPT
Comparative study
Objective type test
33 State reduction and state assignment 50 2 BB
34 Objective type test
Design procedure of clocked sequential circuits 50 2 BB
Design procedure of clocked sequential circuits Quiz
35 50 2 BB
Group discussion
Objective type test
36 Design of counters 50 2 BB
Group discussion
37 Registers ,Shift registers 50 2 BB
Assignment
Quiz
38 Ripple counter and Synchronous counter 50 2 BB
Group discussion
HARDWARE DESCRIPTION LOGIC
Introduction to Hardware Description Language (HDL)-HDL for combinational circuits and Sequential Circuits

Introduction to Hardware Description 1

39 50 BB, PPT Group discussion
Language (HDL)
1 Group discussion
40 HDL – Register Transfer level 50 BB
Comparative study
1 Objective type test
41 HDL of binary multiplier 50 BB
Comparative study
1 Brain storming
42 Algorithmic state machines 50 BB, PPT
1 Surprise test
43 Control Logic 50 BB
Group discussion
1 Comparative study
44 HDL for combinational circuits 50 BB, PPT
Assignment
1 Comparative study
45 HDL for Sequential Circuits 50 BB, PPT
Assignment

BB – Black Board(Chalk & Board) PPT – PowerPoint Presentation

Name of the staffs :

Mrs.G.Sivagami,Ms.TYN.Nagamalliswari,Mr,S.Jagadeesan,Ms.JV.Vidhya,Ms.C.Sindhu,
Mrs.S.Saranya,Mrs.Kiruthikadevi,Ms.D.Vanusha,Mrs.Kanmanisivangar,Mrs.A.JackulinMahariba,
Mrs.C.Jayavarthini,Mrs.G.Abirami,Mr.T.Senthil Kumar

Prepared by Approved by

Mr.T.SENTHIL KUMAR, AP(Sr.G),CSE HOD/CSE