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SDH Basics
AN00091831 (62.1013.105.11-A001)
Edition e, 03.2000
M a r c o n i C o m m u n ic a t io n s G m b H
D -7 1 5 2 0 B a ck n a n g
T e le f o n ( 0 7 1 9 1 ) 1 3 -0 T e le f a x ( 0 7 1 9 1 ) 1 3 - 3 2 1 2
h t t p : / / w w w .m a r c o n i . c o m
C o p y r ig h t 2 0 0 0 b y M a r c o n i C o m m u n ic a t io n s G m b H ( h ie r in b e z e ic h n e t a ls M a r c o n i)
Ä n d e r u n g e n v o r b e h a lt e n é G e d r u c k t in D e u t s c h la n d
M a r c o n i , M a r c o n i C o m m u n i c a t i o n s , d a s M a r c o n i L o g o , d a s g e s c h w u n g e n e 'M ' ,
S k y b a n d , M D R S , M D M S u n d S e r v ic e O n A c c e s s s in d e in g e t r a g e n e M a r k e n z e ic h e n
v o n M a r c o n i C o m m u n ic a t io n s G m b H .
W in d o w s is t e in e in g e t r a g e n e s M a r k e n z e ic h e n d e r M ic r o s o ft C o r p o r a t io n , R e d m o n d .
M a r c o n i C o m m u n ic a t io n s G m b H
D -7 1 5 2 0 B a ck n a n g
T e le p h o n e + 4 9 (7 1 9 1 ) 1 3 -0 T e le f a x + 4 9 (7 1 9 1 ) 1 3 - 3 2 1 2
h t t p : / / w w w .m a r c o n i . c o m
C o p y r ig h t 2 0 0 0 b y M a r c o n i C o m m u n ic a t io n s G m b H ( h e r e in r e f e r r e d to a s M a r c o n i)
S p e c if ic a t io n s s u b je c t t o c h a n g e é P r in t e d in G e r m a n y
M a r c o n i , M a r c o n i C o m m u n i c a t i o n s , t h e M a r c o n i l o g o , t h e s w a s h 'M ',
S k y b a n d , M D R S , M D M S a n d S e r v ice O n A cce ss a re tra d e m a rk s of
M a r c o n i C o m m u n ic a t io n s G m b H .
W in d o w s is a t r a d e m a r k o f M ic r o s o f t C o r p o r a tio n , R e d m o n d .
Notes
This “Introduction to the Synchronous Digital Hierarchy“ is a company-inter-
nal brochure. Marconi Communications GmbH takes no responsibility for the
correctness of its contents!
Have you detected any faults or deficiencies? Do you have any new ideas?
Please let us know them!
Attention:
62.1013.105.11-A001 3
4 62.1013.105.11-A001
Table of contents
Table of contents
1 Introduction
1.1 SDH functional model ............................................................................................................. 1-1
1.2 From the source signal to the transport frame ........................................................................ 1-2
1.3 Transport frame ...................................................................................................................... 1-7
1.4 Section Overhead ................................................................................................................... 1-9
2 Structures
2.1 Synchronous Transport Module Level 1 (STM-1) ................................................................... 2-1
2.2 Structure of the synchronous STM-1 frame ............................................................................ 2-1
2.3 SDH multiplex elements ......................................................................................................... 2-4
2.3.1 Container C .................................................................................................................... 2-4
2.3.2 Virtual container.............................................................................................................. 2-5
2.3.3 Administrative Unit.......................................................................................................... 2-6
2.3.4 Tributary Unit .................................................................................................................. 2-6
2.3.5 Tributary Unit Group ....................................................................................................... 2-8
2.3.6 Administrative Unit Group............................................................................................... 2-8
2.4 Concatenation....................................................................................................................... 2-13
2.5 Synchronous multiplexing ..................................................................................................... 2-14
2.6 Multiframe generation ........................................................................................................... 2-15
2.7 Error monitoring using BIP-X ................................................................................................ 2-17
2.8 SDH transmission sections................................................................................................... 2-18
4 Mapping procedures
4.1 Asynchronous mapping of 140 Mbit/s signals into VC-4 ........................................................ 4-1
4.2 Asynchronous mapping of 34 Mbit/s signals into VC-3 .......................................................... 4-4
4.3 Asynchronous mapping of 2 Mbit/s signals into VC-12 .......................................................... 4-6
4.4 Asynchronous mapping of 1.5 Mbit/s signals into VC-11 ....................................................... 4-7
4.5 Mapping 1.5 Mbit/s signals into VC-12 ................................................................................... 4-8
5 Overhead
5.1 Section Overhead ................................................................................................................... 5-1
5.1.1 Regenerator Section Overhead (RSOH) ........................................................................ 5-2
5.1.2 Multiplex Section Overhead (MSOH) ............................................................................. 5-2
5.2 Path Overhead........................................................................................................................ 5-3
5.2.1 Higher-order POH (VC-3/VC-4) ...................................................................................... 5-3
5.2.2 Lower-order POH (VC-1x/VC-2) ..................................................................................... 5-6
6 Pointers
6.1 Pointer value modification....................................................................................................... 6-1
62.1013.105.11-A001 -5-
Table of contents
7 Reference model
7.1 Lower-order path functions ..................................................................................................... 7-2
7.2 Higher-order path functions .................................................................................................... 7-2
7.3 Transport terminal functions ................................................................................................... 7-2
8 Applications
8.1 Synchronous line equipment .................................................................................................. 8-1
8.1.1 Synchronous line multiplexer.......................................................................................... 8-1
8.1.2 Synchronous line regenerator ........................................................................................ 8-2
8.2 Multiplexers............................................................................................................................. 8-4
8.2.1 Terminal Multiplexer ....................................................................................................... 8-4
8.2.2 Add/Drop Multiplexer ...................................................................................................... 8-6
8.2.3 Cross-connect Multiplexer .............................................................................................. 8-8
8.3 Networks............................................................................................................................... 8-10
8.3.1 Ring networks............................................................................................................... 8-11
8.3.2 Double rings ................................................................................................................. 8-11
9 Protection switching
9.1 Overview................................................................................................................................. 9-1
9.2 Definitions ............................................................................................................................... 9-1
9.3 Protection switching ................................................................................................................ 9-1
9.3.1 MS 1+1 protection .......................................................................................................... 9-3
9.3.2 MS 1:n protection ........................................................................................................... 9-4
9.3.3 MS shared protection ring .............................................................................................. 9-4
9.3.4 MS dedicated protection ring .......................................................................................... 9-6
9.3.5 Path/subnetwork protection ............................................................................................ 9-6
9.3.6 Protocols......................................................................................................................... 9-7
9.4 Network topologies ................................................................................................................. 9-8
9.5 Equipment protection............................................................................................................ 9-15
10 Literature
Index
-6- 62.1013.105.11-A001
List of figures
List of figures
Fig. 1-1 Transmitter/receiver model ................................................................................................ 1-1
Fig. 1-2 Conversion of a serial source signal into a block structure................................................ 1-2
Fig. 1-3 Container ........................................................................................................................... 1-3
Fig. 1-4 Container with label ........................................................................................................... 1-3
Fig. 1-5 Transport frame ................................................................................................................. 1-4
Fig. 1-6 Combining containers to a container group ....................................................................... 1-5
Fig. 1-7 Concatenated containers................................................................................................... 1-6
Fig. 1-8 Transport frame of the 1st hierarchy level ......................................................................... 1-7
Fig. 1-9 Overhead with pointer........................................................................................................ 1-9
Fig. 2-1 STM-1 frame...................................................................................................................... 2-1
Fig. 2-2 Pointer ............................................................................................................................... 2-3
Fig. 2-3 Containers ......................................................................................................................... 2-4
Fig. 2-4 Virtual containers ............................................................................................................... 2-5
Fig. 2-5 Administrative Unit............................................................................................................. 2-6
Fig. 2-6 Tributary Unit ..................................................................................................................... 2-7
Fig. 2-7 Tributary Unit Group .......................................................................................................... 2-8
Fig. 2-8 Administrative Unit Group.................................................................................................. 2-8
Fig. 2-9 Generation of an STM-1 signal from a 140 Mbit/s signal................................................... 2-9
Fig. 2-10 Generation of an STM-1 signal in compliance with ETSI ................................................ 2-10
Fig. 2-11 Generation of an STM-1 signal from a 2.048 Mbit/s signal.............................................. 2-11
Fig. 2-12 Terminal Multiplexer 63 x 2.048 Mbit/s ............................................................................ 2-12
Fig. 2-13 SDH multiplexing procedure ............................................................................................ 2-14
Fig. 2-14 TU-1x/TU-2 Multiframe identification by the H4 byte ....................................................... 2-16
Fig. 2-15 BIP-8 monitoring process ................................................................................................ 2-17
Fig. 2-16 SDH digital signal sections .............................................................................................. 2-18
Fig. 3-1 Synchronous multiplex structure in compliance with ITU-T Recommendation G.707 ....... 3-1
Fig. 3-2 Multiplexing of AU-4 to AUG.............................................................................................. 3-2
Fig. 3-3 Multiplexing N x AUGs into STM-N.................................................................................... 3-3
Fig. 3-4 Multiplexing of three AU-3s into AUG ................................................................................ 3-4
Fig. 3-5 Multiplexing of one TUG-3 into one VC-4 .......................................................................... 3-6
Fig. 3-6 TU-3 pointer....................................................................................................................... 3-7
Fig. 3-7 TU-11 Tributary Unit ......................................................................................................... 3-8
Fig. 3-8 TU-12 Tributary Unit .......................................................................................................... 3-9
Fig. 3-9 TU-2 Tributary Unit ............................................................................................................ 3-9
Fig. 3-10 Multiplexing TU-11, TU-12 and TU-2 into TUG-2 ............................................................ 3-10
Fig. 3-11 Multiplexing seven TUG-2s into one TUG-3 .................................................................... 3-11
Fig. 3-12 Multiplexing seven TUG-2s into one VC-3....................................................................... 3-12
Fig. 4-1 Splitting up VC-4 into 13-byte blocks................................................................................. 4-1
Fig. 4-2 Asynchronous mapping of 140 Mbit/s signals into VC-4 ................................................... 4-2
Fig. 4-3 VC-3 divided up into three partial frames .......................................................................... 4-4
Fig. 4-4 Asynchronous mapping of 34 Mbit/s signals into VC-3 ..................................................... 4-4
Fig. 4-5 Asynchronous mapping of 2 Mbit/s signals into VC-12 ..................................................... 4-6
Fig. 4-6 Asynchronous mapping of 1.5 Mbit/s signals into VC-11 .................................................. 4-7
Fig. 4-7 Conversion of a VC-11 into a VC-12 (1.5 Mbit/s in VC-12) ............................................... 4-8
Fig. 5-1 Overhead bytes ................................................................................................................. 5-1
Fig. 5-2 Higher-order POH.............................................................................................................. 5-3
Fig. 5-3 VC3/VC4 path status (G1) ................................................................................................. 5-4
Fig. 5-4 TU multiframe indicator H4 ................................................................................................ 5-5
Fig. 5-5 Lower Order POH .............................................................................................................. 5-6
Fig. 5-6 Bit assignment of the V5 byte ............................................................................................ 5-6
Fig. 5-7 V5[5-7] Mapping Code....................................................................................................... 5-7
Fig. 6-1 Pointer modification (positive justification)......................................................................... 6-2
Fig. 6-2 Pointer modification (negative justification) ....................................................................... 6-3
Fig. 6-3 AU-3 pointer....................................................................................................................... 6-4
62.1013.105.11-A001 -7-
List of figures
-8- 62.1013.105.11-A001
Introduction
1 Introduction
The Synchronous Digital Hierarchy (SDH) supersedes the previous Plesio-
chronous Digital Hierarchy (PDH) and provides a worldwide uniform multi-
plex hierarchy. Besides standardization, SDH systems offer further
advantages for the setup and operation of modern network topologies:
Transport frame
2 Mbit/s 2 Mbit/s
Transmitter Receiver
140 Mbit/s 140 Mbit/s
2 Mbit/s 2 Mbit/s
Receiver Transmitter
140 Mbit/s 140 Mbit/s
62.1013.105.11-A001 1-1
Introduction
Example: Block size: 260 columns with 9 rows each consisting of 1 byte = 2340 Byte
Number of blocks per second: 8000
The above calculation shows that the transmission capacity of the blocks is
larger than the bit rate of the source signal. In order to compensate this diffe-
rence, each block must contain a certain amount of justification, i.e. stuffing
information.
1-2 62.1013.105.11-A001
Introduction
Containers
The transmission of SDH signals can be compared with the transmission of
containers on a conveyor belt.
er
o ntain
C
For transporting the information, the container needs a label. The latter inclu-
des information on the container contents, monitoring data etc. The receiver
evaluates this information.
Payload
Blind information
er
on tain
C
Label
Fig. 1-4 Container with label
The complete containers are then put on a kind of conveyor belt. This con-
veyor belt is divided up into several frames of identical size. They are used to
transport the containers.
62.1013.105.11-A001 1-3
Introduction
The position of the containers in the frame is arbitrary, i.e. a container does
not have to start at the beginning of the frame. A container can be located on
two adjacent frames.
ta iner
Con
er
tain
Co n
n
ssio
s mi
of t ra n
r e ction
Di
Start of frame
Empty frame
1-4 62.1013.105.11-A001
Introduction
Groups of containers
The type of payload in the containers is unimportant for transportation. The
stuffing information can therefore be regarded as part of the payload. Before
transportation, several small containers can be combined to form a group.
This group is then packed into a larger container. Each of these containers
includes a label which is evaluated by the receiver. Whenever necessary,
stuffing information is added.
The individual containers are assigned a certain position within the group.
The position no. determines the start of the respective container.
Stuffing information
62.1013.105.11-A001 1-5
Introduction
Concatenation
The above description was based on the assumption that the payload is
smaller than the container available. If the payload to be transported is larger
than the container available for it, several containers can be concatenated.
They then form a continuous container chain. In this case, the payload is dis-
tributed on this container chain.
Example: The source signal is 599.04 Mbit/s (broadband ISDN). Since the largest con-
tainer defined can transport only a signal up to 140 Mbit/s, four such contai-
ners have to be concatenated. The position of the container chain on the
conveyor belt is defined for the first container. The position of all other contai-
ners 2, 3 and 4 is determined by the first one.
Concatenation
Position
Start of frame
1-6 62.1013.105.11-A001
Introduction
It is composed of 270 columns and 9 rows. The first 9 columns are reserved
for special transport functions. The other 261 columns are used to transport
payload signals. 8000 frames are transported per second. This corresponds
to a frame duration of 125 µs.
270 columns
Additional
9 rows transport Payload area
capacity
62.1013.105.11-A001 1-7
Introduction
Hierarchy levels
The transport frame of the higher hierarchy levels differ from each other only
with respect to the number of columns. The following hierarchy levels have
been defined:
1-8 62.1013.105.11-A001
Introduction
The Section Overhead also includes a pointer defining the position of the
containers in the payload area. The pointer value, also referred to as offset,
indicates the offset of the container with respect to a reference point of the
frame. The pointer, however, is not part of the Section Overhead!
Before a container is placed on the conveyor belt (add function), the pointer
value is calculated and the container is placed e.g. in position 30, calculated
from the end of the fixed pointer position. On taking the container from the
conveyor belt (drop function), the pointer is evaluated and the position of the
container determined.
The pointer also permits a dynamic adaptation of the container to the trans-
port frame. This means that the container can be moved on the conveyor belt
in both directions by changing the offset value. If a container is to be shifted
to another conveyor belt (cross-connect), this is also done by means of the
pointer.
ter
Poin
on
sm issi
r an
n of t
ctio
Dire Poi
nter
Section Overhead 70
nter
Poi
30
Cro
ter ss-
Poin c on
ne c
t
nter
P oi
40
62.1013.105.11-A001 1-9
Introduction
1-10 62.1013.105.11-A001
Structures
2 Structures
2.1 Synchronous Transport Module Level 1 (STM-1)
The Synchronous Digital Hierarchy (SDH) defines the Synchronous Trans-
port Module Level 1 (STM-1) as multiplex signal of the lowest level. It has a
transmission rate of 155.520 Mbit/s. The STM-N bit rates of the standardized
higher hierarchy level (N= 4 and 16) are always higher by factor 4.
Transport Interface
Synchronous Hierarchy
Transport Module level capacity in
kbit/s Electrical Optical
270 Bytes
1 9
1
SOH
Pointer
9 rows
Payload
SOH
62.1013.105.11-A001 2-1
Structures
The first 9 columns include the Section Overhead (SOH) and the Pointer of
the Administrative Unit (AU pointer). The remaining 261 columns are used for
transporting the payload. It consists of packed and multiplexed payload
signals (tributaries) and an accompanying Path Overhead (POH).
The repetition frequency of the STM-1 frame is 8 kHz, i.e. one STM-1 frame
has a length of 125 µs. The transmission capacity of one byte in an STM-N
frame is thus 64 kbit/s.
2-2 62.1013.105.11-A001
Structures
The payload has no fixed phase relation to the STM-N frame. In order to be
able to access the payload, the Section Overhead block contains a pointer. It
is located in the 4th row of the STM-N frame.
SOH Payload
522 - - ...
... 782 - -
Pointer 0 - - 1 - - ...
STM-1
310
310 - - ...
522
522 - - ...
... 782 - -
310
310 - - ...
The pointer indicates the beginning of the payload frame and permits the
payload to be directly accessed. The first byte of the payload frame (byte 0)
follows the last pointer byte. Bytes 522 to 782 are located in front of the poin-
ter. Pointer values higher than 521 are thus pointing at the next STM frame!
62.1013.105.11-A001 2-3
Structures
2.3.1 Container C
The transmission capacity of the incoming source signal is smaller than the
capacity of the block structure. The source signal is therefore filled up by
adding stuffing information (positive justification).
The process of filling up the incoming information to obtain the defined block
structure is referred to as mapping. The complete block structure is called
Container C. Different container sizes (e.g. C-11, C-12, C-2, C-3, C-4) are
available for the different source signal bit rates.
The digit in the container designation indicates the hierarchy level of the ple-
siochronous signal (e.g. C-4 for 140 Mbit/s). If several containers for different
bit rates are available within one hierarchy level, a second digit defines the bit
rate assignment (C-11=1,5 Mbit/s, C-12=2 Mbit/s).
1 260 1 84
C-4 C-3
1 12 1 4 1 3
2-4 62.1013.105.11-A001
Structures
Note: The POH of VC-11, VC-12 or VC-2 is composed of four bytes (V5/J2/N2/K4).
One byte of this POH is transmitted per VC-n, thus leading to the generation
of a multiframe.
1 261 1 85
VC-4 VC-3
1 12 1 4 1 3
62.1013.105.11-A001 2-5
Structures
AU-4
1 9 10 270
AU-4 pointer
VC-4
AU-3
123 4 90
AU-3 pointer
VC-3
In TU-11, TU-12 and TU-2, there is only space for one pointer byte. However,
three bytes are required for the pointer operations. In order to be able to
transport these bytes, a multiframe has been defined (see “Multiframe gene-
ration” on page 16).
The position of the pointer bytes is depicted in the alternative illustration (see
next figure). The V1 and V2 bytes form the TU pointer. Byte V3 is available
for a dynamic increase in the payload (stuffing).
2-6 62.1013.105.11-A001
Structures
TU-2
V1 321 322 ... 426 427 V2 0 1 ... 105 106 V3 107 108 ... 212 213 V4 214 215 ... 319 320
Pointer bytes
1 4
TU-12 TU-12 TU-12 TU-12
V
in frame #1 in frame #2 in frame #3 in frame #4
TU-12
V1 105 106 ... 138 139 V2 0 1 ... 33 34 V3 35 36 ... 68 69 V4 70 71 ... 103 104
Pointer bytes
1 3
TU-11 TU-11 TU-11 TU-11
V
in frame #1 in frame #2 in frame #3 in frame #4
TU-11
V1 78 79 ... 102 103 V2 0 1 ... 24 25 V3 26 27 ... 50 51 V4 52 53 ... 76 77
Pointer bytes
TU-3
1 86
H1
Pointer H2
H3
bytes
VC-3 H1 595 596 ... H2 ... 763 764 H3 0 1 ...
62.1013.105.11-A001 2-7
Structures
TUG-3
1 12 1 86
TUG-2 TU-3
Stuffing
information
4 x TU-11 → TUG-2
3 x TU-12 → TUG-2
1 x TU-2 → TUG-2
7 x TUG-2 + stuff. info → TUG-3
1 x TU-3 + stuff. info → TUG-3
AUG
10 270
Space for
3 AU-3 or
1 AU-4 pointers
1x AU-4 → AUG
3x AU-3 → AUG
2-8 62.1013.105.11-A001
Structures
Examples
With 140 Mbit/s signals, the generation of an STM-1 signal can be described
as follows:
1. Filling up the 140 Mbit/s signal with stuffing bits -> C-4
2. Adding the Path Overhead (POH)-> VC-4
3. Calculating and adding the pointer -> AU-4
4. Adding the Section Overhead (SOH) -> STM-1
In this case, AUG and AU-4 are identical, i.e. the AUG does not have to be
separately illustrated in the following figure.
270 bytes
9 1
3 SOH
1 PTR
POH
SOH PTR
5 POH
POH C
Payload
62.1013.105.11-A001 2-9
Structures
Bit rate < 140 Mbit/s At bit rates lower than 140 Mbit/s, the plesiochronous signals are converted
into an STM-1 signal via a 2-step procedure. .
No <140 No
<140
Mbit/s
P
Adding the Path O C
Overhead H
Calculating and P
T VC
adding the pointer
R
No <34 No
Mbit/s <34
P
Adding the Path O C-4
Overhead H
Calculating and P
adding the pointer T VC-4
R
2-10 62.1013.105.11-A001
Structures
The following diagram shows how a 2.048 Mbit/s signal is converted into an
STM-1 signal via the different multiplex steps.
SOH
Pointer
9 VC-4 POH
bytes TUG-3
stuff. info
Pointer
SOH stuff. info TUG-2
TU-12 f
STM-1
AU-4 TU-12 pointer
VC-4
VC-12 POH
TUG-3
TUG-2
TU-12
Payload
VC-12 2.048 Mbit/s + stuffing info
C-12
x1 x3 x7 x3
STM-1 AU-4 VC-4 TUG-3 TUG-2 TU-12 VC-12 C-12 2.048 Mbit/s
The individual 2.048 Mbit/s signals are subjected to the same multiplex pro-
cedure in both the transmit and receive direction, however, in the opposite
order. For this reason, the two directions are not separately depicted.
62.1013.105.11-A001 2-11
Structures
7x
TUG-3 21 x 2.048 Mbit/s
7x
TUG-3 21 x 2.048 Mbit/s
2-12 62.1013.105.11-A001
Structures
2.4 Concatenation
If the payload is larger than the container available for it, it can be distributed
to several consecutive containers. The individual containers are concatena-
ted by means of a special pointer value. This pointer value is referred to as
Concatenation Indication.
Example of a VC-4 con- A number of four VC-4 containers are required for an ATM cell stream of the
catenation broadband ISDN with a bit rate of 599.04 Mbit/s. In the first VC-4, a valid
POH is generated. The other three VC-4s are only filled up with payload and
are assembled to form one VC-4-4c Virtual Container.
By adding the pointer, the VC-4-4c is converted into the AU-4-4c group. The
first AU-4 of the AU-4-4c group is provided with a pointer. All other AUs con-
tained in the AU-4-4c group receive the pointer value which indicates the
concatenation of the containers. All following AUs within the AU-4-4c group
receive the Concatenation Indication (CI) instead of the pointer value. The
CI is composed as follows:
1 0 0 1 S S 1 1 1 1 1 1 1 1 1 1
The CI value indicates that this AU-4 belongs to the previous AU-4 and that
all pointer operations of the first AU-4 shall be executed on all AU-4 units
contained in the AU-4-4c group.
62.1013.105.11-A001 2-13
Structures
In this connection, it is pointed out that the Section Overheads (SOH) of the
individual STM-1 signals are not interleaved.
9
1 1 9 9
1 1 4x9 9
Pointer
STM-4 frame
SOH Payload
4x9 4 x 261
SOH
SOH
125µs
2-14 62.1013.105.11-A001
Structures
For this reason, several TU frames are combined to form a multiframe. The
pointer bytes are then distributed to these consecutive TU frames. The still
separate TU frames are arranged in a TUG-2 unit. In compliance with the
multiplex structure, they can be accommodated in a VC-3 or via TUG-3 in a
VC-4. This VC-3 /VC-4 is finally converted into an STM-1 frame.
In order to ensure that the receiver knows that the VC-3/VC-4 includes Tribu-
tary Units with a multiframe, a so-called multiframe indicator (H4) is set and
transmitted in the POH of VC-3/VC-4. The receiver evaluates this indicator
and interprets the pointer bytes in the individual TUs correspondingly.
The relevant ITU-T Recommendations currently only define the 500 µs multi-
frame:
Example: The system generates a TU multiframe composed of four TU-2 frames. The
TU-2 Tributary Units are converted via TUG-2 into a VC-3. The TU pointer
bytes V1 to V4 are distributed to four consecutive VC-3s. By means of a
counting process, the H4 byte determines the VC-3 frames containing the
individual pointer bytes.
62.1013.105.11-A001 2-15
Structures
VC-3/VC-4 POH
V4
9 rows
VC-3/VC-4 Payload
H4 (00)
V1
VC-3/VC-4 Payload
H4 (01)
V2
VC-3/VC-4 Payload
H4 (10)
V3
VC-3/VC-4 Payload
H4 (11)
V4
VC-3/VC-4 Payload
H4 (00)
2-16 62.1013.105.11-A001
Structures
Example: BIP-8 Starting from the first bit of the signal to be monitored, every eighth bit is ana-
lyzed in order to determine the number of logic “ones”. Then the first bit of the
BIP-8 value is defined so that together with this bit, there is an even number
of logic “ones”.
Then the same process is executed starting from the second bit of the signal
to be monitored, i.e. every eighth bit is analyzed and the second bit of the
BIP-8 value is defined by applying the same rule.
This calculation is performed for all eight bits of the BIP-8 value. The result is
then transmitted together with the signal to the opposite station. There the
same calculation is performed. Possible deviations of the calculated value
from the transmitted BIP-8 value permit transmission errors to be detected.
A maximum of 8 parity violations can be identified by means of one BIP-8
value on condition that these parity violations are statistically distributed.
The BIP-2 and BIP-24 monitoring process is based on the same principle.
The BIP-2 value to be transmitted is composed of two bits, the BIP-24 value
of three bytes.
Before being transmitted, the signals are scrambled. On reception, they are
descrambled. The BIP value is calculated in front of the scrambler and inser-
ted in the next frame also in front of the scrambler.
1 9 17 25
Signal 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 0 1 1
1st bit 1 1 + + + +
1 1 + + + +
0 0 + + + +
1 1 + + +
CBH <-
0 0 + + +
0 0 + + +
1 1 + + +
1 1 + + +
62.1013.105.11-A001 2-17
Structures
Lower-order path
Higher-order path
Multiplex Section
Regenerator
VC-3 VC-3
Assembler
Assembler
C-3 Section C-3
Assem- Assem-
bler bler
VC-4
Multiplexer
VC-11, VC-11,
STM-N
STM-N
C-11, C-11,
C-12, VC-12, VC-12, C-12,
C-2 VC-2 VC-2 C-2
VC-3, VC4
VC-3, VC4
Assembler
Assembler
Assem- Assem-
bler bler
C-3, C-3,
C-4 STM-N RSOH C-4
STM-N MSOH
2-18 62.1013.105.11-A001
Multiplex paths in the SDH
This multiplex scheme complies with ITU-T G.707 and includes optional mul-
tiplex paths. The VC-3 can e.g. be multiplexed via TU-3 into VC-4 or the
AU-3 path can be selected.
xN x1 139.264
STM-N AUG AU-4 VC-4 C-4
Mbit/s
N = 1, 4 x3
44.736
x1 Mbit/s
TUG-3 TUG-3
TU-3 VC-3
VC-3 C-3
x3 34.368
Mbit/s
AU-3 VC-3
see note
x7 x7
x3 2.048
TUG-2 TU-12 VC-12 C-12
Mbit/s
x4
Pointer processing 1.544
TU-11 VC-11 C-11 Mbit/s
Note 8 Mbit/s and non-hierarchical bit rates can
be mapped into concatenated VC-2 virtual containers.
Fig. 3-1 Synchronous multiplex structure in compliance with ITU-T Recommendation G.707
62.1013.105.11-A001 3-1
Multiplex paths in the SDH
xN x1 139,264
STM-N AUG AU-4 VC-4 C-4
Mbit/s
N=1, 4
C-4 to AU-4
The 139.264 Mbit/s signal is assembled in a C-4 container. Then the
VC-4 is generated by adding the POH. It is composed of 261 columns, each
consisting of 9 rows.
By adding the AU-4 pointer, the VC-4 is converted into an AU-4. The AU
pointer indicates the relative offset between the frame start of the VC and the
STM-1 frame.
AU-4 to AUG
The AU-4 Administrative Unit is converted into an AUG arrangement. The
AUG represents an information structure composed of 9 rows consisting of
261 columns plus 9 additional bytes in row 4 for the AU pointers. In the
example depicted below, the AUG consists of one VC-4 and one AU-4 poin-
ter. The AU-4 and AUG are identical.
1 261
J1
B3
C2
G1
VC-4-POH F2 C-4 VC-4
H4
F3
K3
N1
no fixed phase
H1 Y Y H2 1* 1* H3 H3 H3
AU-4
fixed phase
AUG
3-2 62.1013.105.11-A001
Multiplex paths in the SDH
AUG to STM-N
The AUGs generated this way can now be either assembled in a STM-1
frame by mapping in an AUG directly or in an STM-N frame by multiplexing N
x AUGs byte by byte.
10 261 10 261
1 9 1 9
#1 #2
AUG AUG
123...N123...N
SOH
123...N123...N
SOH
Nx9 N x 261
STM-N
Phase relation
The phase of the VC-4 has no fixed relation to the STM-N frame. The AU-4
pointer indicates the frame start of VC-4. This pointer is transmitted in the
STM-N signal and establishes thus the phase relation to the STM-N frame.
The AU-4 pointer has a defined phase relation to the AUG and thus to the
STM-N frame.
62.1013.105.11-A001 3-3
Multiplex paths in the SDH
44,736
xN x3 Mbit/s
STM-N AUG AU-3 VC-3 C-3
34,368
N=1, 4 Mbit/s
For mapping three VC-3s into a AUG, two columns with fixed stuffing infor-
mation must at first be inserted in VC-3 (3 x (85 +2) = 261).
1 30 59 87 1 30 59 87 1 30 59 87
J1 J1 J1
VC-3 B3
VC-3 B3
VC-3 B3
C2 C2 C2
G1 G1 G1
F2 F2 F2
H4 H4 H4
F3 F3 F3
K3 K3 K3
N1 N1 N1
H1 H2 H3 H1 H2 H3 H1 H2 H3
A B C
A A A
B B AUG B
A B C A B C A B C C C C
3-4 62.1013.105.11-A001
Multiplex paths in the SDH
Phase relation
The phase of the VC-3 has no fixed relation to the STM-N frame. The AU-3
pointer indicates the frame start of the VC-3. This pointer is transmitted in the
STM-N signal and establishes thus the phase relation to the STM frame.
For each VC-3, the STM-N transmits one pointer, i.e. it contains a total of
three pointers.
The AU-3 pointer has a defined phase relation to the AUG and thus to the
STM-N frame.
62.1013.105.11-A001 3-5
Multiplex paths in the SDH
xN x1
STM-N AUG AU-4 VC-4
N=1, 4 x3
44.736
x1 Mbit/s
TUG-3 TUG-3
TU-3 VC-3
VC-3 C-3
34.368
Mbit/s
By providing the VC-3 with a pointer, the TU-3 Tributary Unit is generated.
This TU-3 is then converted into a TUG-3 arrangement by adding stuffing
information.
A VC-4 has a POH and is composed of 261 columns. Behind the POH of the
VC-4, two columns with fixed stuffing information (pos. justification bits) are
inserted. In the remaining 258 columns, the three TUG-3s are multiplexed by
turns into the VC-3 byte by byte. This process results in a total of 3 x 86 + 2 +
1 = 261 columns.
1 86 1 86 1 86
Stuffing information
P VC-4
O A B C A B C A B C A B C A B C
H
1 2 3 4 5 6 7 8 9 10 11 12 261
3-6 62.1013.105.11-A001
Multiplex paths in the SDH
Phase relation
In the first three bytes of the first column, the TU-3 pointer sets up the phase
relation between VC-3 and TUG-3.
86 columns
H1
TU-3
pointer H2
TUG-3
H3
Stuffing bits
85 columns
J1
B3
C2
G1
VC-3
F2 C-3
H4
F3
K3
N1
VC-3-POH
TUG-3 has a fixed phase relation to VC-4. AU-4 sets up the phase relation to
the STM-N signal.
62.1013.105.11-A001 3-7
Multiplex paths in the SDH
x1 6.312
TU-2 VC-2 C-2 Mbit/s
x3 2.048
TUG-2 TU-12 VC-12 C-12 Mbit/s
x4
1.544
TU-11 VC-11 C-11
Mbit/s
Depending on their bit rate, the payload signals are assembled in containers
C-n of appropriate size. The Virtual Containers (VC-n) are generated by
adding the POHs. By providing these VC-n containers with their pointers, the
TU-n Tributary Units are generated.
Since all SDH stuctures are based on a structure composed of 9 rows, the
TUs can be described as a structure with a certain number of columns and
nine rows.
TU-11
The capacity of a TU-11 is 1,728 kbit/s = 27 bytes per 125 µs. A TU-11 can
be described as a structure composed of three columns and nine rows.
1 3 columns
2
1 2 3
1,728 kbit/s
9 rows
TU-11
27
bytes
27
27 125 µs
TU-12
The capacity of a TU-12 is 2,304 kbit/s = 36 bytes per 125 µs. A TU-12 can
be described as a structure composed of four columns and nine rows.
3-8 62.1013.105.11-A001
Multiplex paths in the SDH
1 4 columns
2
1 2 3 4
2,304 kbit/s
9 rows
TU-12
36
bytes
36
36 125 µs
TU-2
The capacity of a TU-2 is 6,912 kbit/s = 108 bytes per 125 µs. A TU-2 can be
described as a structure composed of 12 columns and nine rows.
1 12 columns
2
1 2 3 4 5 6 7 8 9 10 11 12
9 rows
TU-2
108
bytes
108
6912 kbit/s
108 125 µs
62.1013.105.11-A001 3-9
Multiplex paths in the SDH
TUG-2
A TUG-2 is generated by multiplexing
4 x TU-11 or
3 x TU-12 or
1 x TU-2
4x 3x 1x
1 1 1 1 1 1 1
2 2 2 2 2 2 2
TUG-2 3 3 3 3 3 3 3
4 4 4
3-10 62.1013.105.11-A001
Multiplex paths in the SDH
TUG-3 6.312
x1 TU-2 VC-2 C-2
x7 Mbit/s
x3 2.048
TUG-2 TU-12 VC-12 C-12 Mbit/s
x4
1.544
TU-11 VC-11 C-11
Mbit/s
1 1 1 1 1 1 1
2 2 2 2 2 2 2
TUG-2 3 3 3 3 3 3 3
4 4 4
1 1 1 1 1
2 2 2 2 2
3 3 3 3 3
Stuffing info
4 4 4 4 TUG-3 4
5 5 5 5 5
6 6 6 6 6
7 7 7 7 7
1 234 . . . 82 84 86
Phase relation
The TU-11, TU-12 and TU-2 Tributary Units and the TUG-2 and TUG-3 Tri-
butary Unit Groups have a fixed phase relation to each other. A direct multi-
plexing process without pointer matching is therefore possible.
62.1013.105.11-A001 3-11
Multiplex paths in the SDH
x3 2.048
TUG-2 TU-12 VC-12 C-12 Mbit/s
x4
1.544
TU-11 VC-11 C-11
Mbit/s
1 1 1 1 1 1 1
2 2 2 2 2 2 2
TUG-2 3 3 3 3 3 3 3
4 4 4
VC-3 1 1 1 1 1
POH 2 2 2 2 2
3 3 3 3 3
4 4 4 4 VC-3 4
5 5 5 5 5
6 6 6 6 6
7 7 7 7 7
1 234 . . . 81 83 85
3-12 62.1013.105.11-A001
Mapping procedures
4 Mapping procedures
For all defined PDH bit rates there are mapping procedures which permit the
plesiochonous bit rates to be assembled in the corresponding containers.
In the following sections, the mapping procedures available for signals with
bit rates normally used in Europe are described.
Block 180
Fig. 4-1 Splitting up VC-4 into 13-byte blocks
The first byte of each block is a special byte, the following 12 bytes contain
(12 x 8) = 96 information bits.
The special bytes are referred to as W, X, Y and Z and have the following
order:
W is a normal information byte. Y is a stuffing byte, i.e. its contents are not
defined. The bits of the X byte are assigned as follows:
C R R R R R O O
The O bits can be used as overhead bits for the PDH. Five R bits are filled
62.1013.105.11-A001 4-1
Mapping procedures
with undefined stuffing information. The C bit is a stuffing check bit which
includes the information as to whether this row contains traffic or justification
information in the stuffing position. If the C bit is “0”, the stuffing bits are real
traffic bits. If it is “1”, the stuffing information consists of justification bits only.
Since the X byte is transmitted 5 times per row, five stuffing check bits are
available. On the Rx side, a majority decision prevents transmission errors
from leading to a false interpretation of the stuffing bit contents.
I I I I I I S R
It contains six information bits (I), one fixed stuff bit (R) as well as the justifi-
cation bit (S) that can be used for real or stuffing information.
The following figure shows the first row of VC-4 divided up into 20 blocks.
1 12 bytes
J1 W 96 I X 96 I Y 96 I Y 96 I Y 96 I
POH
byte
X 96 I Y 96 I Y 96 I Y 96 I X 96 I
Y 96 I Y 96 I Y 96 I X 96 I Y 96 I
Y 96 I Y 96 I X 96 I Y 96 I Z 96 I
4-2 62.1013.105.11-A001
Mapping procedures
Bytes Information Fixed stuffing Stuffing check Possible justifi- Overhead bits
bits bits bits cation bits
Bit rate
[kbit/s] 139,248 9,360 360 72 720
62.1013.105.11-A001 4-3
Mapping procedures
1 2 3 4 5 5 6 7 8 ... 80 81 82 83 84 85
J1 ...
B3 ... Partial frame 1
C2 ...
VC-3 G1 ...
POH F2 ... Partial frame 2
H4 ...
F3 ...
K3 ... Partial frame 3
N1 ...
In contrast to the VC-4 mapping procedure, two stuffing positions, i.e. S1 and
S2, with the associated five stuffing check bits C1 and C2 are transmitted
here. Additional overhead bytes are not provided.
R R R R R R R R
I I I I I I I I
4-4 62.1013.105.11-A001
Mapping procedures
1.431 573 10 2 0
4.293 1.719 30 6 0
x3
Bit rate
[kbit/s] 34,344 13,752 240 48 0
62.1013.105.11-A001 4-5
Mapping procedures
V5
R
32 bytes
R
J2
C1 C2 O O O O R R
32 bytes
R
140 N2
bytes C1 C2 O O O O R R
32 bytes
R
K4
R: Fixed stuffing bits (info)
C1 C2 R R R R R S1
O: Overhead bits
S2 I I I I I I I
C1, C2: Stuffing check bit
31 bytes S1, S2: Possible stuffing bits
R I: Information bit
500 µs
Fig. 4-5 Asynchronous mapping of 2 Mbit/s signals into VC-12
The VC-12 has two stuffing positions (S1, S2). They are controlled by the two
stuffing bits (C1, C2). On evaluation of the stuffing check bits C1 and C2, a
majority decision is performed on the receive side. The evaluation of the
information transmitted in each multiframe leads to the following result:
1.016 64 6 2 8
7 9
Bits/500 µs 1.023 73 6 2 8
Bit rate
[kbit/s] 2.046 146 12 4 16
4-6 62.1013.105.11-A001
Mapping procedures
V5
R R R R R R I R
24 bytes
J2
C1 C2 O O O O I R
104 24 bytes
bytes
N2
C1 C2 O O O O R R
24 bytes R: Fixed stuffing bits
O: Overhead bits
K4
C1, C2: Stuffing check bit
C1 C2 R R R S1 S2 R
S1, S2: Possible stuffing bits
24 bytes I: Information bit
500 µs
The two stuffing positions S1 and S2 are controlled by three stuffing check
bits C1 and C2 each.
A majority decision performed on the receive side with regard to the three
check bits determines as to whether the associated stuffing position S is
interpreted as information bit or as justification bit. The evaluation of the infor-
mation transmitted leads to the following result:
768 24 6 2 8
3 13
Bits/500 µs 771 37 6 2 8
Bit rate
[kbit/s] 1.542 74 12 4 16
62.1013.105.11-A001 4-7
Mapping procedures
For this purpose, a VC-11 is generated first of all. This VC-11 consists of 104
bytes which are located in 36 rows (4 basic frames) with 3 columns each. In
each row, the 9th byte of the third column is missing. On providing a column
with fixed stuffing bytes (with even parity!) between column 2 and 3, the 140
bytes of a VC-12 are obtained.
In the entire network, the VC-12 generated this way cannot be distinguished
from a ’normal’ VC-12. Only in the receiver, the initial VC-11 is recovered by
extracting the stuffing information.
V5 V5
J2 J2
N2 N2
K4 K4
500 µs
Fixed stuffing information with even parity
4-8 62.1013.105.11-A001
Overhead
5 Overhead
For monitoring and controlling the SDH network, additional information is
transmitted together with the traffic data (payload). This additional informa-
tion, called Overhead, is divided up into two main groups, i.e. the Section
Overhead and the Path Overhead.
While the RSOH is terminated (i.e. disassembled, evaluated and newly gene-
rated) at each regenerator point, the MSOH passes the regenerator without
being modified and is only terminated at the multiplexers (where the payload
is assembled or disassembled).
A1 A1 A1 A2 A2 A2 J0/
RSOH C1 AU-4
B1 E1 F1
Voice
Service channel
D1 D2 D3
BER moni- STM-1
toring H1 Pointer H2 H3 H3 H3 Autom. prot. switch. sign.
B2 B2 B2 K1 K2
Connection check J1
D4 D5 D6
C-4
MSOH BER monitoring B3
D7 D8 D9 Payload
Ident. of VC contents C2
D10 D11 D12
S1 Z1 Z1 Z2 Path status G1
Z2 M1 E2
User channel F2
Spare channels
62.1013.105.11-A001 5-1
Overhead
C1 STM-N The C1 byte can be used to check an STM-N connection between two multi-
identifier plexers (old meaning, new see J0).
5-2 62.1013.105.11-A001
Overhead
Z1,Z2 Spare bytes These N x 4 bytes are reserved for future applications.
Connection check J1
C-4
BER monitoring B3 Payload
Identif. of VC contents C2
Path status G1
User channel F2
Multiframe indicator H4
User channel F3
Managem. purposes N1
62.1013.105.11-A001 5-3
Overhead
J1 Path Trace This is the first byte in the VC-3/VC-4. Its position is indicated by the pointer
and represents thus the reference point of the VC-3/VC-4 structure. This byte
can be used to transmit either a repetitive telegram with a length of 64 bytes
in any format or a 16-byte telegram in the so-called E.164 format. The Path
Trace permits the link to be checked over the complete path.
E.164 format:
The first byte marks the beginning of the frame. It includes the result of a
CRC-7 calculation performed for the previous frame. The following 15 bytes
are used to transmit the ASCII signs. If the 16-byte format shall be transmit-
ted in a 64-byte format, it must be repeated four times.
B3 BIP-8 monitoring This byte is used for error monitoring over the complete path. The BIP-8
value is calculated over all bits of the current VC3/VC-4 to obtain an even
parity and is inserted into the next VC3/VC-4.
C2 Contents identifier This byte is used as identifier for the VC contents. The following table gives
an overview of the defined codings of the C2 byte.
0 0 0 0 0 0 0 0 00 Unequipped
0 0 0 0 0 0 1 0 02 TUG structure
0 0 0 0 0 0 1 1 03 Locked TU
0 0 0 0 0 1 0 0 04 Asynchronous mapping of
34,368 kbit/s or 44,736 kbit/s into
Container-3
0 0 0 1 0 0 1 0 12 Asynchronous mapping of
139,264 kbit/s into Container-4
0 0 0 1 0 0 1 1 13 ATM mapping
0 0 0 1 0 1 0 1 15 FDDI mapping
G1 Path status Via this byte, the transmission performance data are reported by the path
end to the VC source. Thus, it is possible to monitor the complete path from
any point or from any of the two ends.
1 2 3 4 5 6 7 8
5-4 62.1013.105.11-A001
Overhead
This signal is returned whenever the VC-3/VC-4 assembler does not receive
a valid signal. The following conditions have been defined:
a) Path AIS
b) Loss of signal
c) Wrong path trace (J1 byte)
F2 User channel This 64 kbit/s channel is available for communication between the path start
and path end for user purposes.
H4 Multiframe indicator On generation of a payload multiframe, this byte is used in the lower-order
VC for multiframe synchronization. It is therefore payload-specific.
500 µs TU
multiframe
P1 P1 SL2 SL1 C3 C2 C1 T
1 2 3 4 5 6 7 8
F3 User channel This 64 kbit/s channel is available for communication between the path start
and path end for user purposes.
K3 Autom. protection Bits 1 to 4 are provided for controlling automatic protection switching proces-
switching ses at the higher-order level. Bits 5 to 8 are reserved for future applications.
N1 Network operator This byte is provided for management purposes, e.g. Tandem Connection
byte Maintenance.
62.1013.105.11-A001 5-5
Overhead
V5
Frame 1
J2
Frame 2
POH
N2
Frame 3
K4
Frame 4
500 µs
V5 V5 is the first byte in VC-1x/VC-2. The TU-1x/TU-2 pointer ’points’ at this byte
and represents thus the reference point of the lower-order VC. V5 is used for
transmitting the following information:
1 2 3 4 5 6 7 8
Definitions:
Bit 1, 2 BIP-2 moni- These two bits are used for error monitoring over the complete lower-order
toring path. The result is calculated to obtain an even parity. The calculation is per-
formed for the complete VC-1/VC-2 including the POH bytes, however,
without bytes V1 to V4 of the TU-1/TU-2 pointer. If information is transmitted
in byte V3 in negative justification processes, this byte is included in the cal-
culation.
Bit 3 Remote Error By setting this bit to logic ’1’, the VC source is informed that one or several
Indication parity violations were detected in the BIP-2 calculation. If there are no errors,
(REI) this bit is logic ’0’.
Bit 4 Remote On detection of a fault or failure, this bit is set to logic ’1’. RFI is sent back to
Failure Indi- the VC source.
cation (RFI)
5-6 62.1013.105.11-A001
Overhead
Bit 5, 6, 7 Contents These three bits correspond with the C2 byte of the higher-order POH. The
identifier use of the three special mapping indicators 010, 011 and 100 is optional.
However, these values must not be used for other purposes.
b5 b6 b7 Meaning
0 0 0 Unequipped
0 1 0 Asynchronous
0 1 1 Bit-synchronous
1 0 0 Byte-synchronous
1 0 1
1 1 0 equipped - unused
1 1 1
Bit 8 VC-Path This bit is sent back to the VC source. In normal operation, it is logic ’0’. On
Remote reception of TU1x/TU2 Path AIS or detection of LOS or wrong path trace
Defect Indi- (J2), it is set to logic ’1’.
cation (RDI)
J2 Path Trace The function of this byte is identical with that of byte J1 of the higher-order
POH. This byte can be used to transmit a 16 byte telegram in the E.164 for-
mat. Using the Path Trace, it is possible to check the link over the complete
path.
K4 Autom. pro- Bits 1 to 4 are provided for controlling automatic protection switching proces-
tecting swit- ses at the lower-order level. Bits 5 to 8 are reserved for future applications.
ching
N2 Network ope- This byte is provided for management purposes, e.g. Tandem Connection
rator byte Maintenance.
62.1013.105.11-A001 5-7
Overhead
5-8 62.1013.105.11-A001
Pointers
6 Pointers
A worldwide synchronous network represents an ideal condition that can in
practise not always be achieved. In synchronous networks, failures can lead
to islands without clock connection. In this case, a free-running oscillator
must supply these islands with the required clock information.
The introduction of pointers in the SDH created the possibity to maintain the
synchronous character of the transported information in a not clock-synchro-
nous environment. The information sent to such an island can thus be pro-
cessed without any loss of information and can be passed on although the
clock bit rates are not identical.
The payload has no fixed phase relation to the frame. In order to be able to
access the payload, a pointer is transmitted in the overhead block. It permits
the dynamic adaptation of the phase of the Virtual Container to the frame. In
this connection, dynamic means:
1. The phase of the Virtual Container can differ from that of the frame.
2. At different frequencies, the phase position can continuously vary without
causing any loss of information.
On the receive side, the NDF is evaluated. The new pointer value received
indicates the new position of the Virtual Container.
The NDF with the new pointer value is transmitted only once, i.e. in the first
frame. There must not be any further pointer operations within the next three
frames.
62.1013.105.10-A001 6-1
Pointers
Positive justification
If the frame frequency of the VC is lower than that of the STM-N frame, stuf-
fing bytes must be inserted and the pointer value must be increased by 1 at
regular intervals.
STM-1 frame
1 9 270
Beginning of
VC-4
Pointer (P) H1 H2 H3
Frame n
125 µ s
250 µ s
Pos. stuffing
byte(s)
375 µ s
New pointer
(P+1) H1 H2 H3 Frame n+3
500 µ s
The stuffing bytes are inserted directly behind the last H3 byte. For an AU-3
one stuffing byte, for an AU-4 three stuffing bytes are inserted. The new poin-
ter (P+1) is then transmitted starting at the next frame.
6-2 62.1013.105.10-A001
Pointers
Negative justification
If the frame frequency of the VC is higher than that of the STM-N frame, addi-
tional information of the VC must be transmitted in the H3 bytes and the poin-
ter value must be decreased by 1 at regular intervals.
STM-1 frame
1 9 270
Beginning of
VC-4
Pointer H1 H2 H3 Frame n
125 µs
Pointer (P)
H1 H2 H3
Frame n+1
250 µs
Neg. justification
bytes (data)
Pointer (P)
H1 H2 Frame n+2
375 µs
New poin-
ter (P-1) H1 H2 H3
Frame n+3
500 µs
The following three H3 bytes are filled with information. With AU-3, only the
H3 byte belonging to the VC to be stuffed is filled with information. The new
pointer (P-1) is transmitted starting at the next frame.
62.1013.105.10-A001 6-3
Pointers
1. The phase of VC-3 can differ from that of the STM frame.
2. At different frequencies, the phase position can continuously vary without
causing any loss of information.
The AU-3 pointer is located in the 4rth row of the SOH. It is composed of
three bytes referred to as H1, H2 and H3.
The three bytes with number “0” start to the right of the last pointer byte (H3).
The byte nos. 522 to 782 are located in front of the pointer. Consequently,
pointer values higher than 521 point to the next STM-1 frame.
6-4 62.1013.105.10-A001
Pointers
The three AU-3 pointers are interleaved byte by byte and arranged as fol-
lows:
Pointer a
Pointer b
Pointer c
The three pointers are independent of each other and indicate the beginning
of the corresponding VC, only the bytes of this VC being counted and those
of all others being skipped.
H1, H2 H1 and H2 are read as a 16-bit data word. Bits 1 to 4 form the so-called New
Data Flag NDF. The NDF indicates as to whether a new pointer value has to
be set. Two values have been defined:
Bits 7 to 16 represent the pointer value. As a binary value, the pointer value
indicates the offset between the VC start and the reference point expressed
in bytes.
The bits are by turns referred to as I bit and D bit ( Increment and Decre-
ment). If the pointer value is to be increased by positive justification, this is
indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15).
In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16)
are inverted. On the decoder side, the D bits are evaluated and the informa-
tion contained in H3 is inserted into the payload of the current VC.
N N N N S S I D I D I D I D I D
62.1013.105.10-A001 6-5
Pointers
H1, H2 H1 and H2 are read as a 16-bit data word. It includes the New Data Flag NDF
and the pointer value.
Bits 7 to 16 represent the pointer value. As a binary value, the pointer value
indicates the offset between the VC-4 start (J1 byte) and the reference point
in 3-byte increments.
The bits are by turns referred to as I bit and D bit (Increment and Decrement).
If the pointer value is to be increased by a positive justification process, this is
indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15).
In negative justification processes, the five D bits (bit 8, 10, 12,14 and 16) are
inverted. On the decoder side, the D bits are evaluated in the same way and
6-6 62.1013.105.10-A001
Pointers
N N N N S S I D I D I D I D I D
If the pointer value is 0, it indicates that the VC starts with the byte directly fol-
lowing the last H3 byte.
AU-4 concatenation In case of large payload amounts, several AU-4 Administrative Units are con-
catenated. The first AU-4 contains a normal pointer. The associated following
AU-4s include the CI instead of the pointer value. This CI indicates that these
AU-4s are to be treated in the same way as the previous ones.
1 0 0 1 S S 1 1 1 1 1 1 1 1 1 1
Concatenation Indication CI
62.1013.105.10-A001 6-7
Pointers
1. The phase of VC-3 can differ from that of the TUG-3 frame.
2. At different frequencies, the phase position can continuously vary without
causing any loss of information.
86 columns
TUG-3
H1
H2
TU-3 pointer 85 columns
H3
S J1
T
U B3
F C2
F VC-3
I G1
N
G F2 C-3
H4
F3
K3
N1
VC-3 POH
The TU-3 pointer is located in the first column of the TUG-3 frame. It is com-
posed of three bytes referred to as H1, H2 and H3.
H1, H2 H1 and H2 are read as a 16-bit data word. Bits 1 to 4 represent the New
Data Flag NDF. The NDF indicates as to whether a new pointer value must
be set or not. The following two values have been defined:
Bits 7 to 16 represent the pointer value. As binary value, the pointer value
indicates the offset between the VC-3 start (J1 byte) and the reference point
expressed in bytes.
The bits are by turns referred to as I bit and D bitt (Increment and Decre-
ment). If the pointer value is to be increased by positive justification, this is
indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15).
6-8 62.1013.105.10-A001
Pointers
In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16)
are inverted. On the decoder side, the D bits are evaluated in the same way
and the information contained in H3 is inserted into the payload of the current
VC-3.
N N N N S S I D I D I D I D I D
If the pointer value is 0, it indicates that the VC-3 starts with the byte directly
following the H3 byte. The values for the TU-3 pointer range from 0 to 764.
Pointer values between 595 and 764 point to the next TUG-3 frame!
1 2 3 4 5 6 ... 82 83 84 85 86
1 H1 595 596 597 598 599 ... 675 676 677 678 679
2 H2 680 681 682 683 684 ... 760 761 762 763 764
3 H3 0 1 2 3 4 ... 80 81 82 83 84
4 85 86 87 88 89 ... 165 166 167 168 169
S
5 T 170 171 172 173 174 ... 250 251 252 253 254
U
6 F 255 256 257 258 259 335 336 337 338 339
7 F 340 341 342 343 344 ... 420 421 422 423 424
I
8 N 425 426 427 428 429 ... 505 506 507 508 509
G
9 510 511 512 513 514 ... 590 591 592 593 594
1 H1 595 596 597 598 599 ... 675 676 677 678 679
2 H2 680 681 682 683 684 ... 760 761 762 763 764
3 H3 0 1 2 3 4 ... 80 81 82 83 84
4 0 - - 1 - ... - - 86 - -
5 85 86 87 88 89 ... 165 166 167 168 169
62.1013.105.10-A001 6-9
Pointers
1. The phase of VC-2 can differ from that of the TUG-2 frame.
2. At different frequencies, the phase position can continuously vary without
causing any loss of information.
The bytes required for the pointer operations are referred to as V1, V2, and
V3. These bytes are located in the first byte position of four consecutive
TU-2s. The definition of the byte available in the current TU-2 is performed by
means of the H4 multiframe indicator of the VC-3 POH or VC-4 POH.
V1 321 322 ... 426 427 V2 0 1 ... 105 106 V3 107 108 ... 212 213 V4 214 215 ... 319 320
V1, V2 V1 and V2 can be read as a 16-bit data word. Bits 1 to 4 represent the New
Data Flag NDF. The following two values have been defined:
Bits 5 and 6 are referred to as S S and indicate the type of the TU.
TU-2: S S = 0 0
In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16)
are inverted. On the decoder side, the D bits are evaluated in the same way
and the information contained in V3 is inserted into the payload of the current
6-10 62.1013.105.10-A001
Pointers
VC-2.
N N N N S S I D I D I D I D I D
If the pointer value is 0, it indicates that the VC-2 starts with the byte directly
following the V2 byte. The values for the TU-2 pointer range from 0 to 427.
Pointer values between 321 and 427 point to the next TUG-2 frame!
TU-2 concatenation
In order to be able to transport bit rates not defined by ITU-T within the Syn-
chronous Digital Hierarchy (SDH), several TU-2 Tributary Units can be con-
catenated to TU-2-mc. Thus, it is possible to transport information in
multiples of VC-2 within a VC-2-mc.
1 0 0 1 S S 1 1 1 1 1 1 1 1 1 1
Concatenation Indication CI
62.1013.105.10-A001 6-11
Pointers
1. The phase of VC-11 can differ from that of the TUG-2 frame.
2. At different frequencies, the phase position can continuously vary without
causing any loss of information.
The bytes required for the pointer operations are referred to as V1, V2 and
V3. These bytes are located in the first byte position of four consecutive
TU-11s. The definition of the byte available in the current TU-11 is performed
by means of the H4 multiframe indicator of the VC-3 POH or VC-4 POH.
V1, V2 V1 and V2 can be read as a 16-bit data word. Bits 1 to 4 represent the New
Data Flag NDF. The following two values have been defined:
Bits 5 and 6 are referred to as S S and indicate the Type of the TU.
TU-11: S S = 1 1
In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16)
are inverted. On the decoder side, the D bits are evaluated in the same way
and the information contained in V3 is inserted into the payload of the current
VC-11.
N N N N S S I D I D I D I D I D
6-12 62.1013.105.10-A001
Pointers
If the pointer value is 0, it indicates that the VC-11 starts with the byte directly
following the V2 byte. The values for the TU-11 pointer range from 0 to 103.
Pointer values between 78 and 103 point to the next TUG-2 frame!
62.1013.105.10-A001 6-13
Pointers
1. The phase of VC-12 can differ from that of the TUG-2 frame.
2. At different frequencies, the phase position can continuously vary without
causing any loss of information.
The bytes required for the pointer operations are referred to as V1, V2 and
V3. These bytes are located in the first byte position of four consecutive
TU-12s. The definition of the byte available in the current TU-12 is performed
by means of the H4 multiframe indicator of the VC-3 POH or VC-4 POH.
V1 105 106 ... 138 139 V2 0 1 ... 33 34 V3 35 36 ... 68 69 V4 70 71 ... 103 104
V1, V2 V1 and V2 can be read as a 16-bit data word. Bits 1 to 4 represent the New
Data Flag NDF. The following two values have been defined:
Bits 5 and 6 are referred to as S S and indicate the type of the TU.
TU-12: S S = 1 0
In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16)
are inverted. On the decoder side, the D bits are evaluated in the same way
and the information contained in V3 is inserted into the payload of the current
VC-12.
6-14 62.1013.105.10-A001
Pointers
N N N N S S I D I D I D I D I D
If the pointer value is 0, it indicates that the VC-12 starts with the byte directly
following the V2 byte. The values for the TU-12 pointer range from 0 to 139.
Pointer values between 105 and 139 point to the next TUG-2 frame!
62.1013.105.10-A001 6-15
Pointers
6-16 62.1013.105.10-A001
Reference model
7 Reference model
International standards set up for the Synchronous Digital Hierarchy (SDH)
and the associated equipment units ensure that networks can be established
using equipment from different manufacturers. This is achieved thanks to the
introduction of application-independent reference models.
The general reference model (acc. G.783) specifies both the physical charac-
teristics (bit rates, optical/electrical level, impedances) and definitions regar-
ding the contents of each byte and even bit. These specifications cover the
following aspects:
• Frame structure
• Identification
• Scrambling
• Coding/decoding
• Mapping procedures
• Service channel utilization
• Monitoring and control signals.
STM-M T T T T T
S S S S S
G.703 T T T T T T T T T T T T STM-N
PPI LPA LPT LPC HPA HPT HPC MSA MSP MST RST SPI
S S S S S S S S S S S S
DCC DCC
M R
Higher-order path Q interface
S SEMF MCF
G.703 T T F interface
PPI LPA
T SETS SETPI External
S S synchronization
S S
The SDH definitions used in the reference model such as section, lower-
62.1013.105.11-A001 7-1
Reference model
order path, higher-order path, overhead etc. are generally applicable to both
transmission directions. All functional blocks have a clock reference point “T”
and a management reference point “S”. The reference point “T” communica-
tes with the functional block referred to as SETS, the reference point “S” with
functional block SEMF.
LPA Lower-Order Path This function defines how plesiochronous signals are mapped into C-n con-
Adaption tainers (n=11, 12, 2, 3) and the justification procedures necessary for this
purpose.
LPT Lower-Order Path This function generates and/or evaluates the VC-Path Overhead. The Path
Termination Overhead is carried in the container from its assembly up to its disassembly.
LPC Lower-Order Path This function permits a flexible arrangement of VC-11s, VC-12s, VC-2s and
Connection VC-3s within a VC-4 or of VC-11s, VC-12s, VC-2s within a VC-3 via a so-cal-
led “connection matrix”. This function is required only if the time allocation of
the VC to the STM signal shall not be defined by the card slot.
HPT Higher-Order Path Here the VC-m POH (m = 3, 4) is generated and/or evaluated in accordance
Termination with the LPT function.
HPC Higher-Order Path This function permits the flexible arrangement of the VC-m Virtual Containers
Connection (m = 3, 4) within an STM-N frame.
MSP Multiplex Section This function includes all aspects necessary to ensure that switchover to pro-
Protection tection paths is possible in case of failures on the line side. MSP communica-
tion with the opposite station takes place via the K bytes of the Section
Overhead.
MST Multiplex Section This function generates the MSOH (row 5 to 9 of the SOH) and/or evaluates
Termination it on the receive side.
7-2 62.1013.105.11-A001
Reference model
RST Regenerator Sec- This function generates the RSOH (row 1 to 3 of the SOH) and/or evaluates it
tion Termination on the receive side. In addition, the STM-N signal is scrambled in the trans-
mit direction. Frame alignment and descrambling take place in the receive
direction.
SPI SDH Physical The logic signal is normally converted into an optical STM-N signal appro-
Interface priate for the transmission medium available. Both signal conversion and
clock recovery are performed in the receive direction.
SETSSynchronous This function provides all clocks required by the network element (NE). All
Equipment Timing functions mentioned above receive the necessary clock signals via the refe-
Source rence points T from the SETS.
SETPI Synchronous This is the interface between an external synchronization source and SETS.
Equipment
Timing Physical
Interface
SEMF Synchronous Here the monitoring data (performance data and hardware-specific messa-
Equipment ges) are converted into object-oriented messages which can be transmitted
Management via the DCC or the Q or F interface to a management system or an Operator
Function Terminal. In the opposite direction, messages from the management system
are converted into hardware-specific control signals. The connections to the
individual functional blocks are set up via logic reference points S.
MCF Message Com- This function covers all tasks to be fulfilled in conjunction with the transport of
munication TMN messages to or from the management system via DCC channels or via
Function the Q or F interface.
62.1013.105.11-A001 7-3
Reference model
7-4 62.1013.105.11-A001
Applications
8 Applications
8.1 Synchronous line equipment
In the SDH, no distinction is made between multiplexers and line terminating
units. The “synchronous line equipment“ includes both synchronous multiple-
xers with integrated optical transmitters and receivers and the associated
regenerators.
4 4
F2in F1out Fin1 Fout2 Fin1 Fout2 F1in F2out
16 16
F2in F1out Fin1 Fout2 Fin1 Fout2 F1in F2out
On the multiplex side, the Section Overheads (SOH) of the individual STM-1
signals are terminated (disassembled and evaluated). The payload signals
are multiplexed column by column and a new STM-4 SOH is generated.
On the demultiplex side, the STM-4 SOH is terminated, while the payload
signals are distributed column by column onto the four STM-1 channels. In
addition, a new STM-1 SOH is generated for each STM-1 signal.
62.1013.105.11-A001 8-1
Applications
Alternatively, 140 Mbit/s signals can be applied to the synchronous line multi-
plexer instead of STM-1 signals.
In the transmit direction, the asynchronous 140 Mbit/s signals are converted
into an STM-1 signal. In the receive direction, the initial 140 Mbit/s signals
are extracted from the STM-1 signal.
STM-4
139.264 Mbit/s
4
STM-16
139.264 Mbit/s
16
In the SDH, the tasks of a regenerator are by far more extensive. The signals
are descrambled and the STM-N frame structure is analyzed.
8-2 62.1013.105.11-A001
Applications
the user channel is made available via byte F1 and the service channel via
byte E1. Then the SOH is completed again by forming a new RSOH. Here
the new Regenerator Section begins.
The difference between SLA-4 and SLA-16 consists only in the different
regenerator bit rates.
62.1013.105.11-A001 8-3
Applications
8.2 Multiplexers
Regarding their functions, multiplexers can be divided up into the following
three basic types:
♦Terminal Multiplexers
♦Add/Drop Multiplexers
♦Cross-connect Multiplexers
e.g.:
2 Mbit/s
34 Mbit/s
140 Mbit/s
MS1/4
TMS
STM-4
STM-1
STM-1
MS1/4
MS1/4: FlexPlex MS1/4 STM-4
TMS: Terminal Multiplexer (SDH) TMS
e.g.:
2 Mbit/s
34 Mbit/s
140 Mbit/s
8-4 62.1013.105.11-A001
Applications
Functioning of a The Terminal Multiplexer can split up the signal available at an aggregate
Terminal Multiplexer interface into the subsignals contained. These are then passed on to the
associated tributary interfaces. In the opposite direction, the Terminal Multi-
plexer combines the signals received at the tributary interfaces to one signal
which is routed to the aggregate interface. Fig. 8-4 shows the functioning of a
Terminal Multiplexer with regard to the traffic data to be transmitted.
Aggregate signal
1 n
Tributary signals
(e.g. 2 Mbit/s, 34 Mbit/s, 140 Mbit/s, (STM-1))
62.1013.105.11-A001 8-5
Applications
Fig. 8-5 shows a section of a network topology with a FlexPlex MS1/4 system
functioning as an Add/Drop Multiplexer.
STM-4 STM-4
MS1/4
AMS
STM-1 STM-1
e.g.:
2 Mbit/s
34 Mbit/s
140 Mbit/s
e.g.:
MS1/4: FlexPlex MS1/4 2 Mbit/s
AMS: Add/Drop Multiplexer (SDH) 34 Mbit/s
e.g.:
2 Mbit/s 140 Mbit/s
34 Mbit/s
140 Mbit/s
8-6 62.1013.105.11-A001
Applications
Subsignals not affected by the add/drop functions are switched through from
one aggregate interface to the other. On through-connection, the subsignals
can be switched at TU-12 level.
Fig. 8-6 shows the functioning of an Add/Drop Multiplexer with regard to the
traffic data to be transmitted.
TU-12
Aggregate signal Aggregate signal
West East
(e.g. STM-1, STM-4) (e.g. STM-1, STM-4)
1 n
Tributary signals
(e.g. 2 Mbit/s, 34 Mbit/s, 140 Mbit/s, (STM-1))
62.1013.105.11-A001 8-7
Applications
STM-1
STM-4
MS1/4
MS1/4
XMS4
XMS1
STM-1
STM-4
STM-1
8-8 62.1013.105.11-A001
Applications
The aggregate and tributary interfaces are identical with regard to their cross-
connecting capabilities. A FlexPlex MS1/4 configured as Cross-connect Mul-
tiplexer is also capable of cross-connecting the individual tributary signals.
Thus, it offers maximum flexibility when setting up network structures.
TU-12
1 n
Tributary signals
(e.g. 2 Mbit/s, 34 Mbit/s, 140 Mbit/s, (STM-1))
62.1013.105.11-A001 8-9
Applications
8.3 Networks
If a telecommunications network, e.g. the DBP Telekom network, is divided
up into three levels, i.e. the local area network, the regional long-distance
network and the supraregional long-distance network (see Fig. 8-6), all three
levels can be equipped with SDH units. However, in order to be able to opti-
mally exploit all possiblilities offered by the Synchronous Digital Hierarchy,
different equipment types have to be provided for the different network topo-
logies.
The synchronous line equipment (SLA) available for the transmission capaci-
ties of 622 Mbit/s and 2.5 Gbit/s (SLA 4, SLA 16) is appropriate for the long-
distance network levels where the networks are in most cases implemented
as line networks with point-to-point connections.
The local area network level mostly consists of ring networks implemented
using add/drop multiplexers (ADM). Cross-connect systems can be used at
all network levels.
Long-distance
network 1
Network nodes
SLA4, SLA16
Long-distance
network 2
SLA4, SLA16
Network nodes
ADM
Local area
network
FMUX
ADM
8-10 62.1013.105.11-A001
Applications
to the long-distance
network
The stations have access to all information available in the ring. Thus, each
station can set up a connection to any other station. Furthermore, each sta-
tion included in the ring can enter the long-distance network. A central station
is no longer required for these tasks.
Connections within the ring are set up by informing the corresponding stati-
ons on which part of the STM-N signal (i.e. time slot) is to be used for the
connection.
Since in such configurations, each station transmits and receives the same
information into/from two directions (hot standby), the stations affected by a
cable break must only switch over to the other receive path.
This can be effected automatically and very quickly so that the full operability
of the ring is maintained.
Since the effects of such failures (cable breaks) are eliminated automatically,
these rings are also referred to as self-healing rings.
62.1013.105.11-A001 8-11
Applications
to the long-distance
network
to the long-distance
network
self-healing
Interruption/
cable break
self-healing
8-12 62.1013.105.11-A001
Applications
By a double connection of the two rings via two stations, the reliability can be
further increased.
62.1013.105.11-A001 8-13
Applications
8-14 62.1013.105.11-A001
Protection switching
9 Protection switching
9.1 Overview
The reliability and maintenance of transmission networks are two important
aspects to be taken into account on installation of SDH multiplexers. In this
connection, redundancy plays an important role. Redundancy means that
additional functions are made available on a standby basis. Redundancy
should be provided for both the transmission channels of the network and the
multiplexer modules.
If the function of a multiplexer fails, the system switches over to the redun-
dant function available (equipment protection).
9.2 Definitions
1. Single-ended operation (unidirectional operation)
3. Extra traffic
4. Normal traffic
1. Monitoring
The traffic must be monitored so that faults and failures are immediately
detected.
2. Protection switch
62.1013.105.11-A001 9-1
Protection switching
3. Protocol
4. Control
There are different protection switching procedures. All these procedures are
highly reliable and appropriate for saving the complete traffic protected in
case of a single fault. With multiple faults, this is not always possible.
For some protection switching procedures there are several variants which
differ from each other with regard to the following characteristics:
1. Extra traffic
2. Revertive/non-revertive operation
This option permits the operator to decide whether the system shall switch
back to the original transmission channel on elimination of the fault.
3. Single-ended/dual-ended operation
This option permits the operator to decide whether both directions of trans-
mission shall be switched over in common.
9-2 62.1013.105.11-A001
Protection switching
Multiplex Section
Operating
path
Protection
path
Doubling Selector
62.1013.105.11-A001 9-3
Protection switching
0
Zero
channel
(0)
0
1
Operating Operating
channel section
1 1
1
2
Operating Operating
channel section
2 2
2
15
Extra
traffic Protection
channel section
(15) (0)
15
Bridge Selector
9-4 62.1013.105.11-A001
Protection switching
In the event of a fault, the adjacent multiplexers switch over the normal traffic
at the AU level to the half provided for protection. Operation is dual-ended
and revertive or non-revertive.
In four-fibre rings, there are two protection switching levels. At first the
system tries to protect each section of the ring by an own MS 1:1 protection.
If the fault cannot be eliminated this way, a loop is switched.
E E
N N N N N N
Node 4 Node 3 Node 4 Node 3 Node 4 Node 3
62.1013.105.11-A001 9-5
Protection switching
Each connection occupies only one ring line, however, over the entire ring. In
the event of a fault or failure, the adjacent multiplexers switch over the nor-
mal traffic to the ring line provided for protection purposes. Operation is dual-
ended and optionally revertive or non-revertive.
E E
N N N N N N
Node 4 Node 3 Node 4 Node 3 Node 4 Node 3
Fig. 9-4 Example for the traffic flow in an MS dedicated protection ring
Path protection The payload is available in the form of a container and is doubled. Then each
container is separately assembled in a VC. Thus, there are two independent
VCs which are transmitted via separate paths.
Subnetwork protection The payload is available in the form of a VC and is doubled. Thus, there is
only one VC which is transmitted two times via separate paths.
9-6 62.1013.105.11-A001
Protection switching
The advantages of path/subnetwork protection are (1) the low technical com-
plexity, (2) the possibility of application in any network topology and (3) the
flexibility regarding the decision on which connections are to be protected.
The disadvantages are (1) the relatively high expenditure resulting from the
high number of protection switches and (2) the missing possiblity of extra
traffic, since the normal traffic to be protected is always transmitted redun-
dantly.
Path Protection:
VC-xy #1
C-xy C-xy
C-xy C-xy
C-xy C-xy
Subnetwork Protection:
VC-xy
9.3.6 Protocols
Protocols exchanged between the multiplexers are used to control the pro-
tection switching processes.
• MS 1+1 protection,
• MS 1:n protection,
• MS shared protection ring,
• MS dedicated protection ring.
For path protection, a separate protocol is required for each virtual container
(VC). For this reason, path protection protocols can be appropriately trans-
mitted in the Path Overhead only (bytes K3, K4).
62.1013.105.11-A001 9-7
Protection switching
Linear chain
In a linear chain, the multiplexers are connected in series via Aggregate
Interfaces. The multiplexers at both ends of the chain are Terminal Multiple-
xers, those in between are Add/Drop Multiplexers.
Variant 1 - The protection switches are located only in the multiplexers drop-
ping the path to be protected (see Fig. 9-6).
The reliability of variant 2 is higher, since it also copes with multiple faults on
condition that only one single fault occurs on each section.
9-8 62.1013.105.11-A001
Protection switching
4 x STM-N
TM #1 ADM #2 ADM #3 TM #4
TR TR TR TR
TR ... Tributaries
TM ... Terminal multiplexer
VC-xy VC-xy
VC-xy VC-xy
VC-xy VC-xy
Aggregate Aggregate
VC-xy
VC-xy
Interface Interface
Tributary
Interface
62.1013.105.11-A001 9-9
Protection switching
Rings
Add/drop multiplexers can be operated in a ring (see Fig. 9-8). Between each
multiplexer pair located in a ring, there are two separate transmission paths.
For this reason, rings are especially appropriate for setting up reliable sub-
networks. These rings can include two or four fibres.
Interconnected rings
Rings can be connected with each other so that (1) the connecting lines are
protected and (2) protection switching can be performed independently for
both rings (see Fig. 9-9). The two multiplexers serving one connecting line
form a so-called Serving Node. It is possible to combine the two multiplexers
and their connecting line to one multiplexer.
All ring types available can be interconnected (see Fig. 9-10 and 9-11). Even
connections between different ring types are possible.
A complete recovery of the traffic signals failed is possible, if not more than
one single fault occurs in each ring and with only one single fault in the Ser-
ving Nodes.
9-10 62.1013.105.11-A001
Protection switching
TR
ADM #1
ADM #3
TR TR ... Tributaries
ADM #1
ADM #3
TR
Fig. 9-8 Examples for multiplexer rings with two and four connecting lines
62.1013.105.11-A001 9-11
Protection switching
ADM
ADM ADM
Serving nodes
ADM ADM
ADM ADM
ADM ADM
ADM
9-12 62.1013.105.11-A001
Protection switching
VC-xy
ADM #1 ADM #3
VC-xy
VC-xy
VC-xy
VC-xy VC-xy
VC-xy
VC-xy
VC-xy
VC-xy
VC-xy
VC-xy VC-xy
VC-xy VC-xy
VC-xy
ADM #2 ADM #4
62.1013.105.11-A001 9-13
Protection switching
ADM #1 ADM #3
VC-xy
VC-xy
VC-xy
VC-xy
VC-xy
VC-xy
VC-xy
VC-xy
VC-xy
VC-xy
VC-xy VC-xy
ADM #2 ADM #4
9-14 62.1013.105.11-A001
Protection switching
1. Monitoring
2. Protection Switch
3. Control
• Revertive/non-revertive operation
This option permits the operator to decide whether the system shall switch
back to the original function on elimination of the fault.
Designation Operation
62.1013.105.11-A001 9-15
Protection switching
9-16 62.1013.105.11-A001
Literature
10 Literature
[1] ITU-T Recommendation G.702: Digital Hierarchy Bit Rates (Blue Book)
62.1013.105.11-A001 10-1
Literature
10-2 62.1013.105.11-A001
Index
CI 2-13 , 6-7
Index Concatenation 2-13 , 6-11
A Continuous concatenation 6-11
Sequential concatenation 6-11
A byte 4-4
A1 byte (RSOH) 5-2
Virtual concatenation 6-11
Concatenation Indication 2-13, 6-7
A2 byte (RSOH) 5-2
Concatenation of containers 1-6
Administrative Unit (AU) 2-6
Container C
Administrative Unit Group (AUG) 2-8
AU 2-6 Container sizes 2-4
Container chain 1-6
AU pointer 2-6
Containers 1-3
AU-3 pointer 6-4
Contents identifier (higher-order POH) 5-4
D bit 6-5, 6-8
Contents identifier (lower-order POH) 5-7
H1, H2 pointer bytes 6-5 Conveyor belt 1-3
H3 pointer action byte 6-5 Cross-connect Multiplexer XMS 8-8
I bit 6-5, 6-8
NDF 6-5 D
AU-4 concatenation 6-7 D bit (Decrement) 6-5, 6-8
AU-4 pointer 6-6 D1...D3 byte (RSOH) 5-2
Concatenation 6-7 D4...D12 byte (MSOH) 5-2
D bit 6-6 Data Communication Channel 5-2
H1, H2 pointer bytes 6-6 DCC 5-2
I bit 6-6 DCCM 5-2
NDF 6-6 DCCR 5-2
AUG 2-8 Descrambling 2-17
Autom. protection switching (K4 byte) 5-7 Double ring connection 8-13
Autom. protection switching bytes K1, K2 5-2 Double rings 8-11
Automatic protection switching at the higher-order Dual-ended operation 9-1
path 5-5
E
B E.164 format 5-4
B byte 4-4 E1 byte (RSOH) 5-2
B1 byte 5-2 E2 byte (MSOH) 5-3
B2 byte (MSOH) 5-2 Equipment protection 9-15
B3 byte (higher-order POH) 5-4 Error monitoring byte B3 5-4
BIP 2-17 Error monitoring byte V5 (Bit 1, 2) 5-6
BIP values 2-17 Error monitoring using BIP-X 2-17
BIP-2 monitoring (lower-order POH) 5-6 Extra traffic 9-1, 9-2
BIP-8 monitoring 5-2
BIP-8 monitoring (higher-order POH) 5-4 F
BIP-N x 24 monitoring 5-2 F1 byte (RSOH) 5-2
Bit errors 2-17 F2 byte (higher-order POH) 5-5
Bit Interleaved Parity 2-17 Floating mode 2-15
Bit rates of the STM-1 frame 2-2 Frame alignment signal 5-2
Block structure 2-4
G
C G1 byte (higher-order POH) 5-4
C bit 4-2
C1 bit 4-4, 4-6, 4-7 H
C1 byte (RSOH) 5-2 H1, H2 byte 6-5, 6-6, 6-8
C2 bit 4-4, 4-6, 4-7 H3 byte 6-5, 6-7, 6-9
C2 byte (higher-order POH) 5-4 H4 byte 2-15 , 5-5
62.1011.105.11-A001 I-1
Index
I-2 62.1013.105.11-A001
Index
62.1011.105.11-A001 I-3
Index
I-4 62.1013.105.11-A001