Multilevel Inverters with Level Doubling Network:
A New Topological Variation
Sumit K. Chattopadhyay1 Student Member IEEE, Chandan Chakraborty2 Senior Member IEEE
Department of Electrical Engineering, Indian Institute of Technology Kharagpur, 721302, INDIA
1
email: sumit_chattopadhyay@ieee.org 2email: chakraborty@ieee.org
Abstract: Increasing number of levels has always been a major
motivation in the research of multi level inverters. This paper
proposes a level doubling network and use this to almost double
the number of levels of a multilevel inverter topology. While the
approach is suitable to almost all the existing configurations, the
unit works best for cascaded H-bridge topology. It has been
shown that the level doubling network (LDN) does not consume
any power over a complete cycle. The LDN is basically a
capacitor fed half bridge topology where the capacitor voltage is
self regulated. The proposal of the LDN opens up a new
topological variation for the existing configurations. Operation of
the circuit is verified by simulation result using
MATLAB/Simulink and experiments from laboratory prototype.
Index Terms – Multilevel inverter, power quality, converter
topology
I. INTRODUCTION
Multilevel inverters (MLI) are now very popular and globally
recognized topology for many industrial applications like
medium voltage ac drives, renewable energy, FACTS, traction
and propulsion systems, electric vehicles etc. As a
consequence, extensive investigations are going on to improve
the performance and efficiency of such converters, and to
reduce the cost. High switching frequency in power converters
is responsible for rapid voltages and current transitions. This
leads to several serious problems, such as, generation of
common-mode currents, EMI, shaft voltages, bearing current
and deterioration of motor and transformer insulation [1].
Also, high switching frequency at higher voltage results higher
device stress and device losses. So, it is always desirable to
operate the inverter with higher number of levels. But, the
number of switching device increases with number of levels.
This leads to high implementation cost and poor efficiency
due to high device losses. There are many methods reported to
increase the number of levels of MLI. References [1]–[4] have
presented several techniques for modulation, control and also
topological reviews.
Cascaded MLI has several unique advantages and it
achieves high-quality output voltages and input currents and
also high reliability due to their intrinsic component
redundancy [2]. One of the techniques to increase the number
of levels is by introducing asymmetry in voltage ratio of the
inverter cells. Asymmetric structure of MLI is introduced in
[5]–[7]. For a given topology, the number of levels depends on
the configuration of the dc voltage ratio (leading to binary,
trinary and other configurations). Note that in asymmetric
structure, powers delivered by the various levels are quite
978-1-4799-0224-8/13/$31.00 ©2013 IEEE 6263
different [2]. While, most of the power is delivered by the
highest voltage cell [8], the lower voltage cells deal with only
a fraction of the same. This is a serious limitation of such
configurations for applications where, dc busses of the MLI
are obtained by rectification of isolated ac sources.
As a result of disadvantages discussed earlier, the
asymmetric topology is not very attractive for applications in
MV drives. However, the symmetric cascaded H-bridge
(CHB) structure has definite merits in high power applications
due to its inherent capacitor balancing capability, fault
tolerance/reliability and modularity. The recent trend is to use
symmetric MLI fed by multi-pulse rectifier for high and
medium power applications in industry. References [9]-[17]
are few prominent example of such systems.
The paper is organized as follows: Section-I puts forward
the motivation of the work with a critical review of the
existing techniques to boost up the number of levels. Section-
II explains the operating principle of the topology proposed.
Section-III and IV report the results from simulation and
experimentation respectively. A laboratory prototype is made
for this purpose. Section-V concludes the work.
II. OPERATING PRINCIPLE
The single phase version of the proposed LDN is shown in
Fig.1 along with its operating modes. The LDN is realized by
adding an extra half bridge with rest of the MLI circuit as
illustrated in Fig.1.The concept is valid for any MLI topology
reported in literature so far. However, when this circuit is
added with cascaded H-bridge, there will be some extra
advantages; those will be discussed in later part of this section.
The dc bus voltage of this LDN is half of other bridges. Fig. 1
shows that the LDN network gets connected in series only
when an odd level is required to produce in either half cycle.
LDN is bypassed when an even level is produced in either half
cycle. DC bus of this half bridge does not consume any power.
If this delivers a given amount of power in first half cycle, it
will absorb the same amount of power in next half cycle. This
is because the “current-second area” during a positive voltage
level is same as current-second area during corresponding
negative voltage level. In Fig.1, it is assumed that, the MLI
circuit can generate 2N+1 levels of output voltage without
LDN (i.e. -NV to NV in steps of V). When the half bridge
(LDN) comes in operation, we get N additional levels in the
positive half cycle with corresponding output voltage levels,
such as: V/2, 3V/2, 5V/2... (2N-1)V/2 (by adding the voltage
with 0, V , 2V...(N-1)V). On the other half cycle also N
additional levels are obtained (i.e. –V/2, -3V/2, -5V/2... -(2N- (a)
1)V/2). But the difference with first half cycle is that, the
levels are obtained by algebraically summing the half bridge
voltage with -V, -2V, -4V...-NV respectively. So, the
energy spent by LDN during its positive half cycle is gained
during negative half cycle from the MLI circuit. This is
independent of current waveform magnitude and harmonic
content as long as there is half wave symmetry of current
waveform.
Hence the energy delivered/absorbed in first half cycle will
be equal to the energy absorbed/delivered by LDN in the next
half cycle. Finally the dc bus voltage of the LDN remains
unchanged.
For a poly-phase system, these LDNs of all phases may be (b)
connected to a common dc bus if CHB structure is used. This
will help to reduce the dc bus current ripple with

Fig.2. The LDN connected to (a) Flying capacitor MLI.

(b)Diode clamped MLI.

corresponding reduction in dc bus capacitance. This becomes

very advantageous for applications with higher number of
phases as the requirement of dc bus capacitance of LDN is
inversely proportional to the number of phases, if it is possible
to merge all the LDN dc busses. Fig. 7 shows single phase
version of such circuit, where a three phase CHB structure can
use LDN with common dc bus. This topological version is
realized in laboratory for experimental verification.
Connection of LDN for Flying capacitor (FC) MLI and
Diode clamped (DC) MLI is shown in Fig. 2(a) and Fig. 2(b)
respectively. Similar connection is possible for any other
topology as well. The connection for CHB is shown in the
section of experimental result, as that circuit is used for
obtaining experimental results. The LDNs can share a
common dc bus for a polyphase MLI, if CHB MLI is used.
Due to various possible transients and disturbances, the dc
bus voltage of the LDN can be higher or lower than the
desired voltage for short duration. LDN is having capability to
adjust its voltage to desired value without closed loop control.
So, the LDN does not require any additional power source.
When the LDN voltage is more than the desired voltage, its dc
bus will have more discharging than charging and vice versa.
The fundamental assumptions for satisfactory LDN operation
Fig.1. Operating modes of MLI along with LDN. (a) Positive odd voltage
level generated by adding the LDN voltage. (b) Positive even voltage level
are:
generated by bypassing the LDN. (c) Negative odd voltage level generated by 1. Output voltage and current waveforms will have half
algebraically summing the positive LDN voltage with negative voltage wrt wave symmetry.
ground. (d) Negative even voltage level generated by bypassing the LDN. 2. There will be negligible dc component in output
current waveform under steady state

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 3. The circuit resistance is non zero (even stray
resistances of the conductors and devices are good Phase voltage (a)
enough for the satisfactory operation).
4. A load with back emf will also have half wave
symmetry in back emf. (This is applicable for a load
with back emf)
LDN Voltage
III. SIMULATION RESULTS

The performances of the LDN with various MLI topologies

LDN Current at unity (b)
are evaluated by simulating the circuits in
power factor
MATLAB/SIMULINK. SIMULINK models are developed for
the three phase LDN-CHB, LDN-DC, and LDN-FC circuits
The output voltage and current waveforms and their THD
(total harmonic distortion) are analyzed in detail. Also the
performance of the added three-arm H-bridge and its energy
consumption is investigated.
Third harmonic is injected to increase the line-to-line (c)
voltage by approximately 15%.

Energy supplied by LDN at

Line Voltage unity power factor over a
complete cycle

(d)
Voltage

Phase
LDN Current zero
Voltages
power factor

Time in seconds
Fig. 3. Output line voltage and corresponding phase voltage waveforms of the
proposed topology with fundamental frequency switching and nearest voltage
(e)
level control and third harmonic injection .

(a)
Energy in Joule

Energy supplied by LDN

at zero power factor over a
complete cycle

Time in seconds
(b)
Fig. 5. (a): Thirteen level phase voltage and corresponding LDN voltage.
(b): Current through LDN at unity power factor load (c): Energy
Energy in Joule

supplied/delivered by LDN in Joule over a complete cycle for unity power

factor load. (d): Inductor current at zero power factor lagging load. (e):
Energy supplied/delivered by LDN in Joule over a complete cycle for zero
power factor lagging load.

Time in seconds This also increases the power quality: this is because of higher
Fig. 4. Energy charge-discharge cycle of LDN with 50Hz and modulation number of line-to-line voltage levels at the output. Note that,
index of unity (a) For any topology other than CHB with any number of similar situation occurs in space vector modulation, where
phases (b) With three phase CHB (common dc bus for LDNs of all phases).

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phase voltage has inherently injected third harmonic
component. Fig. 3 illustrates the 25 level line voltage obtained
from third harmonic injected 13 level phase voltages. This 13
level phase voltages are obtained from symmetric CHB MLI
with only three H-bridge cells per phase along with LDN (this
circuit would have given only 7 levels at output without
LDN).
Energy-Time waveform of the LDN to obtain output
voltage as observed in Fig. 3 is shown in Fig. 4. As the LDN
for the three -phase system shares a common dc bus (for LDN-
CHB combination), there are three charging and discharging
cycles over a complete period of the output voltage as
observed in Fig. 4(b). But, for any other topology this will not
be possible: the energy time waveform in this condition will
be as shown in Fig. 4(a). The capacitor requirement for LDN
will be lower in poly-phase LDN-CHB compare to any other
topology. Fig. 6. Output line voltage and corresponding third harmonic injected phase
voltage waveforms of the proposed topology
Fig. 5(a). illustrates 13 level phase voltage and corresponding
LDN voltage. This may be noted that, the LDN is always
contributing a positive voltage in both positive and negative TABLE I
half cycle whenever the output voltage level is odd. LDN HARDWARE SETUP DETAILS
current with unity power factor load is shown in Fig. 5(b). Experimental Parameters Details
Energy delivered /absorbed by LDN with unity power factor Number of H-Bridge Per Phase 2 with binary
load is shown in Fig. 5(c). LDN current with zero power factor asymmetry
Number of Phases at Output 3
lagging load is simulated next, corresponding current and
Load Connection Δ
energy waveforms are illustrated in Fig. 5(d) and Fig. 5(e) H-Bridge DC-Bus Capacitances 11,000 µF
respectively. Energy time waveform at any power factor can Level Doubling Circuit DC Bus 33,000 µF
be geometrically found out by algebraically summing the Capacitance
waveforms of Fig. 5(c) and 5(e) with proper ratio. This may Load time constant 500 µSec
also be observed that, the energy-time waveforms are absolute IGBT Modules (Semikron Make) SKM75GB12T4
flat, when the LDN output voltage is zero: as the LDN is IGBT Gate Drivers (Semikron SKHI 22AR
bypassed at this instant. Make)
Cooling Forced Air
IV. EXPERIMENTAL RESULTS Heat Sink (P3 type Semikron Make) 0.14ºKelvin/Watt

a. Hardware Setup Detail: A multipurpose laboratory

Initially 13 level phase voltage is generated as shown in Fig. 8.
prototype has been used to verify the performance of the
The LDN voltage is observed in channel 3. This is unaffected
proposed system as shown in Fig.6. Dspace 1104 is used to
over a period of cycle. After this, the setup is tested with three
generate the gate pulses by utilizing the
phase R-L load. Line voltage and corresponding third
MATLAB/SIMULINK models of the proposed topologies
harmonic injected phase voltages are captured in Fig. 9. Third
with minor modification. Dspace 1104 control panel can be
harmonic is generated by averaging the instantaneous maxima
seen at the top rack of the prototype, other three racks are
and minima of the three phase reference voltages. 13 levels at
allotted to accommodate the circuits of three phases as shown
the phase voltages and 25 levels at line voltage can be
in Fig.6. Each phase contains three converter stacks connected
observed. The peak line voltage observed is double the peak of
in series. Hardware circuit per phase is as shown in Fig. 7. The
phase voltage. The power factor of the load current is noted as
major parameters of the hardware setup are given in TABLE I.
0.9. Harmonic spectra of the load current are shown in Fig. 10.
b. Hardware Results: Simulated waveforms and the
Third harmonic component is 35db below fundamental: nearly
performance of the level doubling circuit is verified by the
1.8% of the fundamental, fifth harmonic component is below
operating of the prototype to drive an RL load with time
44db of fundamental: 0.65% of the fundamental.
constant of 500 µSec as shown in TABLE I.

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Fig. 7. Inverter structure of one phase used to obtain experimental results
(equivalent to simulated circuit)
Fig. 8. Channel 1: A 13 level phase voltage without third harmonic injection
Channel 2: Load current through R-L load
Channel 3: LDN voltage under self balancing condition
Fig. 9. Line voltage and corresponding third harmonic injected phase voltages
for a three phase system
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Fig. 10. Harmonic spectrum of line current
Fig. 11. Channel 1: LDN voltage observed in ac coupling
Channel 2-4: Three phase voltage under sudden increase of magnitude and
frequency
Fig. 12. Channel 1: LDN voltage observed in ac coupling
Channel 2-4: Three phase voltage under sudden decrease of magnitude and
frequency
All other harmonic components are below 50db of
fundamental: below 0.3% of the fundamental. This spectrum
is obtained without any multicarrier PWM.
In order to verify the robustness of the proposed system under
variable voltage and variable magnitude, the LDN voltage is
observed under voltage and frequency transient condition as
shown in Fig. 11. and 12. In Fig. 11, the modulation index is
suddenly doubled and frequency is also increased from 25Hz
to nearly 50Hz. As shown in channel 2, 3, and 4 of this figure.
The LDN dc bus voltage is observed in channel 1 of this
figure with ac coupling to observe the transient: a very
 negligible voltage dip is observed for short duration. Then, the
frequency and modulation index are reduced to nearly 50%
from initial condition of unity modulation index and 50Hz
frequency, as shown in Fig. 12. The reduction was in three
smaller steps. No disturbance of LDN dc bus is observed even
in ac coupling as observed in channel-1 of this figure.
V. CONCLUSIONS
This paper has presented a new concept to increase the
number of levels in MLI. A 3-phase bridge network is used to
almost double the number of levels of three phase cascaded
MLI. The proposed concept can be applied to all form of
existing MLIs to almost double the number of levels.
However, when applied with a symmetric CHB-MLI topology
this has not only increased the levels but also maintained
uniform power loading of the individual cells of the CHB-
MLI. The dc bus of the LDN remains in self balancing
condition. The operating principle of the circuit is explained.
A detail simulation is presented using MATLAB/SIMULINK.
A laboratory prototype is produced in the lab using
dSPACE1104 controller. Simulation results match well with
the corresponding experimental counterpart confirming the
effectiveness of the proposed topology.
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