Adc Lab

PANIMALAR ENGINEERING COLLEGE
( A CHRISTIAN MINORITY INSTITUTION)

JAISAKTHI EDUCATIONAL TRUST
ACCREDITED BY NATIONAL BOARD OF ACCREDITATION
(AN ISO 9001:2000 CERTIFIED INSTITUTION)
BANGALORE TRUNK ROAD,NASARATHPET, POONAMALLEE,
CHENNAI – 600 123
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DEPARTMENT OF ELECTRONICS AND
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COMMUNICATION ENGINEERING
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EC6311 – ANALOG AND DIGITAL CIRCUITS

LAB
III – Semester - Lab Manual
(2017-2018)
DEPARTMENT OF ECE
VISION
To emerge as a centre of excellence in providing quality education and produce
technically competent Electronics and Communication Engineers to meet the needs of
industry and Society.
MISSION
M1: To provide best facilities, infrastructure and environment to its students, researchers and
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faculty members to meet the Challenges of Electronics and Communication Engineering
field.
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M2: To provide quality education through effective teaching – learning process for their
future career, viz placement and higher education.
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M3: To expose strong insight in the core domains with industry interaction.
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M4: Prepare graduates adaptable to the changing requirements of the society through life
long learning.
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PROGRAMME EDUCATIONAL OBJECTIVES
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1. To prepare graduates to analyze, design and implement electronic circuits and systems
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using the knowledge acquired from basic science and mathematics.
2. To train students with good scientific and engineering breadth so as to comprehend,
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analyze, design and create novel products and solutions for real life problems.
3. To introduce the research world to the graduates so that they feel motivated for higher
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studies and innovation not only in their own domain but multidisciplinary domain.
4. Prepare graduates to exhibit professionalism, ethical attitude, communication skills,
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teamwork and leadership qualities in their profession and adapt to current trends by
engaging in lifelong learning.
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5. To practice professionally in a collaborative, team oriented manner that embraces the

multicultural environment of today’s business world.
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PROGRAMME OUTCOMES
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1. Engineering Knowledge: Able to apply the knowledge of Mathematics, Science,

Engineering fundamentals and an Engineering specialization to the solution of complex
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Engineering problems.
2. Problem Analysis: Able to identify, formulate, review research literature, and analyze
complex Engineering problems reaching substantiated conclusions using first principles of
Mathematics, Natural sciences, and Engineering sciences.
3. Design / Development of solutions: Able to design solution for complex Engineering
problems and design system components or processes that meet the specified needs with
appropriate considerations for the public health and safety and the cultural, societal, and
environmental considerations.
4. Conduct investigations of complex problems: Able to use Research - based knowledge
and research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
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5. Modern tool usage: Able to create, select and apply appropriate techniques, resources,
and modern Engineering IT tools including prediction and modeling to complex Engineering
activities with an understanding of the limitations.
6. The Engineer and society: Able to apply reasoning informed by the contextual
knowledge To access societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional Engineering practice.
7. Environment and sustainability: Able to understand the impact of the professional
Engineering solutions in societal and environmental context, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Able to apply ethical principles and commit to professional ethics and
responsibilities and norms of the Engineering practice.
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9. Individual and Team work: Able to function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
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10. Communication: Able to communicate effectively on complex Engineering activities
with the Engineering community and with society at large, such as, being able to comprehend
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and write effective reports and design documentation, make effective presentations, and
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give and receive clear instructions.
11. Project Management and Finance: Able to demonstrate knowledge and understanding
of the engineering and management principles and apply these to one’s own work, as a
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member and leader in a team, to manage projects and in multidisciplinary environments.
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12. Life – long learning: Able to recognize the needs for, and have the preparation and
ability to engage in independent and life-long learning in the broadest contest of
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technological.
PROGRAMME SPECIFIC OUTCOMES

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1. Graduates should demonstrate an understanding of the basic concepts in the primary area
of Electronics and Communication Engineering, including: analysis of circuits containing
both active and passive components, electronic systems, control systems, electromagnetic
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systems, digital systems, computer applications and communications.

2. Graduates should demonstrate the ability to utilize the mathematics and the fundamental
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knowledge of Electronics and Communication Engineering to design complex systems

which may contain both software and hardware components to meet the desired needs.
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3. The graduates should be capable of excelling in Electronics and Communication

Engineering industry/Academic/Software companies through professional careers.
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COURSE OUTCOMES:
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At the end of the course, the student should be able to:

CO1: Analyze various types of biasing and amplifier configuration.
CO2: Analyze the limitation in bandwidth of single stage and multi stage amplifier
CO3: Measure CMRR in differential amplifier
CO4: Simulate amplifiers using Spice
CO5: Use simplification techniques to design a combinational hardware circuit.
CO6: Design and Implement combinational and sequential circuits.
CO7: Design and Implement a simple digital system.
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EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY LTPC
0 0 3 2
OBJECTIVES:
The student should be made to:
 Study the characteristic of CE, CB and CC Amplifier
 Learn the frequency response of CS Amplifiers
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 Study the Transfer characteristic of differential amplifier
 Perform experiment to obtain the bandwidth of single stage and multistage amplifiers
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 Perform Spice simulation of electronic circuits
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LIST OF ANALOG EXPERIMENTS:
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1. Half Wave and Full Wave Rectifiers, Filters, Power supplies
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2. Frequency Response of CE / CB / CC amplifier and CS Amplifier
3. Darlington Amplifier
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4. Differential Amplifiers- Transfer characteristic, CMRR Measurement

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5. Cascode / Cascade amplifier

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6. Class A and Class B Power Amplifiers
7. Determination of bandwidth of single stage and multistage amplifiers

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8. Spice Simulation of Common Emitter and Common Source amplifiers

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LIST OF DIGITAL EXPERIMENTS:

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9. Design and implementation of code converters using logic gates

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(i) BCD to excess-3 code and vice versa

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(ii) Binary to gray and vice-versa

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10. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
11. Design and implementation of Multiplexer and De-multiplexer using logic gates
12. Design and implementation of encoder and decoder using logic gates
13. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
14. Design and implementation of 3-bit synchronous up/down counter
15. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
TOTAL: 45 PERIODS
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ANALOG CIRCUITS
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(A) ANALOG CIRCUITS LABORATORY
INDEX
S.no EXPERIMENT NAME Page No
Fixed Bias Common Emitter Amplifier Circuit:

1. 7
To Determine a) Q point b) Frequency Response c) Gain d) Bandwidth d)
Gain- Bandwidth Product
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Common Base Amplifier:
2. 13
To Determine a) Q point b) Frequency Response c) Gain d) Bandwidth
d) Gain- Bandwidth Product
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Common Collector Amplifier With Voltage
3. Divider Bias (Self Bias): To Determine a) Q point 19
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b) Frequency Response c) Gain d) Bandwidth d) Gain- Bandwidth Product
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Common Source Amplifier
4. 25
To Determine a) Q point b) Frequency Response c) Gain d) Bandwidth d)
Gain- Bandwidth Product
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Darlington Amplifier Using BJT rin
5. 31
To Determine a) Q point b) Frequency Response c) Gain d) Bandwidth
d) Gain- Bandwidth Product
Differential Amplifier Using BJT:
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6. 37
To determine a)Common mode gain
b)differential mode gain c)CMRR
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Cascode Amplifier:
7. 43
To Determine a). Frequency Response b). Gain c). Bandwidth
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d). Gain- Bandwidth Product

8. Cascade Amplifier: To Determine a). Frequency Response 49
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b). Gain c). Bandwidth d). Gain- Bandwidth Product

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Spice Simulation Of Common Emitter And

9. Common Source Amplifier 53
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To plot the frequency response curve of CE & CS amplifier

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Class-A Power Amplifier 57

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10.
To determine a)gain b) efficiency
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Class B Complementary Symmetry

11. Power Amplifier: 59
To determine a)gain b) efficiency
Power Supply Circuit-Half Wave Rectifier With

Simple Capacitor Filter: 63
12.
To Calculate a) DC voltage under load b) ripple factor.
c) load regulation characteristics using Zener diode
Power Supply Circuit –Full Wave Rectifier
Simple Capacitor Filter 67
13.
To Calculate a) DC voltage under load b) ripple factor.
c) load regulation characteristics using Zener diode
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Circuit Diagram:
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Model Graph:
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a. Frequency Response Curve

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Expt No: FIXED BIAS COMMON EMITTER AMPLIFIER Date:
Aim:
i.To design and construct BJT common emitter amplifier using fixed bias.
ii.To draw DC load line of the transistor and to find Q-point
iii.To measure the gain and to plot the frequency response.
iv. To measure the following parameters listed below
a) Bandwidth b) Gain bandwidth (GBW) product.
v. To justify CE amplifier as a low frequency amplifier.
Components & Equipment required:
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S.No Component/Equipment Range Quantity
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1 Resistors 1.4MΩ,3.3KΩ Each1
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2 Capacitor 0.1μFd 1
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3 Transistor BC 107 1
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4. Function Generator rin 1
5. CRO 1
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6. Power supply (0-30)v 1
Theory:
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The common emitter amplifier is a Low noise amplifier and it is used in the low
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frequency - voltage amplifier circuits. These amplifiers are used typically in the RF circuits.
The common emitter amplifier is an inverting amplifier which provides 180°phase shift. It
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has medium input impedance and high output impedance. Since the current gain and power
gain of the common emitter amplifier is high, it is a most preferable amplifier configuration.
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In fixed bias circuit, base current IB is fixed.The input of this amplifier is taken from the
base terminal, the output is collected from the collector terminal and the emitter terminal is
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common for both the terminals.

DESIGN:
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Step 1: To obtain hfe using multimeter

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hfe= β (it will varies depend up on the material used by the transistor)
Step 2:
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To find RC using KVL at the output side.

Given, VCC =12V, IC=2mA
By applying KVL to output side,
VCC – ICRC – VCE = 0
VCE = VCC - ICRC
Assume equal drops across RC and VCE
VCC
VRC = VCE = =6V, V RC  I C RC
2
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RC = =3KΩ ≈3.3 KΩ
2  10 3
Choosing a standard value for RC as 3.3KΩ
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Step 3 :
To find RB using KVL at the input side
By applying KVL to the input side,

VCC – IBRB – VBE = 0
IC 2  10 3
IB = = = 8µ A
 250
12  0.7
RB= (VCC – VBE) / IB = = 1.4M Ω
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8  10  6
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Design of Input Capacitor:
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f  Take f= 1000Hz, hie=1.6k
2hie c
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c
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1 c=0.1 f
2hie f 2 *1.6k *1k
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Calculation of Bandwidth:
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Bandwidth = fH - fL
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Gain bandwidth product (GBW) = (Amid – 3dB) (fH - fL)
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FREQUENCY RESPONSE:
VIN = 50mV at 1 KHz
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Gain =
Frequency in Hertz Vo (volts) Gain = 20log(Vo/Vin) dB
Vo/Vin
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DC ANALYSIS:
To find Q point:
When Transistor operates at Cut-off region, IC = 0;
VCE = VCC =12V
If Transistor operates at Saturation region,

IC (SAT) = IC (MAX) = VCC / RC
= 12V / 3.3kΩ
=3.636mA
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If Transistor operates at Linear region /Active region,
IB=VCC / RB
= 12V / 1.4MΩ
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=8.5µA
IC =β IB ≈ 2mA
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VC =VCE =VCC - ICRC
= 12 – 2(3.3k)
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=5.4V
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Q point = (VCEQ, ICQ) = (5.4V, 2mA)
Q point analysis: (Practical)

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 measure VCEQ at the collector terminal using multimeter.
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Q-point: (ICQ =_____ ; VCEQ =______ )

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Verification of KVL
At input side, VCC – IBRB – VBE = 0

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12 – 11.2 - 0.7 = 0
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At output side, VCC – ICRC – VCE = 0

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12 – 2(3.3k) – 0.7 = 0
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To do DC ANALYSIS:
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1. All AC voltage sources are removed from the circuit because DC analysis is
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concerned only with DC sources.

2. All the capacitors in the circuit should be short circuited because Capacitors block
DC and Bypass AC.
3. Now let's do the calculations to find the VB, RB, ICQ, and VCEQ. From this, we can
find the Q-point of this transistor circuit.
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b. DC Load Line Curve
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PROCEDURE:
1. Connect the circuit as based on the designed values.
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2. Verify the KVL at both input and output side of the circuit
3. Set Vin =50mV at 1 KHz in the function generator. Keeping input voltage as constant,
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vary the frequency in regular intervals.

4. As per the frequency variations, the changes in the output voltage has to be measured
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using CRO.
5. Calculate the Gain in dB using the formula mentioned.
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6. Plot the graph Gain in dB Vs frequency in Hz in semi log graph.

7. Calculate the Bandwidth and Gain bandwidth product from the frequency response
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graph.
TO PLOT THE FREQUENCY RESPONSE:
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1. The frequency response curve is plotted with Gain(dB) on a semi log scale
2. Line is drawn at 3 dB below with respect to the maximum of Amid & intersection
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points are noted

3. The high frequency point is called the upper 3dB point (fH)
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4. The lower frequency point is called the lower 3dB point (fL)
5. The difference between the upper 3dB point and the lower 3dB point in the
frequency scale gives the bandwidth of the amplifier
6. From the graph the bandwidth was calculated. (i.e.) Bandwidth = fH - fL
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EXERCISE:
1. Construct the CE amplifier using fixed bias with the following specification:
VCC= 10V, IC=1.2mA (find β value and substitute)
VCC =16V, IC=2mA (find β value and substitute)
VCC= 9V, IC=1.8mA, AV= 30 (find β value and substitute)
INFERENCE:
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RESULT:
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(i) Thus a BJT common emitter amplifier with fixed bias circuit is designed and
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constructed.
(ii) The Q point of the transistor is found out and the DC load line is drawn.
(iii)The frequency response curve is plotted as per the readings taken.
(iv) The following parameters are measured and calculated
(i) Bandwidth (BW):
(ii)Gain Bandwidth (GBW):
(v) Thus, the CE Amplifier is justified as low frequency amplifier.
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Circuit Diagram:
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Model Graph:
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Expt No: COMMON BASE AMPLIFIER Date:
Aim:
(i) To design and construct the common base amplifier

(ii) To draw DC load line of the transistor and to find Q-point
(iii) To plot the frequency response of the amplifier
(iv) To calculate the gain and gain bandwidth product.
(v) Compare the performance of the CB amplifier with the CE amplifier.
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Apparatus Required:
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1 Resistors 1KΩ,10KΩ 1,2
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2 Capacitor 100μF,22μF 1,1
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3 Transistor BC 107A 1
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4. Function Generator
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(0-3)MHz 1
5. CRO 30MHz 1
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6. Power supply (0-30)v 1

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Theory:
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A common base amplifier is one of three basic single-stage bipolar junction

transistor (BJT) amplifier configuration, typically used as a current buffer or voltage
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amplifier. In this configuration, the emitter terminal of the transistor serves as the input, the
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collector as the output, and the base is common and connected to ground. This circuit is
usually found in high-frequency amplifiers because its input capacitance does not suffer from
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the Miller effect, which degrades the bandwidth of the common emitter configuration, and
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because of the relatively high isolation between the input and output.
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It is also used as current buffer since it has a current gain of approximately unity.
When the circuit is preceded by a common emitter stage, it is called a cascode circuit. The
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cascode circuit has the benefits of both configurations, such as high input impedance and
isolation
Design: Specification: Vcc = +9V, VEE = -9V IC = 1mA
To Find RE
Apply KVL at the input side
-VEE+ IERE -VBE = 0

IERE =VEE+VBE
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RE = 9+ 10 - 4.5+ ICRC -9=0
ICRC =5.5
RE =
IC= 1mA
RE = 10 KΩ
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To find RC
Apply KVL to the entire loop RC=5.5KΩ
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-VEE +IERE-VCE+ICRC-VCC=0
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DC ANALYSIS:
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Verification of Kirchoff’s law at the input side
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VEE+IERE-VBE = 0
Theoretical: -9 + 10 - 0.7 ≈ 0
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Practical value:
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Verification of Kirchoff’s law at the output side

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VCC+ICRE-VCB = 0
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Theoretical:9 -5.5 -3.5 = 0
Practical value:
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DC LOAD LINE ANALYSIS

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Cut off region IC =0; VCC= VCB =9V Model graph:

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Saturation region/active region/linear

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region:
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= 0.9 mA ≈ 1 mA
αIE =IC =1 mA
VCBQ = VCC –ICRC
= 9 - 1 mA * 5.5 K
= 3.5 V
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Q-point: (ICQ =_____ ; VCEQ =______ )
FREQUENCY RESPONSE:
Vin = 50mV at 1 KHz
Gain =
Frequency Vo(volts) Gain = 20log(Vo/Vin)db
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Vo/Vin
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Calculation of Bandwidth:
Bandwidth = f H  f L
Amid  3dB
Gain bandwidth product (GBW) = ( )( f H  f L )
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PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Set Vin =50mV in the function generator. Keeping input voltage constant, vary the
frequency in regular steps.
3. Note down the corresponding output voltage
4. Plot the graph: Gain in dB Vs Frequency in Hz
5. Calculate the Bandwidth from the frequency response graph

2. Line is drawn at 3 dB below Amid & intersection points are noted
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6. From the graph the bandwidth is obtained. (i.e.) Bandwidth = fH - fL
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INFERENCE
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Exercise 1: Construct the CB amplifier as mentioned below and compare the performance
with the CE amplifier
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Exercise2: Construct the CB amplifier as mentioned below and compare the performance
with the CE amplifier
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RESULT:
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(i) Thus the Common base amplifier is designed and constructed.

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(iii) The frequency response curve of the amplifier is plotted.
i. Bandwidth (BW) :
ii. Gain Bandwidth (GBW)
(v) The Comparison performance of CB with CE amplifier is done.
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Circuit Diagram:
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Model Graph:
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Expt No: COMMON COLLECTOR AMPLIFIER WITH VOLTAGE Date:
DIVIDER BIAS (SELF BIAS)
Aim:
(i) To design and construct BJT Common Collector Amplifier using voltage divider bias
(iii)To plot the frequency response characteristics.
(iv) To measure the following parameters listed below:
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a. Gain b. Gain bandwidth Product
(v) To justify CC amplifier as a unity gain amplifier.
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Apparatus Required:
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1. Resistors 10KΩ,10KΩ,5.6KΩ Each1
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2. Capacitor 0.1μFd
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3. Transistor BC 107 1
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4. Function Generator - 1
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5. CRO 1
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6. Power Supply (0-30)v 1

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Theory:
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A common collector amplifier is a unity gain BJT amplifier used for impedance
matching and as a buffer amplifier. The circuit works well, when a positive half-cycle of the
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input signal is applied to Base emitter junction of transistor the forward bias voltage Vbe is
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increased, which in turn increases the base current Ib of transistor. Since emitter current Ie is
directly proportional to Ib the voltage drop across the Emitter Ve= IeRe is increased, hence,
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output voltage Vo is increased, thus, we get positive half-cycle of the output. It means that a
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positive-going input signal results in a positive going output signal and, consequently, the
input and output signals are in phase with each other. Similarly the negative half cycle of
input signal produces negative going output signal.
At the result, the output voltage is nearly equal to the input voltage. Examined from
the perspective of output voltage change for a given amount of input voltage change, this
amplifier has a voltage gain of almost unity (1), or 0 dB. Common Collector is designed with
output at Emitter terminal. Output follows input, hence called Emitter Follower.
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Design:
Since voltage amplification is done in the transistor amplifier circuit,

We assume equal drops across VCE and Emitter Resistance RE.. So, VRE = 6V.
The quiescent current of 1mA is assumed.
We assume a standard supply of Vcc = 12V. Drop across RE is assumed to be VRE=6V
Drop across VCE is VCC –VRE = 6V; We know that ICQ =IE,
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To find RE :
6v
Now RE = VRE / IE = = 6kΩ
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1 * 10 3
Design of R1 & R2
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Drop across RE is 6V
Drop across VBE is 0.6V
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Drop across the resistance R2 is VR2 = VBE + VRE =6.6V
Assume R1 & R2 of equal values say 10KΩ
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FREQUENCY RESPONSE:
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Vin = 0.1V at 1 KHz
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Gain =
Frequency Vo(volts) Gain = 20log(Vo/Vin)db
Vo/Vin
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DC Analysis:
find the quiescent or just simply the q-point of a Transistor Circuit.
Procedure:
1. All AC voltage sources are taken out of the circuit because they're AC
sources. DC analysis is concerned only with DC sources.
2. All the capacitors in the circuit should be removed since Capacitors block DC.
(i.e) everything before and after capacitors are removed.
3. Now let's do the calculations to find the Vbb, Rb, IEQ, and VCEQ. From this, we
can find the q-point of this transistor circuit.
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 R1 
VBB = VCC  
 ( R1  R 2) 
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= 12  10K  
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 = 6V
 (10K   10K ) 
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RB = R1 II R2
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 10 K *10 K 
=  = 5KΩ
 (10 K  10 K ) 
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   
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 V V   6  0.7 
 BB BE   5K 
IEQ =  RB  R  =
  5.6 K 
= 0.9mA
  ß  1 E   100 
 
VCEQ  VCC  I EQ RE
= 12 - (0.9mA* 5.6k)
= 6.96V
Q point = (VCEQ, IEQ)

= ( 6.96V, 0.9mA)
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Q-point: (VCEQ =______ ,IEQ =_____ ;)
Model Graph (DC Load line):
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Procedure:
1. Connect the circuit as per the circuit diagram with designed values.
2. Set Vin =0.1V in the function generator. Keeping input voltage constant, vary the
frequency in regular steps. As per the frequency variations, the changes in the output
voltage has been measured using CRO.
3. Note down the corresponding output voltage for change in frequency.
4. Calculate the gain in dB, bandwidth using the formula mentioned.
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5. Plot the graph: Gain in dB Vs Frequency in Hz.
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6. Calculate the gain bandwidth product using the formula.
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INFERENCE:
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Note: compare CC with CE and CB.
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Exercise:
1. Construct the CC amplifier using self bias with the following specification
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Vcc = 15v,Ic=2mA, β = (find β value and substitute)

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2. Construct the CC amplifier using self bias with the following specification
Vcc = 12v,IE=1mA, β = (find β value and substitute)
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RESULT:
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(i) Thus a BJT Common Collector Amplifier using voltage divider bias (self bias) is
designed and constructed.
(iii)The frequency response characteristics curve is plotted as per the readings taken.
(i) Gain
(ii) Gain bandwidth Product
(v) CC amplifier is justified as a unity gain amplifier.
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Circuit Diagram:
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Model Graph:
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Expt No: COMMON SOURCE AMPLIFIER Date:
Aim:
(i) To construct the common source amplifier.

(iii) To plot the frequency response of the amplifier.
(iv) To calculate the gain and gain bandwidth product.
Apparatus Required:
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S.No. Name Range Quantity
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Transistor J310 1
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2. Resistor 4.7KΩ,1MΩ,2.2KΩ,68KΩ Each 1
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3. Regulated power supply (0-30)V rin 1
4. Signal Generator (0-3)MHz 1

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5. CRO 30 MHz 1
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6. Bread Board 1
ng
7. Capacitor 0.1µF 2
E
ar
Theory:
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A common-source amplifier is used as a voltage or transconductance amplifier.

The common source circuit provides a high input and low output impedance levels. Like the
m
bipolar common emitter amplifier, the output of the Common Source JFET Amplifier is
180o out of phase with the input signal. JFET amplifier will have very high current gain and
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power gain. This provides a good overall performance and as such it is often thought of as the
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most widely used configuration.
These devices have the advantage over bipolar transistors of having extremely high
input impedance along with a low noise output making them ideal for use in amplifier circuits
that have very small input signals. Self bias is the most common type of JFET bias.
25
Frequency Response:
Keep the input voltage constant (Vin) =……….(Volts)
Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)
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Calculation:
Bandwidth = f2-f1
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Gain bandwidth product (GBW) = ( Amid  3dB ) (f2-f1 )

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= ( Amid  3 dB) (BW)

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PROCEDURE:
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using CRO.
graph
26
DC ANALYSIS
The transistor parameters are specified to be IDSS = 1mA, VP = −1 V

The dc equivalent circuit, obtained from by opening the capacitors.
Assuming operation in the pinch-off region.
The circuit becomes
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The drain current of the JFET is expressed by

2
 V 
E
I D  I DSS 1  GS 
 VP 
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Applying KVL at the input side,

al
IG(106) + VGS + IS(2.2 K) = 0

m
Since, the gate current is zero, so IS = ID and

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VGS = −2200 ID.

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Substitute VGS in ID
2
 V 
VGS = (2 103 )(1103 ) 1  GS 
 1 
Rearranging this expression for VGS ,
2
we get, 2.2 V GS + 5.4VGS + 2.2 = 0 and
VGS = (−0.515 V, - 1.93 V)
VGS must be negative but less negative than the pinch-off voltage of the n-channel JFET,
so, the − 0.50V result must be the correct choice.
27
The corresponding value of ID becomes
 0.50V 
2
3
I D  10 A 1  
 1V 
VDS can be found by applying KVL at the output
VDD- IDRD-VDS-ISRS = 0
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20 – (250 x 10-6 x 33 x103) – VDS – (250 x 10-6 x 2.2 x103) = 0
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VDS = 11.2V
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Substituting VDS = 11.2V in the ID equation
C
IS = ID = 250 μA
g
Q-point :(ID, VGS) rin
Q-point :( 250 μA, 11.2 V)
ee
To verify dc condition
in
Measure following parameters practically using voltmeter and ammeter

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1. VGS : = ____________
2. VDS = ____________
E
3 ID = _______
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Q-point: _____________________
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28
INFERENCE:
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Result:
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(i) Thus , the CS amplifier is constructed.

(iii) The Frequency Response of the amplifier is plotted.
a. Gain :
b. Gain bandwidth Product:
29
Circuit Diagram:
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Model Graph:
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in
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30
Expt No: DARLINGTON AMPLIFIER USING BJT Date:
Aim:
i. To design and construct Darlington amplifier by using BJT BC107.

ii. To plot the frequency response.
iii. To measure the following parameters listed below
a) Bandwidth
b) Gain bandwidth (GBW) product.
Apparatus Required:
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1. Transistor BC 107 1
ol
2. Resistor 22kΩ,100kΩ,1kΩ Each 1
C
3. Capacitor 47µF 2, 1
g
4. Function Generator (0-3)MHz
rin 1
5. CRO 30MHz 1
ee
6. Regulated power supply (0-30)V 1

in
7. Bread Board 1
ng
Theory:
E
Using the NPN Darlington pair as the example, the collectors of two transistors
are connected together, and the emitter of Q1 drives the base of Q2. This configuration
ar
achieves β multiplication because for a base current IB, the collector current is β*IB where the
current gain is greater than one, or unity. Because of direct coupling dc output current of the
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first stage is (1+hfe ) Ib1..Due to very large amplification factor even two stages Darlington
m
connection has large output current and output stage may have to be a power stage. As the
power amplifiers are not uses in this amplifier circuits, it is not possible to use more than two
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transistors in the Darlington connection. In Darlington transistor connection, the second

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transistor amplifies the leakage current of the first transistor and overall leakage current may
be high, which does not desire.
IC = IC1 + IC2
31
DC - Analysis:
β1 and β2 are the gains of the individual
transistors.
Since β= β1=β2; [βD =β1β2]
RB = R1|| R2 = {R1R2 / (R1+ R2)}

=55k
VB = VCC {R2 / (R1+R2)}
= 12{122k / (100k + 122k)}
=6.6v
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Where, VBE = VBE1 + VBE2 =1.4v
Emitter Voltage, VE = IERE = VB - VBE
le
theoretical value =5.2v
Practical value=
ol
C
Base current, IB = (VB -VBE) / (RB + βDRE)
=41µA [considered β =150]
g
practical value= rin
Emitter Current, IE = (βD +1)IB ≈ βD IB
ee
=922mA
practical value=
in
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Collector current, IC
IC = βD IB
= βD {(VB-VBE) / (RB + βDRE)}
E
=922mA
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Apply KVL at the input side:

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VB - VE -VBE =0
6.6v-5.2v-1.4v =0
m
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Apply KVL at output side,

VCC– VCE – IERE = 0
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VCE = VCC – IERE

=6.85v
Q-point:
(VCEQ, ICQ) = (6.8V ,922mA)
32
 Measure VCEQ at the collector terminal using multimeter.
 Measure ICQ at the collector terminal using ammeter.
Q-point: (VCEQ =______ ,IEQ =_____ ;)
Frequency Response :
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Keep the input voltage constant, Vin=……….(Volts)
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Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)
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33
Procedure:
1. To connect the circuit as based on the designed values

2. Verify the KVL at both input and output side of the circuit.
3. Set VIN = at 1 KHz in the function generator. Keeping input voltage as constant,
using CRO.
ge
graph.
le
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2. Line is drawn at 3 dB below with respect to the maximum of Amid & intersection
points are noted
C
g
rin
6. From the graph the bandwidth was calculated. (i.e.) Bandwidth = fH - fL
ee
INFERENCE
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34
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Result:
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i. The circuit is constructed using BC107.

ii. The frequency response of the amplifier is plotted.
iii. The following parameters are measured.
a) Bandwidth :
b) Gain bandwidth (GBW) product :
35
Circuit Diagram:
Common Mode
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Differential Mode:
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36
Expt No: DIFFERENTIAL AMPLIFIER USING BJT Date:
Aim:
i. To design and construct Differential amplifier using BJT BC107.

ii. To calculate Common mode gain and Differential mode gain
iii. To calculate common mode rejection ratio (CMRR)
Apparatus Required:
S.No Name Range Quantity
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1. Resistors 5.6KΩ,5.6KΩ,4.7KΩ,56KΩ, 56KΩ Each1
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2. Transistor BC107 2
ol
C
4. Multimeter - 1
g
5. Dual power supply (0-30)v rin 1
Theory:
ee
The differential amplifier amplifies the difference between two input voltage signals.
Hence it is also called difference Amplifier. In an ideal differential amplifier, the output
in
voltage Vo is proportional to the difference between the two input signals. Hence we can
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write, VO = Ad (V1-V2) Where Ad refers to differential gain, which amplifies the difference
between two input signals.
E
Vo = Ad vd ;
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Ad=Vo/Vd
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Generally the differential gain is expressed in its decibel (dB) value as, Ad=20 log10
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(Ad) in dB. An average level of the two input signals is called common mode signal denoted
as Vc, Vc= (V1+V2)/2 The gain with which it amplifies the common mode signal to produce
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the output is called common mode gain of the differential amplifier denoted as Ac.
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V0=AcVc ;
Ac=VO/Vc
Therefore total output of any differential amplifier can be expressed as,
Vo =AdVd+AcVc
37
Tabulation:
Common Mode:
V1=V2 (Volts) VIN = (V1 + V2 ) / 2 (Volts) V0 (Volts) AC= V0/Vin
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Differential Mode:
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V1 (Volts) V2 (Volts) VIN =V1-V2(Volts) V0 (Volts) Ad= V0/VIN

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38
Practical calculation:
CMRR=Ad/Ac ; CMRR (dB)= 20 log(Ad/Ac)
DESIGN:
I CQ  1mA  I E VCC  10V  VEE

; ;   250
hie =1.2k
Ic 1 * 10 3
ge
 4 A
I B =  = 250
le
Choose RB as 57k
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Applying KVL at input side with AC input as 0v
C
 I B RB  VBE  2I E RE  VEE  0
g
VEE  VBE  I B RB  2 I C RE
rin
10  0.7  (4A * 57 *10K )
ee
V  V BE  I B R B 2 *1 *103
R E  EE = = 4.53K
2I E
in
VCC
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Assume VCE   5V
2
E
Applying KVL at Output side

ar
VCC  (VEE ) VEE  VCC  I C RC  VCE  2 I E RE

=
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VEE  VCC  VCE  2 I E RE 10  10  5  2(1*10 3 * 4.5 *10 3 )

RC 
m
IC
= 1*10 3 = 6K
ni
Theoretical calculation:
Pa
hfeRc
Ad 
Rs  hie
hfeRc
AC 
Rs  hie  2 RE (1  hfe )
39
PROCEDURE:
1. Connect the circuit as based on the designed values (differential mode, common
mode).
2. Verify the KVL at both input and output side of the circuit.
3. Set VIN =50mV at 1 KHz in the function generator. Keeping input voltage as
constant, for both transistors.(at common mode)
4. To find output voltages V01 and V02 and also find output voltage V0.
5. Calculate the common Gain AC in dB using the formula mentioned.
6. Set V1 =50mV at 1 KHz in the function generator input for transistor Q1 and
Set V2 =100mV at 1 KHz in the function generator input for transistor Q2
ge
(at Differential mode)
7. To find output voltages V01 and V02 and also find output voltage V0.
8. Calculate the Differential mode Gain Ad in dB using the formula mentioned.
le
9. Calculate the Common Mode Rejection Ratio (CMRR) = 20 log (Ad/Ac) in dB.
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INFERENCE:
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40
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Result:
(i) Thus, the Differential amplifier is designed and constructed using BJT.
(ii) Common mode gain and Differential mode gain are calculated.
(iii)The CMRR of Differential Amplifier is dB
41
Circuit Diagram:
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Model Graph:
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42
Expt No: CASCODE AMPLIFIER Date:
Aim:
(i) To design and construct a Cascode amplifier circuit

(ii) To plot the frequency response of the amplifier.
(iii)To calculate the gain and bandwidth of the amplifier.
Apparatus Required:
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2. Resistor 47K,22K,8.2K,100K,4.7K 2,1,1,1,1
ol
C
4. Function Generator (0-3) MHz 2
g
5. CRO 30 MHz rin 1
6. Bread Board 1
ee
Theory:
in
Cascode amplifier is a special case of cascade amplifier. Cascode amplifier is a two

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stage amplifier, which comprises a CE amplifier driving a CB amplifier. The CE amplifier

has with significant current and voltage gain, moderate input and output impedance. The CE
is used most often for voltage amplification .It can provide a large output voltage swing.
E
In multistage system current stage output becomes the input of the next stage of the
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system .The emitter resistor amplifier is similar to the CE amplifier but has lower voltage
gain and higher input impedance .The CB amplifier has low input impedance and relatively
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high output impedance.

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In Cascode Amplifier Transistor Q1forms the CE amplifier and CB amplifier utilizes

Q2 .This configuration has the advantage of increased output resistance and wider frequency
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response while maintaining high voltage gain. The low input impedance of the CB circuit
forms the load resistance for the CE stage .The collector current of Q2 is almost equal to the
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collector current of Q1, which in turn drives the load.
Design:
Given, VCC= 20V, IC =1.2mA, AV= 30, , RL = 100KΏ ;
Transistor Parameters: hfe= 50 , hie = 1.2KΏ and hib= 24Ώ
(i) To calculate RC:
Rc = RL / 10 = 90kΏ / 10 = 9KΏ
43
(ii) To calculate RE:
Assume VCE1 = VCE2 = 3V, and VE = 5V;
The voltage drop across collector resistor is given by,
VRC = VCC - VCE1 - VCE2 – VE
= 20V – 3V – 3V- 5V
VRC = 9V
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RE = VE / IE ; Where IE = Ic = 1.1mA
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RE = 4.5K
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(iii) To Calculate Bias Resistors R1, R2, R3 :
C
a. R3 = 10 RE = 47KΩ
g
b. Voltage Across the base of Transistor 1 is given by,
rin
VB1 = VBE + VE
ee
VB1 = 5V + 0.7V = 5.7V

in
I3 = (VB1/ R3) = 5.7V / 47KΏ = 121 μA

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c. Voltage Across the base of Transistor 2 is given by
VB2 = VBE2 + VE + VBE2

E
= 5V + 3V + 0.7V
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= 8.7V
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d. Voltage across resistor R2 is given by

m
VR2 = VB2 - VB1

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VR2 = 8.7V – 5.7V = 3V

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e. The resistor R2 is given by
R2 = (VR2 / I3 ) = (3V / 121μA)
R2 = 24.8KΩ
f. Resistor R1 = [VCC - VB2 / I3 ]
= [ 20V – 8.7V / 121 μA]
= 93.4 KΏ
44
Determination of Capacitor Values:
To Find C1 :
C1 = * 1 / 2πf1 (Zi / 10) ]
Where Zi = ( R3 || R2 ) = 1.1KΩ and
f1 = Lower cut-off frequency= 25HZ
= 57.9μF
ge
To Find C2 :
le
C2 = * 1 / 2πf1 (hie2 / 10) ] = 53 μF
ol
Where hie2= 1.2 KΩ and f1 = Lower cut-off frequency= 25HZ;
C
To Find C3 :
g
C3 = * 1 / 2πf1hib ] rin
Where hib= 24Ω and f1 = Lower cut-off frequency= 25HZ
ee
= 256μF
in
To Find C4 :
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C4 = * 1 / 2πf1 ( (RC + RL) / 10) ]
Where RC = 9KΩ; RL = 100KΩ and

E
f1 = Lower cut-off frequency= 25HZ

ar
= 0.64 μF
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DC Analysis
m
 Here, in this circuit the Q point should be found out for each stage of amplifier.
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 Firstly, CE amplifier’s Q point is calculated and then for CB amplifier as found out in
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the previous experiments.
45
.Frequency Response:
Keep the input voltage constant, Vin =……..(volts)
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Calculation:
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Bandwidth = f2-f1
E

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= ( Amid  3 dB) (BW)

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46
PROCEDURE:
using CRO.
ge
graph
Exercise:
le
1. Try the given circuit in PSPICE Simulation.
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C
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INFERENCE
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Result:
i. The cascode circuit is designed and constructed.

ii. The frequency response of the amplifier is plotted.
iii. The following parameters are measured.
a) Bandwidth :
b) Gain bandwidth (GBW) product :
47
Circuit Diagram:
ge
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Model Graph:
in
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48
Expt No: CASCADE AMPLIFIER Date:
Aim:
(i) To design and construct a Cascade amplifier circuit

(ii) To plot the frequency response of the amplifier.
(iii) To calculate the gain and bandwidth of the amplifier.
(iv) Compare the parameters of cascade amplifier with cascode amplifier.
ge
Apparatus Required:
le
ol
C
3.3kΩ,56kΩ,600Ω,
2. Resistor 1,1,1,1,2,2,2
g
560Ω,33kΩ,5.6kΩ,2.2kΩ
3. Regulated power supply (0-30)V

rin 1
ee
4. Function Generator (0-3) MHz 2
5. CRO 30 MHz 1
in
6. Bread Board 1
ng
7. Capacitor 10μf,22μf,4.7μf 3,1,1

E
Theory:
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A single stage of amplification is not enough for a particular application. The overall
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gain can be increased by using more than one stage, so when two amplifiers are
connected in such a way that the output signal of the first serves as the input signal to the
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second, the amplifiers are said to be connected in cascade. The most common cascade
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arrangement is the common-emitter RC coupled cascade amplifier. Common-emitter

amplifier exhibit high voltage, high current, and high power gains, so they are very familiar
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than other configurations.
Amplifier with two or more stages is also known as multistage amplifier. Multistage
amplifiers can be used either to increase the overall small signal voltage gain, or to provide
an overall voltage gain greater than 1, with a very low output resistance. The bandwidth of
multistage amplifier is always less than that of the bandwidth of a single stage amplifier. Non
linear distortion is more in multistage amplifier than single stage amplifier. In circuit,
Capacitors C1and C3 couples the signal into Q1and Q 2 respectively. C5 is used for coupling
the signal from Q 2 to its load
49
Design:
Given Data:
Vcc = 10v, Ic = 2mA ,   , (Find the value using multimeter)
Step 1:
Vcc
Vc= = 10 / 2 =5V
2
Vc
R3 = = 5 / (2*10-3 ) = 2.5K
Ic
Step 2:
Ie ≈ Ic
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For temperature stability, Ve  1V
Ve
le
R4   1 / (2*10-3 ) = 500 ohms
Ie
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Step 3:
Vbe = Vb – Ve
C
For silicon transistor Vbe = 0.7 V
g
Vbe + Ve = 0.7 + 1 = 1.7V rin
Step 4:
VCC R 2
ee
VR2 = Vb =
R 2  R1
Let R2= 5K,
in
R1= 24K
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Note:
Here, in cascade amplifier,2 stages of CE amplifier is combined to form
E
Cascade amplifier. So, R1 = R5 , R2 = R6, R3 = R7, R4 = R8

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Frequency Response:
Vin =…….(volts)
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Keep the input voltage constant,

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50
Calculation:
Bandwidth = f2-f1
= ( Amid  3 dB) (BW)
DC Analysis
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Here, in this circuit the Q point should be found out for each stage of amplifier.
 Each CE amplifier’s Q point is calculated as per the procedure given in the previous
le
experiment.
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Procedure:
C
g
rin
ee
using CRO.
in
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graph
INFERENCE:
E
Note: Compare parameters of Cascode with Cascade amplifier.

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al
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Exercise:
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1. Design a three stage amplifier using BJT transistor to achieve a gain of 150 and
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input resistance of 100k and output resistance of 50 ohms.
Result:
(i) The cascade circuit is designed and constructed.

(ii) The frequency response of the amplifier is plotted.
(iii)The following parameters are measured.
a. Bandwidth :
b. Gain bandwidth (GBW) product :
(iv) The parameters of cascade amplifier are compared with the cascode amplifier.
51
COMMON EMITTER AMPLIFIER
Circuit Diagram:
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Model Graph:
in
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52
Expt.No: SPICE SIMULATION OF COMMON EMITTER AND Date:
COMMON SOURCE AMPLIFIER
Aim:
(i) To simulate the CE and CB amplifier
(ii) To plot the frequency response characteristics of both the amplifier by using
pspice.
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Software Required:
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ORCAD 9.2 Version
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Procedure:
C
START PROGRAM ORCAD RELEASE 9.2 PSPICE AD
g
FILE NEW NEW TEXT FILE
TYPE PROGRAM
rin
FILE SAVE AS .CIR then change file type as circuit files then CLICK OK
ee
FILE OPEN select file type as circuit type &

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CLICK FILE NAME CLICK OPEN

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RUN PROGRAM
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TRACE ADD TRACE select your input node and output node [Eg:
V(1),V(2),V(3),… etc] CLICK OK
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Note: To view input and output graph separately split the window using the following
procedure
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PLOT ADD PLOT TO WINDOW then TRACE ADD TRACE

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53
Common Emitter amplifier Program:
.LIB NOM.LIB
.OPTIONS NOPAGE NOECHO
.TRAN/OP 50US 2MS
.AC DEC 10 1HZ 80MEGHZ
.OP
VIN 1 0 AC 10MV SIN (0 10MV 1KHZ)
VCC 7 0 DC 15V
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RS 1 2 500
R1 7 3 47K
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R2 3 0 5K
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RC 7 4 10K
RE 5 0 2K
C
RL 6 0 20K
g
C1 2 3 10UF
C2 4 6 10UF rin
CE 5 0 10UF
Q1 4 3 5 0 QM
ee
.MODEL QM NPN (IS=2E-16 BF=100 BR=1 RB=5 RC=1 RE=0 TF=0.2NS TR=5NS
+ CJE=0.4PF VJE=0.8 ME=0.4 CJC=0.5PF VJC=0.8 CCS=1PF VA=100)
in
.PLOT TRAN V(4) V(6) V(1)

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.PLOT AC VM(6) VP(6)

.PROBE
.END
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Common Source Amplifier

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Circuit Diagram:
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54
PROGRAM:
.LIB NOM.LIB
.OPTION NOPAGE NOECHO
VIN 1 0 AC 0.5V SIN (0 0.5V 1KHZ)
VDD 7 0 DC 20V
R1 1 2 50
RG 3 0 0.5MEG
RD 7 4 3.5K
RS 5 0 1.5K
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RL 6 0 20K
C1 2 3 1UF
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C2 4 6 1UF
CS 5 0 10UF
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J1 4 3 5 JMOD
C
.MODEL JMOD NJF (IS=100E-14 RD=10 RS=10 BETA=1E-3 CGD=5PF CGS=1PF
VTO=-5).
g
.AC DEC 10 1HZ 80MEGHZ rin
.TRAN/OP 10US 1MS
.OP
ee
.PLOT TRAN V(6) V(1)
.PROBE
in
.END
ng
Model Graph:
E
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Result:
Thus, the pspice program has been executed and simulated.
55
CIRCUIT DIAGRAM:
Vcc=+12V
+
A (0-10)mA
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RC=1K
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R1=30K
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C1=22uF
B
C
BC548
g
+ C2=100uF
+
Vin=50mV R2=4.7K rin
FG CRO
Freq=1kHZ
RE=470Ω Vout
- -
ee
in
GND
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Model Graph:
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Observation:
VO = Idc =
Design
Input Power:
Pin =Vdc* Idc
Output Power:
vo2
Pout =
RL
Pou t
% Efficiency: %   *100
Pin
56
Expt No: CLASS-A POWER AMPLIFIER Date:
Aim:
(i) To construct the Class - A Power amplifier.
(ii) To calculate the efficiency of a Class A amplifier.
Apparatus Required:

1. Resistors 30KΩ,1KΩ,4.7KΩ,470Ω Each 1
ge
le
3. capacitor 100μfd
ol
4. Ammeter (0-10mA)
C
g
6. CRO 1
7. Power supply
rin (0-30)v 1
ee
Theory:
The power amplifier is said to be Class A amplifier if the Q point and the input
in
signal are selected such that the output signal is obtained for a full input signal cycle.
For all values of input signal, the transistor remains in the active region and never
ng
enters into cut-off or saturation region. When an AC signal is applied, the collector voltage
varies sinusoidally hence the collector current also varies sinusoidally. The collector current
E
flows for 3600 (full cycle) of the input signal i.e. the angle of the collector current flow is
3600.
ar
Procedure:
al
1. Give the connections as per the circuit diagram.

2. Set input as 50mv.
m
3. Note down Idc, Vo in mid frequency region.

ni
4. Calculate η using formulas.

Pa
RESULT:
Thus class A power amplifier is constructed
Efficiency =
57
CIRCUIT DIAGRAM:
With cross over distortion
ge
le
ol
C
g
Without cross over distortion rin
ee
in
E ng
ar
al
m
ni
Pa
58
Expt No: CLASS B COMPLEMENTARY SYMMETRY Date:
POWER AMPLIFIER
Aim:
(i) To analyze a Class B complementary symmetry power amplifier.
(ii) To observe the waveforms with and without cross-over distortion
(iii)To compute maximum output power and efficiency.
Apparatus Required:
ge
S.No Component/equipment Range Quantity
1. Transistor SL100, SK100 1,1
le
22KΩ(2),10Ω,2.2 KΩ,
ol
2. Resistor 1 each
1 KΩ
C
3. Capacitor 100µF 2
4. Diode IN4007 2
g
5. Function Generator
rin 1
6. CRO 30MHz 1
ee

in
Theory:
ng
For class B operation, the quiescent point is located on the X-axis itself. Due to this
collector current flows only for a half cycle of the input signal. Hence the output signal is
E
distorted. To get a full cycle across the load, a pair of transistors is used in class B operation.
The two transistors conduct in alternate half cycles of the input signal and a full cycle across
ar
the load is obtained. The two transistors are identical in characteristics and called matched
transistors.
al
Depending upon the types of the two transistors whether p-n-p or n-p-n, the two
m
circuit configurations of class B amplifier are possible .These are,

1. When both the transistors are of same type i.e. either n-p-n or p-n-p then the circuit
ni
is called push pull class B A.F. power amplifier circuit.

Pa
2. When the two transistors form a complementary pair i.e. one n-p-n and other p-n-p
then the circuit is called complementary symmetry class B A.F.power amplifier
circuit.
59
Model Graph:
(i)With Cross Over Distortion
V0
(V)
t(ms)
Cross over distortion
ge
Without Cross Over Distortion
le
V0(V)
ol
C
t(ms)
g
rin
ee
Formula Used:
in
Vdc * I dc
Input Power (W in ) =
vo2
ng
Output power (W o ) =
RL
E
Wo
Efficiency =
W in
ar
Efficiency Calculation:
al
2
i) Pdc = Vcc Im
m

(Vcc = Vm)
ni
Pa
2 Vm
= Vcc
 RL
 1   Vcc 
2
2    
Vcc 2 ( Pac ) m ax  2   RL   
ii) Pdc =  iii)=      78.5%
 2   Vcc   4 
2
RL p dc
   
    RL 
60
Procedure:
1. Connections are given as per the circuit diagram.

2. Keep Vcc =10v as constant for a input voltage of 2v
3. Vary the resistance and measure the DC current and output voltage.
4. Calculate power and efficiency.
5. Compare the calculated values.
ge
le
ol
C
g
rin
ee
in
E ng
ar
al
m
ni
Pa
Result:
(i) Thus the complementary symmetry class –B Power amplifier was constructed
(ii) Maximum output power and efficiency are calculated and compared with the
theoretical values.
61
Circuit Diagram:
Fig(i): without filter
A 1N4001 K
9
R=1K
AC I/P 230V
CRO
Vo
ge
0
GND
le
ol
C
Fig (ii): with filter
A 1N4001 K
g
9
rin
R=1K C=100uF
AC I/P 230V
CRO
ee
Vo
0
in
GND
ng
Fig (iii): load regulation characteristics

E
ar
A 1N4001 K
9
al
R=1K
+ +
(0-10)mA.
C=100uF (0-10)V
m
A V
AC I/P 230V
Z 9.1
ni
- -
0
Pa
DRB
GND
62
Expt No: POWER SUPPLY CIRCUIT-HALF WAVE RECTIFIER WITH Date:
SIMPLE CAPACITOR FILTER
Aim:
1. To Calculate DC voltage under load and ripple factor and compare with calculated
values.
2. To plot the load regulation characteristics using Zener diode.
ge
Apparatus Required:
le
ol
1. Diode IN 4007,Z 9.1 2
C
2. Resistor 1KΩ 1
g
3. Capacitor 100µfd
rin 1
4. Transformer 9-0-9V 1
ee
5. CRO 1
in
6. DRB 1
ng
7. Voltmeter (0 – 30)V 1
8. Ammeter (0 – 10) mA 1
E
9. Breadboard - 1
ar
Theory:
al
It converts an ac voltage into a pulsating dc voltage using only one half of the applied
m
ac voltage. The rectifying diode conducts during one half of the ac cycle only. During the
ni
positive half cycle of the input signal, the anode of the diode becomes positive with respect to
the cathode and hence the diode conducts
Pa
During the negative half cycle of the input signal, of the anode of the diode becomes
negative with respect to the cathode and hence the diode does not conduct. Output voltage is
seen for positive Half of input only. Output of Rectifier is pulsating DC (With ripples) and
remove them, C Filter is connected parallel with load which Bypasses AC components to
Ground
63
Tabular Column:
Without Filter:
vm vm (vrms ) 2
Vin (dc) vm v rms 2 (v) (v) Ripple Factor=   1
=
(volts) vdc (vdc ) 2
=
ge
v1 = vr  vm  v1
T1= T2=
le
With Filter:
ol
Ripple Factor
C
vr v
Vin (dc) vm
(volts) v r (volts) v rms  vdc v m  r
3 2 = v rms / v dc
g
rin
ee
in
Full Load (80kΩ) No Load (100Ω )

ng
Current (mA)
E
Voltage (Volts)
ar
Load Regulation Characteristics:

al
v NOload  vload
m
Load k Ω Vdc (Volts) Current (mA) % Regulation = *100

v NOload
ni
Pa
Ripple factor (with filter)
1 1
   = 0.05
2 3 f * c * RL 2 3 * 50 * 100 f * 1k
64
PROCEDURE:
1. Connections are given as per the circuit diagram fig(i)

2. output waveform in CRO is observed, Amplitude , Time Period is noted
3. A capacitor is inserted in parallel to load resistor RL (fig ii) which acts as a filter
section.
4. The output waveform with filter obtained in CRO is observed, the amplitude and
the time period are noted and the graph is plotted.
5. The zener diode is connected in parallel (fig iii) with the load and determines the
load regulation characteristics.
ge
Input Wave Form
le
ol
C
g
rin
ee
in
E ng
ar
al
m
ni
Pa
RESULT:
Thus the Half wave Rectifier is designed with and without Capacitor filter and the
corresponding dc voltage and the ripple factors are measured and verified
Ripple Factor Theoretical values Practical values
Without filter 1.21
With filter 0.05
65
Circuit Diagram:
Full wave rectifier without filter fig (i)
A K
1N4001
AC I/P 230V R=1K

CRO
ge
Vo
A K
le
1N4001
ol
C
GND
g
Full wave rectifier with filter fig(ii) rin
A K
ee
1N4001
in
C=100uF
AC I/P 230V R=1K
ng
CRO
Vo
E
A K
1N4001
ar
al
1N4001 GND
m
Load regulation characteristic: fig (iii)

ni
A K
Pa
9
R=1K
+ +
(0-10)mA.
C=100uF (0-10)V +
A V
AC I/P 230V
CRO
Z 9.1 - - Vo
0 -
DRB
GND
66
Expt No: POWER SUPPLY CIRCUIT –FULL WAVE RECTIFIER Date:
SIMPLE CAPACITOR FILTER
Aim:
1. Measurement of DC voltage under load and ripple factor, Comparison with

calculated values.
2. Measurement of load regulation characteristics. Comparisons with calculated

values
ge
Apparatus Required:
le
ol
1. Diode IN 4007 2
C
2. Resistor 1KΩ 1
3. Capacitor 100µfd 1
g
4. Transformer rin 9-0-9V 1
5. CRO -- 1
6. DRB -- 1
ee
7. Voltmeter (0 – 10)V 1
in
8. Ammeter (0 – 10) mA 1
9. Breadboard - 1
ng
Theory:
E
The full wave rectifier conducts for both the positive and negative half cycles of the
input ac supply. In order to rectify both the half cycles of the ac input, two diodes are used in
ar
this circuit. The diodes feed a common load RL with the help of a centre tapped transformer.
The ac voltage is applied through a suitable power transformer with proper turn’s ratio. The
al
rectifier’s dc output is obtained across the load. The dc load current for the full wave rectifier
m
is twice that of the half wave rectifier. The lowest ripple factor is twice that of the full wave
rectifier.
ni
Pa
67
Tabular Column:
Without filter:
vm 2vm (v rms ) 2
Vin (dc) vm (v ) (v ) RippleFactor=   1
= 
(volts) v rms vdc
= 2 (v dc ) 2
ge
vr  vm  v1
le
With filter: v1 = T1= T2=
ol
vr vr Ripple Factor=
Vin (dc) vm v r (volts) vrms  vdc v m 
C
(volts) 2 3 2 v rms / v dc
g
rin
ee
Load Regulation Characteristics:
in
v noload  v load
Load k Ω v dc Current (mA) % Regulation = *100
(Volts) vl oad
E ng
ar
al
Full Load ( 80K Ω ) No Load ( 100Ω )

m
Current (mA)
ni
Voltage (Volts)
Pa
Formula Used:
Ripple factor (with filter)
1 1
   = 0.028
4 3 f * c * RL 4 3 * 50 * 100 f * 1k
The efficiency of full wave rectification is twice that of half wave rectification. The
ripple factor also for the full wave rectifier is less compared to the half wave rectifier
68
Model Graph:
ge
le
ol
C
g
rin
ee
in
E ng
ar
al
m
ni
RESULT:
Pa
Thus the full wave Rectifier is designed with and without Capacitor filter and the
corresponding dc voltage and the ripple factors are measured and verified with the theoretical
values
Ripple Factor Theoretical values Practical values
Without filter 0.48
With filter 0.028
69
SAMPLE VIVA –VOCE QUESTIONS AND ANSWERS
1. What is transistor biasing?
The proper flow of zero signal collector current and the maintenance of proper collector
emitter voltage during the passage of signal is called as transistor biasing.
2. What is the need to draw a DC load line on the output characteristics of a transistor?
To study the effects of biasing conditions on the performance of a transistor, it is

necessary to draw a DC load line on the output characteristics of the transistor
ge
3. What is meant by the term Quiescent point or Operating point?
le
The selected point on the load line, which represents the values of IC and VCE when no
ol
signal is applied at the input, is known as quiescent point or Q-point.
C
4. Give the general expression of stability factor
g
1  rin
dIB
1 .
S= dIC
ee
5. List the advantages and disadvantages of fixed bias method.

in
Advantages:
ng
The advantages of fixed bias method are,

E
1. The biasing circuit is very simple

ar
2. Biasing conditions can be easily set
3. There is no loading of the source by the biasing circuit, as no resistor is used

al
across base-emitter junction.

m
Disadvantages:
ni
The disadvantages of fixed bias method are,

Pa
1. This method provides poor stability
2. There are good chances of thermal runway. This is due to high stability factor S.
6. Why a fixed bias circuit is not commonly used?
Rise in temperature causes increase in leakage current ICO, increase in current

amplification factor  and decrease in base-emitter voltage VBE, so operating point is not
stabilized. This is the reason that fixed bias circuit is not commonly used.
7. List the advantages of voltage divider bias circuit:
70
1. It has the smallest value of S among the three biasing circuits.
2. Stable Q point is got. Widely used biasing method.
8. Why it is necessary to stabilize the operating point of a transistor?
It is necessary to stabilize the operating point of a transistor because the operating point
tends to shift its position due to any or all of the following three main factors.
i) Reverse saturation current, ICO, which doubles for every 10C increase in
temperature
ge
ii) Base-Emitter voltage, VBE, which decreases by 2.5mV per C
le
iii) Transistor current gain, , which increases with temperature.
ol
9. What is meant by CMRR of a differential amplifier?
C
The common mode rejection ratio [CMRR] serves as a figure of merit of a differential
g
amplifier and is defined as the ratio of the differential mode voltage gain (Ad) to the common
rin
mode voltage gain (Ac) CMRR=Ad/Ac
10. What are features of differential amplifier?

ee
(a) High differential voltage gain

in
(b) Low common mode gain

ng
(c) High CMRR

E
(d) Two input terminals

ar
(e) High input impedances

al
(f) Large bandwidth

m
(g) Low offset voltages and currents

ni
(h) Low output impedances

Pa
11. What is the gain of Common Collector Amplifier?
The gain of Common Collector Amplifier is Unity.
12. What is frequency response?
The frequency response of an electronic device or an amplifier is defined as “the

response of the device to the changes in the frequency of the input signal”
13. What is meant by frequency response of an amplifier? (Or)What is meant by

frequency response curve?
71
The curve drawn between the voltage gain and signal frequency of an amplifier is
known as the frequency response of an amplifier.
14. What are the different regions in the frequency response curve?
The different regions in the frequency response curve are,
1. Low frequency region
ge
2. Mid frequency region
le
3. High frequency region
ol
15. Which region is important in the frequency response? Why
C
Midband region is the important region because the amplifier gain is constant
g
16. How a bandwidth can be can be calculated from the frequency response curve?
rin
Bandwidth of an amplifier can be calculated from the frequency response curve by the
following procedure
ee
Step1: Find the mid frequency gain (AV)

in
Step2: Draw a –3dB horizontal line (parallel to x-axis) on the frequency response curve and
ng
obtain the two intersection points.
Step3: Project these points on the x-axis as they correspond to the 3dB frequencies f1 and f2
E
Step4: Calculate BW = f2 – f1
ar
17. Why the frequency response of an amplifier is plotted logarithmically?

al
The frequency response of an amplifier is plotted logarithmically so that a wide range of

m
frequency can be plotted on a convenient size of paper without losing resolution at the low
frequency end. (For example, if it is necessary to scale frequencies directly on average sized
ni
graph paper over the range from 1HZ to 10KHZ, each small division might represent 100HZ.
Pa
It would then be impossible to plot points in the range from 1HZ to 10HZ, where the lower
cutoff frequencies might occur. When the horizontal scale represents logarithmic of
frequency values, the low frequency end is expanded and the high frequency end is
compressed.)
18. Why the amplifier gain reduces at lower and upper frequencies?
At lower frequencies the amplifier gain reduces due to the coupling capacitors C1, C2
and bypass capacitors.
At upper frequencies the amplifier gain reduces due to the internal transistor
capacitance and stray capacitance.
72
19.Mention two disadvantages which are specific to Darlington connection
(i)The main drawback of the Darlington pair is that the leakage current of the first transistor
is also amplified by the second stage, hence the overall leakage current may be high, so
Darlington connection of three or more is impractical.
(ii) The principal merit of Darlington circuit is its high input impedance. But the biasing
arrangement reduces the input impedance considerable in the case of ordinary emitter
follower as well as Darlington emitter follower.
ge
20. List out the difference between small signal and large signal amplifier
S.No Small Signal Amplifier Large Signal Amplifier
le
Other name of small signal amplifier is Other name of large signal amplifier is
ol
1
known as Voltage Amplifier known as Power Amplifier
C
2 Output power is low Output power is high
g
3 Power dissipation is less than 0.5W Power dissipation is greater than 0.5W
rin
It is used as the first stage of an It is used as the last stage of an
4
ee
Electronic system Electronic system
The primary function of an voltage The primary function of the power

in
5 amplifier is to increase the voltage amplifier is to deliver a large amount

ng
level of input signal. of power.
6 Input voltage is in terms of mV Input voltage is in terms of 2-4 volts.

E
7 Transistor size is small Transistor size is Large

ar
RC coupling is used in multistage Transformer coupling is used in

al
8
amplifiers multistage amplifiers
m
21. Give the classification of Power amplifiers?

ni
The classification is based up on the transistor biasing and the amplitude of the input
Pa
signal. (i.e., Position of Q-point on the Load Line).
The power amplifiers are classified as below,
1. Class A Power Amplifier
2. Class B Power Amplifier
3. Class AB Power Amplifier
4. Class C Power Amplifier
5. Class D Power Amplifier
73
22. What is cross over distortion?
In class B amplifiers, the transistors are biased at cutoff region these transistors can
operate in the active region if and only if the base emitter junction is forward biased.
To forward bias the base emitter junction, the i/p voltage must be greater than the cut-in
voltage. The cut-in voltage for silicon transistor is 0.7v
Thus as long as the i/p voltage is less than the cut in voltage, the transistors will
remain in the off state and the o/p will be zero.
ge
23. Define voltage regulators
le
 The output of the filter stage in a DC power supply is not constant.
ol
 The output voltage varies if the input voltage varies or the load current varies. So
C
to regulate the output voltage irrespective of the variations in the supply voltage or
current, voltage regulators are used.
g
24. What are the advantages and disadvantages of HWR?rin
Advantages:-
ee
1. Simple circuit
in
2. Less cost
ng
Disadvantages:-
1. Ripple factor is high

E
2. Only 40.6% is the rectification efficiency

ar
3. The transformer is not effectively utilized i.e., its TUF is only 28.6%
al
4. Large filter circuit is required to filter the ripples

m
ni
5. Very low DC output voltage and current.

Pa
25. Define Source Follower.
Output at source follows the input signal, gain is unity.
74
Pa
ni
m
al
ar
Eng
in
75
ee
rin
g
C
ol
le
ge
Pa
ni
m
al
ar
Eng
in
76
ee
rin
g
C
ol
le
ge
DIGITAL EXPERIMENTS
(B) DIGITAL CIRCUITS LABORATORY
INDEX
Page
S.N0 Experiment Name
N
o
ge
1. Study Of Logic Gates 79
le
2. Design and Implementation of Code Converter 85
ol
Design and Implementation of 4 Bit Binary
C
3. 95
adder/Subtractor and BCD adder using IC 7483
g
Design and Implementation rin of Multiplexer and
4. 99
Demultiplexer using logic Gates
Design and Implementation of Encoder and Decoder using
ee
5. 103
Logic Gates
Construction and Verification of 4 Bit Ripple Counter and
in
6. 107
MOD 10/MOD 12 Ripple Counter
ng
Design and Implementation of 3 Bit Synchronous

7. 113
UP/DOWN Counter
E
Implementation of SISO,SIPO,PISO and PIPO using Flip

8. 117
ar
Flops
al
9. Content Beyond the syllabus 120

m
10. Sample Viva Voce Questions & Answers 133

ni
Pa
77
AND GATE:
SYMBOL: PIN DIAGRAM:
ge
le
OR GATE:
ol
C
g
rin
ee
in
E ng
NOT GATE:
ar

al
m
ni
Pa
78
EXPT NO. : STUDY OF LOGIC GATES
DATE :
AIM:
To study about logic gates and verify their truth tables.
COMPONENTS REQUIRED:
SL. No. COMPONENT SPECIFICATION QTY

1. AND Gate IC 7408 1
2. OR Gate IC 7432 1
ge
3. NOT Gate IC 7404 1
le
4. NAND Gate 2I/P IC 7400 1
5. NOR Gate IC 7402 1
ol
6. X-OR Gate IC 7486 1
C
7. NAND Gate 3 I/P IC 7410 1
g
8. AND Gate 3 I/P IC 7411 1
9. IC Trainer Kit -
rin 1
10. Connecting Wires - Few
ee
THEORY:
in
A logic gate is an electronic circuit which makes logical decisions. To

ng
arrive at these decisions, the most common logic gates used are OR, AND,
NOT, NAND and NOR gates. The NAND and NOR gates are called as the
E
Universal gates. The exclusive OR (XOR) gate is another logic gate which can
ar
be constructed using basic gates such as AND, OR and NOT gates. Each
al
gate has two or more input and only one output except for the Not gate,
m
which has only one input. The logic gates are the building blocks of
hardware which are available in the form of various IC families. Each gate
ni
has a distinct logic symbol and its operation can be described by means of
Pa
an algebraic function. The relationship between input and output variables

of each gate can be represented in a tabular form called a truth table.
AND GATE:
The AND gate performs a logical multiplication commonly known as

AND function. The AND gate has two or more inputs and a single output.
The output of an AND gate is HIGH (1) only when all the inputs are high.
Even if any one of the inputs is low, the output will be LOW (0).
79
2-INPUT NAND GATE:
ge
le
ol
3-INPUT NAND GATE :
C
g
rin
ee
in
E ng
ar
al
NOR GATE:
m

ni
Pa
80
If A and B are the input variables of an AND gate and Y is its output,
then Y = A.B
Where the dot (.) denotes the AND operation.
OR GATE:
The OR gate performs a logical addition commonly known as OR

function. The OR gate has two or more inputs and a single output. The
operation of OR gate is such that a HIGH on the output is produced when
ge
any of the inputs is high. The output is Low only when all the inputs are
le
low.
ol
If A and B are the input variables of an AND gate and Y is its output,
then Y = A+B
C
Where the symbol (+) denotes the OR operation.
g
rin
NOT GATE:
ee
The NOT gate performs the basic logical function called inversion or
complementation. The purpose of this gate is to convert one logic level into
in
the opposite logic level. It has one input and one output. When a HIGH level
ng
is applied to an inverter, a LOW level appears as its output and vice versa.
E
If A is an input variable of a NOT gate and Y is its output, then

Y=
ar
NAND GATE:
al
The NAND gate is a contraction of AND-NOT. It has two or more

m
inputs and a single output. When all inputs are high, the output is LOW. If
ni
any one or both the inputs are low, then the output is HIGH.
Pa
If A and B are the input variables of a NAND gate and Y is its output,
then Y =
NOR GATE:
The NOR gate is a contraction of OR-NOT. It has two or more inputs

and only one output. The output is HIGH when both inputs are low. The
output is LOW if anyone or both inputs are high.
81
X-OR GATE :
SYMBOL : PIN DIAGRAM :
ge
le
ol
C
g
rin
ee
3-INPUT AND GATE:

in
SYMBOL: PIN DIAGRAM :

E ng
ar
al
m
ni
Pa
82
If A and B are the input variables of a NOR gate and Y is its output,
then Y =
Exclusive-OR (X-OR) GATE:
An Exclusive-OR gate is a gate with two or more inputs and one

output. The output of XOR gate is high when any one of the inputs is high.
The output is low when both the inputs are low and both the inputs are
high.
ge
If A and B are the input variables of a XOR gate and Y is its output,
then Y =
le
ol
PROCEDURE:
C
(i) Connections are given as per circuit diagram.
g
(ii) Logical inputs are given as per circuit diagram.
(iii)
rin
Observe the output and verify the truth table.
ee
Exercise
in
1. Draw the truth table for the following logic circuit and find
the output expression. What gate does the expression
ng
represent?
E
ar
al
2. Draw the logic diagram for the following expressions and

m
obtain the truth table F= (A+B)’ (A’+B’)’

ni
3. Implement the Boolean Function F=AB+A’B’+B’C

Pa
i) With AND,OR and Inverter gates

ii) With NAND and Inverter gates
4. Design a Combinational Circuit with three inputs and one
output. The output is one when the binary value of the
inputs is less than 3. The output is zero otherwise.
RESULT:
Thus all logic gates are studied and their truth tables are verified.
83
BINARY TO GRAY CODE CONVERTER
TRUTH TABLE:
Binary input Gray code output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
ge
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
le
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
ol
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
C
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
g
1 1 0 0 1 0
rin 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
ee
in
ng
K-Map for G3: K-Map for G2:

E
ar
al
m
ni
Pa
G3 = B 3 G2=B3’B2 +B3B2’
84
EXPT NO. : DESIGN AND IMPLEMENTATION OF CODE
DATE : CONVERTER
AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter using logic gates.
ge
le
Sl.No. COMPONENT SPECIFICATION QTY.
ol
1. X-OR Gate IC 7486 1
2. AND Gate IC 7408 1
C
g
5. IC Trainer Kit - 1
rin
ee
THEORY:
in
The availability of large variety of codes for the same discrete elements
of information results in the use of different codes by different systems. A
ng
conversion circuit must be inserted between the two systems if each uses
E
different codes for same information. Thus, code converter is a circuit that
makes the two systems compatible even though each uses different binary
ar
code.
al
The bit combination assigned to binary code to gray code. Since each
m
code uses four bits to represent a decimal digit. There are four inputs and
ni
four outputs. Gray code is a non-weighted code.

Pa
The input variable are designated as B3, B2, B1, B0 and the output
variables are designated as C3, C2, C1, Co. from the truth table,
combinational circuit is designed. The Boolean functions are obtained from
K-Map for each output variable.
85
K-Map for G1: K-Map for G0:
ge
le
ol
C
G1 =B1’B2 +B1B2’ G0=B1’B0 +B1B0’
g
rin
ee
LOGIC DIAGRAM:
in
E ng
ar
al
m
ni
Pa
86
GRAY CODE TO BINARY CONVERTER
TRUTH TABLE:
Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
ge
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
le
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
ol
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
C
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
g
1 0 1 1 1
rin 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
ee
in
K-Map for B3: K-Map for B2:

E ng
ar
al
m
ni
Pa
B3 = G3 B2=G3’G2 + G3G2’
87
K-Map for B1: K-Map for B0
ge
le
ol
B1=G3’G2’G1+G3’G2G1’+G3G2G1+G3G2’G1’ B0=G3’G2’G1’G0+G3’G2’G1G0’+G3’G2G1’G0’
C
= G1(G3’G2’+G3G2) + G1’(G3’G2+G2G3’) +G3’G2G1G0+ G3G2 G1’G0+G3G2G1G0’
= G1  (G 2  G3) +G3G2’G1’G0’+G3G2’G1G0
g
LOGIC DIAGRAM:
rin
ee
in
E ng
ar
al
m
ni
Pa
88
BCD TO EXCESS-3 CONVERTER
TRUTH TABLE:
BCD input Excess – 3 output

B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
ge
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
le
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
ol
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
C
1 1 0 1 x x x x
1 1 1 0 x x x x
g
1 1 1 1 x x x x
rin
K-Map for E3: K-Map for E2:
ee
in
E ng
ar
al
m
ni
Pa
E3= B3 + B2B0 + B2B1 E2=B2B1B0 + B2’B0 + B2’B1

= B3 + B2 (B0 + B1) = B2B1B0+B2’(B1+B0)
89
K-Map for E1: K-Map for E0:
ge
le
ol
C
g
rin
LOGIC DIAGRAM
ee
in
ng
E
ar
al
m
ni
Pa
90
EXCESS-3 TO BCD CONVERTER
TRUTH TABLE:
Excess – 3 Input BCD Output

X1 X2 X3 X4 A B C D
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
ge
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
le
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
ol
1 1 0 0 1 0 0 1
C
g
rin
ee
K-Map for A: K-Map for B:
in
E ng
ar
al
m
ni
Pa
A = X1 X2 + X3 X4 X1 B =X2’X3’+ X2’X4’ +X2X3X4

= X1(X2 + X3 X4) =X2’(X3’+X4’)+X2X3X4
91
K-Map for C: K-Map for D:
ge
le
ol
C
LOGIC DIAGRAM
g
rin
ee
in
ng
E
ar
al
m
ni
Pa
92
A code converter is a circuit that makes the two systems compatible
even though each uses a different binary code. To convert from binary code
to Excess-3 code, the input lines must supply the bit combination of
elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps
represents one of the four outputs of the circuit as a function of the four
input variables.
A two-level logic diagram may be obtained directly from the Boolean
ge
expressions derived by the maps. These are various other possibilities for a
logic diagram that implements this circuit. Now the OR gate whose output is
le
C+D has been used to implement partially each of three outputs.
ol
C
PROCEDURE:
g
(i) Connections were given as per circuit diagram.
rin
(ii) Logical inputs were given as per truth table
ee
(iii) Observe the logical output and verify with the truth tables.
in
ng
Exercise:
1. Design a code converter that converts
E
i) The 8,4,-2,-1 code to BCD code

ar
ii) The gray code to 8,4,-2,-1 code

al
2. Design a code converter that converts a 2 4 2 1 code to gray code

m
ni
Pa
RESULT:
Thus the code converters are designed using logic gates and their
truth tables are verified.
93
LOGIC DIAGRAM:
4-BIT PIN DIAGRAM FOR IC 7483: BINARY ADDER/SUBTRACTOR
ge
le
ol
C
g
rin
ee
TRUTH TABLE FOR 4-BIT BINARY ADDER/SUBTRACTOR:

in
ng
Input Data A Input Data B Addition Subtraction

E
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
ar
al
m
ni
Pa
94
EXPT NO. : DESIGN OF 4-BIT ADDER AND SUBTRACTOR
DATE :
AIM:
To design and implement 4-bit adder/subtractor and BCD adder
using IC 7483.
ge
1. Binary Adder IC IC 7483 1
le
2. EX-OR Gate IC 7486 1
ol
C
g
THEORY: rin
4 BIT BINARY ADDER:
ee
A binary adder is a digital circuit that produces the arithmetic sum of
two binary numbers. It can be constructed with full adders connected in
in
cascade, with the output carry from each full adder connected to the input
ng
carry of next full adder in chain. The augends bits of ‘A’ and the addend bits
of ‘B’ are designated by subscript numbers from right to left, with subscript
E
0 denoting the least significant bits. The carries are connected in chain
ar
through the full adder. The input carry to the adder is C0 and it ripples
al
through the full adder to the output carry C4.

m
4 BIT BINARY SUBTRACTOR:

ni
The circuit for subtracting A-B consists of an adder with inverters,

Pa
placed between each data input ‘B’ and the corresponding input of full
adder. The input carry C0 must be equal to 1 when performing subtraction.
95
LOGIC DIAGRAM:
BCD ADDER K Map for Y
Y = S4 S3 + S4 S2
ge
le
ol
C
g
rin
TRUTH TABLE FOR BCD ADDER:
ee
BCD SUM CARRY

S4 S3 S2 S1 Y
in
0 0 0 0 0
0 0 0 1 0
ng
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
E
0 1 0 1 0
0 1 1 0 0
ar
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
al
1 0 1 0 1
1 0 1 1 1
m
1 1 0 0 1
1 1 0 1 1
ni
1 1 1 0 1
1 1 1 1 1
Pa
OUTPUT :
A B Carry Sum
Sl.No
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1
1
96
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one
circuit with one common binary adder. The mode input M controls the
operation. When M=0, the circuit is adder circuit. When M=1, it becomes
subtractor.
4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD,
ge
together with an input carry from a previous stage. Since each input digit
does not exceed 9, the output sum cannot be greater than 19, the 1 in the
le
sum being an input carry. The output of two decimal digits must be
ol
represented in BCD and should appear in the form listed in the columns.
C
A BCD adder that adds 2 BCD digits and produce a sum digit in BCD.
g
The 2 decimal digits, together with the input carry, are first added in the top
4 bit adder to produce the binary sum.
rin
ee
PROCEDURE:
in
(i) Connections were given as per circuit diagram.

ng
(ii) Logical inputs were given as per truth table

E
(iii) Observe the logical output and verify with the truth tables.
ar
Exercise:
al
1. Design Full Adder using Two Half Adders

m
2. Design Full Subtractor using Two Half Subtractors

ni
3. Design and implement 2 x 2 Binary multiplier?

Pa
RESULT:
Thus 4-bit binary adder/subtractor and BCD adder are
designed and implemented using IC 7483.
97
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER: FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
ge
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0
le
ol
CIRCUIT DIAGRAM FOR 4:1 MULTIPLEXER:
C
g
rin
ee
in
E ng
ar
al
m
TRUTH TABLE:
ni
S1 S0 Y = OUTPUT
Pa
0 0 D0
0 1 D1
1 0 D2
1 1 D3
98
EXPT NO. : DESIGN AND IMPLEMENTATION OF
DATE : MULTIPLEXER AND DEMULTIPLEXER
AIM:
To design and implement multiplexer and demultiplexer using logic
gates.
ge
1. 3 I/P AND Gate IC 7411 2
le
ol
C
THEORY:
g
MULTIPLEXER:
rin
Multiplexer means, transmitting a large number of information units
ee
over a smaller number of channels or lines. A digital multiplexer is a
combinational circuit that selects binary information from one of many
in
input lines and directs it to a single output line. The selection of a particular
ng
input line is controlled by a set of selection lines. Normally there are 2n

input line and n selection lines whose bit combination determine which
E
input is selected.
ar
DEMULTIPLEXER:
al
The function of Demultiplexer is in contrast to multiplexer function. It

m
takes information from one line and distributes it to a given number of

output lines. For this reason, the demultiplexer is also known as a data
ni
distributor. Decoder can also be used as demultiplexer.

Pa
In the 1: 4 demultiplexer circuit, the data input line goes to all of the
AND gates. The data select lines enable only one gate at a time and the data
on the data input line will pass through the selected gate to the associated
data output line.
99
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:
FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
LOGIC DIAGRAM FOR 1:4DEMULTIPLEXER:
ge
le
ol
C
g
rin
ee
in
E ng
TRUTH TABLE:
ar
INPUT OUTPUT
al
S1 S0 I/P D0 D1 D2 D3
m
0 0 0 0 0 0 0
0 0 1 1 0 0 0
ni
0 1 0 0 0 0 0
Pa
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
100
PROCEDURE:
(iii) Observe the output and verify the truth table.
Exercise:
ge
1. Implement 16 x 1 Multiplexers with two 8 x 1 and one 2 x 1
le
Multiplexers.
ol
2. Construct a 1 x 8 Demultiplexers with two 1 x 4 Demux.
C
3. Implement a quadruple two-to-one line Multiplexers.
g
rin
ee
in
E ng
ar
al
m
ni
Pa
RESULT:
Thus the multiplexer/Demultiplexer are designed using logic
gates.
101
TRUTH TABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
ge
0 1 1 1 1 1 0
le
ol
D0 = E’A’B’
C
D1 = E’A’B
g
D2 = E’AB’
D3 = E’AB
rin
ee
LOGIC DIAGRAM FOR DECODER:

in
E ng
ar
al
m
ni
Pa
102
EXPT NO : DESIGN AND IMPLEMENTATION OF ENCODER
DATE : AND DECODER
AIM:
To design and implement encoder and decoder using logic gates.
1. 3 I/P NAND Gate IC 7410 2
ge
le
ol
C
g
THEORY: rin
ENCODER:
ee
An encoder is a digital circuit that performs inverse operation of a

decoder. An encoder has 2n input lines and n output lines. In encoder the
in
output lines generates the binary code corresponding to the input value. In
ng
octal to binary encoder it has eight inputs, one for each octal digit and three
output that generate the corresponding binary code. In encoder it is
E
assumed that only one input has a value of one at any given time otherwise
ar
the circuit is meaningless. It has an ambiguity that when all inputs are zero
al
the outputs are zero. The zero outputs can also be generated when D0 = 1.
m
ni
DECODER:
A decoder is a multiple input multiple output logic circuit which
Pa
converts coded input into coded output where input and output codes are
different. The input code generally has fewer bits than the output code. Each
input code word produces a different output code word i.e there is one to
one mapping can be expressed in truth table. In the block diagram of
decoder circuit the encoded information is present as n input producing 2n
possible outputs. 2n output values are from 0 through out 2n – 1.
103
TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
ge
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
le
ol
A= Y4 + Y5 + Y6 + Y7
C
B= Y2 + Y3 + Y6 + Y7
g
C = Y1 + Y3 + Y5 + Y7 rin
LOGIC DIAGRAM FOR ENCODER:
ee
in
E ng
ar
al
m
ni
Pa
104
PROCEDURE:
Exercise:
ge
1. To construct and verify the decoder / driver along with seven
le
segment LED display unit and verify the results.
ol
2. Design and implement four input priority encoder
C
3. Construct 3 to 8 line decoder
g
rin
ee
in
E ng
ar
al
m
ni
Pa
RESULT:
Thus the Decoder and Encoder are designed and implemented
using Logic gates.
105
PIN DIAGRAM FOR IC 7476:
ge
le
ol
C
g
rin
ee
in
E ng
ar
al
m
ni
Pa
106
EXPT NO. : CONSTRUCTION AND VERIFICATION OF 4 BIT
DATE : RIPPLE COUNTER AND MOD 10/MOD 12
COUNTER
AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple
counter.
ge
Sl.No. COMPONENTS SPECIFICATION QTY.
le
1. JK Flip-Flop IC 7476 2
ol
2. NAND Gate IC 7400 1
C
g
rin
ee
THEORY:
in
A counter is a register capable of counting number of clock pulse

ng
arriving at its clock input. Counter represents the number of clock pulses
arrived. A specified sequence of states appears as counter output. This is
E
the main difference between a register and a counter. There are two types of
ar
counter, synchronous and asynchronous. In synchronous common clock is

given to all flip flop and in asynchronous first flip flop is clocked by external
al
pulse and then each successive flip flop is clocked by Q or Q output of

m
previous stage. A soon the clock of second stage is triggered by output of

ni
first stage. Because of inherent propagation delay time all flip flops are not
Pa
activated at same time which results in asynchronous operation.
107
LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:
ge
le
ol
C
g
TRUTH TABLE: rin
CLK QD QC QB QA
0 0 0 0 0
ee
1 0 0 0 1
in
2 0 0 1 0
3 0 0 1 1
ng
4 0 1 0 0
5 0 1 0 1
E
6 0 1 1 0
ar
7 0 1 1 1
al
8 1 0 0 0
m
9 1 0 0 1
10 1 0 1 0
ni
11 1 0 1 1
Pa
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
108
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:
ge
le
ol
TRUTH TABLE:
C
g
CLK QA QB QC
rin QD
(LSB) (MSB)
ee
0 0 0 0 0
1 1 0 0 0
in
2 0 1 0 0
ng
3 1 1 0 0
E
4 0 0 1 0
ar
5 1 0 1 0
6 0 1 1 0
al
7 1 1 1 0
m
8 0 0 0 1
ni
9 1 0 0 1
Pa
10 0 0 0 0
109
LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:
ge
le
ol
C
g
TRUTH TABLE: rin
CLK QA QB QC QD
ee
(LSB) (MSB)
in
0 0 0 0 0
ng
1 1 0 0 0
2 0 1 0 0
E
3 1 1 0 0
ar
4 0 0 1 0
al
5 1 0 1 0
m
6 0 1 1 0
7 1 1 1 0
ni
8 0 0 0 1
Pa
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0
110
PROCEDURE:
Exercise:
ge
1. Construct and verify MOD 5 asynchronous counter using D flip
le
flop
ol
2. Design a counter using JK flip flops with the following binary
sequence 0,1,3,7,6,4.
C
g
rin
ee
in
E ng
ar
al
m
ni
Pa
RESULT:
Thus 4-bit Ripple counter, MOD-10/MOD-12 Counters is
designed and their truth tables are verified.
111
STATE DIAGRAM:
ge
TRUTH TABLE:
le
Input Present Next State A B C
ol
Up/Down State QA+1 Q B+1 QC+1 JA KA JB KB JC KC
QA QB QC
C
0 0 0 0 1 1 1 1 X 1 X 1 X
g
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
rin
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
ee
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
in
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
ng
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
E
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
ar
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
al
1 1 1 1 0 0 0 X 1 X 1 X 1
m
K MAP
ni
Pa
112
EXPT NO. : DESIGN AND IMPLEMENTATION OF 3 BIT
DATE : SYNCHRONOUS UP/DOWN COUNTER
AIM:
To design and implement 3 bit synchronous up/down counter.
1. JK Flip Flop IC 7476 2
ge
2. 3 I/P AND Gate IC 7411 1
le
4. XOR Gate IC 7486 1
ol
C
g
rin
THEORY:
ee
A counter is a register capable of counting number of clock pulse

in
arriving at its clock input. Counter represents the number of clock pulses
ng
arrived. An up/down counter is one that is capable of progressing in

increasing order or decreasing order through a certain sequence. An
E
up/down counter is also called bidirectional counter. Usually up/down

ar
operation of the counter is controlled by up/down signal. When this signal is

high counter goes through up sequence and when up/down signal is low
al
counter follows reverse sequence.

m
ni
Pa
113
ge
CHARACTERISTICS TABLE:
le
Q Qt+1 J K
ol
0 0 0 X
C
0 1 1 X
1 0 X 1
g
1 1 X 0
rin
ee
in
LOGIC DIAGRAM:
E ng
ar
al
m
ni
Pa
114
PROCEDURE:
Exercise:
1. Design a four bit synchronous counter with D flip flops
ge
2. Construct 3 bit synchronous Up/ Down counter using T flip flops
le
ol
C
g
rin
ee
in
E ng
ar
al
m
ni
Pa
RESULT:
Thus the 3-bit synchronous UP/DOWN counter is designed and
its truth table is verified.
115
LOGIC DIAGRAM: PIN DIAGRAM:
SERIAL IN SERIAL OUT:
ge
TRUTH TABLE
le
ol
C
g
rin
ee
in
SERIAL IN PARALLEL OUT:

E ng
ar
al
m
ni
Pa
TRUTH TABLE
116
EXPT NO. : DESIGN AND IMPLEMENTATION OF SHIFT
DATE : REGISTER
AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
ge
(iv) Parallel in parallel out shift registers using Flip Flops.
le
ol
C
1. D Flip Flop IC 7474 2
g
rin
ee
THEORY:
in
ng
A register is capable of shifting its binary information in one or both

directions is known as shift register. The logical configuration of shift
E
register consist of a D-Flip flop cascaded with output of one flip flop
ar
connected to input of next flip flop. All flip flops receive common clock
al
pulses which causes the shift in the output of the flip flop. The simplest
m
possible shift register is one that uses only flip flop. The output of a given
flip flop is connected to the input of next flip flop of the register. Each clock
ni
pulse shifts the content of register one bit position to right.

Pa
117
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
ge
le
TRUTH TABLE:
ol
CLK Q3 Q2 Q1 Q0 O/P
C
1 1 0 0 1 1
g
2 0 0 0 0 0
3 0 0 0 0
rin 0
4 0 0 0 0 1
ee
LOGIC DIAGRAM:
in
PARALLEL IN PARALLEL OUT:

E ng
ar
al
m
ni
Pa
TRUTH TABLE:
DATA INPUT OUTPUT
CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
118
PROCEDURE:
ge
Exercise:
le
1. Construct and verify 8 Bit shift registers using IC 74595
ol
2. Construct and implement 4 bit shift registers using JK flipflop
C
g
rin
ee
in
E ng
ar
al
m
ni
Pa
RESULT:
Thus the Serial in serial out, Serial in parallel out, Parallel in
serial out and Parallel in parallel out are constructed.
119
Pa
ni
m
al
ar
Eng
in
120
ee
rin
g
C
ol
le
CONTENT BEYOND SYLLABUS
ge
LOGIC DIAGRAM:
2 BIT MAGNITUDE COMPARATOR
ge
le
ol
C
g
rin
ee
in
K MAP
E ng
ar
al
m
ni
Pa
121
DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR
AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.
APPARATUS REQUIRED:
ge
1. AND GATE IC 7408 2
le
2. X-OR GATE IC 7486 1
ol
3. OR GATE IC 7432 1
C
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
g
COMPARATOR rin
6. IC TRAINER KIT - 1
7. CONNECTING WIRES -
ee
in
THEORY:
ng
The comparison of two numbers is an operator that determine one

E
number is greater than, less than (or) equal to the other number. A
magnitude comparator is a combinational circuit that compares two
ar
numbers A and B and determine their relative magnitude. The outcome of

al
the comparator is specified by three binary variables that indicate whether

m
A>B, A=B (or) A<B.

ni
Pa
122
TRUTH TABLE
ge
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
le
0 0 0 1 0 0 1
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0 0 1 0 0 0 1
0 0 1 1 0 0 1
C
0 1 0 0 1 0 0
g
0 1 0 1 0 1 0
rin
0 1 1 0 0 0 1
0 1 1 1 0 0 1
ee
1 0 0 0 1 0 0
1 0 0 1 1 0 0
in
1 0 1 0 0 1 0
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1 0 1 1 0 0 1
1 1 0 0 1 0 0
E
1 1 0 1 1 0 0
1 1 1 0 1 0 0
ar
1 1 1 1 0 1 0
al

m
ni
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123
LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR
ge
le
TRUTH TABLE:
ol
C
A B A>B A=B A<B
0000 0000 0000 0000 0 1 0
g
0001 0001 0000 0000 1 rin 0 0
0000 0000 0001 0001 0 0 1
ee
in
PROCEDURE:
ng

E

ar

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m
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RESULT:
Thus the 2 and 8 bit magnitude comparators were designed and the
output was verified.
124
ge
le
ol
C
FUNCTION TABLE:
g
INPUTS
rin OUTPUTS
Number of High Data PE PO ∑E ∑O
ee
Inputs (I0 – I7)

EVEN 1 0 1 0
in
ODD 1 0 0 1
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EVEN 0 1 0 1
ODD 0 1 1 0
E
X 1 1 0 0
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X 0 0 1 1
al
m
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Pa
125
16 BIT ODD/EVEN PARITY CHECKER /GENERATOR
AIM:
To design and implement 16 bit odd/even parity checker generator
using IC 74180.
APPARATUS REQUIRED:
ge
1. NOT GATE IC 7404 1
2. PARITY CHECKER IC 74180 2
le
3. IC TRAINER KIT - 1
4. CONNECTING WIRES - FEW
ol
C
THEORY:
g
rin
A parity bit is used for detecting errors during transmission of binary
information. A parity bit is an extra bit included with a binary message to
ee
make the number is either even or odd. The message including the parity bit
in
is transmitted and then checked at the receiver ends for errors. An error is
ng
detected if the checked parity bit doesn’t correspond to the one transmitted.
The circuit that generates the parity bit in the transmitter is called a ‘parity
E
generator’ and the circuit that checks the parity in the receiver is called a
ar
‘parity checker’.
al
In even parity, the added parity bit will make the total number is even
m
amount. In odd parity, the added parity bit will make the total number is
ni
odd amount. The parity checker circuit checks for possible errors in the
Pa
transmission. If the information is passed in even parity, then the bits

required must have an even number of 1’s. An error occur during
transmission, if the received bits have an odd number of 1’s indicating that
one bit has changed in value during transmission.
126
LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY CHECKER
ge
le
ol
TRUTH TABLE:
C
I7 I6 I5 I4 I3 I2 I1 I0 I7’I6’I5’I4’I3’I2’11’ I0’ Active ∑E ∑O
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0
g
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 rin 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1
ee
LOGIC DIAGRAM:
in
16 BIT ODD/EVEN PARITY GENERATOR

E ng
ar
al
m
ni
Pa
TRUTH TABLE:
I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 Active ∑E ∑O
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
127
PROCEDURE:

ge
le
ol
C
g
rin
ee
in
E ng
ar
al
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RESULT:
Thus the 16 bit odd/even parity checker and generator were designed
and the output was verified.
128
Demonstration of following 3 bit variable Boolean expression
Y=AB’C’+AB’C+ABC+ABC’ using K map and simplifying the same using
logic circuit.
Truth Table For Y
ge
le
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Sum of Products Expression Y= AB’C’+AB’C+ABC+ABC’
C
K map for Y:
g
rin
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Output Y=A
E
Step 1:
ar
Draw the logic diagram for given Expression

al
Y=AB’C’+AB’C+ABC+ABC’
m
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129
Using Boolean algebra techniques, the expression may be simplified as
Y=AB’ (C’+C) + AB (C+C’)
ge
le
Step 2:
ol
Applying Identity law A+A’=1 to the term C+C’=1
C
g
rin
ee
in
ng
Step 3:
E
Now OR1 Gate always produces the output 1 for all input combinations, In
ar
AND2 and AND4 one input is always high. So, these Gates act as a buffer.
al
To simplify the logic circuit, Remove AND2, AND4, OR1 and NOT2 Gates.
m
ni
Reduced expression is Y=AB’+AB

Pa
130
Step 4:
Simplifying the above equation, Y=A (B’+B)
Redrawing the above circuit diagram for simplified expression,
ge
le
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Step 5:
C
Applying Identity law A+A’=1 to the term B’+B=1
g
rin
ee
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Now OR2 Gate always produces output one for all input combinations, after
ng
removing OR2 gate, AND3 gate acts a buffer.

E
Buffer can be represented as,

ar
al
m
ni
Output Expression is Y=A, hence No gates required for the given Boolean
Pa
expression.
131
Experiment No. 4
Design a digital Circuit having a 3 inputs and 1 output in which output will be
high whenever more than one input is high
Experiment No.5
Design a Combinational Circuit with 3 inputs X, Y and Z and 3 outputs A, B,
ge
C When the binary input is 0,1,2,3 the binary output is one greater than the
le
input and when the binary input is 4,5,6,7 binary outputs is one less than
ol
input.
C
g
Experiment No.6 rin
A Boolean Function F designed on 3 input variables X,Y and Z is 1 if only if
ee
no. of 1 inputs is odd. Draw the truth table for the above function and
express it in canonical sum of products
in
E ng
Experiment No.7
ar
Construct a Boolean function of three Variables P,Q and R that has an output
al
one When exactly two P,Q and R are having values Zero and output ‘Zero’ in
m
all other cases.

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Pa
132
SAMPLE VIVA VOCE QUESTIONS AND ANSWERS
1. Give a brief about Analog signals and Digital signals.

 Analog systems process time-varying signals that can take on any
value across a continuous range of voltages (in electrical/electronics
systems).
 Digital systems process time-varying signals that can take on only one
of two discrete values of voltages (in electrical/electronics systems).
 Discrete values are called 1 and 0 (ON and OFF, HIGH and LOW,
ge
TRUE and FALSE, etc.)
le
ol
2. Describe about Logic Gates.
 The most basic digital devices are called Logic gates. Gates got their
C
name from their function of allowing or blocking (gating) the flow of
g
digital information. rin
 A gate has one or more inputs and produces an output depending on
ee
the input(s). A gate is called a combinational circuit.
 Three most important gates are: AND, OR, NOT.
in
ng
3. What do you mean by universal gates?

The universal gates are those gate from which we can make any gate
E
by using them. The universal gates are- NAND & NOR.

ar
al
4. What is the difference between EX-OR & EX-NOR gate?

m
The basic difference between this two gate is that EX-OR gate gives
output when both the inputs are different & EX-NOR gate gives output
ni
when both inputs are same.

Pa
5. Draw the EX-OR gate by using only NAND gates?
133
6. Draw the EX-NOR gate by using only NAND gate?
7. State and Explain Demorgan’s Theorem.
ge
De-Morgan‘s First Theorem
le
It States that ―The complement of the sum of the variables is
ol
equal to the product of the complement of each variable‖. This theorem
C
may be expressed by the following Boolean expression.
g
rin
ee
in
E ng
De-Morgan‘s Second Theorem

ar
It states that the ―Complement of the product of variables is

al
equal to the sum of complements of each individual variables‖. Boolean

expression for this theorem is
m
ni
Pa
134
8. What is a combinational logic circuit? Write an example.
When logic gates are connected together to produce a specified
output for certain specified combinations of input variables, with no
storage involved, the resulting circuit is called ‘combinational logic
circuit’.
9. What is a half-adder?
A half adder is an arithmetic circuit that adds two binary digits. It
ge
has two inputs and two outputs only (sum and carry).
le
10. Draw the logic diagram of a half adder.
ol
C
g
rin
11. What is a full-adder?
ee
A full adder is an arithmetic circuit that adds two binary digits and a
in
carry, i.e. Three bits. It has three inputs and two outputs (sum and carry)
ng
12. Draw the Logic diagram of a full adder.

E
ar
al
m
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(a) for Sum (b) for Carry

13. Implement the full adder using two half adders
135
14. What is a half-subtractor?
A half-subtractor is an arithmetic circuit that subtracts one binary
digit form another. It has two inputs and two outputs (difference and
borrow).
15. Draw the logic diagram of a half subtractor.
ge
le
ol
C
16. What is a full-subtractor?
A full-subtractor is an arithmetic circuit that subtracts one binary
g
digit from another considering a borrow. It has three inputs and two
rin
outputs (Difference and Borrow).
ee
17. What do you mean by cascading of parallel adders? Why is it

in
required?
ng
Connecting the parallel adders in series, i.e. connecting the carry

out of one parallel adder to the carry-in of another parallel adder is
E
called cascading them. It is required when a large number or bits are

ar
to be added.
al
m
18. In what way is a BCD adder different form a binary adder?

ni
While adding BCD numbers, the output is required to be corrected

which is not required in the case of binary adders.
Pa
19. What are code converters?

Code converters are logic circuits whose inputs are bit patterns
representing numbers or characters in one code and whose outputs
are the corresponding representations in a different code.
136
20. List out the differences between Decoder and Encoder.
Encoder Decoder
1. In decoder one of the output 1. In encoder, the output lines
lines is activated corresponding generate the binary code,
to the binary input. corresponding to the input value.
2. Input of the decoder is an 2. Input of the encoder is a decoded
encoded information presented information presented as 2n
as n inputs prodcing 2n possible inputs producing n possible
ge
outputs. outputs.
le
21. What is a priority encoder?
ol
A priority encoder is an encoder circuit that includes the priority
C
function. In priority encoder, if 2 or more inputs are equal to 1 at the
g
same time, the input having the highest priority will take precedence.
rin
22. List out the differences between Multiplexer and Demultiplexer
Parameter Multiplexer Demultiplexer
ee
Definition Multiplexer is a digital Demultiplexer is a circuit

in
switch which allows that receives information

ng
digital information on a single line and

from several sources to transmits this information
E
be routed on to a single on one of 2n possible

ar
output line. output lines.

Number of data inputs 2n 1
al
No of data outputs 1 2n
m
Number of selection n n
ni
lines
Pa
Relationship of input Many to one One to many

and Output
Applications 1. Used as a data 1. Used as a data
selector. distributor.
2. In time division in 2. In time division
multiplexing at the multiplexing at the
transmitting end. receiving end.
137
23. List out the applications of Multiplexer?
 It can be used to realize a Boolean Function
 Data routing
 Control Sequencer
 It can be used in Communication Systems E.g; Time division
Multiplexing
24. Mention the uses of Decoder?
ge
 Decoders are used in Counter system
 Used in code converter
le
 Decoder outputs can be used to drive a display system.
ol
C
25. What is a Comparator?
g
A comparator is a logic circuit that compares the magnitudes of
rin
two binary numbers. The EX – NOR gate(coincidence gate) is a basic
comparator.
ee
in
26. Define – Sequential Logic Circuit. Write an example.

ng
The circuits in which the output variables depend not only on

the present input but they also depend upon the past outputs, which
E
are known as sequential logic circuits. Flip-flops, counters and

ar
registers are the examples of sequential logic circuit.

al
27. What are the classifications of sequential circuits?

m
The sequential circuits are classified on the basis of timing of their

ni
signals into two types. They are,

Pa
1) Synchronous sequential circuit.

2) Asynchronous sequential circuit.
28. What are synchronous sequential circuits?

Synchronous sequential circuits are those in which signal can
affect the memory element only at discrete instants of time. Clocked
flip-flops are examples of synchronous sequential circuits.
138
29. Define Flip flop.
Flip flop is defined as a digital circuit which maintains its output
state either at 1 or 0 until directed by an input signal to change its
state. (1-bit storing element)
(Or)
Flip - flop is a sequential device that normally samples its inputs and
changes its outputs only at times determined by clocking signal.
ge
30. Define Registers.
A register is a group of Flip-flops, Flip flops can store one bit
le
information. so an n-bit register has a group of n flip flops and is
ol
capable of storing any binary information/number containing n bits.
C
31. Difference between Latch and Flip flops
g
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al
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32. What is the operation of SR flip-flop?

• When R input is low and S input is high the Q output of flip-flop is
Set.
• When R input is high and S input is low the Q output of flip-flop is
Reset.
• When both the inputs R and S are low the output does not change.
• When both the inputs R and S are high the output is unpredictable.
139
33. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the
output
Q is set and if D=0, the output is reset.
34. What is the operation of T flip-flop?

T flip-flop is also known as Toggle flip-flop.
• When T=0 there is no change in the output.
ge
• When T=1 the output switch to the complement state (ie) the output
toggles.
le
ol
35. Write truth table for JK flip Flop?
C
g
rin
ee
in
E ng
ar
36. Define race around condition.

al
In JK flip-flop output is fed back to the input. Therefore change

m
in the output results change in the input. Due to this in the positive
half of the clock pulse if both J and K are high then output toggles
ni
continuously. This condition is called ‘race around condition’.

Pa
37. What is edge-triggered flip-flop?

The problem of race around condition can solved by edge
triggering flip flop. The term edge triggering means that the flip-flop
changes state either at the positive edge or negative edge of the clock
pulse and it is sensitive to its inputs only at this transition of the clock.
140
38. What is a shift register?
The binary information in a register can be moved from stage to
stage within the register or into or out of the register upon application
of clock pulses. This type of bit movement or shifting is essential for
certain arithmetic and logic operations used in microprocessors. This
gives rise to group of registers called shift registers.
39. What are the different types of shift registers?
ge
There are five types shift registers. They are,
1) Serial In Serial Out Shift Register
le
2) Serial In Parallel Out Shift Register
ol
3) Parallel In Serial Out Shift Register
C
4) Parallel In Parallel Out Shift Register
g
5) Bidirectional Shift Register rin
40. What is a counter?
ee
In digital logic and computing, a counter is a device which stores (and

in
sometimes displays) the number of times a particular event or process has

ng
occurred, often in relationship to a clock signal.

E
41. Draw the state diagram of MOD-10 counter.

ar
al
m
ni
Pa
141
42. Give the comparison between synchronous & Asynchronous
sequential circuits.
Synchronous sequential circuits Asynchronous sequential circuits
1.Memory elements are clocked flip- 1.Memory elements are either

flops unlocked flip flops or time delay
elements.
ge
2. The change in input signals can 2. The change in input signals can
affect memory element upon affect memory element at any
le
activation of clock signal. instant of time.
ol
3. The maximum operating speed of 3. Because of absence of clock, it can
C
clock depends on time delays operate faster than synchronous
g
involved. circuits.
rin
4. Easier to design 4. More difficult to design
ee
43. What is the Mealy model of the state diagram of a memory

in
element?
ng
In the Mealy model of the state diagram each node in the state
diagram represents a particular state of the FF (0 or 1). The labels on
E
the arcs indicate the input/output, i.e. the input that is given when the
ar
FF is in a particular state and the corresponding output. The

al
directions of the arrows point to the next state the FF will go after the
m
input is applied.
ni
44. What is the Moore model of the state diagram of a memory

Pa
element?
In the Moore model of the state diagram, the state code and the
value of the output are written inside the circle. The directed line
joining one node to the other, or looping back to the same node has the
value of the input written beside the line.
142
45. Compare the state diagram and the state table.
State table
The State table repre The state table representation of a
sequential circuit consists of three sections labelled present state, next
state and output. The present state designates the state of flip-flops
before the occurrence of a clock pulse. The next state shows the states
of flip-flops after the clock pulse, and the output section lists the value
of the output variables during the present state.
ge
State Diagram
le
In addition to graphical symbols, tables or equations,
ol
flip-flops can also be represented graphically by a state diagram. In
C
this diagram, a state is represented by a circle, and the transition
between states is indicated by directed lines (or arcs) connecting the
g
circles.
rin
An example of a state diagram is shown in Figure below
ee
in
E ng
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al
m
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Pa
143

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PANIMALAR ENGINEERING COLLEGE

( A CHRISTIAN MINORITY INSTITUTION)

EC6311 – ANALOG AND DIGITAL CIRCUITS

5. To practice professionally in a collaborative, team oriented manner that embraces the

1. Engineering Knowledge: Able to apply the knowledge of Mathematics, Science,

PROGRAMME SPECIFIC OUTCOMES

systems, digital systems, computer applications and communications.

knowledge of Electronics and Communication Engineering to design complex systems

3. The graduates should be capable of excelling in Electronics and Communication

At the end of the course, the student should be able to:

The student should be made to:

 Study the characteristic of CE, CB and CC Amplifier

 Learn the frequency response of CS Amplifiers

4. Differential Amplifiers- Transfer characteristic, CMRR Measurement

5. Cascode / Cascade amplifier

6. Class A and Class B Power Amplifiers

7. Determination of bandwidth of single stage and multistage amplifiers

8. Spice Simulation of Common Emitter and Common Source amplifiers

LIST OF DIGITAL EXPERIMENTS:

9. Design and implementation of code converters using logic gates

(i) BCD to excess-3 code and vice versa

(ii) Binary to gray and vice-versa

14. Design and implementation of 3-bit synchronous up/down counter

S.no EXPERIMENT NAME Page No

Fixed Bias Common Emitter Amplifier Circuit:

d). Gain- Bandwidth Product

b). Gain c). Bandwidth d). Gain- Bandwidth Product

Spice Simulation Of Common Emitter And

To plot the frequency response curve of CE & CS amplifier

Class-A Power Amplifier 57

Class B Complementary Symmetry

Power Supply Circuit-Half Wave Rectifier With

a. Frequency Response Curve

common for both the terminals.

Step 1: To obtain hfe using multimeter

To find RC using KVL at the output side.

By applying KVL to the input side,

If Transistor operates at Saturation region,

Q point analysis: (Practical)

Q-point: (ICQ =_____ ; VCEQ =______ )

At input side, VCC – IBRB – VBE = 0

At output side, VCC – ICRC – VCE = 0

concerned only with DC sources.

vary the frequency in regular intervals.

6. Plot the graph Gain in dB Vs frequency in Hz in semi log graph.

points are noted

(i) To design and construct the common base amplifier

S.No Component/Equipment Range Quantity

6. Power supply (0-30)v 1

A common base amplifier is one of three basic single-stage bipolar junction

Design: Specification: Vcc = +9V, VEE = -9V IC = 1mA

Apply KVL at the input side

-VEE+ IERE -VBE = 0

Verification of Kirchoff’s law at the output side

Theoretical:9 -5.5 -3.5 = 0

DC LOAD LINE ANALYSIS

Cut off region IC =0; VCC= VCB =9V Model graph:

Saturation region/active region/linear

Vin = 50mV at 1 KHz

TO PLOT THE FREQUENCY RESPONSE:

(i) Thus the Common base amplifier is designed and constructed.

DIVIDER BIAS (SELF BIAS)

Q-point: (ICQ =_ ; VCEQ =__ )

VEE  VCC  VCE  2 I E RE 10  10  5  2(110 3 4.5 *10 3 )