A p p l i c at i o n N o t e

AN 3007
Using NEC Optocouplers as Gate Drivers
in IGBT and Power MOSFET Applications
by Van N. Tran
Staff Applications Engineer, CEL Opto Semiconductors

1. Introduction
todiode (PD), signal processing circuit, and large-current
Rising concern for environmental issues and energy output circuit are also integrated into the device.
savings is driving growth in the use of dynamic power
control and inverters throughout the industrial, power,
and home appliance markets. In the U.S. and Europe, NC 1 8 VCC
the use of general-purpose inverters and AC servos is UVLO

expanding rapidly, especially in the BRICs market. There LED

Output Voltage (V)

ANODE 2 7 VO
has also been steady growth in the use of these devices Signal Output
Processing Drive
in power-related fields like wind and solar generation, Circuit Circuit
CATHODE 3 PD 6 VO
two markets that are expected to grow well into the
future. Power semiconductors such as Insulated Gate
Bipolar Transistors (IGBT) and Power MOSFETs are be- NC 4
Shield
5 VEE
ing used in large quantities in the inverters employed in
power-related equipment in all these fields.
NEC’s PS9552, PS9553, PS9301 and PS9401-2 are Figure 2-1 PS9552 Equivalent Circuit

high-speed optocouplers designed specifically for gate

driving these IGBTs and Power MOSFETs. A newly developed BiCMOS process enables the light-
receiving IC to provide a large output current (IO = 2.5A
Table 1-1 NEC Gate Driver Optocouplers for IGBT/MOSFET max) with low operating circuit current
(ICC = 2 mA typ). It also enables high-
ABSOLUTE MAXIMUM RATINGS
temperature operation (Ta = 100 °C
BV VCC IO(PEAK) ICCH/ICCL IFLH tPLH/tPHL PWD CMH/CML 0.1 uF
Part No. Package max). Moreover, a transparent conduc-
(Vr.m.s.) (V) (A) (mA) (mA) (µs) (µs) (kV/µs
+5V min.) VCC = 15V
tive shield between the IRED and the +HV DC (P Lin
PS9552 1 DIP8 5000 35 2.5 5/5 5 0.5/0.5 0.3 25/25
light receiving IC provides for superb
PS9301 SDIP6 5000 35 0.6 3/3 5 0.7/0.7 0.5 15/15
noise resistance characteristics be-
RG
PS9401-22 SSOP16 5000 35 0.6 3/3 5 0.7/0.7 0.5 15/15 tween input and output. Three
PS9553 DIP8 5000 35 0.6 3/3 5 0.7/0.7 0.5 15/15 An Under-Voltage Lock Out (UVLO) Phase
Output
NOTES 1. Built-in UVLO function 2. Two channel version function protects both the PS9552 and
VEE = –5 V
the IGBT when input signal drops or in
In this application note, NEC’s PS9552 Insulated Gate other conditions where the IGBT could be damaged. –HV DC (N Lin

Driver optocoupler is used as an example to describe the

characteristics, the internal gate drive circuits, the exter- PS9552 Features
nal gate resistance requirements, and the details of gate • Large output peak current (IO = 2.5A max)
driver optocoupler power dissipation in relation to the • High-speed switching (tPLH/ tPHL = 0.5µs max)
MOSFET/IGBT gate charge, based on the desired switch-
ing frequency to turn on and off the MOSFET / IGBT. • Large operating voltage range (VCC –VEE = 15–30 V)
VGS Gate Source Voltage (V)

Qg
• Built-in UVLO (Under-Voltage Lock Out) function
2. PS9552 Overview • High instantaneous common mode rejection voltage
VDR
Figure 2-1 shows the equivalent circuit of the PS9552, (CMH, CML = ±15 kV/µs min.) Peak
Drive
an 8-pin DIP digital, high-speed optocoupler that incor- Voltage
porates a GaAlAs Infrared emitting diode (IRED) on the A PS9552 Truth Table is provided on the next page. More
input side and a single-chip IC on the output side. A pho- details and a data sheet are available at www.cel.com.
Qgs Qgd

Q Gate Charge (nC)

 AN 3007

4. Designing an IGBT Gate Drive Circuit Using the PS9552

Table 2-1 PS9552 Truth Table
14
Electronic control of motors and AC circuits gives an intel-
VCC – VEE VCC – VEE
IRED Voltage Rise Voltage Drop Output NCligent
1 power system a wide range of dynamic 8 VCCflexibility. 12
(Turn-On) (Turn-Off ) (VO) Computer algorithms UVLOcan take charge of systems and op-
erateLED
them with a fine degree of control. 10

Output Voltage (V)

OFF 0 to 30 V 0 to 30V L ANODE 2 7 VO
The basic circuit
Signal
shown
Output
in Figure 4-1 below outlines
ON 0 to 11 V 0 to 9.5V L 8
the fundamentalProcessing
hardware
Circuit
connections, from the system
Drive
Circuit
ON 11 to 13.5V 9.5 to 12V Transition CATHODEcontrol
3 PD on the left to the three-phase 6output
input VO on the 6
ON 13.5 to 30V 12 to 30V H right. The PS9552 as shown serves as the optical isola-
NCtion
4 and driver for one of the power transistors, 5 VEE shown
4
Shield V UVL
3. UVLO – Under-Voltage Lock Out Function ranked in pairs for each phase of the output.
2
One PS9552 Isolated Gate Driver is required for
When gate voltage to the IGBT drops, power dissipation
each power transistor. The control system on the left is
increases and the IGBT heats up, which can lead to 0
shown with a +5V supply. The output of the PS9552 is
breakdown. When the VCC –VEE power supply voltage to
shown with +15V and –5V, which are electrically inde- Po
the PS9552 is insufficient to protect the IGBT, the UVLO
pendent from the driving data input supply. The power
function in the PS9552 maintains a low level Vo output
transistors can have voltages of over +600V connected
to protect both devices.
to them from a separate supply.
When the VCC –VEE power supply voltage to the
PS9552 is low (when the VCC –VEE power supply 0.1 uF
voltage rises from 0 V), the VO output is main- +5V VCC = 15V
+HV DC (P Line)
tained at a low level up to VUVLO+, even if the IRED
is on (Figure 3-1). Conversely, when the VCC –VEE
drops (changes to a negative voltage), the VO out- RG
Three
put is held at a high level until VUVLO–, but when it Phase
drops lower than VUVLO–, the VO output is lowered Output

to the low output level — even if the IRED is on. VEE = –5 V

Based on this characteristic, if the VCC –VEE

power supply voltage of the PS9552 drops below
VUVLO– (9.5 to 12 V) due to some anomaly in the
IGBT drive circuit, the VO output of the PS9552 becomes
low level in approximately 0.6µs even if the IRED is on.
Thereafter, if the VCC –VEE power supply voltage exceeds
VUVLO+ (11 to 13.5V), the VO output returns to high level
–HV DC (N Line)
Figure 4-1 Example of an IGBT drive circuit using the PS9552.
The gate resistance settings described in 4.1 and 4.2 are implemented.
This Isolated Gate Driver solution enables a multi-sup-
VGS Gate Source Voltage (V)

in approximately 0.8µs (when IRED on). ply system to work, Qg providing data flow from the input to
action at the output. Besides optical isolation between
Figure 3-1 Output vs. Power Supply Voltage the power supply and power transistor, the PS9552 also
VDR
provides the gate drive, eliminating Peak the need for any ad-
14 Drive
ditional drive components.Voltage
12 4.1. Calculation of Minimum Value of IGBT
external Gate Resistance RG’
10 Qgs Qgd
Output Voltage (V)

4.1.1 From the perspective of the optocoupler:

8 Q Gate Charge (nC)
The external gate resistance RG’ must be selected so the
UVLO HYS
peak output current IOL(PEAK) of the PS9552 does not ex- P
6
ceed its maximum rating. The minimum value of RG’ can
4 be approximated using the following equation:
14
V UVLO – (10.7 V) V UVLO+ (12.3 V) 1000nC
2 12 RG’ ≥ {(VCC – VEE) – VOL }/IOL(PEAK) (Equation 4.1)
500nC
4.8 µJ 100nC
10 VCC –VEE @is7.27
the difference between the power supply volt-
E SW (µJ)

0 5 10 15 20 8 ages of the PS9552. (When negative voltage is not used,

Power Supply Voltage V CC – V EE (V) 6 VEE = 0V)
4 
2
 AN 3007
14

12
VOL equals the low-level output voltage of the PS9552. Where:
10
The minimum value of the external gate resistance Qgs = the gate- source charge
Output Voltage (V)

8
RG’ is calculated based on the following conditions: Qgd = the gate-drain charge
IOL(PEAK) = 2.5 UVLO
A HYS Qg = the total gate charge at which VGS equals the peak
6
drive voltage VDR — or the charge that must be applied
VCC –VEE = 20 V
4 to the gate,
14
either to swing it by a given amount or to
VOL = 2 V … Voltage
V UVLO – (10.7 V)
drop at IOL = 2.5 A
V UVLO+ (12.3 V) achieve full switching.
2 NCcurves
Refer to 1 8 VCC
in Figure 4-2 VOL vs. IOL Characteristics. 12
UVLO The equation for the gate charge is:
From Equation LED4.1: Q =10C x V

Output Voltage (V)

0 ANODE
5 2 10 15 20 7 VO
Power Supply
RG’ ≥ Voltage
{(VCC –VVCCEE–)V–EESignal
V(V)
OL}/I OL(PEAK)
Output
Where Q is
8 the total charge
Processing Drive
Circuit Circuit
= (20
CATHODE 3 – 2)/2.5
PD 6 VO The relationship UVLO HYS
between gate capacitance, switching
6
= 7.2 W time, and the gate driver current is:
4
5
NC 4
Shield
5 VEE dQ/dt = C x dV/dt = IG
V UVLO – (10.7 V) V UVLO+ (12.3 V)
100° C Or the current
2 to be delivered to the gate is:
4 25° C
Line)
– 40° C IG = Qg / ts
0 5 10 15 20
3 Where ts is the switching time required by the system.
V OL (V)

Power Supply Voltage V CC – V EE (V)

Since a constant voltage drive is used, the relationship
2
between the peak value of the gate current IG and the
t
1
total gate resistance RG would be:
RG = VDR / IG 5
0.1 uF 100° C
Line)
0 0.5 1.0 1.5 2.0 2.5 Where RG is the sum of the driver’s output impedance,
+5V VCC = 15V 4 25° C
IOL (A) theDCexternal
+HV (P Line) gate resistance, and the series
– 40° C
resistance of
the gate itself, and VDR3 is the peak driver voltage.
Figure 4-2 VOL vs. IOL Characteristics at Temperature
V OL (V)

RG
AsThree
a result, to match an2 optocoupler to a MOSFET / IGBT
Phase
in Output
a particular application, the total gate resistance cal-
4.1.2 From the perspective of the MOSFET/IGBT culated for the MOSFET 1 / IGBT should be greater than
VEE = –5 V
Refer
VO to the gate charge curve provided in the MOSFET the external gate resistance required by the optocoupler.
or IGBT data sheet for your application. This data is re- –HV DC (N Line)
0 0.5 1.0 1.5 2.0 2.5
quired to calculate the value of total gate resistance. 4.2 Allowable Dissipation Verification
IOL (A)
Typically,
IO the gate charge curve will be similar to Figure and RG’ Adjustment for the PS9552
4-3 below: The total power dissipation PT of the PS9552 is the sum
of the power dissipation PE of the IRED on the input (pri-
mary) side plus the power dissipation PO of the light re-
VGS Gate Source Voltage (V)

Qg ceiving IC on the output (secondary) side.

PO = VO x IO
PT = PE + PO V(Equation
O
4.2)

VDR
Esw (Qg, Rg) = Esw (on) + Esw (off )
Peak
Drive
4.2.1 Power dissipation of IRED
Voltage The power dissipation
IO of the IRED can be found by using
the following equation:

Qgs Qgd PE = IF x VF x Duty Ratio (Equation 4.3)

Q Gate Charge (nC)

PO = VO x IO
Figure 4-3 Gate Charge vs. Gate Source Voltage Characteristics

Esw (Qg, Rg) = Esw (on) + Esw (off )

14
1000nC
12 500nC 
4.8 µJ 100nC
10
@ 7.27
 VGS Gate
Qgs Qgd
14 AN 3007
Q Gate Charge (nC)
12

10 Figure 4-5 Switching Loss per Cycle

4.2.2 Power Dissipation of the Light Receiving IC
Output Voltage (V)

14
8 The power dissipation PO of the light receiving IC can be 1000nC
calculated as follows: UVLO HYS 12 500nC
6 100nC
4.8 µJ
PO = PO(Circuit) + PO (Switching) (Equation 4.4) 10
@ 7.27

E SW (µJ)
4 8
VPO(Circuit) = Circuit powerVdissipation
UVLO – (10.7 V)
of the light receiving
UVLO+ (12.3 V)
2 IC (power dissipation by ICC.) 6

PO(Switching) = Power output of the light receiving IC 4

0 charging/discharging
5 10 gate15capacitance
20 (power dissipa- 2
tion by IO ).
Power Supply Voltage V CC – V EE (V)
0 10 20 30 40 50
(1) Circuit power dissipation of the light receiving IC: RG Gate Resistance (7)

PO (Circuit) = ICC x (VCC – VEE) (Equation 4.5)

5 (3) Power dissipation of the light receiving IC:
ICC = Circuit supply current
100° C of the light receiving IC.
From equations 4.4, 4.5 and 4.6, the power dissipation
(P Line) VCC – V4 EE = Difference25° C
between the power supply voltages
– 40° C of the light receiving IC is:
of the light receiving IC.
3 PO = PO (Circuit) + PO (Switching)
V OL (V)

ee (2) Output
2 power of the light receiving IC charging/dis- = ICC x (VCC –VEE ) + ESW (RG’, Qg) x fSW
ase
tput
charging IGBT gate capacitance.
(Equation 4.7)
PO1 (Switching) = ESW (RG’, Qg) x fSW (Equation 4.6)
ESW (RG’, Qg) = Unit power dissipation per cycle of IGBT
(N Line)
0 0.5 charge/discharge.
gate capacitance 1.0 1.5 2.0 2.5 4.2.3 Allowable dissipation verification
IOL4-5)
(Refer to Figures 4-4 and (A) and RG’ adjustment of the PS9552

fSW = Switching Frequency The power dissipation of the PS9552 is calculated using
RG’ = 7.2W, Duty Ratio (max) = 80%, Qg = 500nC,
f SW= 20kHz, IF (max) = 16mA, and TA = 85°C. From the
graph in Figure 4-5, ESW = 4.8µJ(@ RG’ = 7.2W).

VO
(1) The power dissipation PE at the input side can be cal-
culated from Equation 4.3:
PE = IF x VF x Duty Ratio
IO
= 16 mA x 2.1 V x 0.8 = 27 mW
(2) The power dissipation PO at the output side can be
calculated From Equation 4.7:
PO = ICC x (VCC –VEE ) + ESW (RG’, Qg) x fSW
PO = VO x IO
= (5mA x 20 V) + (4.8 µJ x 20 kHz)

Esw (Qg, Rg) = Esw (on) + Esw (off ) = 100 mW + 96 mW

= 196 mW
Figure 4-4 Power Dissipation Waveform
196mW is greater than the absolute maximum rating of
during switching of PS9552
178mW power dissipation at 85° C for the detector side
of the PS9552 (Figure 4-6). Therefore it’s NOT an allow-
able value. Circuit values MUST be changed to prevent
damage to the device in this operating condition.


 AN 3007

350

300
(4) Adjustment
300
of the Gate Resistance: RG’
225 mW
Detector Power Dissipation PC (mW)

The value of RG’ must be set so that the @power

+85° Cdissipa-

Total Power Dissipation PT (mW)

250 178 mW 250
@ +85° C tion of the PS9552 does not exceed the absolute maximum
200 rating of 200
allowable dissipation.
150 IGBT No.1 ON From Equation
150 4.4 ( With RG’ = 7.2W, see Data Sheet):
+HV DC (P Line)

100 Upper Arm

PO100
(Switching) = PO (max) – PO (Circuit)
PS9552 No. 1 X
50
= 178
50
mW – 100 mW
Output
= 78 mW
PS9552 No. 2 X 40 Lower Arm
0 20 60 80 100 120 From Equation
0 4.6:
20 40 60 80 100 120
–HV DC (N Line)
Ambient Temperature TA (°C)
IGBT No.2 ON
ESW (max) =Ambient Temperature TA (°C)
PO(Switching)/fSW

Figure 4-6 Detector Power Dissipation vs. Ambient Temperature = 78 mW/20 kHz
= 3.9 µJ
In making your calculations, note that the Input Power
From Figure 4-5, when Qg = 500nC, RG’ = 10.2W at 3.9µJ.
Dissipation, PE, is dependent on input driving condi-
tions. The Detector Power Dissipation, PO, is dependent
LED Q2 Light Receiving IC Selection of a suitable value for gate resistance RG’ is
on the power
TJE dissipation Tof
JD
the internal detector IC itself,
extremely important during design of the gate driving
as well as factors from the load being driven:
circuit as it has major impact on the performance of the
PO =Q1PO(Circuit) +QP
3 O (Switching) IGBTs. The smaller the RG’, the faster the switching speed
(3) Total Power Dissipation, PT, is the sum of PE + PO: for the IGBT input capacitance charge/discharge, and
the smaller the switching loss. However, a small RG’ can
PE + PO = PTaT
also result in large voltage fluctuation (dV/dt) and cur-
27mW + 196 mW = 223mW rent fluctuation (di/dt) during switching. Therefore, the
A PT of 223mW is less than the derated device total of gate resistance must be optimized per the IGBT’s technical
225mW at 85°C (Figure 4-7) — and this appears to be documents (as mentioned in section 4.1.2) and verified
an allowable figure. But even though the total may be in actual operation.
allowed, the Detector Power Dissipation PO component
of this total exceeds its allowed value, so the design’s
values will need to be adjusted. 5. PS9552 Peripheral Circuit
5.1 Layout
350
(1) Minimize the stray capacitance between the primary
300 225 mW and secondary sides (input-output) by designing the lay-
out so the pattern wiring of the primary and secondary
Total Power Dissipation PT (mW)

@ +85° C
250
sides are not contiguous on the PCB. The wiring should
200 also not cross on a multilayer board.

150 (2) Minimize the effect of transient noise on the PS9552

by separating the circuit pattern of the collector/emitter
100
of the IGBT and the DC lines (P and N lines) of the invert-
50 er circuit, as these often pass large amounts of current.
Provide as much separation as possible between the LED
drive circuit and the VCC and VO lines of the PS9552.
0 20 40 60 80 100 120

Ambient Temperature TA (°C) (3) Position the bypass capacitor (0.1µF or higher) be-
tween the VCC – VEE on the secondary (output) side of the
PS9552 so that its pins are as close as possible to the
Figure 4-7 Total Power Dissipation vs. Ambient Temperature VEE (pin 5) and the VCC (pin 8).


 AN 3007

5.2 IRED Drive Circuit Dead-time, TDEAD, should be set so that IGBT1 and IGBT2
Design the circuit so that the current IF and voltage VF are not on at the same time (Figure 6-3). A value greater
that are applied to the IRED fall within these recom- than the difference between the maximum total turn-off
mended ranges: time (tOFF Total max)IGBT
andNo.1
theON
minimum total turn-on time
+HV DC (P Line)
(tON Total min) of the PS9552 and IGBTs should be set.
PS9552 No. 1 Upper Arm PS9552 No. 1
Item Symbol MIN TYP MAX Unit tDEAD ≥ tOFF Total max – tON Total min
Input Voltage (OFF) VF (OFF) –2 — 0.8 V = (tPHL PS9552 + tON IGBTOutput
) max
Input Current (ON) IF (ON) 7 10 16 mA minus
PS9552 No. 2(tPLH PS9552 + tOFF IGBT
Lower Arm ) min PS9552 No. 2

Table 5-1 Recommended Operating Conditions for PS9552 IRED = (tPHL max – tPLH min PS9552)
–HV DC (N Line)
plus (tOFF max
IGBT –No.2
tONOFF
min IGBT )
For IRED OFF: To ensure the OFF state of the IRED when = PDD PS9552 + (tOFF max – tON min IGBT )
common-mode transient immunity is at low level output
(CML), a reverse bias should be applied to the IRED
within these recommended operating condition ranges If
t DEAD
(Table 5-1). PS9552 No. 1
t
LED
For IRED ON: To ensure the ON state when the common- If Optocoupler TJE
Input Signal
mode transient immunity is at high level output (CMH), PS9552 No. 2
t
IRED current should be set to the maximum value within Q1
these recommended operating condition ranges. IO
IGBT No. 1
6. Setting Dead-Time t
IO IGBT Output
The inverter control circuit provides output to drive its Current
IGBT No. 2
load by switching IGBT1 (Upper Arm) and IGBT2 (Lower t
Arm) alternately on and off as shown in Figure 6-1. If the
Figure 6-3 Dead-time (tDEAD)
dead-time is insufficient, IGBT1 and IGBT2 could both
switch on, causing a short-circuit current and breakdown
To simplify dead-time setting, the difference in transmis-
of the IGBTs as shown in Figure 6-2.
sion delay time (PDD) between the tPHL and tPLH of the
IGBT No.1 ON
PS9552 is regulated (±0.35µs—refer to the data sheet).
IGBT No.1 ON
+HV DC (P Line) This PDD value is based on+HVtPHL
DC (Pand
Line) tPLH measurements

PS9552 No. 1 Upper Arm taken at

PS9552 No.the
1 sameXtemperature
Upper Armand in the same mea- 350

surement
300
conditions. Therefore, in designing the board 300
Detector Power Dissipation PC (mW)

Output layout, make sure the ambient

Outputconditions are the same

Total Power Dissipation PT (mW)

PS9552 No. 2 Lower Arm for optocouplers
250
PS9552 No. 2 inXboth the upper
Lower Arm and lower arms. Set
178 mW 250
@ +85° C
the dead-time
200
based on thorough verification of the 200
–HV DC (N Line) –HV DC (N Line)
actual system, then add extra margin for safety.
IGBT No.2 OFF IGBT No.2 ON
150 150

100 100
Figure 6-1 Normal Operation of the Inverter Control Circuit
50 50
If IGBT No.1 ON
+HV DC (P Line)
t DEAD
PS9552 No. 1
Upper Arm t 0 20 40 60 80 100 120 0
PS9552 No. 1
If X Optocoupler
LED Q2 Light Receiving IC
TJE TJD
Input Signal Ambient Temperature TA (°C)
PS9552 No. 2 Output
t
PS9552 No. 2 X Lower Arm Q1 Q3

IO
–HV DC (N Line)
IGBT No. 1 IGBT No.2 ON
t Ta
IO IGBT Output
Figure 6-2 Short Circuit of the Inverter Control Circuit
Current
IGBT No. 2
t

 X
–HV DC (N Line)
IGBT No.2 ON

AN 3007

7. Calculating Junction Temperature TJE = (R11 x PE) + (R12 x PD) + TA

LED Q2 Light Receiving IC = (244°C/W x 27mW) + (136 °C/W x 178mW) + 85 °C
TJE TJD
= 116 °C

Q1 Q3
TJD = (R21 x PE) + (R22 x PD) +TA
= (136°C/W x 27mW) + ( 182°C/W x 178mW) + 85 °C
Ta = 121 °C
Figure 7-1 PS9552 Thermal Resistance Model Set junction temperatures TJE and TJD to values equal to
or lower than 125 °C.
Figure 7-1 shows the thermal resistance model of the
PS9552. It is modeled with two heat sources: the IRED
8. Recommended optocouplers for IGBT ratings
and light receiving IC.
TJE = IRED junction temperature The tables below list recommended optocouplers for 200
and 400VAC motors. These are provided as guidelines
TJD = Light receiving IC junction temperature
only, optocouplers should be selected based on actual
TA = Ambient temperature specifications of the IGBTs to be used.
350
q1 = Thermal resistance between the IRED
IGBT AC MOTOR
and the ambient temperature.
300 VCES IC Output Power Recommended
225 mW
q2 = Thermal resistance between the IRED (V) (A) (kW) Optocoupler
Total Power Dissipation PT (mW)

@ +85° C
250 and the light receiving IC. 15 0.4
q3 = Thermal resistance between the light
200 20 1.5
PS9301
receiving IC and the ambient temperature. 30 2.2 PS9401-2
150 PS9553
In this model, the junction temperatures of the IRED and 50 3.7
IO (Peak) = 0.6 A max
the 100
light receiving IC can be expressed as the follows: 75 7.5
600
100 11
50TJE = (R11 x PE) + (R12 x PD) + TA (Equation 7.1)
150 15 PS9552
TJD = (R21 x PE) + (R22 x PD) + TA (Equation 7.2) IO (Peak) = 2.5A max
200 22
0 20 40 60 80 100 120
Where: 300 30
Ambient Temperature TA (°C)
PE = Power dissipation of IRED 400 45 IGBT Gate Drive Optocoupler
plus current booster
PD = Power dissipation of light receiving IC 600 55

R11 = IRED and ambient temperature thermal Table 8-1 IGBT Gate Driving Optocouplers for 200 VAC Motors
resistance parameter (R11 = q1 || (q2 + q3))
R12, R21 = IRED and light receiving IC IGBT AC MOTOR

thermal resistance parameter VCES IC Output Power Recommended

(R12, R21 = (q1 x q3)/( q1 + q2 + q3)) (V) (A) (kW) Optocoupler

15 1.5
R22 = Light receiving IC-ambient temperature
20 2.2
thermal resistance parameter PS9301
30 3.7 PS9553
(R22 = q3 || (q1 + q2))
50 7.5 IO (Peak) = 0.6 A max

75 11
Thermal Resistance Parameters (°C/W) 1200
R11 R12 , R21 R22 100 15

150 22 PS9552
TYP 244 136 182
200 37 IO (Peak) = 2.5mA max

Table 7-1 Thermal Resistance Parameters for PS9552 300 55

For example, from equations 7.1 and 7.2, if PE = 27mW, 400 75 IGBT Gate Drive Optocoupler
plus current booster
Po = PD = 178 mW, and Ta = 85 °C: 600 110

Table 8-2 IGBT Gate Driving Optocouplers for 400 VAC Motors


 AN 3007

9. Conclusion
This application note describes the characteristics of and
the methods for using IGBT/MOSFET gate driving opto-
couplers. We hope this document will be helpful in devel-
oping your designs. Furthermore, we will be expanding
our lineup of gate driving optocouplers to include new
products which feature internal protection circuits and
support large-current IGBTs.

Information and data presented here is subject to change without notice. California
Eastern Laboratories assumes no responsibility for the use of any circuits described
herein and makes no representations or warranties, expressed or implied, that such 4590 Patrick Henry Drive, Santa Clara, CA 95054-1817
circuits are free from patent infringement. Tel. 408-919-2500 FAX 408-988-0279 www.cel.com

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