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International Conference and Workshop on Emerging Trends in Technology (ICWET 2011) – TCET, Mumbai, India

Wireless Data Assistance in Real time Environment using

DSP processor
D C Shah U D Dalal
Department of EXTC, Department of Electronics
Smt. Indira Gandhi college of Engineering, S.V.N.I.T,
Kopar Khairane, Navi Mumbai 400709. Surat, 395007
+91 99390610020 +91 9898057727

This paper presents a wireless solution for data acquisition
working in real time environment using DSP processor
TMS320F2812. The design presented gives multi edge benefits of
signal processing besides employing wireless medium for remote
transmission of acquired data in highly secured medium. Cypress
made Radio Frequency transceiver CYWUSB6935 using Direct
Sequence Spread Spectrum (DSSS) modulation interfaced with
DSP processor using Serial Peripheral Interface (SPI). The design
represents extended External Interface (XINTF) of the DSP
processor by means of programming CPLD XCR3256. It is a
solution for process industries where continuous monitoring of
diverse process parameters fritter away many man power hours.
The data is available to the monitoring computer on one press of
button without laying long cables in maladroit industry
environment. This leads towards automation and cost saving
solution for industries. It can be modified to handle very low
sampling rate creating database of long time as well as to the real
time alarm generation system. The design can be enhanced for Figure 1 System setup diagram
various applications like remote security system, RF counting of
inventory, traffic monitoring system, weather control system and through transducers simultaneously using Analog to Digital (ADC)
many more. input lines of the processor. The transmission could be query based
or situation based. The data can be transferred by wireless medium
Categories and Subject Descriptors using DSSS modulation over RF link between wireless modems
C.2.1 [Network Architecture and Design] : Wireless attached to the processors at both ends. The sampling rate of
communication channels is modifiable by software to accommodate high speed
variable and slowly varying system parameters which makes the
General Terms system to operate in progressively real time situations. The
acquired data could be stored in external non volatile RAM (NV-
Measurement, , Design, Experimentation, verification RAM) apart of 18K word internal flash memory of TMS320F2812
1. INTRODUCTION which is used for embedded programming of the processor. An
optional Complex Programmable Logic Device (CPLD) can be
TMS320F2812 is a very basic DSP processor made by Texas utilized for interfacing of numerous modules like key pads, LCD
Instrument is the heart of the design. System level set up can be display etc. to make the entire embedded system user friendly. The
separated as data acquisition and data monitoring part as shown in RF transceiver as specified to support range of 50 meters. Before
RF communication transceivers are required to be programmed in
figure 1. Data monitoring part can monitor up to sixteen physical priority over SPI.
process parameters like pressure, temperature, humidity etc.
The embedded programming of DSP processor is done Code
Composite Studio (CCS) utilizing fundamentals of C++
Permission to make digital or hard copies of all or part of this work for programming. This embedded programming comprises set up
personal or classroom use is granted without fee provided that copies are
values for various modules and peripherals with memory mapping
not made or distributed for profit or commercial advantage and that
copies bear this notice and the full citation on the first page. To copy and addressing. Testing of the program can be done by using
otherwise, or republish, to post on servers or to redistribute to lists, simulator/emulator and downloading is done using JTAG interface
requires prior specific permission and/or a fee. of the processor. Monitoring part generates query using executable
ICWET’11, February 25–26, 2011, Mumbai, Maharashtra, India. file generated using C programming on computer which is attached
Copyright © 2011 ACM 978-1-4503-0449-8/11/02…$10.00. to the DSP processor using Serial Communication Interface (SCI).

International Conference and Workshop on Emerging Trends in Technology (ICWET 2011) – TCET, Mumbai, India

provides hardware modification flexibility at External Interface

(XINTF) of the DSP processor.[3]
2. HARDWARE DESIGN DESCRIPTION The DS1258W 3.3V 128k x 16 Non volatile SRAM is a
2,097,152-bit, fully static, non volatile (NV) SRAM, organized as
131,072 words by 16 bits. The two nos. of such RAM storing
256K word is interfaced to the DSP processor. The entire design of
the various modules interfaced to the processor can be represented
by the figure 2. Downloading of complied C++ codes in DSP
processor is performed using JTAG (Joint Test Access Group)
tool. The CPLD can also be programmed by its specified JTAG
lines using JTAG tool. The entire design of the various modules
interfaced to the processor can be represented by the figure 2.


3.1 Functions of DSP Processor
(i) Reset Boot loader process: The GPIOF pins are configured
such that at reset the address accessed is the flash address 0x3F
7FF6. The branch instructions are programmed prior to reset to re-
Figure 2 Design of hardware cards direct code execution at the Flash memory location of 0x3D 8000.
* Optional for card II, ** Only for card II, ‡ Only for card I, (ii) Oscillator, PLL and Clock: The External crystal oscillator of
† For future expansion 10MHz , attached to the pins X1 / Xclkin and X2, is used for the
clock of peripherals of the DSP processor. The configuration is
Input path is of transducer to two stages of unity gain op amp done such a way that SYSCLKOUT is achieved as 50MHz. The
AD828 connected to ADC lines of the processor. These provides configuration registers are set to provide High and Low speed
isolation to the DSP processor and expansion in input voltage peripheral clocks to peripherals.
range with voltage divider used to get 3.3V maximum which is (iii) External Interface (XINTF): The External Interface of DSP
acceptable to the ADC line of the DSP processor. The salient processor is used to interface the external CPLD to the processor.
features like fast settling time of 45 ns to 0.1%, 0.1 dB flatness to The external interface consists of 19 address lines and 16 data
40 MHz, low differential gain low input offset voltage and lines. The nonvolatile RAMs are connected through this external
operation with single and dual power supply of range +5V to +15V interface for storage of the fault records. The address lines and data
[1] of AD828 makes it most suitable for the design. lines of the external interface are buffered by CPLD so that the
The TMS320F28x series has integrated peripherals specifically DSP processor can drive multiple external devices on the external
chosen for embedded control applications. These include various interface.
functional and peripheral modules like Event Managers (EV A/B), (iv) Interrupts: From the total 96 Interrupts available, In the
Multi Channel Buffered Serial Port (McBSP), Enhanced Controller application several PIE interrupts are enabled. The interrupt for
Area Network (eCAN), Serial Peripheral Interface (SPI), Serial generation of SOC of ADC module as well as SPI transmission
Communication Interface (SCI), 12 bit Analog to Digital and reception interrupts for wireless communication are utilized.
Conversion (ADC) modules, Watchdog Timers and General (v) 12 bit ADC lines: ADC is configured for sequential mode of
Purpose I/O lines (GPIO).[1] operation. Connect the input lines whose data are to be monitored
The CYWUSB6935 is a transceiver which uses DSSS Gaussian to the ADC line using analog input block. The monitored quantity
Frequency Shift Keying baseband radio operating in 2.4GHz ISM is digitalized and stored in respective ADC registers. This data is
band supports wireless communication up to 50 meters and more. sent to RAM memory location to avoid overwriting and to
This module uses Frequency Division and Code Division generate the record. The stored data can be monitored by the
Multiplexing. Forty-nine spreading codes selected for optimal remote monitoring part. Based on the difference in the successive
performance (Gold codes) are supported across 78 1-MHz samples the alarm can be generated to alert the local observers.
channels yielding a theoretical spectral capacity of 3822 channels (vi)Event Manager (EV): Event Manager A, GP timer1 is
[2]. The RF module in both the parts is needed to be programmed configured to generate SOC interrupt at the desired sampling rate.
for parameters such as baud rate, PN code selection, TX/ RX The ADC end-of-conversion interrupt will be used to prompt the
interrupts etc. through SPI of TMS320F2812. The RF module is CPU to copy the results of the ADC conversion into a RAM
responsible for the RF communication between fault acquisition memory.
and monitoring part in specified frame format. (vii) Serial Peripheral Interface (SPI): This interface is used
The XPLA3 Extended Programmable Logic Array family of interfacing of the RF module CYWUSB 6935 to the DSP
CPLDs is targeted for low power applications that include processor. The fault data stored in the nonvolatile RAM can be
portable, handheld, and power sensitive applications. The CPLD sent to the remote observer whenever query is received from
208-pin PQFP (164 user I/O pins) attached to the DSP processor monitoring part. In the case of alarm situation the alerting signal
is used for building up various logic and buffer circuits which can be transmitted to the remote monitoring personal.

International Conference and Workshop on Emerging Trends in Technology (ICWET 2011) – TCET, Mumbai, India

(vii) Serial Communication Interface (SCI): In the remote CYWUSB6935 has a fully synchronous SPI slave interface for
monitoring system computer is attached to the DSP processor connectivity to the application MCU. Configuration and byte
TMS320F2812 using SCI module. The computer can generate oriented data transfer can be performed. An interrupt is provided to
query for acquired data from the data acquisition part. In response trigger real time events. The SPI receives SCK from an application
to the query the acquisition part will send the acknowledgement to MCU on the SCK pin. Data from the application MCU is shifted in
the monitoring part prior to the data. The data sent to the on the MOSI pin. Data to the application MCU is shifted out on
monitoring part will be stored in a text file of the monitoring PC. the MISO pin. The active-low Slave Select (SS’) pin must be
3.2 The RF module CYWUSB6935 asserted to initiate a SPI transfer. The application MCU can initiate
a SPI data transfer via a multi-byte transaction.

Figure 4 SPI frame format

The first byte is the Command/Address byte, and the following

bytes are the data bytes. The SS signal should not be deasserted
between bytes. The SPI communications is as follows: (1)
Command Direction (bit 7) = “0” Enables SPI read transaction. A
“1” enables SPI write transactions (2) Command Increment (bit
6) = “1” Enables SPI auto address increment. When set, the
address field automatically increments at the end of each data byte
Figure 3 Block diagram of RF module CYWUSB6935 in a burst access, otherwise the same address is accessed (3) Six
bits of address (4) Eight bits of data. The SPI communications
Above figure 3 of RF modem shows internal diagram of interface has a burst mechanism, where the command byte can be
CYWUSB6935. The connection of the modem to the DSP followed by as many data bytes as desired. A burst transaction is
processor over SPI interface includes four lines MOSI, MOSI, SS’, terminated by deasserting the slave select (SS’ = 1). The four-wire
and SCK. The 2.4 GHz Radio is a single-conversion low- SPI communications interface of RF module is connected to the
Intermediate Frequency (low-IF) architecture with fully integrated respective SPI lines of the processor. The DSP processor acts as a
IF channels matched filters, Voltage Controlled Oscillator (VCO), master for all data transfer between the RF module and the
and synthesizer to achieve high performance in the presence of processor.
interference. An integrated Power Amplifier (PA) provides an
output power control range of 30 dB in seven steps. The 4.2 Wired communication : SCI
transmitter uses a DSP-based vector modulator to convert the 1-
MHz chips to an accurate GFSK carrier. The receiver uses a fully This SCI supports digital communication between the DSP
integrated Frequency Modulator (FM) detector with automatic data processor and the asynchronous peripherals that use the standard
slicer to demodulate the GFSK signal [2]. non-return-to-zero (NRZ) format. The F2812 device includes two
DSSS baseband digital spreader converts data to DSSS chips. An serial communications interface (SCI) modules. The SCI receiver
oversampled correlator performs despreading. The DSSS baseband and transmitter are double-buffered, and each has its own separate
cancels spurious noise and assembles properly correlated data enable and interrupt bits. Both can be operated independently or
bytes. CYWUSB6935 has a data Serializer / Deserializer simultaneously in the full-duplex mode. The data-word format
(SERDES), which provides byte-level framing of transmit and includes one start bit, data-word length programmable from one to
receive data. Bytes for transmission are loaded into the SERDES eight bits, optional even/odd/no parity bit and one or two stop bits.
and receive bytes are read from the SERDES via the SPI interface. To ensure data integrity, the SCI checks received data for break
The SERDES provides double buffering of transmit and receive detection, parity, overrun, and framing errors. The bit rate is
data. While one byte is being transmitted by the radio the next byte programmable to over 64K different speeds through a 16-bit baud-
can be written to the SERDES data register insuring there are no select register.
breaks in transmitted data. After a receive byte has been received it
is loaded into the SERDES data register and can be read at any 5. SOFTWARE ALGORITHMS
time until the next byte is received, at which time the old contents
of the SERDES data register will be overwritten. CYWUSB6935 5.1 Algorithm for data acquisition part
is powered from a 2.7V to 3.6V DC[2].
Step 1: Disable all the Interrupts. Clear All RAM and data
4. COMMUNICATION INTERFACES locations. Initialize system clock and configure registers of all the
functional modules of the DSP processor.
4.1 RF communication interface: SPI Step 2: For multichannel DAS split available memory into parts
for each channel,

International Conference and Workshop on Emerging Trends in Technology (ICWET 2011) – TCET, Mumbai, India

Step 3: Initialize PIE interrupt module for generation of Start of

Conversion (SOC) for ADC module at desired data rate. Copy 12
bit ADC results to the external RAM.
Step 4: Check if any query is generated from monitoring part. If
query is generated disable ADCSOC interrupt and send
acknowledgement to the remote monitor over RF link after
confirming the query.
Step 5: Initialize the pointer to the first memory location and start
sending byte to byte data over SPI interface.
Step 6: After transmission of desired number of data terminate RF
communication and enable ADCSOC interrupt.
5.2 Algorithm for data monitoring part
Step 1: Follow steps 1 as in the acquisition part. The data rate for
wired communication through SCI and RF communication over
Data transmission by bytes on RF link
SPI should be configured to be at the same data rates.
temp =data to be transmitted
Step 2: The monitoring PC should have a program to generate
temp1, temp2 = LSB and MSB of data
the query of fixed pattern over serial port using RS232 to the SCI
of the DSP processor.
Step 3: The processor will continuously look up for any query
form the SCI line and if query is received, it will immediately send
it to the SPI for transmission over RF link.
Step 4: After reception of acknowledgement of generated query
over RF link all the data received over SPI will be temporarily
stored at a memory location where it could be split in to LSB and
MSB for wired transmission over SCI.
Step 5: All the data received by the monitoring PC can be stored
to generate a text format database in the PC.


The designed system is verified to perform the desired operation of
fault monitoring and communication through wired and unwired
medium. Entire system can operate at 64 kbps flawlessly. The
numerous operations of the CPLD are also verified. The on
demand query based transmission and reception of data is achieved
perfectly and can be easily referenced in the text file of the
monitoring PC. This requires perfect match of baud rate and delays
for SPI and SCI module. The wired and unwired communication
can support the distances up to 3 to 5 Kms and up to 50 meters
respectively. Data transfer for eight channels and up to 256K word
is transmitted and received. The system can be extended to any
form of process variable like pressure, temperature etc. using
transducers at the input of analog input section. The CPLD
attached provide ease of modification of hardware at the External
Interface of the DSP processor. Additional devices like Real Time
Clock, LCD display, Key board can be attached for enhancement
of design. The use of Watch dog timer can be utilized for Real
Time mode in true sense. The acquired data can be applied through
various kind of filters and signal processing in real time. The
PWM generation of the used DSP processor gives brilliant results
for control operation for multi facet process industries.

Actual hardware photograph of Data acquisition/Monitoring

CPLD design utilization report (Generated by Xilinx)
Digitized acquired data stored in external RAM at memory
location 90000

International Conference and Workshop on Emerging Trends in Technology (ICWET 2011) – TCET, Mumbai, India

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