VIVEK SAKALESHPUR

9886122291
#184, 5th cross, 2nd Main
Ramanjaneya Nagar, Chikkalasandra
Bangalore – 560061

19 Years of Experience in Physical design implementation as a

Individual contributor, Subject matter expert and Technical lead.
4 years as a Software engineer.

Work Experience
• Altran technologies, Bangalore
Senor Technical Lead and Subject matter specialist
Dec 17 - Tilldate

• Eximius Design systems, Bangalore

Senior Technical lead
Jan 15 – Nov 17
• Synapse Design systems, Bangalore
Senior Technical Lead
Mar11 to Jan 15

• Qualcomm, Inc, Bangalore, India

Senior Design Engineer,
Nov 04 – Mar 11

• Spike Technologies, Bangalore, India

Senior Design Engineer
Nov03 – Nov-04

• Cadence Design Systems, Inc, Noida, India

Senior Consultant, Apr 03 – Nov 03

Signet Design Solutions, Inc, USA

Design Engineer, Apr 01 – June 02

• Tech Solv, Inc, USA

Design Engineer, Apr 99 – Apr 01
• Microcon International, Inc India
 Software Engineer, Mar 96 – Apr 99

Education:

B.E. in Electronics & Communication Engineering, Sep 96 Mysore University, India.

Skills:
Technical management of Physical implementation team of 25 members.
Subject matter expert
Individual contibutor
EDA tools:
• Cadence (Innovus, SOC Encounter, Silicon Ensemble, Voltage Storm)
• Synopsys (ICC2, ICC1, Primetime-SI, Primepower)
• Magma (Blast Chip, Blast Fusion, Talus).
• Mentor Graphics (Calibre)
• Atoptech (Aprissa)
• Apache (Redhawk)

Work Details:

Intel:
Contact thru Altran:
Project: Bigcore projects (Oct 18 to tilldate)
Responsible for supporting 40 partitions. Leading a team of 25 members.
Project lead for physical implementation team. Design challenges included. Debugging
and solutions for the team.
• 3 ghz freq design
• Latch based design.
• Multiple latch transparencies
• Timing Closure
• 14nm design
• Complex clock tree structure.
• Training the team on Intel flow and methodology.
• Individual responsibility of two partitions.

Contact thru Altran:

Project: Digital IPS at Intel (May 18 to Oct 18)
Responsible for supporting 2 subsystems. 10 partitions. Leading a team of 10 members.
Working as subject matter expert and Project lead for physical implementation team.
Design challenges included. Debugging and solutions for the team.
• 1 ghz freq design
 • Timing Closure
• 10nm design
• Custom routing of Signal nets.
• Complex clock tree structure.
• Training the team on Intel flow and methodology.

Intel:
Contact thru Altran:
Project: ICXD (Dec 17 to May 18)
Subject matter expert and Responsible for supporting 22 Mesh partitions and lead a team
of 10 members.
Worked as subject matter expert for physical implementation team. Design challenges
included.
• 5ghz freq design
• Timing Closure for latch based design
• 10nm design
• Custom routing of Signal nets.
• Custom placement of Standard cells.
• DRC/LVS. Fixing DP issues.
• EM Analysis & Fixing EM violations
• Managing the team

Intel:
Contact thru Eximius:
Project: ICXD (Oct 16 to Nov17)
Responsible for 8 Mesh partitions and lead a team of 5 members
Implemented large high performance blocks using & ICC tool suite. This involved achieving
Floor planning, timing closure, CTS using the latest synthesis based place and route technology.
Design challenges included
• High performance
• Timing Closure
• 10nm design
• DRC/LVS. Fixing DP issues.
• Power Analysis
• EM Analysis & Fixing EM violations

Broadcom:
Contract thru Eximius
Project : Vulcan 16nm (Oct 15 to Sep 16 )
Responsible for 2 CPU blocks and lead a team of three engineers
Implemented large high performance CPU blocks using Cadebce EDI tool suite. This
involved achieving Floor planning, timing closure, CTS using the latest synthesis based
place and route technology. Design challenges included
 • High performance
• Highly congested block.
• Timing Closure
• 16nm design
• Multipoint CTS
• Optimizing Source synchronous paths
• DRC/LVS
• Power Analysis
• EM Analysis & Fixing EM violations
• Crosstalk fixing

Avago:
Contract thru Eximius (Jan15 to Oct 15)
Project: Tornedo 28nm
Implemented 2 million gate design, using IC compiler tool suite. This design is 28nm design,
involved in complete STA of full chip. This involved achieving timing closure using the latest
synthesis based place and route technology. Design challenges included
• Placement challenges
• 28nm design
• Complicated CTS
• Serdes logic
• Desired insertion delay embedded memories and signed off with multiple corners
• DRC/LVS

Broadcom
Contract thru Synapse
Project : Tahitip 28nm (Oct 13 to Jan 15)
Implemented large high performance blocks using & Atoptech tool suite. This involved
achieving Floor planning, timing closure, CTS using the latest synthesis based place and
route technology. Design challenges included

• High performance
• Highly congested block.
• Timing Closure
• 28nm design
• DRC/LVS
• Power Analysis
• EM Analysis & Fixing EM violations
• Crosstalk fixing

Marvell Semiconductors
Contract thru Synapse
Project: Falcon 28nm (June 12 to Oct13)
Implemented 2 million gate design, using Cadence SOC encounter tool suite. This design is
45nm design, involved in complete STA of full chip. This involved achieving timing closure
using the latest synthesis based place and route technology. Design challenges included
• Placement challenges
• 45nm design
• Complicated CTS
• Serdes logic
• Desired insertion delay embedded memories and signed off with multiple corners
• DRC/LVS

Texas Instruments
Contract thru Synapse
Project : Hilda 45nm (Nov 11 to June 12)
Implemented large high performance blocks using & Magma tool suite. This involved
achieving Floor planning, timing closure, CTS using the latest synthesis based place and
route technology. Design challenges included

• High performance
• Highly congested block.
• Timing Closure
• 40nm design
• DRC/LVS
• Power Analysis
• EM Analysis & Fixing EM violations
• Crosstalk fixing.

Texas Instruments
Contract thru Synapse
Project: J1 48nm Mar11 to Nov 11

Implemented 2 million gate design, using Cadence SOC encounter tool suite. This design is
45nm design, involved in complete STA of full chip. This involved achieving timing closure
using the latest synthesis based place and route technology. Design challenges included
• Placement challenges
• 45nm design
• Complicated CTS
• Serdes logic
• Desired insertion delay embedded memories and signed off with multiple corners
• DRC/LVS
Qualcomm, Inc Project:
Waverider 28nm Jan 10 – Mar11
Implemented large high performance blocks using Cadence & Magma tool suite. This involved
achieving Floor planning, timing closure, CTS using the latest synthesis based place and route
technology. Design challenges included
• High performance
• Aggressive clock skew
• 28nm design
• DRC/LVS
• Split grid methodology
• Power Analysis
• EM Analysis & Fixing EM violations
• Cross talk analysis & Fixing

Qualcomm, Inc Project :

Phantom 45nm Jan 09 - Jan 10

Implemented 5 million gate design, using Cadence & Magma tool suite. This design is 65nm
design, involved in complete STA of full chip. This involved achieving timing closure using the
latest synthesis based place and route technology. Design challenges included
• Placement challenges
• 45nm design
• Complicated CTS
• Split grid me
• Desired insertion delay embedded memories and signed off with multiple corners
• DRC/LVS

Qualcomm, Inc Project :

Blackbird 45nm Jan 08 – Jan 09

Implemented large high performance blocks using Cadence & Magma tool suite. This involved
achieving Floor planning, timing closure, CTS using the latest synthesis based place and route
technology. Design challenges included
• High performance
• Aggressive clock skew
• 45nm design
• DRC/LVS
• Split grid methodology
• Power Analysis
• EM Analysis & Fixing EM violations
 • Cross talk analysis & Fixing

Project : Mustang 45nm Apr07 – Jan08

Implemented 5 million gate design, using Cadence & Magma tool suite. This design is 65nm
design, involved in complete STA of full chip. This involved achieving timing closure using the
latest synthesis based place and route technology. Design challenges included
• Placement challenges
• Complicated CTS
• Split grid methodology
• Desired insertion delay embedded memories and signed off with multiple corners
• DRC/LVS

Project : Koel 65nm Apr06 – Apr07

Implemented 10 million gate design, using Cadence & Magma tool suite. This involved
achieving timing closure using the latest synthesis based place and route technology. Design
challenges included
• High performance
• Aggressive clock skew
• Desired insertion delay embedded memories and signed off with multiple corners
DRC/LVS

QualComm, Inc Sep05 – Apr06

Project : Raven 65nm

Implemented 5 million gate design, using PC/Astro tool suite. This design is 65nm design,
involved in complete STA of full chip. This involved achieving timing closure using the latest
synthesis based place and route technology. Design challenges included
• Placement challenges
• Complicated CTS
• Desired insertion delay embedded memories and signed off with multiple corners
• DRC/LVS

Project : Raven 90nm Nov -04 – Sep05

Implemented large high performance blocks using Cadence & Avanti tool suite. This involved
achieving Floor planning, timing closure, CTS using the latest synthesis based place and route
technology. Design challenges included
• High performance
• Aggressive clock skew
• DRC/LVS
• Power Analysis
• EM Analysis & Fixing EM violations
 • Cross talk analysis & Fixing

Spike Technologies, Nov03 – Nov-04

Projects: Tarang & Trinity 130nm
Client: Texas Instruments, Bangalore

Implemented 1 million gate design, using Magma tool suite. This involved achieving timing
closure using the latest synthesis based place and route technology. Design challenges included
• High performance
• Aggressive clock skew
• Desired insertion delay embedded memories and signed off with multiple corners
DRC/LVS

Cadence Design Systems, Inc Apr 03 – Nov 03

Project: Neptune-ULS 180nm
Client: Motorola, Inc
Implemented large high performance (up to 300 Mhz) blocks using Cadence tool suite. This
involved achieving timing closure using the latest synthesis based place and route technology.
Design challenges included
• High performance
• Aggressive clock skew
• Desired insertion delay embedded memories and signed off with multiple corners
• DRC/LVS

Signet Design Solutions, Inc, USA Apr 01 – June 02

Projects: Black Water 180nm
Client: Texas Instruments, Dallas, TX USA

Implemented ten blocks using Magma tool suite using the timing driven place and route. This
involved achieving timing closure in a single pass and achieving the desired clock skew and
insertion delay requirements. Single pass timing closure involved the following steps
• Pre-layout timing analysis using the right wire load models.
• Placing the standard cells and doing timing analysis using ideal conditions.
• Insertion of the clock tree, measuring the skew and insertion delay.

• Routing the block and extracting the parasitics and doing a final timing analysis using the
actual parasitics
• Running DRC/LVS.

Projects: Timing driven place and route.

Client: Motorola, Austin, TX USA

Implemented large (200K – 300K moveable objects), high performance (up to 300 Mhz) blocks
using Magma tool suite. This involved achieving timing closure using the latest synthesis based
place and route technology. Design challenges included
• High performance
 • Aggressive clock skew
• Desired insertion delay embedded memories and signed off with multiple corners
• DRC/LVS

Tech Solv, Inc Apr 99 – Apr 01

Projects: Timing driven place and route
Client: Signet Design Solutions, Inc TX USA
Implemented three blocks using Cadence tool suite. This involved achieving timing closure in a
single pass and achieving the desired clock skew and insertion delay requirements. Single pass
timing closure involved the following steps.pre-layout timing analysis using the right wire load
models.
• Placing the standard cells and doing timing analysis using ideal conditions.
• Insertion of the clock tree, measuring the skew and insertion delay.
• Routing the block and extracting the parasitics and doing a final timing analysis using the
actual parasitics- running DRV/LCS.

Microcon International, Inc India Mar 96 – Apr 99

Project: Bar code generation and decoding unit.
Client: Microcon International, Inc. Involved in the generation of Bar code using C language.
The Bar code could be read on the address field of the Microprocessor(8085).

Project: Optical fibre communication

The objective of this project was to develop a communication between telephone lines using
optical fibre. Optical fibre has a great advantages compared to other communication media.

Project: Object Simulator System

The objective of the system is to develop Simulation for a vehicle. Involved in the development
and maintenance of a project. OPENGL was used to create the objects in three dimensions.
OPENGL involves the concepts of complex 3-D objects. The object can be moved vertically and
horizontally.

Project: Heart Surgery Simulation System

The objective of the system was to develop Simulation system for Heart Surgery. It is the
interactive simulation that would be helpful for the surgeons to perform vascular thoracic
Surgery. The objects were created using the components of OpenGL. Involved in the
development of GUI.