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V200R001C02
Hardware Description
Issue 03
Date 2012-07-23
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Notice
The purchased products, services and features are stipulated by the contract made between Huawei and the
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Email: support@huawei.com
Related Version
The following table lists the product version related to this document.
Intended Audience
This document describes the equipment structure, chassis structure, and board classification.
This document also describes each board of these classes in details.
This document helps you get the detailed information about the equipment hardware.
Symbol Conventions
Symbol Description
Symbol Description
TIP Indicates a tip that may help you solve a problem or save
time.
Command Conventions
Convention Description
GUI Conventions
Convention Description
Change History
Updates between document issues are cumulative. Therefore, the latest document issue contains
all updates made in previous issues.
Contents
6 Filler Panel....................................................................................................................................82
6.1 Functions and Features.....................................................................................................................................83
6.2 Appearance and Valid Slots.............................................................................................................................83
10 Safety Labels.............................................................................................................................112
11 Indicators...................................................................................................................................114
12 Power Consumption and Weight.........................................................................................120
13 Interface Specifications..........................................................................................................122
13.1 Technical Specifications of the GE and FE Optical Interfaces....................................................................123
13.2 Technical Specifications of FE and GE Electrical Interfaces.......................................................................124
1 Overview
The ATN series are case-shaped products used for multi-service access on the edge of the
Metropolitan Area Network (MAN). The ATN models include the ATN 910 ATN 910 and ATN
950B. The ATN series, together with the CX600 series, can be used to construct end-to-end
routed MANs oriented towards Fixed-Mobile Convergence (FMC).
Taking the challenges faced by carriers with respect to resources, cost, and services at the access
layer during the evolvement of mobile networks, the ATN series, which adhere to Huawei's
"Any Media" conception, provide sustainable IP RAN solutions to 2G, 3G, and Long Term
Evolution (LTE) applications.
1.1 Appearance of the Device
ATN 950B is case-shaped for easy deployment.
1.2 Slot Allocation
This section describes the slot allocation of the ATN 950B.
1.3 Boards and Valid Slots
Boards are the key hardware components of the equipment. This section describes the boards
supported by the ATN 950B and their valid slots.
1.4 System Architecture
Boards for the ATN 950B are used together to provide various functions for the equipment.
1.5 Technical Specifications
The dimensions of the ATN 950B are 442 mm (width) x 220 mm (depth) x 2 U (height, 1 U =
44.45 mm).
The ATN 950B can be installed indoors or outdoors. The installation must satisfy the requirement
of running environment for equipment. To better satisfy the requirement, you can install the
equipment in an IMB network cabinet or an APM30H outdoor cabinet. Use the EPS30-4815AF
external AC power supply system to provide power to the IMB network box or outdoor cabinet.
Table 1-1 Boards supported by the ATN 950B and their valid slots
Board Name Board Description Valid Slot
Table 1-2 describes priorities of slots where boards supported by the ATN 950B can be inserted.
NOTE
l Boards using rigid cables such as E1 cables are preferred to be inserted in slots 4 and 6. Boards using
flexible cables such as optical fibers are preferred to be inserted in slots 3 and 5.
l To facilitate cabling deployment, do not insert the E1 board and the EM8T, EM8F, EM4T, or EM4F
board to the two slots at the same layer.
1 2 3 4
FE/GE
EM4T/EM4F
FE/GE EM4T/EM4F FE/GE
EM8T/EM8F Service processing
10GE and forwarding FE/GE
EX1 EM8T/EM8F
module
E1
ML1/ML1A/ 10GE
EX1
ML1B
E1
MD1A/MD1B
Clock module
CXP
NOTE
Technical Description
Specifications
Dimensions (width x 442 mm x 220 mm x 2U (17.40 in. x 8.66 in. x 2U), 1U=44.45mm
depth x height) (1.75 in.)
Technical Description
Specifications
Environment Requirements
Item Description
Running 5% to 95%
relative
humidity
Running ≤ 4000 m (13123.2 ft) [If the altitude is lower than 1800 m (5905.44 ft), the
altitude equipment works normally. If the altitude is between 1800 m and 4000 m
(3280.8 ft and 13123.2 ft), the equipment working temperature should be 1 ºC
(1.8°F) decreased with every 220 m (721.78 ft) increased in the altitude.]
NOTE
l When the equipment is installed in a network cabinet, the temperature at the air intake vent of the
network cabinet must be within the range of -20 °C to 50 °C (-4°F to 122°F). For details on the
requirements for network cabinets, see the Installation Guide.
l When the equipment is installed in an APM30 outdoor cabinet, the temperature at the air intake vent
of the outdoor cabinet must be within the range of -40 °C to 50 °C (-40°F to 122°F). For details on the
requirements for outdoor cabinet, see the Installation Guide.
l If the equipment is installed in the cabinet, the effect of radiation can be ignored. If the equipment is
installed outdoors, proper protection should be provided for the equipment against the radiation.
l The temperature and relative humidity are measured at the place 1.5 m (4.92 feet) above floor and 0.4
m (1.31 feet) to the front cabinet without any front or rear protection panel.
Reliability Specifications
Item Description
MTTR 2 hours
System Configurations
Item Description
The TND1PIU inputs -48 V DC power to the ATN 950B, or an EPS30-4815AF external AC
power supply system inputs 220 V AC power, and converts the AC power to the DC power, and
then outputs the DC power to the ATN 950B. Both DC and AC power supplies support 1+1 hot
backup.
PIU PIC
-48V/-60V
12V
Figure 2-2 shows the AC power supply structure. The EPS30-4815AF converts external AC
power supplies into DC power supplies and provides power supplies to the ATN 950B.
PIU PIC
EPS30-4815AF
-48V/-60V
12V
220V AC
2.2.1 Overview
The TND1PIU (PIU for short) is a power interface board. The function version of the PIU is
TND1. The PIU is housed in slot 9 or slot 10.
Power access Each of the two PIU accesses one -48 V DC (or -60 V DC) power
supply for the equipment.
Power protection The PIU protects the power supply against overcurrent and short
circuit. In this way, the overcurrent is prevented from shocking
board and components on it.
Surge protection The PIU protects the equipment against lightning and reports an
alarm if the protection fails.
Power backup Two PIU boards can achieve 1+1 hot backup. One PIU is capable
of supplying power for the entire chassis.
Figure 2-3 Block diagram for the working principle of the PIU
Backplane
-48 V/-60 V Communication unit
module Each board
Board in-position
signals
Slot ID module CXP
Slot ID signals
Board in-position module CXP
Slot ID Module
This module reports the slot ID information to the AND1CXPA/AND1CXPB.
Indicators
The following indicator is present on the front panel of the PIU.
PWR, green, which indicates the power supply status. When PWR is on and green, it indicates
that power is accessed.
For details on indications of indicators, see 11 Indicators.
Interfaces
The PIU accesses one power supply. Table 2-2 lists the types of the interfaces on the PIU and
their respective usage. For cable corresponding to the interfaces, see 9.1 Power Supply Cables
and Grounding Cables.
Label
Operation warning label: indicates the following precaution, which should be taken for removal
or insertion of the PIU board.
CAUTION
Multiple power supplies are accessed for the equipment. When powering off the equipment,
make sure that these power supplies are disabled.
Do not remove or insert the board with power on.
Structure
Figure 2-5 shows the appearance of the EPS30-4815AF and Table 2-4 lists the components of
the EPS30-4815AF.
CAUTION
The interface on the monitoring module is reserved. Do not use the interface on the monitoring
module; otherwise, the EPS30-4815AF will be reset or damaged.
Component Description
Monitoring module Monitors the EPS30-4815AF and storage batteries. Two RS232/
RS485 communication interfaces and one DB50 interface are
reserved on the monitoring module.
AC/DC power distribution Provides an interface for inputting AC power, two load
frame interfaces, and an interface for connecting to the storage
batteries, and the fuses that can be replaced.
Functions
Functions of the EPS30-4815AF are as follows:
l Provides an interface for inputting AC power to provide 220 V AC power to the equipment.
l Provides two hot-pluggable rectifier modules to convert AC power to DC power. The two
rectifier modules work at the same time in load-sharing mode and they are hot backups for
each other.
The EPS30-4815AF is configured with one or two rectifier modules. When one rectifier
module is configured, the maximum output current is 15 A; when two rectifier modules
are configured, the maximum output current is 30 A.
NOTE
A filler panel must be inserted into an empty slot intended for a rectifier module.
l Reserves an active and a standby RS232/RS485 communication interfaces for extended
real-time communication with the equipment in future, and a DB50 interface for
implementing the extended monitoring function in future.
l Provides two load interfaces for outputting -53.5 V DC power to two PIUs, which provide
power to the ATN 950B.
l Provides two load control fuses, that is, FU-1 with a fuse capacity of 10 A and FU-2 with
a fuse capacity of 20 A. These fuses enable/disable output of the load and provide overload
and short-circuit protection for the load.
l Provides one interface for connecting to a group of storage batteries. When working
normally, the EPS30-4815AF is charging the storage batteries. When input of the 220 V
AC power stops, the storage batteries provide power to the ATN 950B. This ensures
uninterrupted power supply to the ATN 950B.
Figure 2-6 shows the appearance of a storage battery and Figure 2-7 shows a storage
battery tray with storage batteries.
l Provides a storage battery protection fuse, that is, FU-3 with a fuse capacity of 20 A. This
fuse enables/disables the storage batteries and provides overload and short-circuit
protection for the storage batteries.
Tray
Indicators
Indicators for the rectifier and monitoring modules are present on the front panel of the
EPS30-4815AF. Table 2-5 and Table 2-6 list the indications of indicators for the rectifier and
monitoring modules respectively.
Note 1: When a severe fault occurs, the indicator (red) is on and the indicators (yellow and green) are off. The
indicators (yellow and green) are on only when the indicator (red) is off.
Note 2: The indicator (yellow) is always on when communication on a rectifier module is interrupted, a rectifier
module is overheated or endures overcurrent or undercurrent, or a rectifier module is disabled.
Interfaces
Table 2-7 lists types and usage of the interfaces on the front panel of the EPS30-4815AF.
BATT 1 - Interface for connecting to the The pins marked with + and - are
storage batteries connected to the 48V+ and 48V-
poles of the cable connector
respectively.
Table 2-8 lists the relationships of the
load output interfaces, interface for
connecting to the storage batteries,
and fuses.
Table 2-8 Relationships of the load output interfaces, interface for connecting to the storage
batteries, and fuses
DIP Switch
There is a DIP switch on the monitoring module of the EPS30-4815AF. Figure 2-9 shows the
default setting and location of the DIP switch.
CAUTION
Do not change the default setting of the DIP switch. Otherwise, the EPS30-4815AF is affected.
The DIP switch indicates eight bits in binary format (on: 1; off: 0). The default value of the eight
bits is 00000100. The functions of the eight bits are as follows:
l The first five bits indicate the local and remote power addresses. Bit 5 is the highest bit and
bit 1 is the lowest bit.
l Bit 6 sets the baud rate of communication between the monitoring module and equipment.
When bit 6 is 1, the baud rate is 9600 bit/s; when bit 6 is 0, the baud rate is 19200 bit/s.
l Bits 7 and 8 are reserved.
Maximum input 10 A
current
Frequency 50/60 Hz
Capacity 40 Ah
Number of 4
batteries
The heat dissipation system is responsible for the heat dissipation of the entire device. Heat
generated by the boards is dissipated through the heat dissipation system. In this manner, the
temperatures of the components on the boards are controlled within a normal range, enabling
the boards to work stably.
3.2.1 Overview
The AND1FAN (FAN for short) is an FAN board. The function version of the FAN is AND1.
The FAN is housed in slot 11.
Figure 3-2 shows the block diagram for the working principle of the FAN.
Figure 3-2 Block diagram for the working principle of the AND1FAN
Fans x 6
12 V
12 V
12 V
CXP
Start-delay Combiner
Filter module
CXP
12 V Combiner/
12 V
soft-start module
12 V power shut signals
Communication unit
module Inter-board communication bus
CXP
Start-delay/Combiner Module
This module provides start delay to the combined two 12 V power supplies and protecting fans
against overcurrent.
Filter Module
This module filters the LC low frequency to enhance the EMC feature of the system.
Indicators
The following indicators are present on the front panel of the FAN:
l AND1FAN indicator, red or green, which indicates status of fans.
l CRIT indicator, red, which indicates critical alarms.
l MAJ indicator, orange, which indicates major alarms.
l MIN indicator, yellow, which indicates minor alarms.
The CRIT, MAJ, and MIN indicators on the front panel of the AND1FAN indicate the current
alarm severity of the subrack.
For details on indications of indicators, see 11 Indicators.
Handle
The handle is used for pushing the FAN into or pulling the FAN out of the chassis during board
replacement.
Label
The following labels are present on the front panel of the FAN:
l ESD protection label, which indicates that the equipment is static-sensitive.
l Fan warning label, which says that do not touch the fan leaves before the fan stops rotating.
4.1 Overview
The AND1CXPA/AND1CXPB (CXPA/CXPB for short) is a control, cross-connect, and
protocol processing board. The function version of the CXPA/CXPB is AND1. The CXPA/
CXPB is housed in slot 7 or slot 8.
4.2 Functions and Features
The AND1CXPA/AND1CXPB controls the system, grooms services, processes the clock, and
provides auxiliary interfaces.
4.3 Working Principle and Signal Flow
The AND1CXPA/AND1CXPB mainly consists of the service processing and grooming module,
system control module, clock processing module, auxiliary interface module, and power supply
module.
4.4 Front Panel
On the front panel of the AND1CXPB, there are indicators, buttons, switch for the ejector lever,
and interfaces.
4.5 CF Card and DIP Switch
A board has a set of DIP switches and a hot-swappable CF card.
4.6 Technical Specifications
The technical specifications of the AND1CXPA/AND1CXPB include board dimensions,
weight, and power consumption.
4.1 Overview
The AND1CXPA/AND1CXPB (CXPA/CXPB for short) is a control, cross-connect, and
protocol processing board. The function version of the CXPA/CXPB is AND1. The CXPA/
CXPB is housed in slot 7 or slot 8.
Auxiliary interface function Provides one 10 Mbit/s or 100 Mbit/s auto-sensing Ethernet
NM interface or Console interface for communication with
the NMS.
Tact switches Provides two tact switches. When you rotate the ejector levers
to remove the board, the two tact switches are triggered to
start the active/standby protection switching.
NOTE
When you rotate only one ejector lever, the protection switching is not triggered. The protection switching
is triggered only when you rotate the two ejector levers.
Management
bus
Service signals
PICs
Under-voltage/over- Service processing and
Service
voltage detection bus grooming module
communication bus
The other CXP
-48V/-60V System
power supply
-48V/-60V System
Power supply power supply
module 12V
FAN
3.3V
Interface cards
l The CPU control unit works with the logic control unit to detects alarms and hardware
faults, control boards, process overhead, and manage the equipment.
l The logic control unit provides interfaces through which the CPU control unit connects to
other chips on the board. The logic control unit specifies the working states of chips,
initializes chips, and operates the register. In addition, the logic control unit achieves log
control on active/standby switching, monitors the working state of the board, and detects
the states of other boards.
l Provides working clock signals for the key chips on the AND1CXPA/AND1CXPB.
l Supports the physical-layer clock synchronization, and provides system clock signals for
each boards.
l Processes the IEEE 1588V2 protocol to achieve clock/time synchronization.
l Supports the 1588 ACR clock.
l Supports the NTP clock.
Indicator
The following indicators are present on the front panel of the AND1CXPB:
l STAT indicator, red, green, or orange, which indicates the working status
l PROG indicator, red or green, which indicates the running status of the program
l SYNC indicator, red or green, which indicates the clock synchronization status
l ACTX indicator, green, which indicates the cross-connection or clock active/standby status
l ACTC indicator, green, which indicates the active/standby system control board
For details on meanings of indicators, see 11 Indicators.
Button
The following buttons are present on the front panel of the AND1CXPB:
l CF RCV button, which is reserved for later use.
l RRST button, which is used for reset on the board. When you press the RST button and
then release it, the board is reset.
l LAMP button, which is used to test the indicators. When you press the LAMP button, all
the board indicators on the NE are on.
Interface
Table 4-2 lists the types and usage of the interfaces on the AND1CXPB.
7 Unspecified
87654321 3 Unspecified
6 Unspecified
7 Unspecified
8 Unspecified
1 Unspecified Unspecified
2 Unspecified Unspecified
87654321 3 Negative input for the 1pps Negative output for the 1pps
signal signal
(RS422 level) (RS422 level)
6 Positive input for the 1pps Positive output for the 1pps
signal signal
(RS422 level) (RS422 level)
2 Grounding end
5 Grounding end
6 Grounding end
ON DIP
CF Card
DIP Switch
CF Card
The size of the CF card on AND1CXPA/AND1CXPB is 512 MB. The CF card is used to backup
data and load packages.
DIP Switch
You can use the DIP switches to delete the configuration file loaded on the device.
Set DIP switches on AND1CXPA/AND1CXPB to 1, 1, 0, and 1. During startup, the device
deletes the loaded configuration file based on the DIF switch status.
CAUTION
l This operation should be executed with caution. Use it under the guidance of technical
personnel.
l After the configuration file is deleted, reset the DIF switches to 0, 0, 0, and 0. In this way,
you do not need to delete the configuration file at each startup.
l The numeral indicates 1, and the letter indicates 0.
l The device password is deleted when the configuration file is deleted.
This topic describes the PIC cards that can be used by the ATN 950B.
5.1.1 Overview
The AND1EM4T (EM4T for short) is a four channels FE/GE adaptive electrical interface board.
The function version of the EM4T is AND1. The AND1EM4T is housed in any of slots 1 to 4.
Figure 5-1 shows the block diagram for the functions of the AND1EM4T.
Management bus
Management bus Clock signals
Transmit Direction
The service packets from AND1CXPA/AND1CXPB are sent to the service processing module
through the backplane-side interface of the AND1EM4T. The service processing module
identifies the destination interfaces for the packets, and buffers and schedules the packets. Then,
the service processing module sends the processed packets to the service access module, where
coding/decoding and serial/parallel conversion are performed. Finally, the service access module
outputs the packets through the GE/FE interfaces on the front panel.
Receive Direction
The GE/FE interfaces on the front panel receive GE/FE service signals. Then, the service access
module performs serial/parallel conversion and coding/decoding on the services, and then sends
the services to the service processing module. The service processing module buffers the service
packets, schedules the packets, and finally outputs the packets through the backplane-side
interface.
l In the receive direction, this module receives the GE/FE services from the interfaces on the
front panel, performs serial/parallel conversion and coding/decoding, and then sends the
services to the service processing module. .
l In the transmit direction, this module receives the service packets from the service
processing module, performs coding/decoding, and serial/parallel conversion on the
packets, and then outputs the packets through the GE/FE interfaces on the front panel
l This module extracts the synchronous Ethernet clock.
l In the receive direction, this module receives and buffers the service packets from the
interface conversion module. Then, this module schedules packets from different
interfaces. Finally, this module outputs the packets through the backplane-side interface.
l In the transmit direction, this module receives service packets from the AND1CXPA/
AND1CXPB, identifies the destination interfaces of the packets, and buffers and schedules
the packets based on the access capability of the EM4T and the access bandwidth setting
at each interface. Finally, this module outputs the packets to the service access module.
l This module extracts and inserts IEEE 1588 V2 packets.
Management Module
This module is used with the CXP to manage and control each module on the EM4T.
Clock Module
This module performs the following functions:
l Provides the working clock for each module on the EM4T.
l Supports the synchronous Ethernet and SSM protocols.
l Supports the IEEE 1588 V2 protocol.
l Supports the 1588 ACR clock.
Indicator
The following indicators are present on the front panel of the AND1EM4T:
l STAT indicator, red, green, or orange, which indicates the working status
l LINK indicator, green, which indicates the connection status of the port
l ACT indicator, yellow, which indicates the data transceiving status of the port
NOTE
.Above each service interface, there is a service port connection status indicator (LINK) and a service port
transmit/receive status indicator (ACT).
Interface
Table 5-2 lists the types and usage of the interfaces on the AND1EM4T.
Interface Specifications
Table 5-4 lists the specifications of the electrical interfaces on the AND1EM4T board.
Item Specification
Electrical signal interface rate Supports interface rates at 100 Mbit/s and
1000 Mbit/s.
Physical Specifications
Board dimensions (mm): 22.86 (H) x 225.75 (D) x 193.80 (W)
5.2.1 Overview
The AND1EM8T (EM8T for short) is an eight channels FE/GE adaptive electrical interface
board. The function version of the EM8T is AND1. The AND1EM8T is housed in any of slots
1 to 2.
Management bus
Management bus Clock signals
Transmit Direction
The service packets from AND1CXPA/AND1CXPB are sent to the service processing module
through the backplane-side interface of the AND1EM8T. The service processing module
identifies the destination interfaces for the packets, and buffers and schedules the packets. Then,
the service processing module sends the processed packets to the service access module, where
coding/decoding and serial/parallel conversion are performed. Finally, the service access module
outputs the packets through the GE/FE interfaces on the front panel.
Receive Direction
The GE/FE interfaces on the front panel receive GE/FE service signals. Then, the service access
module performs serial/parallel conversion and coding/decoding on the services, and then sends
the services to the service processing module. The service processing module buffers the service
packets, schedules the packets, and finally outputs the packets through the backplane-side
interface.
l In the receive direction, this module receives the GE/FE services from the interfaces on the
front panel, performs serial/parallel conversion and coding/decoding, and then sends the
services to the service processing module. .
l In the transmit direction, this module receives the service packets from the service
processing module, performs coding/decoding, and serial/parallel conversion on the
packets, and then outputs the packets through the GE/FE interfaces on the front panel
l This module extracts the synchronous Ethernet clock.
l In the receive direction, this module receives and buffers the service packets from the
interface conversion module. Then, this module schedules packets from different
interfaces. Finally, this module outputs the packets through the backplane-side interface.
l In the transmit direction, this module receives service packets from the AND1CXPA/
AND1CXPB, identifies the destination interfaces of the packets, and buffers and schedules
the packets based on the access capability of the EM8T and the access bandwidth setting
at each interface. Finally, this module outputs the packets to the service access module.
l This module extracts and inserts IEEE 1588 V2 packets.
Management Module
This module is used with the CXP to manage and control each module on the EM8T.
Clock Module
This module performs the following functions:
l 3.3 V
l 3.0 V
l 2.5 V
l 1.8 V
l 1.2 V
Indicator
The following indicators are present on the front panel of the AND1EM8T:
l STAT indicator, red, green, or orange, which indicates the working status
l LINK indicator, green, which indicates the connection status of the port
l ACT indicator, yellow, which indicates the data transceiving status of the port
NOTE
Above each service interface, there is a service port connection status indicator (LINK) and a service port
transmit/receive status indicator (ACT).
Interface
Table 5-6 lists the types and usage of the interfaces on the AND1EM8T.
Interface Specifications
Table 5-8 lists the specifications of the electrical interfaces on the AND1EM8T board.
Item Specification
Electrical signal interface rate Supports interface rates at 100 Mbit/s and
1000 Mbit/s.
Physical Specifications
Board dimensions (mm): 22.86 (H) x 225.75 (D) x 193.80 (W)
5.3.1 Overview
The AND1EM4F (EM4F for short) is a four channels FE/GE optical interface board. The
function version of the EM4F is AND1. The AND1EM4F is housed in any of slots 1 to 4.
Management bus
Management bus Clock signals
Transmit Direction
The service packets from AND1CXPA/AND1CXPB are sent to the service processing module
through the backplane-side interface of the EM4F. The service processing module identifies the
destination interfaces for the packets, and buffers and schedules the packets. Then, the service
processing module sends the processed packets to the service access module, where coding/
decoding, serial/parallel conversion, and E/O conversion are performed. Finally, the service
access module outputs the packets through the GE/FE interfaces on the front panel.
Receive Direction
The GE/FE interfaces on the front panel receive GE/FE service signals. Then, the service access
module performs O/E conversion, serial/parallel conversion, and coding/decoding on the
services, and then sends the services to the service processing module. The service processing
module buffers the service packets, schedules the packets, and finally outputs the packets through
the backplane-side interface.
l In the receive direction, this module receives the GE/FE services from the interfaces on the
front panel, performs O/E conversion, serial/parallel conversion, and coding/decoding, and
then sends the services to the service processing module.
l In the transmit direction, this module receives the service packets from the service
processing module, performs coding/decoding, serial/parallel conversion, and E/O
conversion on the packets, and then outputs the packets through the GE/FE interfaces on
the front panel.
l This module extracts the synchronous Ethernet clock.
l In the receive direction, this module receives and buffers the service packets from the
service access module. Then, this module schedules packets from different interfaces.
Finally, this module outputs the packets through the backplane-side interface.
l In the transmit direction, this module receives service packets from the AND1CXPA/
AND1CXPB, identifies the destination interfaces of the packets, and buffers and schedules
the packets. Finally, this module outputs the packets to the service access module.
l This module extracts and inserts IEEE 1588 V2 packets.
Management Module
This module is used with the AND1CXPA/AND1CXPB to manage and control each module on
the EM4F.
Clock Module
This module performs the following functions:
l Provides the working clock for each module on the EM4F.
l Supports the synchronous Ethernet and SSM protocols.
l Supports the IEEE 1588 V2 protocol.
l Supports the 1588 ACR clock.
Indicator
The following indicators are present on the front panel of the AND1EM4F:
l STAT indicator, red, green, or orange, which indicates the working status
l L/A0 to L/A3 indicators, green or orange, which indicate the port connection status and
data transmit/receive status
For details on meanings of indicators, see 11 Indicators.
Interface
Four SFP interfaces are present on the EM4F. Table 5-10 lists the types and usage of the
interfaces on the EM4F.
Interface Specifications
Table 5-11 and Table 5-12 lists the specifications of the interfaces on the AND1EM4F board.
Fiber type Multi- Single- Single- Single- Single- Single- Single- Single-
mode mode mode mode mode mode mode mode
Working 770 to 1270 to 1260 to 1500 to Tx: 1260 Tx: 1480 Tx: 1260 Tx: 1480
waveleng 860 1360 1360 1580 to 1360 to 1500 to 1360 to 1500
th range Rx: 1480 Rx: 1260 Rx: 1480 Rx: 1260
(nm) to 1500 to 1360 to 1500 to 1360
Minimum 0 -3 -3 -3 –3 –3 –3 –3
overload
(dBm)
Minimum 9 9 9 9 6 6 6 6
extinction
ratio (dB)
Item Specification
Physical Specifications
Board dimensions (mm): 22.86 (H) x 225.75 (D) x 193.80 (W)
Weight (kg): 0.44
Power consumption (W, room temperature): 12.0
5.4.1 Overview
The AND1EM8F (EM8F for short) is an eight channels FE/GE optical interface board. The
function version of the EM8F is AND1. The AND1EM8F is housed in any of slots 1 to 2.
Management bus
Management bus Clock signals
Transmit Direction
The service packets from AND1CXPA/AND1CXPB are sent to the service processing module
through the backplane-side interface of the EM8F. The service processing module identifies the
destination interfaces for the packets, and buffers and schedules the packets. Then, the service
processing module sends the processed packets to the service access module, where coding/
decoding, serial/parallel conversion, and E/O conversion are performed. Finally, the service
access module outputs the packets through the GE/FE interfaces on the front panel.
Receive Direction
The GE/FE interfaces on the front panel receive GE/FE service signals. Then, the service access
module performs O/E conversion, serial/parallel conversion, and coding/decoding on the
services, and then sends the services to the service processing module. The service processing
module buffers the service packets, schedules the packets, and finally outputs the packets through
the backplane-side interface.
l In the receive direction, this module receives the GE/FE services from the interfaces on the
front panel, performs O/E conversion, serial/parallel conversion, and coding/decoding, and
then sends the services to the service processing module.
l In the transmit direction, this module receives the service packets from the service
processing module, performs coding/decoding, serial/parallel conversion, and E/O
conversion on the packets, and then outputs the packets through the GE/FE interfaces on
the front panel.
l This module extracts the synchronous Ethernet clock.
l In the receive direction, this module receives and buffers the service packets from the
service access module. Then, this module schedules packets from different interfaces.
Finally, this module outputs the packets through the backplane-side interface.
l In the transmit direction, this module receives service packets from the AND1CXPA/
AND1CXPB, identifies the destination interfaces of the packets, and buffers and schedules
the packets. Finally, this module outputs the packets to the service access module.
l This module extracts and inserts IEEE 1588 V2 packets.
Management Module
This module is used with the AND1CXPA/AND1CXPB to manage and control each module on
the EM8F.
Clock Module
This module performs the following functions:
Indicator
The following indicators are present on the front panel of the AND1EM8F:
l STAT indicator, red, green, or orange, which indicates the working status
l L/A0 to L/A7 indicators, green or orange, which indicate the port connection status and
data transmit/receive status
For details on meanings of indicators, see 11 Indicators.
Interface
Eight SFP interfaces are present on the EM8F. Table 5-14 lists the types and usage of the
interfaces on the EM8F.
Interface Specifications
Table 5-15 and Table 5-16 lists the specifications of the interfaces on the AND1EM8F board.
Fiber type Multi- Single- Single- Single- Single- Single- Single- Single-
mode mode mode mode mode mode mode mode
Item Specification
Working 770 to 1270 to 1260 to 1500 to Tx: 1260 Tx: 1480 Tx: 1260 Tx: 1480
waveleng 860 1360 1360 1580 to 1360 to 1500 to 1360 to 1500
th range Rx: 1480 Rx: 1260 Rx: 1480 Rx: 1260
(nm) to 1500 to 1360 to 1500 to 1360
Minimum 0 -3 -3 -3 –3 –3 –3 –3
overload
(dBm)
Minimum 9 9 9 9 6 6 6 6
extinction
ratio (dB)
Item Specification
Physical Specifications
Board dimensions (mm): 22.86 (H) x 225.75 (D) x 193.80 (W)
5.5.1 Overview
The AND1EX1 (EX1 for short) is a one channel 10 GE optical interface board. The function
version of the EX1 is AND1. The AND1EX1 is housed in any of slots 5 to 6 (when working
with the AND1CXPA) and in any of slots 3 to 6 (when working with the AND1CXPB).
Figure 5-9 shows the block diagram for the functions of the AND1EX1.
Management bus
Management bus Clock signals
Transmit Direction
The service packets from AND1CXPA/AND1CXPB are sent to the service processing module
through the backplane-side interface of the EX1. The service processing module buffers and
schedules the packets. Then, the service processing module sends the processed packets to the
service access module, where coding/decoding, and serial/parallel conversion are performed.
Finally, the service access module outputs the packets through the 10 GE interface on the front
panel.
Receive Direction
The 10 GE interface on the front panel receives 10 GE service signals. Then, the service access
module performs serial/parallel conversion, and coding/decoding on the services, and then sends
the services to the service processing module. The service processing module buffers and
schedules the service packets, and finally outputs the packets through the backplane-side
interface.
l In the receive direction, this module receives the 10 GE services from the interfaces on the
front panel, performs serial/parallel conversion, and coding/decoding, and then sends the
services to the service processing module.
l In the transmit direction, this module receives the service packets from the service
processing module, performs coding/decoding, and serial/parallel conversion on the
packets, and then outputs the packets through the 10 GE interfaces on the front panel.
l This module extracts the synchronous Ethernet clock.
l In the receive direction, this module receives and buffers the service packets from the
interface conversion module. Then, this module schedules packets based on the access
capability of the EX1 and the access bandwidth settings at the interface. Finally, this module
outputs the packets through the backplane-side interface.
l In the transmit direction, this module receives service packets from the AND1CXPA/
AND1CXPB, buffers and schedules the packets. Finally, this module outputs the packets
to the service access module.
l This module extracts and inserts IEEE 1588 V2 packets.
Management Module
This module is used with the AND1CXPA/AND1CXPB to manage and control each module on
the EX1.
Clock Module
This module performs the following functions:
l 5.0 V
l 3.3 V
l 1.8 V
l 1.2 V
Indicator
The following indicators are present on the front panel of the AND1EX1:
l STAT indicator, red, green, or orange, which indicates the working status
l L/A indicators, green or orange, which indicate the port connection status and data transmit/
receive status
For details on meanings of indicators, see 11 Indicators.
Interface
One SFP interface is present on the AND1EX1. Table 5-18 lists the types and usage of the
interfaces on the AND1EX1.
Interface Specifications
Table 5-19 lists the specifications of the electrical interfaces on the AND1EX1 board.
Mean launched -6 to -1 -1 to 2 0 to 4
optical power (dBm)
Physical Specifications
Board dimensions (mm): 22.86 (H) x 225.75 (D) x 193.80 (W)
Weight (kg): 0.42
Power consumption (W, room temperature): 13.1
NOTE
The AND1ML1 and AND1ML1A have the same functions and features except for the matched impedance
(AND1ML1: 75 ohms E1; AND1ML1A: 120 ohms E1).
5.6.1 Overview
The functional version of the AND1ML1/AND1ML1A is AND1. The AND1ML1/AND1ML1A
is housed in any of slots 1 to 6.
The ML1A has two function versions, that is, AND1 and AND2. Table 5-20 lists the differences
between these two versions.
Table 5-20 Differences between the two function versions of the ML1
Function Difference
AND1ML1/AND1ML1A AND2ML1A/
AND2ML1B
Basic functions Accesses and processes 16 x E1 signals and supports the ATM
E1, IMA, CES, and ML-PPP protocols.
Maximum number of E1 16
links in each IMA group
The packet loading time of the CES service can be set. The
encapsulation buffer time ranges from 1 ms to 3 ms, and the
step value is 1 ms.
Figure 5-11 Block diagram for the working principle of the AND1ML1/AND1ML1A
Backplane
Serial
Management bus
management
bus
Management bus Control module CXP
In Transmit Direction
The AND1ML1/AND1ML1A first distributes the signals in Ethernet packets from the backplane
to different protocol processing chips according to the service types. The system-side processing
module decapsulates the concatenated services and buffers the services in queues. Then, this
module schedules the egress queues according to the service types, processes and converts the
services, and finally sends the services to the line-side processing module. The line-side
processing module performs coding, dejitter, pulse shaping, and line driving for the services,
and finally sends the services to E1 interfaces.
In Receive Direction
The line processing module performs impedance match, signal equalization, signal level
conversion, clock data recovery, dejitter, and decoding for the accessed E1 signals. Then, the
signals are sent into the system-side processing module, which frames the signals, encapsulates
the IMA, CES, and ML-PPP services in PWE3, and schedules PWs. Finally, this module sends
the signals in Ethernet packets to the backplane interface module.
Control Module
This module controls the reading and writing on the chip, resets the chip, and detects faults in
the chip.When used with the AND1CXPA/AND1CXPB, this module controls the board.
Clock Module
This module provides various clock signals for the board to operate normally, detects clocks,
and selects the line recovery clock.
Figure 5-13 shows the appearance of the front panel of the AND1ML1A.
Indicators
The following indicators are present on the front panel of the AND1ML1/AND1ML1A:
l STAT indicator, red, green, or orange, which indicates the working status
Interfaces
There is one Anea 96 interface on the front panel of the AND1ML1/AND1ML1A. Table
5-22 lists the type and usage of the interface. For cables corresponding to the interfaces, see
9.4.2 75-Ohm 16 x E1 Cables and 9.4.3 120-Ohm 16 x E1 Cables.
Table 5-22 Type and usage of the interface on the front panel of the ML1
1 Rx1 25 Tx1
2 26
3 Rx2 27 Tx2
4 28
5 Rx3 29 Tx3
6 30
7 Rx4 31 Tx4
8 32
9 Rx5 33 Tx5
10 34
11 Rx6 35 Tx6
12 36
13 Rx7 37 Tx7
14 38
15 Rx8 39 Tx8
16 40
17 Rx9 41 Tx9
18 42
19 R x 10 43 T x 10
20 44
21 R x 11 45 T x 11
22 46
23 R x 12 47 T x 12
24 48
49 R x 13 73 T x 13
50 74
51 R x 14 75 T x 14
52 76
53 R x 15 77 T x 15
54 78
55 R x 16 79 T x 16
56 80
5.6.5 Specifications
The technical specifications of the AND1ML1/AND1ML1A include the interface
specifications, dimensions, weight, and power consumption.
Table 5-24 lists the specifications of the interfaces on the AND1ML1/AND1ML1A.
Board dimensions (mm): 20.32 (H) x 225.75 (D) x 193.80 (W)(0.80 in.×8.89 in.×7.63 in.)
Weight (kg): 0.56(1.23 lb)
Power consumption (W, room temperature): 13.1
NOTE
The mapping impedance of an interface on the AND3ML1A is 75 ohm, and the mapping impedance of an
interface on the AND3ML1B is 120 ohm. Except the difference of mapping impedance, the functions and
features of the AND3ML1A and AND3ML1B are the same.
5.7.1 Overview
The AND3ML1A/AND3ML1B (ML1A/ML1B for short) is a 16 channels E1 interface board.
The function version of the ML1A/ML1B is AND2. The AND3ML1A/AND3ML1B is housed
in any of slots 1 to 6.
Basic functions Accesses and processes 16 x E1 signals and supports the ATM TC,
IMA, CES, and ML-PPP protocols.
The jitter compensation buffer time of the CES service can be set.
The jitter buffer time ranges from 2 ms to 8 ms.
The packet loading time of the CES service can be set. The
encapsulation buffer time ranges from 1 ms to 3 ms.
-48V/-60V System
3.3V Power
Clock . . power supply
. .
supply
module . .
-48V/-60V
1V module System
power supply
System clocks
Line clocks CXP
CXP
Transmit Direction
The service signals from the AND1CXPA/AND1CXPB are sent to the service processing
module. The service processing module performs PWE3 decapsulation and PW scheduling for
the service signals, processes the service signals based on the IMA/ATM, CES, and ML-PPP
protocols, performs the E1 framing function, and sends the service signals to the service access
module. The service access module performs encoding and line drive for the signals and outputs
the signals through the backplane-side interfaces.
Receive Direction
The board accesses service signals through the backplane-side interfaces, and then the signals
are sent to the service access module. The service access module performs interference isolation,
lightning-proof, impedance matching, level conversion, signal balancing, decoding, and then
sends the processed signals to the service processing module. The service processing module
performs E1 framing, processes service signals based on the IMA/ATM, CES, and ML-PPP
protocols, implements PWE3 encapsulation and PW scheduling, and sends the signals to the
AND1CXPA/AND1CXPB through the backplane-side interfaces.
l In the receive direction, this module isolates common mode interference, protects circuits
against transient failures, matches the impedance in the receive direction with the internal
impedance, and performs level conversion, balancing, and decoding for the service signals.
Finally, this module sends the processed signals to the service processing module.
l In the transmit direction, this module receives the service signals from the service
processing module, encodes the signals, drives the line, and outputs the service signals
through the backplane-side interfaces.
Management Module
This module manages and controls each module on the board.
Clock Module
This module performs the following functions:
l When used with the AND1CXPA/AND1CXPB, processes the recovered line clock.
l Provides the working clock for each module on the board.
Indicators
The following indicators are present on the front panel of the AND3ML1A/AND3ML1B:
l STAT indicator, red, green, or orange, which indicates the working status
For details on meanings of indicators, see 11 Indicators.
Interfaces
There is one Anea 96 interface on the front panel of the AND3ML1A/AND3ML1B. Table
5-26 lists the type and usage of the interfaces. 9.4.2 75-Ohm 16 x E1 Cables and 9.4.3 120-
Ohm 16 x E1 Cables list the cables corresponding to the interfaces.
Table 5-26 Type and usage of the interfaces on the front panel of the AND3ML1A/AND3ML1B
Interface Interface Usage
on the Type
Front AND3ML1A AND3ML1B
Panel
1 Rx0 25 Tx0
2 26
3 Rx1 27 Tx1
4 28
5 Rx2 29 Tx2
6 30
7 Rx3 31 Tx3
8 32
9 Rx4 33 Tx4
10 34
11 Rx5 35 Tx5
12 36
13 Rx6 37 Tx6
14 38
15 Rx7 39 Tx7
16 40
17 Rx8 41 Tx8
18 42
19 Rx9 43 Tx9
20 44
21 R x 10 45 T x 10
22 46
23 R x 11 47 T x 11
24 48
49 R x 12 73 T x 12
50 74
51 R x 13 75 T x 13
52 76
53 R x 14 77 T x 14
54 78
55 R x 15 79 T x 15
56 80
Interface Specifications
Table 5-28 lists the specifications of the interfaces on the AND3ML1A/AND3ML1B.
Physical Specifications
Board dimensions (mm): 20.32 (H) x 225.75 (D) x 193.80 (W)(0.80 in.×8.89 in.×7.63 in.)
Weight (kg): 0.44(0.97 lb)
Power consumption (W, room temperature): 9.5
The mapping impedance of an interface on the AND2MD1A is 75 ohm, and the mapping impedance of an
interface on the AND2MD1B is 120 ohm. Except the difference of mapping impedance, the functions and
features of the AND2MD1A and AND2MD1B are the same.
5.8.1 Overview
The AND2MD1A/AND2MD1B (MD1A/MD1B for short) is a 32 channels E1 interface board.
The function version of the MD1A/MD1B is AND1. The AND2MD1A/AND2MD1B is housed
in any of slots 1 to 6.
Basic functions Accesses and processes 32 x E1 signals and supports the ATM TC,
IMA, CES, and ML-PPP protocols.
The jitter compensation buffer time of the CES service can be set.
The jitter buffer time ranges from 2 ms to 8 ms.
The packet loading time of the CES service can be set. The
encapsulation buffer time ranges from 1 ms to 3 ms.
Transmit Direction
The service signals from the AND1CXPA/AND1CXPB are sent to the service processing
module. The service processing module performs PWE3 decapsulation and PW scheduling for
the service signals, processes the service signals based on the IMA/ATM, CES, and ML-PPP
protocols, performs the E1 framing function, and sends the service signals to the service access
module. The service access module performs encoding and line drive for the signals and outputs
the signals through the backplane-side interfaces.
Receive Direction
The board accesses service signals through the backplane-side interfaces, and then the signals
are sent to the service access module. The service access module performs interference isolation,
lightning-proof, impedance matching, level conversion, signal balancing, decoding, and then
sends the processed signals to the service processing module. The service processing module
performs E1 framing, processes service signals based on the IMA/ATM, CES, and ML-PPP
protocols, implements PWE3 encapsulation and PW scheduling, and sends the signals to the
AND1CXPA/AND1CXPB through the backplane-side interfaces.
Management Module
This module manages and controls each module on the board.
Clock Module
This module performs the following functions:
l When used with the AND1CXPA/AND1CXPB, processes the recovered line clock.
l Provides the working clock for each module on the board.
Indicators
The following indicators are present on the front panel of the AND2MD1A/AND2MD1B:
l STAT indicator, red, green, or orange, which indicates the working status
For details on meanings of indicators, see 11 Indicators.
Interfaces
There are two Anea 96 interfaces on the front panel of the AND2MD1A/AND2MD1B. Table
5-30 lists the type and usage of the interfaces. 9.4.2 75-Ohm 16 x E1 Cables and 9.4.3 120-
Ohm 16 x E1 Cables list the cables corresponding to the interfaces.
Table 5-30 Type and usage of the interfaces on the front panel of the AND2MD1A/AND2MD1B
1 Rx0 25 Tx0
2 26
3 Rx1 27 Tx1
4 28
5 Rx2 29 Tx2
6 30
7 Rx3 31 Tx3
8 32
9 Rx4 33 Tx4
10 34
11 Rx5 35 Tx5
12 36
13 Rx6 37 Tx6
14 38
15 Rx7 39 Tx7
16 40
17 Rx8 41 Tx8
18 42
19 Rx9 43 Tx9
20 44
21 R x 10 45 T x 10
22 46
23 R x 11 47 T x 11
24 48
49 R x 12 73 T x 12
50 74
51 R x 13 75 T x 13
52 76
53 R x 14 77 T x 14
54 78
55 R x 15 79 T x 15
56 80
Interface Specifications
Table 5-32 lists the specifications of the interfaces on the AND2MD1A/AND2MD1B.
Physical Specifications
Board dimensions (mm): 20.32 (H) x 225.75 (D) x 193.80 (W)(0.80 in.×8.89 in.×7.63 in.)
Weight (kg): 0.49(1.08 lb)
Power consumption (W, room temperature): 12.1
6 Filler Panel
Appearance
Figure 6-1 shows the appearance of a filler panel.
Valid Slots
A filler panel can be housed in any of slots 1-6 of a chassis.
Optical interface boards for the ATN 950B use the enhanced small form-factor pluggable (eSFP)
optical module.
The eSFP optical module, which is a protocol-independent optical transceiver applicable to
optical communication, implements O/E and E/O conversion for signals, and supports query of
information such as the transceiver performance and manufacturer.
7.1 Appearance and Application
The eSFP optical module can be inserted in GE and FE optical interfaces.
7.2 Optical Module Labels
Optical module labels, attached on back of the optical modules, are used to distinguish different
types of optical modules.
Appearance
Figure 7-1 shows the appearance of the eSFP optical module.
Application
Table 7-1 lists the boards where the eSFP optical module is applicable.
1.25G-80km-1550nm
34060360
As shown in Table 7-2, different types of optical modules have different part numbers.
Appearance
Figure 8-1 shows the appearance of the SFP electrical module.
Part Number
Table 8-1 lists the part number and the type of the pluggable module.
9 Cables
This chapter describes various fibers and cables used on the equipment, including power cables,
grounding cables, management cables, clock cables, alarm cables, service cables, and fibers.
screwdriver
-48V cable
(blue)
0 V cable
(black)
2 U DC connector
Structure
Figure 9-2 shows an AC input power cable connecting the mains to the EPS30-4815AF.
Figure 9-2 AC input power cable connecting the mains to the EPS30-4815AF
Figure 9-3 shows a power cable connecting the EPS30-4815AF to the output terminal of a
storage battery.
Figure 9-3 Power cable connecting the EPS30-4815AF to the output terminal of a storage battery
Main label
View A X2
W1 (Blue)
1
A W2 (Blue)
2
3 W3 (Black)
4 W4 (Black)
X1 X3
X1 W1 X2
Figure 9-5 shows a power cable connecting the EPS30-4815AF to the PIU.
X2
View A
W1 (Blue)
1
A W2 (Blue)
2
3 W3 (Black)
4 W4 (Black)
X1 X3
Technical Specifications
Cable Item Description
Fireproof class CM
Fireproof class CM
Fireproof class CM
Fireproof class CM
Note 1: A power cable is named in the format of "Connector 1 Type-Cable Material Type-
Connector 2 Type".
Note 2: The specifications of power cables for inputting the mains vary in different countries
or regions. In this document, the AC power cables complying with international standards are
considered as examples.
Table 9-2 Technical specifications of the power cable and PGND cable
Electronic/Electric wire, 450 V/750 V, H07Z, General terminal, OT, 6 mm2(0.009 in.2), tin
K, 4 mm2(0.006 in.2), yellow green, fire plating, pre-insulated ring terminal,
resistant cable with low smoke and no 12-10AWG, yellow
halogen
Cable type Twisted-Pair Cable, 100 ohm,Category 5e UTP, 0.51 mm(0.0200 in.),
24AWG, 8 Cores, PANTONE 430U
Structure
Figure 9-8 shows the structure of the RJ45 connector used on the external clock cable.
Pin Assignment
The external clock cables must be made on the equipment installation site. When the CLK and
TOD interfaces are used as external clock interfaces, the pin assignment of the RJ45 connector
is as listed in Table 9-5; when the CLK and TOD interfaces are used as external time interfaces,
the pin assignment of the RJ45 connector is as listed in Table 9-6.
Table 9-5 Pin assignment of the RJ45 connector (external clock mode)
6 Green Unspecified
8 Brown Unspecified
Table 9-6 Pin assignment of the RJ45 connector (external time mode)
Technical Specifications
Table 9-7 and Table 9-8 lists the technical specifications of the external clock cable.
Item Specification
Number of Eight
cores
Item Specification
Number of Eight
cores
Structure
Figure 9-9 shows the structure of the 120-to-75-ohm clock bridging cable.
8 A
W5 Heat-shrink tube W2
1
W3
X1
W4
30 m
Pin Assignment
Table 9-9 lists the pin assignment of the clock bridging cable connector.
X1.2 White
X1.5 White
X1.6 White
X1.8 Brown
Technical Specifications
Table 9-10 lists the technical specifications of the clock bridging cable.
120-ohm cable Twisted-Pair Cable, 120 ohm, SEYVP, 0.4 mm(0.02 in.), 26AWG, 4Pairs,
type Pantone 430U
Structure
Figure 9-10 shows the appearance of the network cable.
RJ45 connectors are used at both ends of a network cable. Figure 9-12 shows an RJ45 connector
and Figure 9-13 shows the structure of the network cable.
W 8
8
1 1
X1 X2
NOTE
For a crossover cable, pins 1 and 2 of the RJ45 connector at one end must be cross-connected to pins 3 and
6 of the RJ45 connector at the other end respectively.
Pin Assignment
Table 9-11 and Table 9-12 list the pin assignment of the network cable connector.
straight-through Cable
Technical Specifications
Table 9-13 lists the technical specifications of the shielded cable.
Number of Eight
cores
Number of Eight
cores
Structure
Figure 9-14 shows the appearance of the 75-ohm 16 x E1 cable and Figure 9-15 shows the
structure of the cable.
X1 A
View A Pos.96
Cable Connector, Anea, 96PIN,
Female Connector
Pos .1
Pin Assignment
Table 9-15 lists the pin assignment of the 75-ohm 16 x E1 cable connector.
1 Tip 1 R0 25 Tip 2 T0
2 Ring 26 Ring
3 Tip 3 R1 27 Tip 4 T1
4 Ring 28 Ring
5 Tip 5 R2 29 Tip 6 T2
6 Ring 30 Ring
7 Tip 7 R3 31 Tip 8 T3
8 Ring 32 Ring
9 Tip 9 R4 33 Tip 10 T4
10 Ring 34 Ring
11 Tip 11 R5 35 Tip 12 T5
12 Ring 36 Ring
13 Tip 13 R6 37 Tip 14 T6
14 Ring 38 Ring
15 Tip 15 R7 39 Tip 16 T7
16 Ring 40 Ring
17 Tip 17 R8 41 Tip 18 T8
18 Ring 42 Ring
19 Tip 19 R9 43 Tip 20 T9
20 Ring 44 Ring
22 Ring 46 Ring
24 Ring 48 Ring
50 Ring 74 Ring
52 Ring 76 Ring
54 Ring 78 Ring
56 Ring 80 Ring
Technical Specifications
Diameter of the shield 12.4 mm(0.49 in.) - 1.6 mm(0.06 in.) - 0.26 mm(0.01 in.)
layer - diameter of the
internal insulation
layer - diameter of the
internal conductor
Number of cores 32
Available length 5 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, 50 m
16.40 ft.,32.80 ft.,49.21 ft.,65.62 ft.,82.02 ft.,98.42 ft.,114.83 ft.,
131.23 ft.147.64 ft.,164.04 ft.
Structure
Figure 9-16 shows the appearance of the 120-ohm 16 x E1 cable and Figure 9-17 shows the
structure of the cable.
X1 A
View A Pos.96
Cable Connector, Anea, 96PIN,
Female Connector
Pos .1
Pin assignment
Table 9-17 lists the pin assignment of the 120-ohm 16 x E1 cable connector.
Technical Specifications
Cable Trunk Cable, 120 ohm, 16E1, 0.4 mm(0.02 in.), Anea 96F,
120CC32P0.4P430U(S), +45deg
Cable type Twisted-Pair Cable, 120 ohm, SEYVP, 0.4 mm(0.02 in.), 26AWG,
32Pairs, Pantone 430U
Available length 5 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, 50 m
16.40 ft.,32.80 ft.,49.21 ft.,65.62 ft.,82.02 ft.,98.42 ft.,114.83 ft.,
131.23 ft.147.64 ft.,164.04 ft.
9.5 Fibers
This section describes the types of fibers and fiber connectors.
2 mm multi- 3 m, 5 m, 10 m, 20 m, 30 m
mode fiber 9.84 ft..16.40 ft.,32.81 ft.,
65.62 ft.,98.42 ft.
2 mm multi- 10 m, 20 m, 30 m
mode fiber 32.81 ft.,65.62 ft.,98.42 ft.
2 mm multi- 10 m, 20 m
mode fiber 32.81 ft.,65.62 ft.
Select proper fiber connectors and fibers of proper length according to the site survey.
LC/PC Plug-in square fiber connector/ Used at the optical interfaces on all the
protruding polished boards on the equipment
FC/PC Round fiber connector/protruding Used at the client-side ODF or the optical
polished interfaces on other equipment
Only axial operations instead of rotation is required to insert or remove the LC/PC fiber
connector. To insert or remove an LC/PC fiber connector, do as follows:
l To insert the fiber jumper into the LC/PC connector, align the head of the fiber jumper with
the optical interface and then push the fiber jumper with proper force into the connector.
l To remove the LC/PC fiber jumper, press the clip first, push the fiber connector inward
slightly, and then pull out the connector.
l To insert the fiber jumper into the FC/PC connector, align the head of the fiber jumper with
the optical interface on the optical interface board carefully, to avoid any damage to the
internal ceramic pipe. After inserting the fiber jumper to the bottom of the optical interface,
clockwise rotate the external screw to tighten the fiber jumper into the optical interface.
l To remove the fiber jumper, first anticlockwise rotate the external screw of the optical
interface. When the screw is loosened, remove the fiber jumper with proper force from the
optical interface.
10 Safety Labels
The equipment has various safety labels. This section describes the suggestions and locations
of these safety labels.
Label Description
There are labels on the chassis and boards. See Table 10-1.
Fan warning label The label suggests that do not touch the fan
leaves when the fan is rotating.
HUAWEI
华为技术有限公司 中国制造
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
Product nameplate label The label suggests the product name and
certification.
Label Position
Figure 10-1 shows positions of labels on the chassis.
1类激光产品
Class 1 Laser Product
N14036
合格证/QUALIFICATION CARD
この装置は、クラスA情報技術装置 です。この装置を家庭環境 で
使用すゐと電波妨害 を引き起こすことがぁります 。この場合には使用
者が適切な対策を講ずゐよぅ 要求されゐことがぁります 。 VCCI-A
11 Indicators
This section describes the names of various indicators and their indications.
Index of Indicators
For boards and their indicators, see Boards and Their Indicators.
For board status indicators, see:
l Description of the Board Status Indicator (STAT)
l Description of the Program Running Indicator (PROG)
l Description of the Synchronization Status Indicator (SYNC)
l Description of the CXP Switching Status Indicator (ACTX)
l Description of the CXP Control Status Indicator (ACTC)
l Description of the Power Supply Status Indicator (PWR)
l Description of the Fan Status Indicator (FAN)
For service port status indicators, see:
l Description of the Service Port Transmitting/Receiving Status Indicator (ACT)
l Description of the Port Status Indicator of the EM4T/EM8T (LINK)
l Description of the Port Connection and Data Transmitting/Receiving Status
Indicators of the EM4F/EM8F/EX1 (L/A)
For system alarm indicators, see:
l Description of the Critical Alarm Indicator (CRIT)
l Description of the Major Alarm Indicator (MAJ)
l Description of the Minor Alarm Indicator (MIN)
For combination of indicators in different start statuses on the system control board, see
Description of the Start Status Indicator Combination on the System Control Board.
AND1EM4T STAT
AND1EM8T STAT
AND1EX1 L/A
AND1ML1/ML1A STAT
AND3ML1A/ML1B STAT
AND2MD1A/MD1B STAT
AND1PIU PWR
Status Indication
On for 100 ms and off for Loading of the board software is in process.
100 ms alternately (green)
On for 300 ms and off for The BIOS is guiding the upper-layer software.
300 ms alternately (green)
On (green) l The clock works in free-run mode and the system clock
priority list is not set. By default, the system clock priority
list contains only internal sources.
l The clock works in locked mode and is tracing a clock source
other than the internal sources in the priority list.
l The system clock is working in time synchronization mode,
and the PTP time and system clock are in the tracing state.
On (red) l The system clock priority list is set. All the clock sources,
however, are lost except for the internal clock sources. The
clock works in holdover mode or free-run mode.
l The system clock is working in time synchronization mode,
but no synchronization source is available. The system clock
and PTP time are working in holdover or free-run mode.
On for 100 ms and off for 100 ms alternately The data of the equipment is backed up in
(green) batch.
Status Indication
Description of the Start Status Indicator Combination on the System Control Board
From power on to normal running, the system control board goes through various status. Table
11-1 shows the indicator combination corresponding to these statuses.
NOTE
a: When the system control board is running, the ACTC and ACTX indicators may be off, in green or
blinking (green). When services are normal, the indicator is green. For other statuses of the indicator, see
Description of the CXP Switching Status Indicator (ACTX) and Description of the CXP Control
Status Indicator (ACTC).
This chapter lists the power consumption and weight of each board used for the ATN 950B.
0.12(0.26) 0.5
13 Interface Specifications
Item Specification
Fiber type Multi- Single- Single- Single- Single- Single- Single- Single-
mode mode mode mode mode mode mode mode
Working 770 to 1270 to 1260 to 1500 to Tx: 1260 Tx: 1480 Tx: 1260 Tx: 1480
waveleng 860 1360 1360 1580 to 1360 to 1500 to 1360 to 1500
th range Rx: 1480 Rx: 1260 Rx: 1480 Rx: 1260
(nm) to 1500 to 1360 to 1500 to 1360
Minimum 0 -3 -3 -3 –3 –3 –3 –3
overload
(dBm)
Minimum 9 9 9 9 6 6 6 6
extinction
ratio (dB)
Item Specification
Mean launched -6 to -1 -1 to 2 0 to 4
optical power (dBm)