An Algorithm for Via Minimization in Two Layer Channel Routing of VLSI Design
Subrata Das
Dept. of Information Technology
Assam University, Silchar
Silchar, India
subrata.academia.das@gmail.com
Leena Barua
Dept. of Information Technology
Assam University Silchar
Silchar, India
barualeena@hotmail.com
Abstract— Via minimization plays an increasingly important
role in the routing phase in the design process of VLSI circuits
and systems. A via is an electrical connection that establishes the
connectivity between two layers. Vias are established at points
where a net changes layer. But if the number of vias is more, then
it not only reduces the reliability of the product but also causes
delay and affects the circuit performance. Therefore, via
minimization plays an increasingly vital role in the efficient yield
of the circuit. In this paper, we devise an algorithm for reducing
the number of vias by using the concepts of maximum
independent set, net intersection graph and segment intersection
graph. Also in this approach the number of horizontal tracks is
minimized, thus minimizing the routing area.
Keywords— Channel routing, via, horizontal track, routing
area, maximum independent set, net intersection graph, segment
intersection graph.
I. INTRODUCTION (HEADING 1)
The paper deals with the routing phase of VLSI physical
design. Routing [3] is one of the many phases of VLSI
physical design which is concerned with finding the
geometrical layouts of all the nets. The process of routing
builds connections between terminals on the periphery of
different cells. Connections are realized using wire segments
on the different layers of interconnect. Some technologies
allow only two layers of wiring. This is referred to as two-
layer routing [3]. More recent fabrication technologies allow
additional layers of interconnects. Multi-layer routing [3]
refers to routing using at least three layers of interconnect.
Connections between the layers are made using via holes[3].
In a strict two layer routing of nets[2], all the horizontal
segments should be placed in one layer, called the horizontal
layer and all the vertical segments should be routed in another
layer called the vertical layer. This strict layering of nets
results in the necessity to use more number of vias to
interconnect the net components in different layers. But if the
number of vias is more, then it is disadvantageous as it
decreases the circuit’s yield and also increases the routing area
125
Nikumani Choudhury
Dept. of Information Technology
Gauhati University
Guwahati, India
nikumani.choudhury.2014@ieee.org
Ajoy Kr Khan
Dept. of Information Technology
Assam University Silchar
Silchar, India
ajoyiitg@gmail.com
which is not desirable. Therefore, we must focus on reducing
the number of vias. The channel routing problem(CRP) is the
problem of computing a feasible route for the nets so that the
number of tracks required(and hence the channel area) is
minimized. In order to minimize the routing area, the
horizontal wire segments of the nets need to be distributed
amongst the minimum number of tracks[1]. The problem that
is concerned with in this paper aims at minimizing the number
of vias.
II. IDEA OF USE
A via is a single contact for a wire, which establishes the
connectivity between two layers. Vias are established at points
where a net changes layer and no two distinct nets intersect on
the same layer. Vias are necessary to establish multi-layer
connections.
In a routing layout where each signal net is formed by the wire
segments interconnecting a set of electrically connected
terminals, vias are used to connect wire segments on different
layers. Vias introduce some drawbacks. Besides increasing the
manufacturing cost and complexity, vias in a circuit degrade
its performance and reliability[3]. The via minimization
problem is to minimize the number of vias used in a layout.
There are two types of via minimization problem.
1. Constrained via minimization (CVM)
2. Unconstrained via minimization(UVM)
A. Constrained Via Minimization
One kind of the via minimization problem is to reduce the
number of vias in a completed detailed routing by re-assigning
the wire segments to different layers. This type of via
minimization is called Constrained Via Minimization (CVM)
[2].Here the placement of the wire segments cannot be
changed.
B. Unconstrained Via Minimization.
In this approach [2], the problem is to both place the segments
and also assign the layers so as to minimize the total number
of vias. Here, the actual layout of wires can be changed and
thus it offers more flexibility as compared to the CVM
approach[2]. It is also known as topological via minimization.
III. MOTIVATION AND IMPORTANCE OF THE PROBLEM
An increase in the number of vias decreases the reliability of
the product. Via minimization is essential because it also
increases cost of manufacture, size of chip etc. After routing a
chip completely, the layout is improved using via
minimization. The importance for reducing the number of vias
can be stated as follows:
In the fabrication of integrated circuit, the circuit yield is
inversely proportional to the number of vias. A chip with more
vias has less probability of being fabricated correctly.
Step 1: Find the net intersection graph
Step 2: Initialize:
Set I={all the nodes of NIG}
Set MIS=ij
Step 3: Find the degree of all the nodes
Step 4: Repeat steps 5 and 6 until I=ij
Step 5: Start with the node with lowest degree and store it in
MIS
Step 6: Delete the node and its neighbours from the set I and
update the degrees of the remaining vertices.
Step 7: Stop
b) Expalnation with example:
Consider the following channel instance:

• Every via has a resistance associated with it that affects the

performance of the circuit.
• The size of via is generally larger than the width of the
wire. Thus more vias lead to more routing space.
• Completion rate of routing is also inversely related to the Fig. 1. Channel instance
number of vias.

IV. PROPOSED APPROACH AND IMPLEMENTATION

The algorithm uses two phases for optimizing via
minimization:
Phase 1: Finding the Maximum Independent Set Phase and
hence finding the maximum abutment set. And then re-routing
the nets in the maximum independent set by moving terminals
so that the nets in maximum independent set can be connected
without horizontal tracks and vias.
Phase 2: Taking the output channel from phase 1 and
removing non-essential vias by changing layers.
A. Phase 1 : Finding the Maximum Independent Set Phase
and hence finding the maximum abutment set
The problem of minimizing the number of horizontal tracks
and that of minimizing the number of vias can be solved by
using movable terminals. An abutment [1] does not need any
horizontal tracks and vias to interconnect terminals in a
channel. Minimizing the number of vias and horizontal tracks
is equivalent to maximizing the number of abutments and
finding a maximum independent set [1] with a largest number
of vertices in net intersection graph. We use an algorithm to
find the maximum independent set of the net intersection
graph.
a) Algorithm for finding maximum independent set
Fig. 2. Net Intersection Graph for the given channel
Here different colors represent different layers and
represents via.
First find the Net intersection graph for the channel and then
define the sets I and MIS: I ={1,2,3,4,5,6} MIS=ij. Then
evaluate the degree of all the nodes : From the NIG, Degree
of node 1 =0,Degree of node 2 =4,Degree of node 3 =4,Degree
of node 4 =2,Degree of node 5 =3, Degree of node 6 =3. Next
start with lowest degree node and place it in MIS and delete it
and its adjacent vertices from set I. Update the degree of the
vertices. Repeat until I=ij: After 1st iteration: MIS={1},
I={2,3,4,5,6}. After 2nd iteration: MIS={1,4}, I={5,6}.
Updated degree of the remaining nodes in I: Updated degree
of node 5=1, Updated degree of 6=1. After 3rd iteration:
MIS={1,4,5} I=ij Therefore the MIS={1,4,5}. Finally the
nets in MIS can be connected without any vias and horizontal
tracks. Therefore the channel becomes:

Input: Net intersection matrix

Output: Maximum Independent Set (MIS)

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 b) Explanation with example
Consider the output channel of Phase 1:

Fig. 3. Output channel after using maximum independent set

In this way by finding the Maximum Independent Set (MIS),
we can reduce the number of vias and number of tracks by
shifting the terminals without changing their relative position.
The following table depicts the reduction in number of vias
and horizontal tracks achieved:
Fig. 4. Output channel of phase 1
a) First divide the nets into segments and name the
segments as in Fig.5 and then construct the segment
intersection graph.

Table 1. Reduction in number of vias and horizontal tracks achieved

after phase 1
Number of Number of vias Number of Number of
vias finally(after horizontal horizontal tracks
initially applying MIS) tracks finally(after
initially applying MIS)
10 6 5 3
Fig. 5. Channel after naming the segments

B. Phase 2: Eliminating non-essential vias by changing

layers
After vias are eliminated in the 1st phase by finding the
maximum independent set and then shifting terminals, in this
phase more optimization in reduction in number of vias is
achieved by violating the strict layering of the nets. Here we
overcome the strict layering of nets in which all horizontal
segments are placed in one layer and all vertical segments in
another layer, by reconnecting the net components and placing
them in whichever layer possible such that it reduces the Fig. 6. The segment intersection graph
number of vias.
Input: The output channel of phase 1 The degrees of all the nodes are then found. The degrees of the
Output : A channel in which the number of vias is minimum nodes are: Degree of node 1 =0,Degree of node 2 =2,Degree
of node 3 =3,Degree of node 4 =1,Degree of node 5 =2,Degree
a) Algorithm for Phase 2 of node 6 =1,Degree of node 7 =1,Degree of node 8 =5,Degree
of node 9 =2,Degree of node 10 =3,Degree of node 11
Step 1: Divide the channel into segments and name all the =2,Degree of node 12 =1. Next the nodes(segments)
segments of the nets associated with a via : via_node is given. via_node=set of all
Step 2: Construct the segment intersection graph for the the nodes associated with via.
named segments.
Step 3: Find the degree of all the nodes via_node={4,5,6,7,8,9,10,11,12}. For all the nodes in
Step 4: Read the via_nodes from user via_node If degree=1 then, the via associated with that
node(segment) is eliminated.
Step 5: From the set of via_nodes find those nodes whose
degree is 1 Set of via_nodes with degree 1={4,6,7,12}
Step 6: Eliminate the vias used by these segments and re-route
the wires attached to these vias on the same layer Therefore the vias associated with the segments(nodes) 4,6,7
Step 7: Stop and 12 gets eliminated. Thus 4 vias got eliminated in the 2nd
phase leaving the channel with only two vias. This is shown
below:

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 1) Example 1

a) b)

Fig. 7. The output channel after applying our approach

The following table shows the scenario:

Table 2. : Reduction in number of vias and horizontal tracks c)

achieved after phase 2 Fig. 8. a)Before via minimization b)After using MIS
No,of No.of No.of vias No.of No.of c) Final channel after via minimization
vias vias after phase horizontal horizontal
initially after 2(finally) tracks initially tracks finally
phase 1 2) Example 2
10 6 2 5 3
Thus by using both the phases of the given approach, it can be
see that the number of vias eliminated is optimized, that is
maximum possible number is eliminated by our approach.
a) b)

V. CONCLUSION & RESULTS

Java language has been used for implementation of the
proposed algorithm. In the first phase, the algorithm takes as
input the channel instance and finds the number of vias that
got reduced. In the second phase, the output channel of first
phase is given as input and the output is a further reduction in Fig. 9. a)Before via minimization b)After using MIS
the number of vias. Table 3 shows the comparison of number c) Final channel after via minimization
of vias and number of horizontal tracks for different channel
instances before and after our algorithm is used for via 3) Example 3
minimization. From the results it can be claimed that with the
implementing of the given approach, a considerable decrease
in the number of vias is achieved as vias are eliminated in both
phases. This reduction in the number of vias is much more
than the reduction in number of vias achieved by existing
approaches. Also using our approach, the number of
horizontal tracks used by the channel is reduced, which in turn a)
reduces the routing area.

Table 3. Experimental results using the proposed approach

Ex. No.of No.of No.of No.of vias No.o % reduction
horizontal horizont vias after f vias in the
tracks al tracks initially finding finall number of
initially finally MIS y vias
1 2 1 4 2 0 100%
b)
2 3 2 6 4 1 83.33%

3 5 3 10 6 2 80.00%

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 c)

Fig. 10. A)Before via minimization b)After using MIS

c) Final channel after via minimization

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