ANNA UNIVERSITY COIMBATORE

B.E/ B.TECH DEGREE EXAMINATIONS: MAY/JUNE 2010

REGULATIONS: 2008
FOURTH SEMESTER
080250010- MICROPROCESSOR AND MICROCONTROLLERS
COMMON TO CSE/IT
Time: 3 hours Max.Marks: 100

PART-A
ANSWER ALL THE QUESTIONS

1. What is assembly language?

2. Mention the function of microprocessor in a system.
3. State the difference between CPU bus and system bus.
4. What is DAA?
5. How 20-bit physical address is generated in 8086.
6. State the function of direction flags.
7. Give the different types of instructions in 8086.
8. Define EQU and DB directive.
9. What is meant by co-processor?
10. List out the advantages of microprocessor system.
11. What is bus contention?
12. Give the types of multiprocessor configuration.
13. How does Port C of 8255 differ from Port A and Port B.
14. State the function of CAS0-CAS2 and SP/EN pins in 8259.
15. What is chip select and how it is generated?
16. Mention the function of terminal count register.
17. List out some of the applications of microcontroller.
18. Give the addressing modes of 8051 microcontroller.
19. What is Data Pointer?
20. Write a program to subtract two 8-bit numbers and exchange digits using 8051.

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 PART-B
ANSWER ANY FIVE QUESTIONS

21.a) Write the ALP to add and multiply two 8 bit numbers.(6)
b) Give the assembly language implementation of the following(6)
1.do-while 2.for

22.a) Explain Overflow condition with 8 bit signed data. Generate Overflow using other flags of
8086.(8)
b) Discuss the system bus cycle of 8086 with a neat diagram?(4)

23.a) Convert 1259.125base10 in short real, long real and temporary real format.(6)
b) Write an instruction programming with 8087 coprocessor to find the area of the circle.(6)

24.a) Explain the communication between 8086 and 8089.(6)

b) Discuss the DMA operation using 8089.(6)

25.a) Discuss in detail about the interrupt services routines with interrupt cycle of 8086.(8)
b) Discuss the action taken by 8086 when INTR pin is activated.(4)

26.a) Draw and explain command and mode word format of 8251.(6)
b) Draw a flowchart to transmit a message from an 8085 to a CRT using serial communication
interface(6).

27.a) Discuss the architecture of 8051 with its block diagram.(8)

b) What happens when an interrupt initiated in 8051?(4)

28. Explain with neat diagram how push button and LED can be connected to 8051.

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 PART A

1. What is an assembly language?

To make programming easier, usually programmers write programs in assembly
language. They then translate the assembly language to machine languages so that it can be
loaded into memory and executed. Assembly language uses two, three or four letter words to
represent each instruction types. These words are referred to as mnemonics.
2. Mention the function of microprocessor in the system.
A microprocessor consists of multiple internal function units. A basic design has an
arithmetic logic unit (ALU), a control unit, a memory interface, an interrupt or exception
controller, and an internal cache. More sophisticated microprocessors might also contain
extra units that assist in floating-point match calculations, program branching, or vector
processing
3. State the difference between CPU bus and system bus.
The System Bus
All communication between the major components of the computer is via the
System Bus. The bus is merely a cable which is capable of carrying signals representing data
from one place to another. The bus used in a particular individual computer may be specific
to that computer or may (increasingly) be an industry-standard bus. If it is an industry
standard bus then it should be easy to upgrade the computer by buying a component from an
independent manufacturer which can plug directly into the system bus. Most modern
Personal Computers use the PCI bus; older machines used the ISE bus. The system bus
carries data and control signals.
Possible transfers of information via the system bus are:
 Data transmitted from main memory to the CPU.
 Input data from (say) the keyboard travels from the device to main memory.
 Information from External Memory is transmitted to Main Memory.The bus that
connects the CPU to main memory on the motherboard. I/O buses, which connect
the CPU with the systems other components, branch off of the system bus.
The system bus is also called the front side bus, memory bus, local bus, or host bus
CPU Bus :
A bus that operates only within the internal circuitry of the CPU, communicating
among the internal caches of memory that are part of the CPU chip’s design. This bus is
typically rather quick and is independent of the rest of the computer’s operations.

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 Contrast with external data bus. The bit width of internal and external data buses is not
always equal.
4. What is DAA?
Decimal adjust accumulator
DAA: The contents of the accumulator are changed from a binary value to two 4-bit
binary coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to
perform the binary to BCD conversion, and the conversion procedure is described below. S,
Z, AC, P, CY flags are altered to reflect the results of the operation. If the value of the low-
order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to
the low-order four bits. If the value of the high-order 4-bits in the accumulator is greater
than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits.
5. How 20-bit physical address is generated in 8086.
There were also four sixteen-bit segment registers that allowed the 8086 CPU to
access one megabyte of memory in an unusual way. Rather than concatenating the segment
register with the address register, as in most processors whose address space exceeded their
register size, the 8086 shifted the 16-bit segment only 4 bits left before adding it to the 16-bit
offset (16·segment + offset), therefore producing a 20-bit external (or effective or physical)
address from the 32-bit segment: offset pair. As a result, each external address could be
referred to by 212 = 4096 different segment: offset pairs.
6. State the function of direction flags.
The Direction Flag is a flag stored in the FLAGS register on all x86 compatible
CPUs. It is bit 10. When it is set to 0, it means that instructions, that auto increment the
source index and destination index (like MOVS) will increase both of them. In case it is set to
1, the instruction will decrease them. This flag is used to determine the direction (forward or
backward) in which several bytes of data will be copied from one place in the memory, to
another. The direction is important mainly when the original data position in memory and the
target data position overlap.
7. Give the different types of instructions in 8086.
Instructions vary from one CPU to another, General
Groupings Possible:
 Arithmetic/Logic
 Add, Subtract, AND, OR, shifts
 Performed by ALU
 Data Movement
 Load, Store (to/from registers/memory)

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  Transfer of Control
 Jump, Branch, procedure call
 Test/Compare
 Set condition flags
 Input/Output
 In, Out (Only on some CPUs)
 Machine controls
 Halt, NOP
8. Define EQU and DB directive.
EQU:The EQU directive assigns a value to a label. This label can then be used in later
expressions. A label assigned to a value by the EQU directive is a constant and can not be
changed or redefined.
Syntax:
.EQU label = expression
Example:
.EQU io_offset = 0x23
.EQU porta = io_offset + 2
.CSEG ; Start code segment
clr r2 ; Clear register 2
out porta,r2 ; Write to Port A
DB:The DB directive reserves memory resources in the program memory or the
EEPROM memory. In order to be able to refer to the reserved locations, the DB directive
should be preceded by a label.The DB directive takes a list of expressions, and must
contain at least one expression.The DB directive must be placed in a Code Segment or an
EEPROM Segment. The expression list is a sequence of expressions, delimited by
commas. Each expression must evaluate to a number between -128 and 255. If the
expression evaluates to a negative number, the 8 bits two's complement of the number
will be placed in the program memory or EEPROM memory location.
Syntax:
LABEL: .DB expressionlist
Example:
.CSEG
consts: .DB 0, 255, 0b01010101, -128, 0xaa
.ESEG
eeconst:.DB 0xff

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9. What is meant by co-processor?
A special-purpose processing unit that assists the CPU in performing certain types
of operations. For example, a math coprocessor performs mathematical computations,
particularly floating-point operations. Math coprocessors are also
called numeric and floating-point coprocessors.
10. List out the advantages of multiprocessor system.
Advantages of multiprocessor:
1. Improves cost/performance ratio of the system.
2. Several processors may be combined to fit the need of an application while avoiding
the expanse of the unneeded capabilities of a centralized system. Yet this system
provides room for expansion
3. Tasks are divided among the modules. If failure occurs, it is easier and cheaper to
find and replace the malfunctioning processor than replacing the failure part of the
complex processor.
11. What is bus contention?
Bus contention, in computer design, is an undesirable state of the bus in which
more than one device on the bus attempts to place values on the bus at the same time. Most
bus architectures require their devices follow an arbitration protocol carefully designed to
make the likelihood of contention negligible. However, when devices on the bus have logic
errors, manufacturing defects or are driven beyond their design speeds, arbitration may
break down and contention may result. Contention may also arise on systems which have a
programmable memory mapping and when illegal values are written to the registers
controlling the mapping.
12. Give the types of multiprocessor configuration.
Types of multiprocessor configuration:
1. Coprocessor configuration
2. Closely coupled configuration
3. Loosely coupled configuration
13. How does Port C of 8255 differ from Port A and Port B.
The 8255 has 24 input/output pins in all. These are divided into three 8-bit ports. Port A
and port B can be used as 8-bit input/output ports. Port C can be used as an 8-bit input/output
port or as two 4-bit input/ouput ports or to produce handshake signals for ports A and B.
The three ports are further grouped as follows:
1) Group A consisting of port A and upper part of port C.
2) Group B consisting of port B and lower part of port C.

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14. State the function of CAS0-CAS2 and SP/EN pins in 8259.
CAS0-CAS2:
Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on these
lines. In slave mode, the PIC reads slave ID no. from master on these lines. It may be
regarded as slave-select.
SP / EN :
Slave program / enable. In non-buffered mode, it is SP-bar input, used to distinguish
master/slave PIC. In buffered mode, it is output line used to enable buffers
15. What is chip select and how it is generated?
Chip select (CS) or slave select (SS) is the name of a control line in digital
electronics used to select one chip out of several connected to the same computer bus
usually utilizing the three-state logic. When an engineer needs to connect several devices to
the same set of input wires (e.g., a computer bus), but retain the ability to send and receive
data or commands to each device independently of the others on the bus, they can use a
chip select. The chip select is a command pin on most ICs which connects the input pins on
the device to the internal circuitry of that device, and similarly for the output pins.
16. Mention the function of terminal count register.
Each channel of 8257 Block diagram has two programmable 16-bit registers named
as address register and count register. Address register is used to store the starting address of
memory location for DMA data transfer. The address in the address register is automatically
incremented after every read/write/verify transfer. The count register is used to count the
number of byte or word transferred by DMA. The format of count register is,

14-bits B0-B13 is used to count value and a 2-bits is used for indicate the type of DMA
transfer (Read/Write/Veri1 transfer). In read transfer the data is transferred from memory to
I/O device. In write transfer the data is transferred from I/O device to memory. Verification
operations generate the DMA addresses without generating the DMA memory and I/O
control signals.
17. List out some of the applications of microcontroller.
Microcontrollers are found in almost all "smart" electronic devices. From
microwaves to automotive braking systems, they are around us doing jobs that make our

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 lives more convenient and safer. Microcontrollers are essentially small computers. Unlike
your desktop computer, microcontrollers interact with other machines rather than humans.
A microcontroller might be used to measure the temperature of your toast at breakfast and
when the temperature reaches a predetermined measure, the toaster could be turned off. A
microcontroller could also be used to count the number of customers entering the ball park
through a turnstile thereby keeping track of ticket sales. The uses for these small versatile
devices is diverse. Perhaps you can imagine a microcontroller application that will improve
a product or decrease the time required to complete a process.
18. Give the addressing modes of 8051 microcontroller.
Addressing modes of 8051:
 Immediate Addressing MOV A,#20h
 Direct Addressing MOV A,30h
 Indirect Addressing MOV A,@R0
 External Direct MOVX A,@DPTR
 Code Indirect MOVC A,@A+DPTR
19. What is Data Pointer?
The Data Pointer (DPTR) is the 8051s only user-accessible 16-bit (2-byte) register.
The Accumulator, "R" registers, and "B" register are all 1-byte values. DPTR, as the name
suggests, is used to point to data. It is used by a number of commands which allow the 8051
to access external memory. When the 8051 accesses external memory it will access external
memory at the address indicated by DPTR. While DPTR is most often used to point to data in
external memory, many programmers often take advantage of the fact that its the only true
16-bit register available. It is often used to store 2-byte values which have nothing to do with
memory locations.
20. Write a program to subtract two 8-bit numbers and exchange digits using 8051.
Program : subtract two 8-bit numbers and change digits
MOV A, #9F ; Get The First Number In A
MOV R0, #40 ; Get The Secnd Number In R0
CLR C ; Clear Carry
SUBB A, R0 ; A=A-R0
SWAP A ; Exchange Digits

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 PART B

21. a)Write the AL program to add and multiply two 8 bit numbers

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21.b) Give the assembly language implementation of the following.
i) do-while ii) for
i) do-while
Like Do-WHILE statement in higher level language, the assembler supports
.WHILE - .ENDW statement. The .WHILE statement is used with a condition to begin
the loop, and the .ENDW statement ends the loop
.MODEL SMALL
.DATA
PASS DB 'ABC'
MES1 DB 10,13,'ENTER 3 CHARACTER PASSWORD $'
MES2 DB 10,13,'PASSWORD IS CORRECT $'
MES3 DB 10,13,'PASSWORD IS WRONG $'
.CODE
START: MOV AX,@DATA ; [Initialize
MOV DS, AX ; data segment]
MOV AH, 09H
LEA DX, MES1
INT 21H ; Display message
MOV CL, 00 ; Clear count
MOV DL, 00H ; Clear number of match
XOR DI, DI ; Initialize pointer
.WHILE CL! = 3 ; Check if count = 3 if not Continue
MOV AH, 07H
INT 21H ; Read character
LEA BX, PASS ; [Set pointer
MOV AH,[BX+DI] ; to password ]
.IF AL==AH ; Compare read character with password
ADD DL,01 ; Increament match count if match occurs
.ENDIF
INC DI ; Increment pointer
INC CL ; Increment counter
.ENDW
.IF DL == 3 ; [ if match count = 3
MOV AH,09H ; display message
LEA DX,MES2 ; password is correct ]

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 INT 21H
.ELSE ; [ if match count <> 3
MOV AH,09H ; display message
LEA DX,MES3 ; password is wrong ]
INT 21H
.ENDIF
MOV AH,4CH ; [ Exit to
INT 21H ; DOS ]
END START
END
ii) for
.REPEAT - .UNTIL statements allow to execute series of instructions repeatedly
until some condition occurs
.MODEL SMALL
.DATA
MES1 DB 10,13,'HERE IS THE LIST OF ALPHBETS',10,13,'$'
.CODE
START: MOV AX,@DATA ; [ Initialise
MOV DS,AX ; data segment ]
MOV AH,09H
LEA DX,MES1
INT 21H ; Display message
MOV DL,'A'
.REPEAT
MOV AH,02H
INT 21H ; Display character
INC DL
.UNTIL DL > 'Z'
MOV AH,4CH ; [ Exit to
INT 21H ; DOS ]
END START
END

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22. a) Explain Overflow condition with 8 bit signed data. Generate Overflow using other
flags of 8086
Arithmetic operations have a potential to run into a condition known as overflow.
Overflow occurs with respect to the size of the data type that must accommodate the result.
Overflow indicates that the result was too large, if positive, or too small, if negative, to fit in the
original data type. When two signed 2's complement numbers are added, the overflow flag OF
indicates one of the following:
 Both operands are positive and the result is negative, or
 Both operands are negative and the result is positive.
When two unsigned numbers are added, the carry flag CF indicates an overflow, that is,
 There is a carry out of the leftmost (most significant) bit.
Computers don't know the difference between signed and unsigned binary numbers. This
is a good thing, because it makes logic circuits fast. This is also a bad thing, because
distinguishing between signed and unsigned becomes programmer's responsibility. Distinction
between signed and unsigned data types is very important when detecting an overflow after
addition or subtraction. Correct approach to detect the overflow is to consider two separate cases:
 Overflow when adding signed numbers is indicated by the overflow flag, OF.
 Overflow when adding unsigned numbers is indicated by the carry flag, CF.
INC and DEC Instructions:
The INC instruction adds one to the destination operand, while preserving the state of the
carry flag CF:
 The destination operand can be a register or a memory location.
 This instruction allows a loop counter to be updated without disturbing the CF
flag.
The DEC instruction subtracts one from the destination operand, while preserving the
state of the CF flag. Especially useful for incrementing and decrementing counters. A register is
the best place to keep a counter. The INC and DEC instructions always treat integers as unsigned
values never update the carry flag CF, which would otherwise (i.e. ADD and SUB) be updated
for carries and borrows. The instructions affect the OF, SF, ZF, AF, and PF flags just like
addition and subtraction of one.
INC and DEC Example
XOR AL, AL ; Sets AL = 0. XOR instruction always clears OF and CF flags.
MOV BL, 0FEH
INC BL ; 0FFh SF = 1, CF flag not affected.
INC BL ; 000h SF = 0, ZF = 1, CF flag not affected.

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CLC, STC, CMC - Direct Carry Flag Manipulation the following instructions allow direct carry
flag manipulation:
 CLC clears Carry Flag, CF = 0
 STC sets Carry Flag, CF = 1
 CMC complements Carry Flag, CF = NOT (CF).
Overflow Flag Examples :
Examples of 8-bit signed and unsigned addition and subtraction:
.DATA
mem8 BYTE 39
.CODE
; Addition + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MOV AL, 26
INC AL
ADD AL, 76
ADD AL, [MEM8]
MOV AH, AL
ADD AL, AH
; Subtraction- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOV AL, 95
DEC AL
SUB AL, 23
MOV [MEM8], 122
SUB AL, [MEM8]
MOV AH, 119
SUB AL, AH
(OF) overflow flag indicates that result is too large to fit in the 8-bit destination operand:
 the sum of two positive signed operands exceeds 127.
 the difference of two negative operands is less than -128.
(CF) carry flag indicates that the sum of two unsigned operands exceeded 255.
(SF) sign flag indicates that result goes below 0.

22.b)Discuss the system bus cycle of 8086 with a neat diagram?

Each BUS CYCLE on the 8086 equals four system clocking periods (T states). The clock
rate is 5MHz, therefore one Bus Cycle is 800ns. The transfer rate is 1.25MHz. Memory
specifications (memory access time) must match constraints of system timing. For example, bus

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timing for a read operation shows almost 600ns are needed to read data. However, memory must
access faster due to setup times, e.g. Address setup and data setup. This subtracts off about 150ns.
Therefore, memory must access in at least 450ns minus another 30-40ns guard band for buffers
and decoders. 420ns DRAM required for the 8086.
READY
An input to the 8086 that causes wait states for slower memory and I/O components. A
wait state (TW) is an extra clock period inserted between T2 and T3 to lengthen the bus cycle.
For example, this extends a 460ns bus cycle (at 5MHz clock) to 660ns.

23. a) Convert 1259.12510 In Short Real, Long Real And Temporary Real Format.

Step 1: Convert This Decimal Number To Binary Format

Integer part: Remainders

16 1259 B LSB

16 78 E

4 4

4EBH = (100 1110 1011)

4 E B

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 Fractional Part:
.125 × 2 =0.25 0
0.25 × 2 = 0.5 0
0.5 × 2 = 1.0 1
0
= 0.001
Binary Number = 10011101011001 × 210
Step 2: Normalize the Number
10011101011.001 = 1.0011101011001 × 210
Now we will see the representation of the number in different formats.
1. Short Real
For the given number
S = 0, E = 10, F = 0011101011001
Bias for the short real format = 127
Biased exponent = 10 + 127 = 137 =10001001
Number in short real format
0 10001001 0011101011001 … 0 = 1259.12510
S Exponent Fraction
2. Long Real
Bias for long real format =1023
Biased exponent =10 + 1023 = 1033 =10000001001
Number in long real format
0 10000001001 0011101011001 … 0 = 1259.12510
S Exponent Fraction
3. Temporary Real Format
Bias for temporary real format = 16383
Biased exponent =10 + 16383 = 16393 =100 0000 0000 1001
Number in temporary real format
0 100 0000 0000 1001 0011101011001 … 0 = 1259.12510
S Exponent Fraction

23. b) Write An Instruction Programming With 8087 Coprocessor To Find The Area Of
The Circle.
Area of the circle = ΠR2
: Program Calculates The Area Of A Circle.

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 ; The Radius Must Be Stored At Memory Location Radius.
; The Result Found In Memory Location Area after the Program Execution.
.MODEL SMALL
.DATA
RADIUS DD 3.4
AREA DD ?
.CODE
START: MOV AX,@DATA;[initialize
MOV DS, AX ; data segment]
FINIT ; initialize 8087
FLD RADIUS ; loads radius (R) in ST
FMUL ST, ST (0) ; square radius (R x R)
FLDPI ; Π to ST
FMUL ; multiply ST =STx ST (1) i.e. (Π x R x R)
FSTP AREA ; save area
END START
24.a) Explain communication between 8086 and 8089

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Page 17 of 36
Page 18 of 36
24.b) Discuss the DMA operation using 8089

DMA Transfers

The XFER (transfer) instruction prepares the channel for a DMA transfer. It suspends
program execution and enters the DMA transfer mode, using the channel registers setup by the
program before executing the XFER instruction.

Data are transferred from a source to a destination. The source and destination may be
located in the CPU’s memory space or in the IOP’s memory space. The IOP makes no distinction
between memory and I/O devices, thus transfers may be made:

 from memory to I/O device;

 from I/O device to memory;
 from memory to memory;
 from I/O device to I/O device.

Transfer cycles may be:

 synchronized by a DMA request signal from the source or from the destination. The
channel waits for the synchronizing signal before starting the next transfer cycle.

 unsynchronized, in which case the channel begins the next transfer cycle immediately
upon completion of the previous cycle.

A transfer cycle is performed in two steps: reading a byte or word from the source into
the IOP and then storing it from the IOP into the destination. The IOP automatically optimizes the
transfer to use efficiently the available data bus. For example, if data is being transferred from a
8-bit device to memory using a 16-bit bus, the IOP will perform two read cycles and then will
store the full word in a single cycle. Between the read and store cycles, the IOP can operate on
the data. A byte may be translated to another code (e.g., EBCDIC to ASCII), or compared to a
search value, or both.

A transfer can be terminated by several conditions:

 when a specified number of bytes (up to 64 KB) has been transferred;

 by a signal from an external device, applied to the corresponding pin of the channel
(EXT1 or EXT2 - External Terminate);
 when a byte (possibly translated) compares equal, or unequal, to a search value;
 after one byte or word has been transferred (single-cycle termination).

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 When the transfer terminates, the channel automatically resumes program execution. The
channel program can determine the cause of the termination in situations where multiple
terminations are possible (e.g., terminating when a CR character is encountered or 80 bytes are
transferred, whichever occurs first). To determine if the transfer was performed successfully, the
channel program could read a result register from the I/O device controller. If, for example, a
CRC error was detected by the controller, the channel program could retry the operation without
CPU intervention.

A channel program usually ends by placing the result of the operation in the parameter
block, optionally interrupting the CPU, and then halting the channel. When the channel halts, its
BUSY flag in the channel control block is cleared to indicate its availability for another operation.
As an alternative to being interrupted by the channel, the CPU can check by polling the BUSY
flag to determine when the operation has been completed.

Bus Configurations

The IOP can access memory or I/O ports located in a 1-MB system space and memory or
ports located in a 64-KB I/O space. Although the IOP has only one physical data bus, it is useful
to consider that the IOP is accessing the system space over a system bus and the I/O space over
an I/O bus (both are data buses).

The distinction between the two logical buses is based on the signals that indicate the
type of bus cycle generated by the 8288 bus controller. Components in the system space respond

to the MEMR and MEMW signals, whether they are memory or I/O devices. Components in the

I/O space respond to the IOR and IOW signals (even if they are memory devices).

The two configurations differ in the degree to which the IOP shares these buses with the
CPU. Both configurations require an 8086 CPU configured in maximum mode.

1) Local Configuration

The IOP or IOPs shares both buses with the CPU. The IOP system space corresponds to
the CPU memory space, and the IOP I/O space corresponds to the CPU I/O space. Channel
programs are located in the system space; I/O devices may be located in either space (Figure 1).

The IOP uses the bus to fetch channel program instructions, as well as DMA and
programmed transfers. The IOP and the CPU may not use the bus simultaneously.

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 Figure 1. 8089 IOP in Local Configuration.

The advantage of the local configuration is that intelligent DMA may be added to a
system with no additional components beyond the IOP. The parallel operation of the CPU and
IOP is limited to cases in which the CPU has instructions in its queue that can be executed
without using the bus.

2) Remote Configuration

The IOP shares a common system bus with the CPU. Access to this bus is controlled by
8289 Bus Arbiters. The IOP’s local I/O bus is physically separated from the CPU. Two IOP’s can
share the local I/O bus. Any number of remote IOP’s may be contained in a system, configured in
groups of one or two.

The local I/O bus need not be the same physical width as the shared system bus, allowing
an IOP, for example, to interface 8-bit peripherals to an 8086 (Figure 2).

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 Figure 2. 8089 IOP in Remote Configuration.

In the remote configuration, conflicts to the system bus will be reduced, because the IOP
can access local I/O devices and memory without using the shared system bus. These conflicts
can further be reduced by locating the IOP’s channel programs in the local I/O space. The IOP
can then fetch instructions without accessing the system bus. However, memory blocks used for
the communication between CPU and IOP (CB, PB) must be located in system memory, so that
both processors can access them.

This configuration increases the degree to which a CPU and an IOP can operate in
parallel, with the price of additional hardware to arbitrate the shared bus, and to separate the
shared and local buses.

It is also possible to configure an IOP remote to one CPU, and local to another CPU. The
local CPU could be used to perform routines which need more complex processing.

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25.a) Discuss in detail about the interrupts and interrupt service routines with interrupt
cycle of 8086.
INTERRUPTS
There are two main types of interrupt in the 8086 microprocessor, internal and external
hardware interrupts. Hardware interrupts occur when a peripheral device asserts an interrupt input
pin of the microprocessor. Whereas internal interrupts are initiated by the state of the CPU (e.g.
divide by zero error) or by an instruction.
Provided the interrupt is permitted, it will be acknowledged by the processor at the end of
the current memory cycle. The processor then services the interrupt by branching to a special
service routine written to handle that particular interrupt. Upon servicing the device, the processor
is then instructed to continue with what is was doing previously by use of the "return from
interrupt" instruction.

The status of the program being executed must first be saved. The processors registers
will be saved on the stack, or, at very least, the programme counter will be saved. Preserving
those registers which are not saved will be the responsibility of the interrupt service routine. Once
the program counter has been saved, the processor will branch to the address of the service
routine.
Edge or Level sensitive Interrupts
Edge level interrupts are recognised on the falling or rising edge of the input signal. They
are generally used for high priority interrupts and are latched internally inside the processor. If
this latching was not done, the processor could easily miss the falling edge (due to its short
duration) and thus not respond to the interrupt request.
Level sensitive interrupts overcome the problem of latching, in that the requesting device
holds the interrupt line at a specified logic state (normally logic zero) till the processor
acknowledges the interrupt. This type of interrupt can be shared by other devices in a wired 'OR'
configuration, which is commonly used to support daisy chaining and other techniques.
Maskable Interrupts
The processor can inhibit certain types of interrupts by use of a special interrupt mask bit.
This mask bit is part of the flags/condition code register, or a special interrupt register. In the

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8086 microprocessor if this bit is clear, and an interrupt request occurs on the Interrupt Request
input, it is ignored.
Non-Maskable Interrupts
There are some interrupts which cannot be masked out or ignored by the processor. These
are associated with high priority tasks which cannot be ignored (like memory parity or bus faults).
In general, most processors support the Non-Maskable Interrupt (NMI). This interrupt has
absolute priority, and when it occurs, the processor will finish the current memory cycle, then
branch to a special routine written to handle the interrupt request.
Advantages of Interrupts
Interrupts are used to ensure adequate service response times by the processing.
Sometimes, with software polling routines, service times by the processor cannot be guaranteed,
and data may be lost. The use of interrupts guarantees that the processor will service the request
within a specified time period, reducing the likelihood of lost data.
Interrupt Latency
The time interval from when the interrupt is first asserted to the time the CPU recognises
it. This will depend much upon whether interrupts are disabled, prioritized and what the processor
is currently executing. At times, a processor might ignore requests whilst executing some
indivisible instruction stream (read-write-modify cycle). The figure that matters most is the
longest possible interrupt latency time.
Interrupt Response Time
The time interval between the CPU recognising the interrupt to the time when the first
instruction of the interrupt service routine is executed. This is determined by the processor
architecture and clock speed.
The Operation of an Interrupt sequence on the 8086 Microprocessor:
1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an
internal interrupt occurs.
2. The CPU finishes the present instruction (for a hardware interrupt) and sends Interrupt
Acknowledge (INTA) to hardware interface.
3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from
the hardware interface.
4. The contents of the flag registers are pushed onto the stack.
5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the trap
or single-step feature.
6. The contents of the code segment register (CS) are pushed onto the Stack.
7. The contents of the instruction pointer (IP) are pushed onto the Stack.

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 8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP and
from (4 x N +2) into the CS so that the next instruction executes at the interrupt service
procedure addressed by the interrupt vector.
9. While returning from the interrupt-service routine by the Interrupt Return (IRET)
instruction, the IP, CS and Flag registers are popped from the Stack and return to their
state prior to the interrupt.
Interrupt Service Routines
An interrupt service routine (ISR) is a software routine that hardware invokes in response
to an interrupt. ISRs examine an interrupt and determine how to handle it. ISRs handle the
interrupt, and then return a logical interrupt value. If no further handling is required because the
device is disabled or data is buffered, the ISR notifies the kernel with a SYSINTR_NOP return
value. An ISR must perform very fast to avoid slowing down the operation of the device and the
operation of all lower priority ISRs.
25. b) Describe the action taken by 8086 when INTR pin is activated.
An external hardware applying voltage to the INTR pin of the microprocessor, which
indicates that the external device, such as printer or keyboard, requires service (hardware-based
interrupt).

Interrupt program context switching mechanism.

When an interrupt signal occurs, the MPU must suspend what it is doing in the main
part of the program and pass control to a special routine (called the interrupt-service routine) that

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performs the function required by the external device. For example, when the printer causes an
interrupt, the printer driver (interrupt service routine) is called, but how does the microprocessor
know where tojump? The 8086 microprocessor is capable of implementing any combination of
up to256 interrupts.
An interrupt vector table is stored in the first 1 kbyte of memory (starting at address
00000h and ending at 003FFh). This is a pointer table to indicate the location of service routines
corresponding to interrupt types 0 to 255. The CS and IP in the interrupt vector table indicate the
location of the service routine for the corresponding interrupt. For example, when an interrupt of
type 32 occurs, the microprocessor looks at address 32 * 4 = 128 = 80h and (after pushing the
current CS and IP) loads the new values of CS and IP from 80h to jump to the interrupt service
routine.The first 32 interrupt types have dedicated functions or are reserved.
Interrupts are serviced on a priority basis. Type 0 identifies the highest priority interrupt,
and type 255 identifies the lowest-priority interrupt. If an interrupt-service routine has been
initiated to perform a function assigned to a specific priority level, only interrupts with higher
priority are allowed to interrupt the active service routine. Lower-priority devices have to wait
until the current service routine is completed. • The user normally assigns tasks that must not be
interrupted frequently to higher-priority levels and those that can be interrupted to lower-priority
levels (e.g., the keyboard is high-priority and the floppy disk is low-priority). If the IF flag is set
(IF = 1), it enables the external interrupt request pin (INTR) input for operation (i.e., enables
hardware interrupts). If IF = 0 the INTR pin is disabled and external devices cannot interrupt the
microprocessor operation.

Interrupt vector table of the 8086 microprocessor.

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26.a) Draw and explain command and mode wod formats of 8251 Control words
There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)
1) Mode Instruction
Mode instruction is used for setting the function of the 8251. Mode instruction
will be in "wait for write" at either internal reset or external reset. That is, the writing of a
control word after resetting will be recognized as a "mode instruction."
Items set by mode instruction are as follows:
• Synchronous/asynchronous mode
• Stop bit length (asynchronous mode)
• Character length
• Parity bit
• Baud rate factor (asynchronous mode)
• Internal/external synchronization (synchronous mode)
• Number of synchronous characters (Synchronous mode)
The bit configuration of mode instruction is shown in Figures 2 and 3. In the case
of synchronous mode, it is necessary to write one-or two byte sync characters. If sync
characters were written, a function will be set because the writing of sync characters
constitutes part of mode instruction.

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2) Command
Command is used for setting the operation of the 8251. It is possible to write a command
whenever necessary after writing a mode instruction and sync characters.
Items to be set by command are as follows:
• Transmit Enable/Disable
• Receive Enable/Disable
• DTR, RTS Output of data.
• Resetting of error flag.
• Sending to break characters
• Internal resetting
• Hunt mode (synchronous mode)

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Page 29 of 36
26.b) Draw a flowchart to transmit a message from an 8085 to a CRT using serial
communication interface

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27 a).Discuss the architecture of 8051 with its block diagram.
The 8051 is a low-power, high-performance CMOS 8-bit Microcomputer with 4K bytes
of Flash programmable and erasable read only memory (PEROM). The device is manufactured
using ’s high-density nonvolatile memory technology and is compatible with the industry-
standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be
reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a
versatile 8-bit CPU with Flash on a monolithic chip, the 8051 is a powerful microcomputer which
provides a highly-flexible and cost-effective solution to many embedded control applications

BLOCK DIAGRAM:

VCC - Supply voltage.

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GND - Ground.
PORT 0:
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance
inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during
accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also
receives the code bytes during Flash programming, and outputs the code bytes during program
verification. External pull-ups are required during program verification.
PORT 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled
low will source current (IIL) because of the internal pull-ups Port 1 also receives the low-order
address bytes during Flash programming and verification.
PORT 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled
low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external data memory
that uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull-ups
when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @
RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-
order address bits and some control signals during Flash programming and verification.
PORT 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled
low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various
special features of the 8051 as listed below: Port 3 also receives some control signals for Flash
programming and verification.

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RST
Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator
frequency, and may be used for external timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can
be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a
MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable
bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external program memory. When the 8051 is
executing code from external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH. Note,
however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be
strapped to VCC for internal program executions. This pin also receives the 12-volt programming
enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.

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OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier
which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either quartz
crystal or ceramic resonator may be used. To drive the device from an external clock source,
XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no
requirements on the duty cycle of the external clock signal, since the input to the internal clocking
circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.
The 8051 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM,
32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt architecture, a full duplex
serial port, and on-chip oscillator and clock circuitry. In addition, the 8051 is designed with static
logic for operation down to zero frequency and supports two software selectable power saving
modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and
interrupt system to continue functioning. The Power Down Mode saves the RAM contents but
freezes the oscillator disabling all other chip functions until the next hardware reset
SPECIAL FUNCTION REGISTERS
A map of the on-chip memory area called the Special Function
Register (SFR). Note that not all of the addresses are occupied, and unoccupied addresses may
not be implemented on the chip. Read accesses to these addresses will in general return random
data, and write accesses will have an indeterminate effect. User software should not write 1s to
these unlisted locations, since they may be used in future products to invoke new features. In that
case, the reset or inactive values of the new bits will always be 0.
TIMER 2 REGISTERS
Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The
register pair (RCAP2H, RCAP2L) is the Capture/Reload registers for Timer 2 in 16-bit capture
mode or 16-bit auto-reload mode.
INTERRUPT REGISTERS
The individual interrupt enable bits are in the IE register. Two priorities can be set for
each of the six interrupt sources in the IP register.
TIMER 0 AND 1
Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in
the 8051.
UART
The UART in the AT89C52 operates the same way as the UART in the 8051.

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INTERRUPTS
The 8051 has a total of Five interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (Timers 0, 1), and the serial port interrupt. Each of these interrupt sources
can be individually enabled or disabled by setting or clearing a bit in Special Function Register
IE. IE also contains a global disable bit, EA, which disables all interrupts at once.

27. b). What happens when an interrupt initiated in 8051.

An interrupt is a special feature which allows the 8051 to provide the illusion of "multi-
tasking," although in reality the 8051 is only doing one thing at a time. The word "interrupt" can
often be subsituted with the word "event."
An interrupt is triggered whenever a corresponding event occurs. When the event occurs,
the 8051 temporarily puts "on hold" the normal execution of the program and executes a special
section of code referred to as an interrupt handler. The interrupt handler performs whatever
special functions are required to handle the event and then returns control to the 8051 at which
point program execution continues as if it had never been interrupted.
The topic of interrupts is somewhat tricky and very important. For that reason, an entire
chapter will be dedicated to the topic. For now, suffice it to say that Interrupts can cause program
flow to change.
The 8051 has a total of Five interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (Timers 0, 1), and the serial port interrupt. Each of these interrupt sources
can be individually enabled or disabled by setting or clearing a bit in Special Function Register
IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
The Fig. Shows the interrupt structure of 8051.

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28. Explain with a neat diagram how push button and LED can be connected to 8051

The figure shows the interfacing diagram. P1.0 and P1.1 are used to connect LEDs while
P1.2 and P1.3 are used to connect push buttons. The statuses of the switches are sensed by BIT
TEST instruction and LEDs are driven by BIT SET instructions.
Program :
MOV P1,#0Ch ;configure P1.2 and P1.3
BACK : JNB P1.2, GLOW_L1
SETB P1.0
JNB P1.3, GLOW_L2
SETB P1.1
JMP BACK ; keep polling
GLOW_L1: CLR P1.0
JMP BACK ; keep polling
GLOW_L2: CLR P1.1
JMP BACK ; keep polling

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