Superlattices and Microstructures 96 (2016) 36e46

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Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Impactful study of dual work function, underlap and hetero

gate dielectric on TFET with different drain doping profile for
high frequency performance estimation and optimization
Dharmendra Singh Yadav*, Dheeraj Sharma, Bhagwan Ram Raad, Varun Bajaj
Nanoscale Devices, Circuit and System Design Lab., Electronics and Communication Engineering Discipline, PDPM Indian Institute of
Information Technology Design and Manufacturing, Jabalpur, 482005, India

a r t i c l e i n f o a b s t r a c t

Article history: This manuscript presents a comparative study of different combination for the dual
Received 15 April 2016 workfunction gate material, underlap and hetero gate dielectric tunnel field-effect tran-
Accepted 16 April 2016 sistors (TFET’s). Their performances have been analyzed in terms of ON-state current,
Available online 29 April 2016
ambipolar behaviour and RF response along with different drain doping profile. For this,
the Dual work function of gate provides enhancement in ON-state current by reducing the
Keywords:
tunnel barrier width at source/channel interface. Whereas, the underlap of gate is done
Band to band tunneling
near to the drain region, helps in reduction of ambipolar conduction by creating deficiency
Dual material gate
Source pocket
of hole for the conduction, which is major hurdle for TFET. Further, the combinations of the
Gate underlap dual workfunction and underlap give combine advantages of both such as improve ON-
Hetero gate dielectric state current and suppressed ambipolar current. Apart from this, the combination of
hetero gate dielectric dual workfunction under lapping leads to superior device perfor-
mance in terms of ON-state current and ambipolar behaviour. The use of hetero gate
dielectric and Gaussian doping profile with gate underlap reduces the gate to drain
capacitance that also improves the RF parameters of the device.
© 2016 Elsevier Ltd. All rights reserved.

1. Introduction

High speed, low power and portable devices are the dire need of this era. For continuous realization of the Moores pre-
diction, the size of metal oxide semiconductor field effect transistor (MOSFET) is reduced to nanometer regime. The purpose
of scaling is to achieve the higher chip density, lower power consumption, enhanced ON-state current and better analog/RF
performance. As per the latest research, MOSFETs size is in nano meter regime, so the scaling of MOSFETs is effected by short-
channel-effects (SCEs), drain induced barrier lowering (DIBL), higher leakage current and physical limitation on subthreshold
slope (SS) at room temperature [1]. In order to get rid of above mentioned problems many devices have been studied. Out of
them, tunnel field effect transistor (TFET) is one of the most permissible device which has very small subthreshold slope (SS <
60 mV/dec) and low leakage current as compared to conventional MOSFETs [2]. Apart from these advantages, TFET suffers
from the problems of ambipolar conduction and low current driving capability. In order to short out these problems many
approaches have been studied to suppress the ambipolar conduction such as lower drain doping, Gaussian doping profile in

* Corresponding author.
E-mail addresses: tech.dharmendra26@gmail.com (D.S. Yadav), dheeraj24482@gmail.com (D. Sharma), bhagwanramraad@gmail.com (B.R. Raad),
bajajvarun056@yahoo.co.in (V. Bajaj).

http://dx.doi.org/10.1016/j.spmi.2016.04.027
0749-6036/© 2016 Elsevier Ltd. All rights reserved.
 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46 37

drain region [3], and use of hetero gate dielectric material etc. Strained silicon, band gap engineering, pocket doping, use of
high-k material, and work function engineering [4,5] are used to enhance the ON-state current and also helps in reduction of
ambipolar current [6,7].
In this paper for the first time, we considered dual work function of gate material, underlap gate and hetero gate dielectric
with different drain doping profile in TFET at a time for getting advantages in terms of suppression of ambipolar behaviour
and improved ON-state current with better RF performance [8e10]. For this, we present an integrated gate underlap hetero
gate dielectric dual metal TFET with improved RF performance and huge reduction in ambipolar behaviour. In the same
concern, a low work function on the source side of the gate material is used to enhance the ON-state current. Apart from this,
under lapping of gate towards drain side is done for the suppression of ambipolar behaviour by reducing the concentration of
holes on the channel/drain junction which widens the depletion width at same junction. it also reduces the gate to drain
parasitic capacitance as required for high frequency application. Apart from these the use of hetero gate dielectric reduces
gate to drain capacitance which leads to enhancement in RF performance and better device controllability. Furthermore,
Gaussian doping profile is implied in drain region which increases the energy barrier at the drain/channel interface, hence,
further reduction in ambipolar current is observed. It also reduces gate to drain capacitances which leads to enhancement in
analog/RF performance.
The rest of the paper is arranged as follows: Section II describes the device structures and simulation setup. Section III,
demonstrates the DC characteristics for various combination of dual workfunction of gate material, underlap and hetero gate
dielectric tunnel field-effect transistors (TFET’s). Section IV, Describes the optimization of gate workfunction and underlap
length of underlap HGD DW TFET. A detailed discussion regarding analog/RF performance is investigated in Section V. Finally,
the impactful findings of this paper are enlightened as conclusion in Section VI.

2. Device structure and simulation setup

Fig. 1(aef) shows a cross sectional view of different architectures of TFET’s devices. For simulation, the following device
dimensions and doping are considered as shown in Table 1:
To incorporate the physical phenomenons, the following models in the technology computer aided design (TCAD)
simulation are taken into account

(a) Band to band tunneling model.

(b) Band gap narrowing model.
(c) Schcokly Read Hall recombination model.
(d) Auger recombination model.
(e) Fermi-Dirac statistical model.

Apart from these models, Wentzel-Kramers-Brillouin (WKB) method is used for numerical calculations and these simu-
lations are carried out by the 2-D ATLAS Silvaco international Version 5.19.20.R [11e13].

Fig. 1. Device schematic of (a) Single metal source pocket hetero junction double gate TFET (Conventional TFET), (b) dual workfunction TFET, (c) underlap dual
workfunction TFET, (d) Underlap HGD DW TFET, (e) Underlap Conventional TFET, and (f) Conventional HGD TFET.
38 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46

Table 1
Device design parameters.

Parameter name Symbol Value Unit

Drain length LD 100 nm
Source length LS 100 nm
Channel length LG 50 nm
Gate oxide thickness tox 3 nm
Silicon body thickness tsi 10 nm
Pocket length th 2 nm
Drain doping concentration Nd 5
1018 cm3
Source doping concentration Na 1
1020 cm3
Channel doping concentration Nch 1
1017 cm3
Pocket doping concentration Np 5
1018 cm3
Auxiliary gate length L1 30 nm
Tunnel gate length L2 20 nm

3. DC characteristics

This section consists of DC characteristics analysis of the devices shown in Fig. 1 with various combinations. These analysis
have been carried out in terms of thermal equilibrium, ON-state, OFF-state and ambipolar state with Uniform Doping and
Gaussian drain doping profile. Fig. 2(a) exhibits the carrier concentration distribution under the thermal equilibrium along
the channel direction. It can be observed that there is no accumulation of electron in channel region. It shows the symmetric
electron and hole concentration in the channel without applying any bias for all structures. Fig. 2(b) shows the Energy band
diagram in thermal equilibrium along the horizontal cut line at 1 nm below the surface of silicon film. Under this condition a
potential barrier is formed in the channel due to absence of accumulation of electron in the channel, therefore, the probability
of passing of electron is very negligible for all the devices. It is observed that smaller barrier is formed at the source/channel
interface for underlap DW TFET, DW TFET and underlap HGD DW TFET as compared to conventional TFET, underlap con-
ventional TFET and conventional HGD TFET due to the lower workfunction of the tunnel gate.
Fig. 3(aeb) represents the carrier concentration and energy band diagram of all structures in OFF state condition. In
Fig. 3(a), the hole concentration is larger than the electron concentration in channel region. Thus, the wider tunneling barrier
width between source and channel is found for all the structures as shown in Fig. 3(b), which does not allow the tunneling of
electron from source to channel region. Further from Fig. 3(b), it can observed that the widening of energy barrier width at
drain/channel interface occurs due to under-lapping of gate in case of underlap DW TFET, underlap HGD DW TFET and
underlap conventional TFET.
The ON-state carrier concentration profiles are shown in Fig. 4(a). It can be analyzed that the electron concentration in the
channel region increases after applying gate bias due to tunneling of electron from valance band of source to the conduction
band of channel. In this concern, Fig. 4(b) represents the energy band diagram in ON-state condition. It is shown that the
barrier width at source/channel interface decreases after applying a positive gate voltage. As a result, it allows the tunneling of
electron from source to drain in case of all structures.
Fig. 5(a) illustrates the carrier concentration under the ambipolar state. It can be seen that as the negative gate voltage is
applied, the hole concentration is increases rather than electron concentration in the channel region due to tunneling of hole
from conduction band of drain to the valance band of the channel. This is responsible for ambipolar current in all devices. In
this regard, Fig. 5(b) depicts the energy band diagram in the ambipolar state. It can be observed that by applying a negative
bias gate voltage, the tunneling barrier width at the channel and drain interface become narrower which allows the current is
named as ambipolar current in all structures. Further from this figure. It illustrates that the lowest energy barrier at drain/
channel interface occurs in case of conventional TFET and DW TFET. However, the highest energy barrier is found in underlap
HGD DW TFET.
Fig. 6(a) shows the comparison of transfer characteristic for different TFET configurations with uniform doping profile. In
conventional TFET, the tunneling width is larger than the other structures. Which is one of the main cause for low ON state
current. Whereas, conventional TFET and DW TFET have lowest energy barrier at drain/channel interface which results in
higher ambipolar behaviour. Further, it can observe that the presence of Dual work function of gate in case of DW TFET and
other structures increases the ON state current in comparison to conventional TFET. The lower work function (F2) of gate
towards the source side is responsible for accumulation of electron concentration at source/channel interface, as a result it
reduces the tunnel barrier width and hence increases the ON-state current. However, the issue of ambipolar behaviour still
remains the problem in case of conventional TFET and DW TFET. So, the underlap Dual work function TFET approach, provides
higher ON-state current and reduction in ambipolar current. The under lapped gate and lower oxide at the drain side reduces
the ambipolar current due to lesser accumulation of electrons at the drain/channel interface. Further, we have considered
Underlap HGD DW TFET to improve the ON state current and reduction of ambipolar current, it provides the optimum results
from the other possible combination. The under lapped gate and lower oxide at drain side reduces the ambipolar current due
to lesser accumulation of electrons at drain/channel interface whereas the high-k dielectric and pocket layer at the source/
 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46 39

Fig. 2. Carriers concentration and energy band diagram in equilibrium state.

Fig. 3. Carriers concentration and energy band diagram in OFF state.

Fig. 4. Carriers concentration and energy band diagram in ON state.

40 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46

Fig. 5. Carriers concentration and energy band diagram in ambipolar state.

Fig. 6. (a) Ids  Vgs characteristics of TFET for different configurations with uniform doping at Vds ¼ 1 V and (b) Ids  Vgs characteristics of TFET for different
configurations with Gaussian doping at Vds ¼ 1 V.

channel interface provides more accumulation of electrons. Underlap conventional TFET and conventional HGD TFET also
reduces the ambipolar behaviour but their ON state current is poor in compare to other structures.
Fig. 6(b) shows the transfer characteristic of different TFET configurations with Gaussian doping profile. Ambipolar con-
duction is the main hurdle to use a TFET in the circuit design. Here we are using an alternative approach called Gaussian
doping which is also helpful in reduction of ambipolar behaviour. Use of Gaussian doping reduces the charge carrier con-
centration at drain/channel interface. This leads to widening of tunneling barrier width and helps in suppression of ambipolar
behaviour. Whereas the use of dual workfunction engineering increases the ON-state current. As it is depicted from Fig. 6(b)
the ON state current of the (conventional TFET, Underlap conventional TFET, and Conventional HGD TFET) is approximately
same but it is quite low. While the ON state current in case of DW TFET, Underlap DW TFET, Underlap HGD DW TFET is quite
high as compared to conventional TFET. Besides, higher ON state current these TFETs also shows the steep subthreshold slope
and suppressed ambipolar behaviour.

4. Underlap HGD DW TFET work function optimization and gate underlap

As reported in previous section that underlaps HGD TFET provides better results in comparison to other structures. So, in
this section an investigation has been performed for the impact of variation in Work function (TG and Aux.G) of Underlap HGD
DW TFET over ON state current (ION) and OFF state current (IOFF).
 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46 41

Fig. 7. (a) Energy band diagram in ON-State with various Aux.G work function for the device. (b) Energy band diagram in OFF-State with various Aux.G work
function for the device.

Fig. 7 shows the energy band diagram of Underlap HGD DW TFET in the ON-state and OFF-state respectively for Aux.G
having different work functions. Fig. 7(a) shows the energy band diagram of Underlap HGD DW TFET in the ON-state. From
the figure, it can be observed that the band diagram is not affected significantly by the variation of Aux.G work function.
Hence, ON state current remain same in Fig. 8. However, from Fig. 7(b), it can be observed that as the work function of Aux.G is
increases, the tunneling barrier increases at the source side which results in reduction in OFF state current as shown in Fig. 8.
Further, it can be analyzed that for Aux.G workfunction greater than 4.6 eV a significant reduction in tunneling barrier occurs
at drain/channel interface which increases OFF state current as shown in Fig. 8. Thus for Aux.G workfunction 4.6 eV gives
better results in terms of OFF state current and ambipolar behaviour in Fig. 8.
Fig. 9(aeb) depicts the energy band diagram of Underlap HGD DW TFET in the OFF-state and ON-state respectively for TG
having different work function while the Aux.G work function is considered to be equal to 4.6 eV. From Fig. 9(a), it can be
illustrated that the variation in work function of TG does not affect the band position significantly at drain/channel interface,
thus, the ambipolar-state current is not affect to a great extent. In ON state, the band overlapping at source/channel interface
increase as the work function of TG decreases which result in improvement in ON state current (Fig. 9(b) and Fig. 10). But, for
tunnel gate work function less than 4.4 eV significant increment is found in OFF state current (Fig. 10). Therefore, from above
analysis, we can observe that TG ¼ 4.4 eV at Aux.G ¼ 4.6 eV provides better result in terms of ON state current, OFF state
current and ambipolar behaviour. From Fig. 10, it can be analyzed that as the work function of TG decrease as it improves ON
current. Thus, it can be observed that Fig. 10 for TG ¼ 4.4 eV provides better performance in terms of ON state current, OFF
state current and better RF performance.

Fig. 8. Transfer characteristics of the device at different Aux.G work function.

42 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46

Fig. 9. (a) Energy band diagram in OFF-State with various TG for the device. (b) Energy band diagram in ON-State with various TG for the device.

Fig. 10. Transfer characteristics of the device at different TG workfunction.

The underlapping of gate length at the drain end shows variation in channel resistance. This variation in channel resistance
significantly effects the ON state current of the device. In this regard, Table 2 shows the effect of gate underlapping on device
performance. From Table 2 it is illustrate that the OFF current of the device remain approximately in order of 1017 in all value
of underlap length (UL). Where the ambipolar current and parasitic gate to drain capacitance decreases as underlap length
increases. However, in case of ON state current significant reduction is observed at UL ¼ 20 nm. Hence, Underlap length 15 nm
is considered for Underlap HGD DW TFET for getting optimum performance of the device in terms of ION, IOFF, Iambi and Cgd.

Table 2
Underlap length for HGD DW TFET.

Particular UL ¼ 05 nm UL ¼ 10 nm UL ¼ 15 nm UL ¼ 20 nm UL ¼ 25 nm
ION (A/mm) 1.14
1004 1.14
1004 1.14
1004 8.5
1005 2.16
1005
IOFF (A/mm) 1.9
1016 1.2
1016 1.0
1016 8.0
1017 7.0
1017
Iambi (A/mm) 1.37
1010 7.99
1011 1.14
1013 1.86
1014 8.16
1015
(Cgd (fF/mm) 1.1
1014 8.22
1015 4.20
1015 2.2
1016 1916
1017
 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46 43

Fig. 11. (a) Transconductance for different configurations of TFET having uniform doping profile and (b) Transconductance for different configurations of TFET
having Gaussian doping profile.

5. Analog/RF performance

This section presents a comparative analog/RF performance for all the devices. The device suitability in analog and high
frequency applications are assessed by the analysis of transconductance (gm), gate-to-source capacitance (Cgd), gate-to-drain
capacitance (Cgd), cutoff frequency (fT) and gain bandwidth product (GBP). The analysis of above mentioned parameter is
carried out for the uniform and Gaussian drain doping profile. Transconductance (gm) is an important parameter for analog
circuit design point of view, the parameter should be high in order to obtain an efficient design. Transconductance of a device
is a measure of current driving capability of the device. In Fig. 11(aeb) DW TFET has higher gm than conventional and under
lapped TFET due to higher drain current. The variation in doping profile has no impact on gm as the area of tunneling remains
same irrespective of the doping profile.
Parasitic capacitance plays an important role in device controllability and RF parameter extraction. In this regard, Fig. 12 (a)
shows the variation in gate to drain capacitance with Vgs. The value of Cgd increases with the gate bias due to formation of
inversion charge layer from drain to source. It increases gate to drain coupling. In the same figure the use of dual work
function increases the gate to drain capacitance for higher values of Vgs. Moreover, use of under lapping of gate on drain side
significantly reduces the gate to drain capacitance. Apart of this, the combined use of dual work function, under lapping of

Fig. 12. (a) Cgd characteristics of TFET for different configurations with uniform doping profile and (b) Cgd characteristics of TFET for different configurations with
Gaussian doping.
44 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46

Fig. 13. (a) Cgs characteristics of TFET for different configurations with uniform doping profile and (b) Cgs characteristics of TFET for different configurations with
Gaussian doping.

gate, and hetero gate oxide leads to reduction in Cgd due to increment in barrier between gate and drain. Hence, Cgd is
minimum in case of underlap HGD DW TFET. However, the presence of Gaussian doping in the drain region further reduces
Cgd as shown in Fig. 12 (b) due to increment in depletion width.
Fig. 13(aeb) show the variation of Cgs with Vgs for all the structures. From this figure it can be observed that Cgs reduces
with gate to source voltage because of reduction in channel barrier. In the same, highest value of parasitic capacitance occurs
in the case of DW TFET. Whereas, lowest value of gate to source capacitance is found in underlap HGD DW TFET and underlap
DW TFET for both the drain doping profile (UD and GD). The parameter like (fT), and GBP are very important for the analysis of
RF performance (fT) is the frequency at which, the short circuit current gain of the device falls to unity, which depend upon
ratio of (gm) to the total gate capacitance and can be defined as [14,15]

gm gm
fT ¼  . ffiz 
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  (1)
2pCgs 1 þ 2Cgd Cgs 2 p Cgs þ Cgd

Here, Cgs and Cgd are the gate to source and gate to drain capacitances.
Fig. 14(aeb) shows fT as a function of Vgs for different drain doping profiles. It is clearly seen that fT increases with Vgs
because of increment in gm. However, for higher value of Vgs cut off frequency start decreasing because of sudden increment in

Fig. 14. (a) fT versus Vgs curve with different TFET configurations in uniform doping profile and (b) fT versus Vgs curve with different TFET configurations in
Gaussian doping.
 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46 45

Fig. 15. (a) GBW product for different configurations of TFET having uniform doping profile and (b) GBW product for different configurations of TFET having UD
doping profile.

Cgd and degradation in mobility. In the same figure, the better performance of fT in compression to other structure is obtained
in underlap HGD DW TFET because of significant reduction in Cgd by the presence of under lapping of gate and Gaussian
doping profile. Further, it can be observed that the maximum value of fT for underlap HGD DW TFET occurs at lower value of
gate bias which is beneficial for ultra low power applications. Other important parameter for RF analysis is GBW which
signifies the product of gain and bandwidth at a constant DC gain value 10. It can be defined as

gm
fA ¼   (2)
20p Cgd

Fig. 15(aeb) shows effect of change in gate to source voltage on GBW for all the devices. In this figure, the same observation
is found as in case of fT. From Table 3 and Table 4 the better performance of underlap HGD DW TFET in terms of ON current,
OFF current and RF figure of merits provides utility of the device in ultra low power high frequency applications.

6. Conclusion

In this paper, various key points are observed which are as follows:-

(a) Dual workfunction increases ON-state current of the device by narrowing the tunneling region.

Table 3
Uniform drain doping profile.

Device ION (A/mm) IOFF (A/mm) fT (Hz) GBP (Hz)

Conventional TFET 3.69
1005 8.36
1011 2.42
1010 1.21
1010
DW TFET 1.81
1004 7.29
1010 8.11
1010 2.06
1010
Underlap DW TFET 1.16
1004 8.19
1017 9.90
1010 2.14
1010
Underlap HGD DW TFET 1,14
1004 1.36
1012 1.16
1011 2.23
1010
Underlap Conventional TFET 3.68
1005 4.18
1017 3.30
1010 8.28
1009
Conventional HGD TFET 3.68
1005 3.12
1016 4.00
1010 1.77
1010

Table 4
Gaussian drain doping profile.

Device ION (A/mm) IOFF (A/mm) fT (Hz) GBP (Hz)

Conventional TFET 3.61
1005 2.22
1017 3.84
1010 1.74
1009
DW TFET 1.02
1004 1.34
1017 8.97
1010 2.53
1010
Underlap DW TFET 9.44
1005 8.80
1018 1.25
1011 2.99
1010
Underlap HGD DW TFET 8.86
1005 4.10
1018 1.48
1011 3.98
1010
Underlap Conventional TFET 3.56
1005 3.58
1018 5.90
1010 1.52
1010
Conventional HGD TFET 3.58
1005 1.28
1017 4.93
1010 2.14
1010
46 D.S. Yadav et al. / Superlattices and Microstructures 96 (2016) 36e46

(b) Hetero gate dielectric and gate under lapping on drain side reduces ambipolar current. A huge reduction is noticed by
the combine effect of hetero gate dielectric and gate under lapping. Whereas, the use of Gaussian drain doping profile
with hetero gate and underlap provides entirely suppression of ambipolar behaviour and enhanced RF performance.
(c) Combination of dual workfunction, hetero gate dielectric and under lapping with Gaussian doping profile gives an
optimized performance in terms of ON-state current, OFF-state current and RF performance for. Hence, in future
underlap HGD DW TFET will provide better platform for development of RF circuit for ultra low power applications.
This makes underlap HGD DW TFET as a most suitable device for future technology.

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