Documente Academic
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August 2002
DRAIN SOURCE D
DRAIN (FLANGE) DRAIN
(FLANGE) SOURCE
GATE
DRAIN GATE
GATE
SOURCE
G
TO-220AB DRAIN TO-262AB
TO-263AB
FDP SERIES (FLANGE)
FDB SERIES FDI SERIES
S
Thermal Characteristics
o
RθJC Thermal Resistance Junction to Case TO-220, TO-263, TO-262 0.48 C/W
o
RθJA Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2) 62 C/W
2 o
RθJA Thermal Resistance Junction to Ambient TO-263, 1in copper pad area 43 C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 150 - - V
VDS = 120V - - 1
IDSS Zero Gate Voltage Drain Current µA
VGS = 0V TC = 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage V GS = VDS, ID = 250µA 2 - 4 V
ID = 33A, VGS = 10V - 0.014 0.016
ID = 16A, VGS = 6V, - 0.016 0.024
rDS(ON) Drain to Source On Resistance Ω
ID = 33A, VGS = 10V,
- 0.040 0.048
TC = 175oC
Dynamic Characteristics
CISS Input Capacitance - 5870 - pF
VDS = 25V, VGS = 0V,
COSS Output Capacitance - 615 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 135 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V - 82 107 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 2V VDD = 75V - 11 14 nC
Qgs Gate to Source Gate Charge ID = 33A - 23 - nC
Qgs2 Gate Charge Threshold to Plateau Ig = 1.0mA - 13 - nC
Qgd Gate to Drain “Miller” Charge - 19 - nC
1.2 125
VGS = 10V
1.0
POWER DISSIPATION MULTIPLIER
100
50
0.4
0.2 25
0
0
0 25 50 75 100 125 150 175
25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
2.0
DUTY CYCLE - DESCENDING ORDER
1.0 0.5
0.2
0.1
0.05
THERMAL IMPEDANCE
0.02
ZθJC, NORMALIZED
0.01
PDM
0.1
t1
t2
NOTES:
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10 -5 10-4 10 -3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)
2000
TC = 25 oC
FOR TEMPERATURES
1000 TRANSCONDUCTANCE
MAY LIMIT CURRENT ABOVE 25oC DERATE PEAK
IN THIS REGION CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
I = I25 175 - TC
150
VGS = 10V
100
50
1000 200
10µs STARTING TJ = 25oC
100
DC
1
If R = 0
SINGLE PULSE tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
TJ = MAX RATED If R ≠ 0
TC = 25oC tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0.1 1
Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7515 and AN7517
Figure 6. Unclamped Inductive Switching
Capability
180 180
PULSE DURATION = 80µs VGS = 10V VGS = 7V
DUTY CYCLE = 0.5% MAX 150
150
VDD = 15V
VGS = 6V
ID , DRAIN CURRENT (A)
120 120
TJ = 175oC 90
90
TC = 25oC
60 VGS = 5V
60
TJ = 25oC TJ = -55oC
30
PULSE DURATION = 80µs
30
DUTY CYCLE = 0.5% MAX
0
0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0
VGS , GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)
18 3.0
PULSE DURATION = 80µs PULSE DURATION = 80µs
DRAIN TO SOURCE ON RESISTANCE (m Ω)
17 2.5
VGS = 6V
ON RESISTANCE
16 2.0
15 1.5
VGS = 10V
14 1.0
Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On
Current Resistance vs Junction Temperature
1.4 1.2
VGS = VDS, ID = 250µA ID = 250µA
BREAKDOWN VOLTAGE
THRESHOLD VOLTAGE
NORMALIZED GATE
1.1
1.0
0.8
1.0
0.6
0.4 0.9
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (o C)
Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature
10000 10
VGS , GATE TO SOURCE VOLTAGE (V) VDD = 75V
6
1000
CRSS = CGD 4
WAVEFORMS IN
2 DESCENDING ORDER:
100 ID = 33A
VGS = 0V, f = 1MHz ID = 16A
50 0
Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant
Voltage Gate Currents
VDS BVDSS
tP
VDS
L
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT
tP
0V IAS 0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms
VDS
VDD Qg(TOT)
VDS
L
VGS = 10V
VGS
+
VDD VGS
-
DUT VGS = 2V
0 Qgs2
Ig(REF)
Qg(TH)
Qgs Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
+
VGS
VDD
10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
RθJA (o C/W)
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T –T )
JM A (EQ. 1) 40
P D M = -----------------------------
R θ JA
R
19.84
= 26.51 + -------------------------------------
θ JA (EQ. 2)
( 0.262 + Area )
Area in Inches Squared
R
128
= 26.51 + ----------------------------------
θ JA (EQ. 3)
( 1.69 + Area )
Area in Centimeters Squared
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*190),3))}
.MODEL MmedMOD NMOS (VTO=3.55 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.01)
.MODEL MstroMOD NMOS (VTO=4.2 KP=145 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.9 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=10.1 RS=0.1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
50 DBREAK
dp.dbody n7 n5 = model=dbodymod -
6 RDRAIN
dp.dbreak n5 n11 = model=dbreakmod ESG 8 11
dp.dplcap n10 n5 = model=dplcapmod EVTHRES DBODY
+ 16
+ 19 - 21
LGATE EVTEMP MWEAK
spe.ebreak n11 n7 n17 n18 = 159 8
GATE RGATE + 18 - 6
spe.eds n14 n8 n5 n8 = 1 1 MMED EBREAK
9 22 +
spe.egs n13 n8 n6 n8 = 1 20
RLGATE MSTRO 17
spe.esg n6 n10 n6 n8 = 1 18 LSOURCE
spe.evthres n6 n21 n19 n8 = 1 CIN - SOURCE
8 7
spe.evtemp n20 n6 n18 n22 = 1 3
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A S2A
12 RBREAK
13 14 15
l.lgate n1 n9 = 9.56e-9 8 13
17 18
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 7.71e-9 S1B S2B RVTEMP
13 CB 19
CA
14 IT -
res.rlgate n1 n9 = 95.6 + +
VBAT
res.rldrain n2 n5 = 10 EGS
6
EDS
5
8 8 +
res.rlsource n3 n7 = 77.1
- - 8
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u RVTHRES
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
FDB2532
CTHERM1 TH 6 7.5e-3
CTHERM2 6 5 8.0e-3
CTHERM3 5 4 9.0e-3 RTHERM1 CTHERM1
CTHERM4 4 3 2.4e-2
CTHERM5 3 2 3.4e-2
CTHERM6 2 TL 6.5e-2
6
RTHERM1 TH 6 3.1e-4
RTHERM2 6 5 2.5e-3
RTHERM3 5 4 2.0e-2
RTHERM2 CTHERM2
RTHERM4 4 3 8.0e-2
RTHERM5 3 2 1.2e-1
RTHERM6 2 TL 1.3e-1
5
SABER Thermal Model
SABER thermal model FDB2532
template thermal_model th tl RTHERM3 CTHERM3
thermal_c th, tl
{
ctherm.ctherm1 th 6 =7.5e-3
4
ctherm.ctherm2 6 5 =8.0e-3
ctherm.ctherm3 5 4 =9.0e-3
ctherm.ctherm4 4 3 =2.4e-2
ctherm.ctherm5 3 2 =3.4e-2 RTHERM4 CTHERM4
ctherm.ctherm6 2 tl =6.5e-2
rrtherm.rtherm1 th 6 =3.1e-4
rtherm.rtherm2 6 5 =2.5e-3 3
rtherm.rtherm3 5 4 =2.0e-2
rtherm.rtherm4 4 3 =8.0e-2
rtherm.rtherm5 3 2 =1.2e-1
RTHERM5 CTHERM5
rtherm.rtherm6 2 tl =1.3e-1
}
RTHERM6 CTHERM6
tl CASE
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
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As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. I1