CS 8491 COMPUTER ARCHITECTURE TWO MARK QUESTIONS-UNIT III

CAPE INSTITUTE OF TECHNOLOGY, LEVENGIPURAM

DEPARTMENT OF CSE & IT
CS8491 COMPUTER ARCHITECTURE

TWO MARKS QUESTIONS WITH ANSWERS

1. Define Data path element.

A unit used to operate on or hold data within a processor. In the MIPS
implementation, the data path elements include the instruction and data, the
register file, the ALU, and adders.
2. Define Register file.
A state element that consists of a set of register that can be read and written
by supplying a register number to be accessed.

3. Draw the data path used for fetching instructions and incrementing the
program counter (PC).

4. Give examples for R-format instructions.

add, sub, AND, OR and slt

5. What is the need sign-extend unit ?

Sign-extend unit is used to sign extend the 16-bit off set field in the
instruction to a 32-bit signed value. To increase the size of a data item by replicating

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the high-order sign bit of the original data item in the highorder bits of the larger,
destination data item.

6. Mention the use of ALU in different instructions.

 For load word and store word instructions, the ALU computes the
memory address by addition.
 For the R-type instructions, the ALU needs to perform one of the five
actions (AND, OR, subtract, add, or set on less than), depending on the value
of the 6-bit funct (or function) field in the low-order bits of the instruction.
 For branch equal, the ALU must perform a subtraction

7. Why a Single-Cycle Implementation is not used today?

In this single-cycle design:
The clock cycle must have the same length for every instruction .
 the clock cycle is determined by the longest possible path in the processor
 Clock cycle is too long, performance is poor.
8. What is pipelining?

Pipelining is an implementation technique in which multiple instructions are

overlapped in execution.

9. List the five stages of pipelining in MIPS.

 Fetch instruction from memory(IF)
 Read registers while decoding the instruction. The regular format of MIPS
instructions allows reading and decoding to occur simultaneously. (ID)
 Execute the operation or calculate an address.(EX)
 Access and operand in data memory. (MEM)
 Write the result into a register. (WB)
10. What is hazard? What Are the types?
The situations in pipelining when the next instruction cannot execute in the
following clock cycle. There are three different types of hazards:

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 Structural hazard
 Data hazard
 control hazard

11. Define Structural hazard.

When a planned instruction cannot execute in the proper clock cycle because the
hardware does not support the combination of instructions that are set to execute.

12. Define Data hazard.

When a planned instruction cannot execute in the proper clock cycle because
the data that is needed to execute the instruction is not yet available.

13. Define Control hazard (branch hazard).

When the proper instruction cannot execute in the proper pipeline clock
cycle because the instruction that was fetched is not the one is needed; that is, the
flow of instruction addresses is not what the pipeline expected.
14. What is forwarding (bypassing)?
It is a method of resolving a data hazard by retrieving the missing data element
from internal buffers rather than waiting for it to arrive from programmer-visible
register or memory by adding extra hardware to retrieve the missing item early
from the internal resources is called forwarding (bypassing).

15. What is load-use data hazard?

It is a specific form of data hazard in which the data being loaded by a load
instruction has not yet become available when it is needed by another instruction.

16. Define pipeline Latency.

The number of stages in the pipeline or the number of stages between two
instructions during execution is called pipeline latency.

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17. Define Branch prediction.

A method of resolving a branch hazard that assumes a given outcome for the
branch and proceeds from that assumption rather than waiting to ascertain the
actual outcome is called branch prediction.

18. What are two basic styles of pipeline figure?

 multiple-clock-cycle pipeline diagram
 Single-clock-cycle pipeline diagram.
19. What is the use of single-clock-cycle pipeline diagram.
o It shows the state of the entire data path during a single clock cycle.
o It can be used to know the details of what is happening within the pipeline
diagram during each clock cycle.

20. What is the use of multiple-clock-cycle pipeline diagram

 It is simpler but do not contain all the details as single-clock-cycle
diagram.
 It is used to give overview of pipelining situations.
21. Define nop.
It is an instruction that does no operation to change state.
22. Define flush.
Discarding instructions in a pipeline, usually due to an unexpected event is
called flush.
23. Define branch target address .
It is the address specified in a branch, which becomes the new program
counter (PC) if the branch is taken. In the MIPS architecture the branch target is
given by the sum of the off set field of the instruction and the address of the
instruction following the branch.
24. Define branch taken and branch not taken
Branch taken: A branch where the branch condition is satisfied and the
program counter (PC) becomes the branch target. All unconditional jumps are
taken branches.

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Branch not taken: A branch where the branch condition is false and the
program counter (PC) becomes the address of the instruction that sequentially
follows the branch.

25. What is dynamic branch prediction?

It is an approach to look up the address of the instruction to see if a branch

was taken the last time this instruction was executed. If so, to begin fetching new
instructions from the same place as the last time. ie, Prediction of branches at
runtime using runtime information.

26. Define Branch prediction buffer (branch history table).

It is a small memory indexed by the lower portion of the address of the
branch instruction and that contains one or more bits indication whether the
branch was recently taken or not.

27. What is 1-bit prediction scheme ?

If the prediction turns out to be wrong, the incorrectly predicted instructions
are deleted, the prediction bit is inverted and stored back, and the proper
sequence is fetched and executed. This is called 1-bit prediction scheme.

28. What is the drawback of 1-bit prediction scheme?

Even if a branch is almost always taken, we can predict incorrectly twice,

rather than once, when it is not taken.

29. What is 2-bit prediction scheme ?

In a 2-bit scheme, a prediction must be wrong twice before it is changed.

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30. What is branch delay slot ?

The slot directly after a delayed branch instruction, which is filled by an
instruction that does not affect the branch is called branch delay slot.

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