6476
9, SEPTEMBER 2016
Dual Flying Capacitor Active-Neutral-Point-Clamped
Multilevel Converter
Roozbeh Naderi, Student Member, IEEE, Arash Khoshkbar Sadigh, Member, IEEE,
and Keyue Ma Smedley, Fellow, IEEE
Abstract—Hybrid multilevel converters combine features of con-
ventional multilevel topologies to provide an acceptable tradeoff
between the advantages and disadvantages of these converters.
For many industrial applications, common dc link is a require-
ment that limits the choice of topologies to neutral point clamped
(NPC) and flying capacitor multicell (FCM) hybrid types. This
paper investigates the operation of a hybrid five-level topology and
proposes a modulation method that takes the advantage of the
combined features of NPC and FCM. The dual flying capacitor
(FC) active-neutral-point-clamped (DFC-ANPC) converter pro-
vides certain advantages such as natural soft switching of line
frequency switches, elimination of the transient voltage balanc-
ing snubbers, and a more even loss distribution. Simulation results
and experimental verification of the five-level DFC-ANPC con-
verter are presented to validate the performance of the converter
as well as the applied modulation technique.
Index Terms—Flying capacitor (FC), multilevel converter,
neutral point clamped (NPC).
I. INTRODUCTION
EDIUM-VOLTAGE multilevel converters have found
M wide use in applications such as motor drive, grid-tied
inverter and rectifier, and medium voltage dc (MVDC) [1], [2].
The main motivation for the use of multilevel converters is to
achieve higher voltage capability with commercially available
lower voltage semiconductor devices. Typical fast switches such
as IGBTs and IGCTs with voltage ratings up to 6.5 kV can
reliably operate at about 4 kV [3], [4]. One way to handle higher
voltage applications is direct series connection of switching
devices; however, this solution has inherent transient voltage
balancing and high dv/dt issues. Multilevel converters thus rose
to the occasion. They also have the added advantages of better
waveform quality, lower total harmonic distortion (THD), and
Manuscript received May 14, 2015; revised August 26, 2015; accepted
November 2, 2015. Date of publication November 18, 2015; date of current
version March 25, 2016. Recommended for publication by Associate Editor
J. R. Rodriguez.
R. Naderi is with the Department of Electrical Engineering and Com-
puter Science, University of California Irvine, Irvine, CA 92697 USA (e-mail:
rnaderi@uci.edu).
A. K. Sadigh was with the Department of Electrical Engineering and
Computer Science, University of California Irvine, Irvine, CA 92697
USA. He is now with Extron Electronics, Anaheim, CA 92805 USA (e-mail:
akhoshkb@uci.edu).
K. M. Smedley is with the Department of Electrical Engineering and Com-
puter Science, University of California Irvine, Irvine, CA 92697 USA, and
also with One-Cycle Control, Inc., Irvine, CA 92618 USA (e-mail: smedley@
uci.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2015.2501401
0885-8993 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO.
lower electromagnetic interference (EMI) over their two-level
counterparts [5].
For applications such as MVDC, a common dc link among the
three phases is a requirement. For some other applications such
as motor drive, a common dc link offers the option of eliminating
or reducing the complexity of phase-shift transformer at the
passive front end. For certain configurations such as active front
end, typically a common dc link is required. In addition, less
protection and clamp circuit is required for a single common dc
link in contrast to several dc links [5]–[9].
Conventionally, two multilevel converter topologies, neutral
point clamped (NPC) [10] and flying capacitor multicell (FCM)
[11], [12], are known to provide a common dc link. NPC and its
enhanced variety, active NPC (ANPC), are widely used in indus-
try for three-level applications [7]. For higher levels, however,
NPC encounters the critical dc-link voltage balancing problem,
excessive number of clamping diodes, and unbalanced loss dis-
tribution among semiconductor devices. FCM stands out as an
alternative for higher levels with balanced flying capacitor (FC)
voltage and excellent loss distribution [9]. The disadvantage of
FCM topology, however, is the excessive number of capacitors
in higher levels. Capacitors are usually avoided due to high
initial price, maintenance and replacement surcharges, and low
reliability [13].
Hybrid multilevel converter topologies with a common dc
link combine some features of NPC and FCM that opens the
possibilities to take advantages of both topologies. Among hy-
brid topologies, the five-level FC active NPC (FC-ANPC) pro-
vides an acceptable compromise between cost and performance
and consequently, found its way to industrial applications [14].
FC-ANPC provides a balanced dc-link voltage by using only
one FC at the cost of four additional switches per phase com-
pared to the conventional basic topologies [15]. It offers a good
tradeoff compared to the disadvantages of FCM and NPC con-
verters. One drawback of the FC-ANPC topology is the four
pairs of series-connected switches, which, although operating
at the line frequency, require transient voltage balancing snub-
bers [16]. The uneven loss distribution among semiconductor
devices is another major issue that limits the nominal power of
this converter.
In this paper, the operation of a hybrid multilevel converter
topology, dual FC-ANPC (DFC-ANPC), proposed originally in
[17], [18], is investigated in Section II. Certain features such
as zero-voltage switching of line frequency switches are pre-
sented, which reduces the switching loss and eliminates the
need for transient voltage balancing snubbers. In Section III,
carrier-based and non-carrier-based modulation techniques for
NADERI et al.: DUAL FLYING CAPACITOR ACTIVE-NEUTRAL-POINT-CLAMPED MULTILEVEL CONVERTER 6477

TABLE I
SWITCHING STATES OF THE FIVE-LEVEL DFC-ANPC CONVERTER

Level State S1 S2 S3 S4 S5 S6 C1 C2

+2E +2E 1 1 1 1 1 0 N.A. N.A.

+E +EP 1 0 1 1 1 0 i x > 0 Charge N.A.
i x < 0 Discharge
+E0 0 1 1 1 1 0 i x > 0 Discharge N.A.
i x < 0 Charge
0 0P 0 0 1 1 1 0 N.A. N.A.
00 0 0 1 1 1 1 N.A. N.A.
0N 0 0 1 1 0 1 N.A. N.A.
−E −E0 0 0 1 0 0 1 N.A. i x > 0 Charge
i x < 0 Discharge
−EN 0 0 0 1 0 1 N.A. i x > 0 Discharge
i x < 0 Charge
−2E −2E 0 0 0 0 0 1 N.A. N.A.

S 1 , S 2 , S 3 , S 4 are switched complementary to S 1 , S 2 , S 3 , S 4 , respectively.

i x > 0 represents outbound current and i x < 0 represents inbound current.
N. A. = Not Affected.

voltage, i.e., 2E, which may be realized by two switches in

Fig. 1. Five-level DFC-ANPC topology.
the five-level DFC-ANPC converter are presented. Section IV
briefly presents the generalized case of DFC-ANPC. Section
V provides a comparison between selected five-level converter
topologies featuring a common dc link. Simulation and exper-
imental verification of the operation of five-level DFC-ANPC
are provided in Section VI.
II. DFC-ANPC TOPOLOGY AND OPERATION
The five-level DFC-ANPC topology, as shown in Fig. 1, can
be viewed as two three-level FCM converter units connected
to the output through line frequency switches S5 and S6 . The
top FCM unit uses high-frequency switches S1 , S1 , S2 , and S2
along with capacitor C1 to generate the positive half cycle of the
pulsewidth-modulated (PWM) waveform. The generated volt-
age is transferred to the output through S5 during the positive
half cycle. During the negative half cycle, the bottom FCM
unit, consisting of S3 , S3 , S4 , S4 , and C2 , generates the PWM
waveform, which is transferred to the output through S6 .
The voltage of the FCs, C1 and C2 , can be individually bal-
anced through the existing redundant states of each FCM unit.
Table I lists the switching states for the DFC-ANPC converter
and the effect of each state on the FCs voltages. The redundant
states for level +E, i.e., +EP and +E0, are used to balance C1 ’s
voltage. Similarly, the redundant states for level −E, i.e., −E0
and −EN, are used to balance C2 ’s voltage.
During the normal operation, the operating voltage of both
FCs in the DFC-ANPC five-level converter is a quarter of the
dc-link voltage, which means E. This results in clamping the
voltage stress of high-frequency switches to E. For line fre-
quency switches, however, voltage stress is half of the dc-link
series, as shown in Fig. 1.
An important feature of this topology is the “soft cycle com-
mutation” between the positive and negative half cycles. States
0P, 0N, and 00, as listed in Table I, can generate level 0 ei-
ther through the top part switches S1 , S2 , S5 , the bottom part
switches S3 , S4 , S6 , or both. The inbound and outbound current
paths in each case are shown in Fig. 2. At the transition from 0P
to 00, S6 must turn on while the voltage across it is near zero.
When switching back from 00 to 0P, S6 must turn off while
the voltage across it is near zero. In a similar fashion, the volt-
age across S5 is near zero when switching between 00 and 0N.
Therefore, if 00 is used as an intermediate state between 0P and
0N, line frequency switches S5 and S6 will hold zero-voltage
switching operation at all times. So, when the phase voltage half
cycle changes, the operating FCM unit can be softly detached
from output, and the operation can be softly handed over to the
other FCM unit. An advantage of this phenomenon is the elim-
ination of switching loss on S5 and S6 . More importantly, no
transient voltage balancing snubber is required when realizing
S5 and S6 by series-connected switches. Note that the blocking
mode voltage balancing resistors may still be required due to
the switching devices’ cutoff current tolerance [16].
III. MODULATION TECHNIQUES
Various modulation techniques may be adapted for the DFC-
ANPC topology. Carrier-based modulation with sinusoidal or
modified reference as well as non-carrier-based techniques such
as space vector modulation (SVM) and selective harmonic elim-
ination (SHE) may be used to generate the gate signals [5], [19].
The choice of a modulation technique is mostly a tradeoff among
the requirements of the application, complexity of the software,
and relative cost of the control hardware. For the DFC-ANPC
topology, the main requirement is to ensure the FC voltages are
balanced and the neutral point voltage is maintained at half of
the dc-link voltage.
6478
Fig. 2. Soft cycle commutation concept. Inbound and outbound current paths for states (a) 0P, (b) 00, and (c) 0N.
A. Carrier-Based Modulation
Carrier set’s arrangement and reference waveform’s shape
are the main sources of varieties in carrier-based modulation
techniques for multilevel converters.
As for carrier set’s arrangement, level-shifted carriers (LSCs)
and phase-shifted carriers (PSCs) are the two main categories
that are suitable for diode-clamped and multicell structures.
Two members in the LSC family, alternative phase opposition
disposition (APOD) and phase disposition (PD), are known to
generate the best results for singe-phase and three-phase con-
verters, respectively [19]. PSC in its original form has been
shown to generate a multilevel PWM waveform that matches
with APOD [20]. Also a modified version of PSC with dynamic
phase shift has been shown to match with PD [21].
The reference for single-phase applications is usually a sim-
ple sinusoidal waveform. For three-phase applications, a variety
of reference waveforms are available due to the possibility of
common-mode injection in three-phase structure. This flexibil-
ity has been used to serve different purposes such as increased
dc-link utilization, lower THD, lower loss, and neutral point
voltage control [22], [23].
For the DFC-ANPC converter, a hybrid modulation technique
is required due to the hybrid structure of the topology. Fig. 3
illustrates the carrier-based modulation technique using PSC
with sinusoidal reference for single-phase case. It is intuitive
to separate the operation to positive and negative half cycles,
since each one is generated with an independent three-level
FCM unit. The gate signals for each FCM unit is then generated
using PSC to provide natural voltage balancing for the FCs [24].
Switches S5 and S6 must be on during the positive and negative
half cycles, respectively, to connect the associated FCM unit to
the output. Note that, soft cycle commutation, S5 and S6 can
be achieved by a short duration of overlap at transition from
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016
positive half cycle to negative half cycle and vice versa. The
PWM waveform generated at the output matches the APOD
scheme.
For three-phase cases, a similar approach may be adopted
except that, to generate a PD scheme equivalent, the positive
half cycle carriers should hold π/2 phase shift with respect to
the negative half-cycle carriers. Also, the carriers incorporate
a dynamic phase shift, which always adds up by π/2 at the
carrier band transitions for sampled reference waveforms [21].
For the reference waveform, centered space vector PWM (CSV-
PWM) sampled at half PD carrier period can provide similar
performance as SVM [22], [25]. Fig. 4 illustrates the modula-
tion technique using sampled CSV-PWM along with modified
PSC for the DFC-ANPC converter. It is important to choose a
reference waveform with balanced common-mode injection to
maintain the neutral point’s voltage balance. Also, higher fre-
quency and lower amplitude of the injected common mode can
decrease the neutral point’s voltage ripple.
B. Non-carrier-based Modulation
For non-carrier-based modulation techniques such as SVM
and SHE, the five-level PWM waveform may be generated first
and then decomposed to the required switching signals. In this
procedure, as shown in Fig. 5, the five-level PWM waveform
is first separated to positive and negative half-cycle three-level
PWMs. Each half cycle is then decomposed to switching signals
either through a state machine decoder or an active balancing
algorithm. The state machine decoder ensures that transitions
are uniformly distributed between the switches and, therefore,
provides natural voltage balancing [26]. The active balancing
algorithm compares the FCs voltages to their target value at
each transition. Based on this comparison, it decides whether the
NADERI et al.: DUAL FLYING CAPACITOR ACTIVE-NEUTRAL-POINT-CLAMPED MULTILEVEL CONVERTER
Fig. 3. Carrier-based modulation using PSC with sinusoidal reference for
single-phase converters. (a) Reference and carriers arrangement. (b) Gate sig-
nals. (c) Output waveform.
capacitor needs to be charged or discharged. Then considering
the direction of output current at the moment, it determines
which redundant state to switch to, to provide the charging or
discharging and, therefore, to balance the FCs voltages [27].
To provide soft cycle commutation, cycle separation unit
needs to know the half cycle change before it actually occurs.
This cannot be extracted from the five-level PWM signal itself,
since the half-cycle change cannot be detected until the first
transition in the next half cycle occurs when it is too late to
generate the 00 state. Therefore, PWM modulator should notify
the half-cycle separator block of half-cycle change in advance.
It is important to note that this procedure is independent of the
adopted modulation technique. Therefore, it can be used with
carrier-based modulation techniques or non-carrier-based ones.
This should be a good alternative when the complexity of the
carrier-based technique is relatively high, e.g., for PD scheme.
6479
Fig. 4. Carrier-based modulation using modified PSC with sampled CSV-
PWM reference for three-phase converters. (a) Reference and carriers arrange-
ment. (b) Gate signals. (c) Output waveform.
IV. GENERALIZATION
The DFC-ANPC topology can be generalized to higher num-
ber of levels. The number of levels should be odd and greater
than or equal to five, due to the symmetry of the topology
with respect to the neutral point. Fig. 6 shows the generalized
topology for an N-level converter. The top and bottom units
are (N + 1)/2-level FCM converters that are connected to the
output through SN and SN +1 . Each FCM unit can individually
balance the associated FCs during its operating half cycle, us-
ing the available redundant states. SN and SN +1 are realized
by (N − 1)/2 switches in series without any transient voltage
balancing snubber due to the soft cycle commutation advantage
of the DFC-ANPC converter. Modulation techniques similar to
those mentioned in Section III may be used for the generalized
case.
6480 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016

TABLE II
COMPARISON OF FIVE-LEVEL TOPOLOGIES

Topology Capacitors Switches Diodes Loss Comments

Distribution

NPC 0 24 36 Poor Low switch count

High diode count
Unbalanced dc-link voltage
FCM 18 24 0 Excellent High capacitor count
Low switch count
SMC 6 36 0 Good Low capacitor count
High switch count
FC-ANPC 3 36 0 Fair Very low capacitor count
High switch count
Low-frequency series switches
CFC-ANPC 2 34 0 Poor Very low capacitor count
High switch count
DFC-ANPC 6 36 0 Good Low capacitor count
High switch count
Soft-switched series switches

Fig. 5. Non-carrier-based modulation for a phase leg of DFC-ANPC converter

using: (a) state machine decoder and (b) active balancing algorithm.
Fig. 6. Generalized topology of N-level DFC-ANPC.
V. COMPARISON
This section provides a general comparison between the DFC-
ANPC topology and other five-level converter topologies with
a common dc link. Table II lists the number of capacitors,
switches, and diodes for a three-phase five-level converter for
NPC, FCM, stacked multicell (SMC), FC-ANPC, common FC-
ANPC (CFC-ANPC), and DFC-ANPC topologies.
The advantage of NPC is the use of low number of switches
and no FCs in the circuit topology. However, excessive num-
ber of diodes, uneven loss distribution among semiconductor
switches, and unbalanced voltage of dc-link capacitors make
five-level NPC topology less of an option for MV converter.
The 12 diodes per phase leg might not be a big cost and reli-
ability burden alone, but the added fact that each diode should
have its own cooling system adversely affects the total cost of
this topology. Loss distribution among semiconductor switches
at low modulation index maybe improved through space vector
redundancies but the problem persists in high modulation index.
For the active-front-end configuration, NPC converter has been
shown to have the ability to balance dc-link capacitors. Yet, the
cost is the limitation on power factor, which is unfavorable for
the main target application of regenerative motor drives [28].
The FCM converter has the advantages of low switch count,
balanced FCs voltages, and uniform loss distribution. The main
problem with this topology is the excessive number of capaci-
tors, which are expensive, less reliable, and require maintenance
and replacement.
In an attempt to decrease the number of capacitors in FCM
converter, SMC topology were developed, which requires only
two capacitors per phase leg and also provides good loss dis-
tribution between switches [26], [29], [30]. A drawback of this
topology is the need for four extra switches per phase leg. More
importantly, the use of bidirectional switches for connecting the
neutral point to the output degrades the loss distribution at low
modulation indexes.
In contrast to the aforementioned topologies, FC-ANPC is
a viable alternative [15]. One FC per phase leg and balanced
voltages of main dc-link capacitors are the advantages of this
topology. The disadvantages include high switch count and four
pairs of series-connected switches per phase leg, which require
transient voltage balancing snubbers. The added snubber loss
is small since the associated switches are switching at line fre-
quency. Another disadvantage of this topology is the uneven loss
NADERI et al.: DUAL FLYING CAPACITOR ACTIVE-NEUTRAL-POINT-CLAMPED MULTILEVEL CONVERTER 6481

TABLE III
SIMULATION AND EXPERIMENT PARAMETERS

Circuit Parameter Value

Simulation dc-link voltage (V d c ) 16 kV

Experiment dc-link voltage (V d c ) 400 V
DC-link capacitors (C d c ) 1.6 mF
FCs (C x x ) 400 μF
Phase modulation index (M) 1
Phase fundamental frequency (f o ) 50 Hz
Phase switching frequency (f s ) 1650 Hz
Load inductance (L l o a d ) 15 mH
Load resistance (R l o a d ) 18 Ω
Balance booster inductance (L b o o s t ) 1.85 mH
Balance booster capacitance (C b o o s t ) 20 μF
Balance booster resistance (R b o o s t ) 1.5 Ω

CSV-PWM with modified PSC used for modulation.

Load configuration is Y.

distribution. The four switches of the FCM unit are operating at

high frequency at all times, while the other eight switches are
conducting only half a cycle and switching at line frequency.
Despite the disadvantages, FC-ANPC has provided a realistic
tradeoff and has been commercially used for five-level medium-
voltage motor drive application [9], [14].
The CFC-ANPC topology proposed in [31] shares two ca-
pacitors between all three phases and, therefore, greatly reduces
the number of capacitors. The number of switches is higher than
NPC and FCM but lower than the other topologies in the list.
The disadvantage of this topology is its uneven distribution of
losses, since the common switches must conduct the current of
all three phases.
The DFC-ANPC topology requires 12 switches per phase leg,
which is in this aspect similar to SMC and FC-ANPC topologies.
However, compared to FC-ANPC, it provides a more even loss
distribution among semiconductor switches. As can be seen in
Figs. 3(b) and 4(b), the high-frequency transitions are evenly dis-
tributed among top and bottom FCM units. Therefore, switching
loss is distributed among eight switches. Also, all the switches
are operating in half a cycle, which provides a better distribution
of conduction loss. Since each switch has an individual cooling
system, a better loss distribution means each switch can operate
at higher current. Therefore, lower current derating is required
and the topology is expected to provide higher nominal power
compared to FC-ANPC. Moreover, the series-connected switch
pair S5 and S6 does not need transient voltage balancing snub-
bers due to the soft cycle commutation concept explained in
Section II. In addition to the lower cost, this will slightly de-
Fig. 7. Simulation results. (a) Phase voltages and currents. (b) Line voltages.
crease the total switching loss compared to the FC-ANPC case.
The advantage of soft cycle commutation is more prominent
for higher levels where more series-connected switches are re-
quired. These advantages come at the cost of an additional FC VI. SIMULATION AND EXPERIMENTAL VERIFICATION
per phase leg compared to the FC-ANPC topology. Neverthe- To verify the performance of DFC-ANPC converter, a
less, since each capacitor is operating half cycle, the rms current 5-MVA three-phase, 10-kV, five-level model has been simulated
passing through each is 2 times smaller than that of the single with PSIM software. The model has been tested under different
capacitor of FC-ANPC. In other words, the capacitor loss is also situations including high and low modulation indexes and dif-
distributed among two capacitors, and therefore, longer lifetime ferent modulation techniques, output powers, power factors etc.
and better reliability are expected from each of them [13]. According to the obtained simulation results, the DFC-ANPC
6482 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016

Fig. 8. Simulation results. (a) FC voltages. (b) Neutral point voltage.

Fig. 10. Experimental results. (a) Phase voltages and currents. (b) Line
voltages.

converter performs well in all the situations generating the ex-

pected output waveform and keeping the capacitors voltages
balanced. In this paper, the simulation results for a typical case
with parameters listed in Table III is presented. Fig. 7(a) shows
the five-level phase voltages and currents, and Fig. 7(b) shows
the nine-level line voltages with a THD of about 17%. The six
FCs’ voltages, shown in Fig. 8(a), are well balanced at 4 kV
with a ripple amplitude of about 5%. As shown in Fig. 8(b),
despite the common-mode injection due to the applied modula-
tion technique, the neutral point voltage with respect to dc link’s
negative is fixed at 8 kV with a small ripple.
A small-scale three-phase prototype has been implemented to
experimentally verify the performance of the DFC-ANPC con-
verter. Fig. 9 shows the implemented converter and experiment
setup. The switching signals are generated by a TMS320F28335
DSP microcontroller and supplied to the switch modules through
a buffering and dead time generation circuit. The experiment
Fig. 9. Prototype of the DFC-ANPC converter and experimental setup. has been setup with similar circuit parameters as the simulation,
listed in Table III, except for the voltage that has been scaled
NADERI et al.: DUAL FLYING CAPACITOR ACTIVE-NEUTRAL-POINT-CLAMPED MULTILEVEL CONVERTER 6483

down by 40 times. Consequently, the currents and the power

are scaled down by 40 and 1600 times, respectively. However,
the percentage of voltage ripple for FCs and the neutral point
remain the same.
The experimental five-level phase voltages and currents and
the nine-level line voltages are shown in Fig. 10. In practice
the FCs should be precharged to the target value either through
the ac side or precharge circuitry to avoid overvoltage on the
switches at the startup transient. Yet the startup transient with-
out precharging shown in Fig. 11(a) illustrates the FC voltages
evolving to their target value. The steady state FC voltages are
shown in Fig. 11(b). It can be seen that the FCs voltages are
balanced at 100 V with a ripple of about 5%, similar to the sim-
ulation case. For the neutral point voltage shown in Fig. 11(c),
similar to the simulation, the ripple is very small. But an aver-
age voltage drift of about 1.5 V can be observed that is due to a
small imbalance in the experimental setup. In this case, an active
neutral point voltage control can solve this issue [5], [23].

VII. CONCLUSION
In this paper, the operation of the DFC-ANPC topology has
been investigated and the associated modulation techniques have
been presented and verified by simulation and experimental re-
sults. Compared to the commercialized five-level FC-ANPC
converter, the DFC-ANPC converter under the proposed modu-
lation method has the following features:
1) provides more even loss distribution among semiconduc-
tor switches and thus higher power rating is expected;
2) eliminates the transient voltage balancing problem of
series-connected switches;
3) decreases the switching loss and thus slight improvement
in efficiency is expected;
4) can be extended to higher levels without transient voltage
balancing problem.
The comparison presented in this paper is mostly based on
abductive reasoning and not quantified. For future work, a com-
parative study of the FC-ANPC and DFC-ANPC thermal models
will verify the thermal performance superiority and provide an
estimation of the amount of extra power processing capability.

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Roozbeh Naderi (S’12) received the B.S. degree in
electrical engineering from the University of Mazan-
daran, Babolsar, Iran, in 2005, and the M.S. degree
in electrical engineering from the Iran University of
Science and Technology, Tehran, Iran, in 2009. He
is currently working toward the Ph.D. degree in the
Department of Electrical Engineering and Computer
Science, University of California Irvine, CA, USA.
His current research interests include power elec-
tronics circuits, multilevel converters, and energy
storage systems.
Arash Khoshkbar Sadigh (S’09–M’15) received the
B.S. and M.S. degrees (both with first-class Hons.) in
electrical engineering from the University of Tabriz,
Tabriz, Iran, in 2007 and 2009, respectively, and the
Ph.D. degree in electrical engineering from the Uni-
versity of California, Irvine, USA, in 2014.
He was with AranNagshAra Consultant Engineer-
ing Company, Tabriz, from 2007 to 2010, where he
was involved in the design of power transmission and
distribution lines. During summer 2012 and 2013, he
was an Intern with the RTDS Advanced Technology
Laboratory, Southern California Edison. In 2015, he joined Extron Electronics,
Anaheim, CA, USA, as a Power Electronics Design Engineer. He is the author or
coauthor of more than 50 journal and conference papers and one book chapter,
and he holds one patent. His current research interests include power electronics
circuits, multilevel converters and their applications in power grid and system,
power quality, and flexible ac transmission system devices.
Dr. Khoshkbar Sadigh was selected by the University of Tabriz as the Dis-
tinguished Student in 2006. In 2007, he joined the Iran’s National Elites Foun-
dation as he ranked second in the National Entrance Exam for graduate study
in electrical engineering with a major in power engineering. He was a recipient
of an Outstanding Presentation Award from the Annual IEEE Applied Power
Electronics Conference and Exposition in 2013.
Keyue Ma Smedley (S’87–M’90–SM’97–F’08) re-
ceived the B.S. and M.S. degrees in electrical
engineering from Zhejiang University, Hangzhou,
China, in 1982 and 1985, respectively, and the M.S.
and Ph.D. degrees in electrical engineering from the
California Institute of Technology, Pasadena, CA,
USA, in 1987 and 1991, respectively.
She is currently a Professor in the Department of
Electrical Engineering and Computer Science, Uni-
versity of California, Irvine (UCI), USA, the Direc-
tor of the UCI Power Electronics Laboratory, and
a Cofounder of One-Cycle Control, Inc., Irvine. Her current research inter-
ests include high-efficiency dc–dc converters, high-fidelity class-D power am-
plifiers, single-phase and three-phase PFC rectifiers, active power filters, in-
verters, V/VAR control, energy storage system, and utility-scale fault current
limiters. She is an Inventor of One-Cycle Control and the Hexagram power
converter. Her work has resulted in more than 160 technical publications,
more than 10 U.S./international patents, two start-up companies, and numerous
commercial applications.
Dr. Smedley is a Recipient of the UCI Innovation Award in 2005. Her
work with One-Cycle Control, Inc., has won her the Department of the Army
Achievement Award in the Pentagon in 2010.