Journal of Advances in Communication Engineering and Its Innovations

Volume 4 Issue 2

Hw/Sw Co-Design Implementation on Zedboard

Shruti Vinayak Shet*, Dr. Nitesh Guinde

Student*, Associate Professor**
Department of Electronics and Telecommunication
Goa College of Engineering mPonda, India
Corresponding author’s email id: shrutishet908@gmail.com, nitesh.guinde@gec.ac.in

Abstract
Field Programmable Gate Arrays is an empowering technology for
application-oriented systems, providing a means for rapid prototyping and
evaluation, as well as algorithm acceleration. Many FPGA vendors have
recently started experimenting with embedded processors in their devices, like
Xilinx with ARM Cortex A cores, together with programmable logic cells.
These are known as Programmable System on Chip (PSoC). These ARM cores
(embedded in the Processing System or PS) communicate with the
programmable logic cells (PL) using ARM standard AXI buses. The hardware
setup used in this project is Zedboard along with ADFMCOMMS2-EBZ is a
high speed analog module which has preinstalled IIO OSCILLOSCOPE and
GNU RADIO software. The IIO OSCILLSCOPE Linux Application supports
different plots for real time processing and analyzing the signals obtained
from the antennas of the analog module. This application captures the desired
incoming RF signal in the IIO OSCILLOSCOPE wherein the entire
computation is run on to the PS, while the FPGA fabric remained idle during
this process. During profiling it was found that the most computational
expensive block is Fast Fourier transform (FFT) block that took a longer time
to display the output. So to lessen the computation time we transfer the FFT
block on to the PL side via AXI buses to communicate to the PS side of the
board. Due to the parallel nature of FPGA the capability to calculate large
mathematical calculation can be made smoother and in lesser time period.

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

Key Words: Field Programmable Gate Arrays, Programmable System on

Chip, IIO OSILLOSCOPE, Zedboard Fast Fourier transform, AXI buses.

INTRODUCTION The Zynq®-7000 SoC family incorporates

System-on-a-Chip (SoC) technology was the software programmability of an
designed for applications that require all ARM®-based processor with the hardware
components implemented at the chip level programmability of an FPGA, enabling
and also to maintain the smaller key analytics and hardware acceleration
dimension. This refers to integrating all while integrating CPU, DSP, ASSP and
components of an electronic system into a mixed signal functionality on a single
single integrated circuit. This chip can device.
contain a variety of signals including
digital, analog, mixed-signal, and often RF ZYNQ-7000 ARCHITECTURE
functions, and it does all in one single A. Main Purpose of Zedboard
chip. The recent development in the SoC The real reason for choosing the Zedboard
family is the Programmable Systemon- as the prime element in the project was to
Chip devices which are designed to explore the H/W S/W compatibility
replace multiple traditional MCU-based between the PS and PL and the ease to
system components with one, low cost modify the programmable blocks with the
single-chip programmable device. PSoC, help of necessary software tools such as
as the name suggests devices that mainly Xilinx Vivado and the Hardware
include configurable blocks of analog and Description Language (HDL) such as
digital logic, as well as programmable VHDL and Verilog .
interconnects. This architecture not only
allows the user to create customized B. ZYNQ- 7000 SOC Specifications
peripheral configurations that match the The Zedboard is an evaluation and
requirements of each individual development board based on the Xilinx
application and also provides integration Zynq-7000 Protactible Processing
of a fast CPU, Flash program memory, Platform. Interfacing a dual Cortex-A9
SRAM data memory, and configurable I/O Processing System (PS) with 85000
that are binded together in a range of Series-7 Programmable Logic (PL) cells,
convenient pinouts and packages. this Zynq-7000 can be marked for a
broader use in many applications. The

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 Journal of Advances in Communication Engineering and Its Innovations
Xilinx Vivado suite offers the designer a
variety of environment to work on the
zedboard that includes flexible design,
support for designing and testing of IP
blocks which can be used and reused for
various design approach. The Zedboard’s
powerful mix of on-board peripherals and
expansion capabilities make it an ideal
platform for both starter and experienced
designer. This board contains everything
that is necessary for any developer to
create a Linux, Android, Windows® or
other OS/RTOS based design.
The Zynq SOC chip consist of 2 major
sections
PS: Processing System
 Dual ARM Cortex-A9 processors,
866 MHz to 1GHz frequency.
 Multiple peripherals
 Hard silicon core
 Dedicated DDR memory controller
PL: Programmable Logic
 Logic cells – 28k-44k
 AD converter – two 12 bits
 Provides the user the ability to
develop their own custom logic or
IP which can work in conjunction
with the software running on
processor core.
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Volume 4 Issue 2
The essential part of the Zedboard is that
the PS and PL are both linked by a series
of interfaces which follow the AMBA
AXI4 interconnect standard as seen in Fig-
1. This interface enables a designer to
implement custom logic blocks according
to their requirements in the PL which can
then be connected to the PS and also
extend the range of peripherals that are on
the AXI bus are easily available and are
visible on to the processor’s memory map
through the use of software.
C. AD9361- ANALOG DEVICES
The AD-FMComms2-EBZ is an FPGA
Mezzanine Cards (FMC) board for
AD9361,a highly integrated RF Agile
Transceiver™. The purpose of the AD-
FMComms2-EBZ is to provide an RF
platform which shows the greater extent
performance of the AD9361.
The expected performance displayed by
this platform according to the datasheet
specification is up to 2.4GHz frequency.
This device combines an RF front end with
a flexible mixed- signal baseband section
and integrated frequency synthesizers,
simplifying design-in by providing a
configurable digital interface to a
processor or FPGA as seen in Fig-2
Zedboard is interfaced with AD9361.
 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

Figure: - 1 Zynq-7000 SOC Architecture internal

Fig-2 Hardware setup of Zedboard and AD9361 RF Device

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

D. ADI IIO OSCILLOSCOPE tuning and filter profiles of a particular RF

The ADI IIO OSCILLOSCOPE is a
product by Analog Devices, Inc. that uses
libiio to interface with Linux IIO Devices
developed by Analog Devices. It is
basically a Linux application, which
demonstrates to interface with various
evaluation boards i.e. AD9361 From
within a Linux Application. This
application also supports plotting of
various RF captured data in 4 different
modes (time domain, frequency domain,
constellation and cross correlation) as
observed in Fig-3.This is a great tool for
testing, debugging and fine tuning of an
RF system. Parameters such as gain,
signal can be observed and modified on
the fly.
E. Fast Fourier Transform IP Core
A Fast Fourier Transform (FFT) is
basically an algorithm that computes the
direct Fourier Transform (DFT) of a
particular sequence, or its inverse (IDFT).
Fourier analysis converts a desired signal
from its original domain (often time or
space) to a representation in the frequency
domain and vice versa. The DFT obtained
above by decomposing sequence of values
into different components of different
frequencies.

Fig-3 Waveform generated by an Incoming RF signal

detected by the antennas.

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

The Fast Fourier Transform code that is
used in this project is composed of a series
of stages. These stages right from the start
are split into an even and odd stage. The
first stage is numbered N according to the
size it represents, the second stage is
labelled as N/2, N/4 and so on down to
N=8 as seen in the Fig-5. Internal to each
FFT stages is a butterfly and complexes
multiply stage. These FFT stages are a
form of decimation in frequency FFT, the
coefficients are alternated between 2
stages. The even stages get all the even
coefficients, and the odd stages get all the
odd coefficients. Each stage spends the
first N/4 clocks storing its inputs into the
allocated memory, and then the next N/4
clocks pairing a stored input with a single
external input, so this value obtained
becomes input to the butterfly. Later on
the butterfly coefficients is read from
small ROM table.
Making use of synchronization pulse to
keep track of the butterfly output and a
counter which is used to keep things
aligned, produces the first pulse, next N/4
clock cycles will produce valid butterfly
outputs. The left output is sent
immediately to the next FFT stage, where
the right output is saved in the memory.
Once this cycle is complete the butterfly
outputs will be invalid for the next N/4
clock cycles. During this clock cycles, the
FFT stage output’s data that had been
stored in the memory as can be analyzed in
Fig-5. The complex multiply formed in the
internal of butterfly, is formed from three
very simple shifts and adds multiplies,
whose output’s is then transformed into a
single complex output. The complex
coefficient, Zn, for these multiplies are
given by

Figure-4 FFT Black Box Representation

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

Zn = Cn + jSn , where With the availability of this high-end

Cn = [2 C – 2 Cos ( 2πn/N) + ½],
Sn = [2C – 2 Sin ( 2πn/N) + ½], and
C is the number of bits allocated to the
coefficient. (See Figure:-5)
HARDWARE SETUP
Xilinx FPGA’s have a long application in
the implementation of fixed-point DSP and
video algorithms in hardware.
flexibility of programmable logic allows
the fixed-point arithmetic calculations to
use custom bit widths tat are not bounded
to the 8-, 16- or 32-bit boundaries that are
prescribed for a fixed- point processors.
processing systems in the project Xilinx
Zynq™- 7000 All Programmable SOC,
makes it ideal for any user to fully utilize
the processing system and programmable
logic at the same time.
An accurate embedded system should
possess the best accuracy and adaptation
The between hardware acceleration blocks and
software execution and processing
management, this is called a proper
combination of H/W S/W co-design
environment.

Fig-5 Single FFT butterfly output stage

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

Due to timing and speed constraints of the are then either transmitted or received
system have made it mandatory to make based on the user requirements and
use of H/W acceleration, since algorithms displayed on to the in-built Linux
implemented in the PL will need lesser Application of IIO OSCILLOSCOPE. The
execution time compared to its software above Fig-6 demonstrates the hardware
counterpart. connection and its internal connection
between Zynq platform and AD-
The AD-FMComms2 EBZ analog module FMComms2 board. Since the application
is interfaced with zedboard to create a IIO OSCILLOSCOPE runs entirely on PS
Software Defined Radio (SDR) platform side and therefore the highly extensive
which enables the hardware to capture or calculations needed for the Linux
send signals of desired application on to Application makes it a slower process.
the antennas of the AD9361. These signals

Fig-6 Basic Hardware Arrangement

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

A. System Architecture Integrated Development Environment

The whole system is design is centered on (IDE). The IP Integrator environment of
the programmable logic. The main Vivado IDE is an excellent tool for the
interface between the programmable logic creation and generation of a Zynq
and processing system is a set of processor based design which can be
communication protocols composing of implemented on the Zedboard. Later on
multi-channels called the AXI bus the generated design is passed through the
interface. The role of this dedicated Software Development Kit (SDK) which
communication protocol and interfaces is creates the software application of the
to execute a convenient and fast data above design which helps to run on the
interaction while processing. Zynq’s ARM processing System to control
the hardware that is implemented in the
The process of designing a Zynq system is Programmable Logic.
created with the help of Xilinx Vivado™

Fig-7 Overall Procedure Used in Project

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 Journal of Advances in Communication Engineering and Its Innovations
1) Creating IP
A user has got no restriction on the
complexity of an intellectual property (IP)
that can be added in the fabric to be tightly
coupled with the Zynq SOC PS. Since the
Zynq deices comprises of both PS and PL
parts, the IP's that are created are made to
run on to the PL, it should therefore be
able to communicate with software
running on the PS. Therefore this requires
that IP should be packaged with an
interface that is compactable with the PS.
When creating IP in HDL, Vivado
provides a list of AXI interface templates
which can be created and customized via
the Create and Package IP Wizard.
2) Custom Embedded Linux OS on
Zedboard
The ultimate aim of this project is to load
the custom design created by the designer
on to the FPGA Fabric. To initialize this
process we need to build a custom
Embedded Linux OS on to the Zedboard.
It basically means we need to setup
environment according to the application
in order to build the HDL project from the
available Analog Devices repository.
Below are procedures that give us insight
of how to have a communication between
PL and PS side of Zedboard.
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a) First Stage Boot Loader: Once the
BootRom is configured, the very next step
to forward is creating the First Stage Boot
loader (FSBL) for Zynq. “The FSBL
configures the FPGA with HW bit stream
(if it exists) and loads the Operating
System (OS) Image or Standalone (SA)
Image or 2nd Stage Boot Loader image
from the non-volatile memory
(NAND/NOR/QSPI) to RAM (DDR) and
starts executing it. It supports multiple
partitions, and each partition can be a code
image or a bit stream." This is a better
explanation is provided by the Xilinx in
the SDK software while opting for zynq
fsbl.
b) Programmable Logic Hardware Bit
stream File: "A Bit Stream or bit stream is
a time series or sequence of bit."
From the above it gives a clearer idea that
PL HW Bit stream file is a sequence of
bits which contains HW and PL
configuration of a particular board selected
by the user details in the form of binary
language so that the selected board can
understand and implement.
c) Second Stage Boot Loader U-Boot: U-
Boot is an open-source, primary boot-
loader used in embedded devices to
package the instructions to boot the
device's operating system kernel. It boots
 Journal of Advances in Communication Engineering and Its Innovations
an operating system by reading the kernel
and any other required data into memory
and executing the kernel with the proper
argument.
d) Generation of "boot.bin" file: For
adding the Boot image partitions, the most
important order that is to be followed is:
First, bootloader i.e. First Stage Boot
Loader ("zynq fsbl.elf"); second the
Programmable Logic
Bitstream("system.bit") and finally the
software application _le i.e. U-Boot("u-
boot.elf"). All this _le names are stored in
a boot.bif file. "Bootgen" is a standalone
tool to create a bootable image appropriate
for Zedboard. Making use of following
command:
bootgen -image boot.bif -o i boot.bin.
The above program assembles the boot
image by merging the elf an the bit files to
develop a single boot image with the
binary output file boot.bin file which is
then introduced in the SD Card.
e) Device Tree Binary, "devicetree.dtb":
The Linux Kernel uses board specific data
structure called "Device Tree Blob" or
"Device Tree Binary (DTB)" to describe
the hardware. It basically is a database
which represents the hardware components
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Volume 4 Issue 2
on a given board and has been choosen by
default mechanism to be passed on as low-
level hardware information from the
Bootloader to the Kernel. The DTB file is
build from the Device Tree Source (DTS)
file. The DTS file is the DTB file write in
a human-editable format.
f) Linux Kernel File, uImage: It is a
zImage file that has a U-Boot wrapper that
includes the OS types and loader
information.
g) Root File System Image, "uramdisk.
image.gz": It is basically a compressed _le
which contains all the operating system
files. Below Fig- illustrates in brief all
accommodation of _les in the SD Card
which is then later on attached to the SD
Card slot in the Zedboard.
The below Fig-8 give a brighter step by
step initializatoion of creating Custom
Embedded OS on Zedboard. This all files
are then later on embedded into the SD
Card which is attached to the SD Card slot
of the Zedboard as can be seen in Fig-9.
 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

Fig-8 Step by Step Execution of Creating Custom Embedded OS on Zedboard

Fig-9 SD Card Various files needed to boot the system

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

RESULTS AND DISCUSSIONS In the Previous chapter a detailed

The hand written code implemented on the
Vivado IP Integrator using Verilog code of
the Fast Fourier Transform may have
many errors that is to be rectified, so the
Vivado has functionalities that check the
code by passing the code through various
steps of Evalaution such as Synthesis,
Verification and Implementation. This
further gives a detailed insight of the code
and the project itself develops a RTL
structure of the said IP and also creates a
netlist out the available details enlisted by
the user.
Discussion was mentioned further how to
create a custom embedded OS on to the
Zedboard with the help of SD card and the
requirements of each and every _le that
helps in the Zedboard to act according to
the user requirements. This is basically a
medium of interaction between the
Software Implementation of the designer
code with the implementation of Hardware
by the Zedboard. The Below Fig-7 gives a
brief idea about how overall process has
been conducted for the manipulation of
FFT core on to the Zedboard.

Fig-10 Synthesis Result

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

Fig-11 IP fft_fifo_ip inclusion in the analog project

Below Fig-10, shows the systhesis result
obtained from the interaction of Axi Bus
pheripheral master and slave units with the
Fast Fourier Transform IP. After the
overall process has been completed a code
is run on to the PS side of the Zedboard so
as to map the evaluation results obtained
from the PL on to the PS and directly
display on the user console so as to view
the correctness of the code an also to
evaluate the speed of the Fast Fourier
Transform on to the ARM processor.
Basically mmap is used for mapping the
outputs of the PL onto the PS. mmap() is
basically a Unix System call that allocates
or maps files or devices on to the memory.
The c code is run on to the Zedboard and it
automatically reads the driver code and
implements the necessary allocation of
data on the memory and makes it available
on the display console.
CONCLUSION
The dissertation aim was to implement a
custom application-specific design on the
Programmable Logic of the Zedboard
fabric was accomplished with optimized
and proper output. This experiment not
only gave the insight that due to to its
Computing platform and excellent
performance to perform parallel in nature
and also to execute at a faster rate than the
Processing System of The ARM. The Task
of communication with the PL an d PS

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

was very much accomplished with the help Electronics (Comptelix) Manipal
of a AXI- standard bus which had its own University Jaipur, Malaviya
sets of peripherals that enabled any user to National Institute of Technology
create a custom code in association with Jaipur & IRISWORLD, July 01-
peripherals and talk to the PS with no 02,2017
further disturbances. The use of Software
gave better perspective of a System-on- II. Real-Time System Implementation
Chip process. Later on the software details for Image Processing with Hard-
had to be made available in the proper ware/Software Co-design on the
bootable image that was developed using Xilinx Zynq Platform M. Ali
the Software Development Kit. Lastly Altuncu, Taner Guven, Yasar
using a executable c code that was Becerikli, and Suhap Sahin
compactible with the ARM Processing International Journal of
system was executed and result was then Information and Electronics
obtained. Engineering, Vol. 5, No. 6,
November 2015.
ACKNOWLEDGMENT
I would like to thank the immense III. REAL TIME
guidance provided by my guide Prof. IMPLEMENTATION OF
Nitesh Guinde in accomplishing this SPATIAL FILTERING ON FPGA,
dissertation. I would also like to thank my Chaitannya Supe, Advances in
College for providing me access to various Vision Computing: An
materials and hardware facility whenever I International Journal (AVC),
would require. Vol.1, No.4, December 2014

REFERENCES IV. Design of Image Display

I. A Robust Technique for Image Controller Component for VGA
Processing based on interfacing of Inter- faced Monitor using
Raspberry- Pi and FPGA using ZedBoard, Divyansh A Thakar,
IoT, Ajay Rupani, Pawan Whig , Rikin J Nayak, Jaiminkumar B
Gajendra Sujediya, Piyush Vyas, Chavda, Jay R Patel, Mit P Patel,
2017 International Conference on 2nd International Conference on
Computer, Communications and Current Research Trends in

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 Journal of Advances in Communication Engineering and Its Innovations
Volume 4 Issue 2

Engineering and Technology c X. Vivado Design Suite Tutorial,

2018 IJSRSET | Volume 4 | Issue 5 Embedded Processor Hardware
| Print ISSN: 2395-1990 | Online Design by Xilinx
ISSN : 2394-4099 Themed
Section: Engineering and
Technology

V. Zynq FPGA based and Optimized

Design of Points of Interest De-
tection and Tracking in Moving
Images for Mobility System
Abdelkader BEN AMARA,
Mohamed ATRI, Edwige
PISSALOUX,
VI. Richard GRISEL (IJACSA)
International Journal of Advanced
Computer Science and
Applications, Vol. 9, No. 10, 2018

VII. https://wiki.analog.com/resources/e
val/user-guides/ad-fmcomms2
ebz/software/linux/zynq 2014r2

VIII. https://wiki.analog.com/resources/f
pga/docs/build

IX. The Zynq Book Tutorials by

Louise H. Crockett, Ross A. Elliot,
Martin A.Enderwitz, Robert W.
Stewart

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