J Shanghai Univ (Engl Ed), 2010, 14(5): 349–353

Digital Object Identifier(DOI): 10.1007/s11741-010-0657-3

Integration and verification case of IP-core based system on chip design

HU Yue-li (  )1,2 , ZHOU Chen ( ) 2

1. School of Mechanical and Electronic Engineering and Automation, Shanghai University, Shanghai 200072, P. R. China
2. Key Laboratory of Advanced Display and System Application, Shanghai 200072, P. R. China
©Shanghai University and Springer-Verlag Berlin Heidelberg 2010

Abstract In this paper, the design and verification process of an automobile-engine-fan control system on chip (SoC) are
introduced. The SoC system, SHU-MV08, reuses four new intellectual property (IP) cores and the design flow is accomplished
with 0.35 μm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP
cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP
cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and
the first tape-out achieves success which proves the validity of our design

Keywords system on chip (SoC), intellectual property (IP)-core integration, verification, pulse width modulation (PWM)-
analog digital converter (ADC) linkage running

Introduction chitecture, the four intellectual property (IP) cores,

the pulse width modulation (PWM)-analog-digital con-
With the development of system on chip (SoC), chip verter (ADC) linkage running mode and the IP cores
system can be easily applied to a wide range of areas. integration. Section 2 demonstrates the verification en-
SHU-MV08, an SoC realized by integrating four IP cores vironment, flow and the results. Section 3 is the conclu-
on the original platform, is designed to control the run- sion of the paper.
ning of the automobile engine fan (motor).
References [1] and [2] introduce the motor-control 1 Design of SHU-MV08
theory and implementation method. In addition some
control chips are available now, e.g. TC64x provided by 1.1 Architecture of SHU-MV08
microchip. However in most of these methods, the mo- SHU-MV08 is a digital-analog-mixed SoC with an 8-
tor running signals are fed back to the motor control bit micro-controller unit (MCU) which controls the run-
module in the manner of software instructions, which ning of the automobile-engine-fan. To meet the needs
is not instantaneous. In the design of SHU-MV08, the of application, four IP cores, PWM, ADC, FLASH and
whole process is running in the manner of hardware multi-source watch dog timer (MSWDT) are embedded
(the linkage running mode), and the moment of signal- on the original SoC platform.
sampling is well chosen. Hence, the running of the au- Figure 1 displays the architecture of SHU-MV08.
tomobile engine fan is under better control. The MCU kernel is the controller of the entire chip which
Verification is a troublesome problem in integrated controls the running of all the IP cores. Both the orig-
circuit (IC) design cases, which has taken more than inal IP cores (Core A, Core B, etc.) and the new ones
70% of the entire design period[3] . It drives us to find a are connected with the kernel by buses. The control of
reliable verification tool. Nanosim is introduced in the the automobile-engine-fan is realized by integrating new
verification of SHU-MV08 which has been proved to be IP cores.
helpful in other design cases[4] . The final verification 1.2 Four IP cores and PWM-ADC linkage
results prove the validity of our design. running mode
The organization of the remaining part of the pa- PWM generates PWM wave which controls the run-
per is as follows. Section 1 introduces the SoC ar- ning of the automobile-engine-fan. PWM wave could be
Received Nov.22, 2009; Revised Dec.24, 2009
Project supported by the IC Special Foundation of Shanghai Municipal Commission of Science and Technology (Grant
No.09706201300), the Shanghai Municipal Commission of Economic and Information (Grant No.090344), the Shanghai High-
Tech Industrialization of New Energy Vehicles (Grant No.09625029), and the Graduate Innovation Foundation of Shanghai
University
Corresponding author HU Yue-li, Ph D, Prof, E-mail: huyueli@shu.edu.cn
350
generated in compensated form, and dead-time[6] could
be inserted into the compensated wave which ensures
the security of the running of the automobile engine fan.
Fig.1 SHU-MV08 system architecture
ADC is an analog IP core which works in the succes-
sive approximation register (SAR) conversion manner.
It samples the external signals and converts them into
digital ones. Especially, the running of ADC could be
triggered by PWM module (PWM-ADC linkage mode)
which replaces the traditional software instruction con-
trol method. Each ADC conversion happens at the cen-
ter of every high level of the PWM wave. It is because
that the analog signals sampled by the ADC are fed
back to the PWM module to adjust the running of the
fan. Therefore, the choice of sampling point is fairly
critical. At the center of each high level of the PWM
wave, drive circuits of the automobile engine fan work
in stable states which provides the best sampling condi-
tion for the ADC.
Figure 2 displays such PWM-ADC linkage running
mode. ADS, the running start signal of the ADC, trig-
ger the conversion of the ADC at the center of every
high level of PWM wave.
Fig.2 PWM-ADC linkage running mode (Conversions of
ADC can be triggered by PWM at the center of
each high level of PWM wave)
Besides that, MSWDT and FLASH improve the
SHU-MV08 performance. MSWDT is an innovative IP
J Shanghai Univ (Engl Ed), 2010, 14(5): 349–353
core which can not only reset the system when some-
thing wrong happens but also locate the source of the
error program. FLASH is another analog IP core, which
realizes the on-chip code memory function of SHU-
MV08.
1.3 IP cores integration
One of the most acceptable IP reuse methods in an
SoC is connecting the new IP core with the kernel by sys-
tem buses. Most digital IP cores are integrated in this
manner. In the case of integrating PWM and MSWDT,
this classical method is adopted. In SHU-MV08, there
are three types of buses: address bus, data bus and
the control bus. Thus the process of integrating PWM
and MSWDT is connecting the two IP cores with these
buses. Figure 3 presents that digital IP cores are con-
nected with the MCU kernel by three buses which is the
integration method of PWM and MSWDT.
Fig.3 Classical IP reuse method (Different IP cores are
connected to kernel by a variety of buses)
Compared with the digital IP cores, the integra-
tion of the ADC involves more problems. Seven pins are
added to enable the ADC to its own independent power
supply and input signals. Owning to the fact that ADC
is an analog hard-core which can not be modified, an
ADC control soft-core is designed by Verilog. The soft-
core is connected with the kernel and the ADC hard-core
by buses as well. Once the soft-core receives the instruc-
tions from MCU, it will start the A/D conversion.
When embedding FLASH, what considered most is
port reuse. There are four 8-bit ports in the original
system, and three of them are reused to transmit differ-
ent kinds of signals when FLASH is in the programming
state. RESET, the reset signal, is also reused to distin-
guish the two different states. When RESET is set high,
MCU stops working and FLASH is in the programming
state. If RESET is set low, MCU is in the working state
and reads instructions from FLASH. A new pin, VPP, is
added as the programming pin to bear the programming
voltage of the height of 6.5 V.
J Shanghai Univ (Engl Ed), 2010, 14(5): 349–353
2 Verification and results
Due to the reliability of the IP cores, the verification
method introduced below will focus on the system level
verification. Mixed-signals verification is very difficult
task and will be paid more attention to.
2.1 Verification environment and flow
A mixed-signal verification environment is estab-
lished on our design work station which is able to carry
out not only the digital signal verification throughout
the flow, but also the mixed-signal verification on dif-
ferent hierarchies. Some electronic design automation
(EDA) tools are used in the environment, e.g. verilog
compiled simulator (VCS), design compiler, NanoSim,
etc.
To deal with the challenge of mixed-signal verifica-
tion, NanoSim is used. NanoSim obtains the advan-
tages of simulation at full chip level which also promises
the accuracy. By combining NanoSim with VCS and in-
tegrating them into new mixed-signal simulation flow,
some shortages in traditional flow, e.g. large time con-
sumption are overcome, and an agility speed-versus-
accuracy tradeoff is achieved. Furthermore, this method
can be integrated into the existing design flow easily and
can be carried out at different levels.
The complete verification environment is shown in
Fig.4. A top level test bench written in Verilog is the
common top level throughout the flow. Digital parts
are described by Verilog or by netlist. In order to reduce
the simulation time, SRAM and FLASH are described
by the behavioral model in the front end design. ADC is
described by spice netlist and NanoSim realized through
the combination of digital parts and the ADC by an
interface called resistance map. When the mixed-signal
verification needs running, independent power, reference
voltage, and input signals are needed by the ADC. All
these are packed together with the ADC in the wrapper
module.
Fig.4 Verification environment of SHU-MV08
The design flow follows the traditional method basi-
cally. With the help of VCS, the wave can be checked
at different levels. The synthesis process is finished by
the design compiler. NanoSim will be called at differ-
351
ent levels whenever the mixed-signal verification needs
executing. Besides that, formal verification method is
introduced to ensure the design quality.
2.2 Results
All the four IP cores have been verified successfully
during the verification flow, but it is impossible to lay
out the total results. In this paper, the result of one
mixed-signal verification procedure is presented. During
this procedure, the instructions saved in FLASH order
PWM to generate the waveform which triggers the con-
versions of ADC (PMW-ADC linkage mode). In other
words, three IP cores can be verified by the procedure
alone.
To obtain more reliable results, a worse verification
environment is selected for the analog parts. The sys-
tem clock frequency is 13 MHz. Using the traditional
simulation tool, e.g. spectre, the running time of one
conversion period can be dozens of minutes. With the
help of Nanosim, the simulation time is greatly reduced,
and the accuracy is ensured as well. In this case, the
simulation time is set to 1 ms, and the total CPU run-
ning time is 26 min for 37 times of conversions.
Figure 5 demonstrates the results, which are sepa-
rated into two parts. The instructions are stored in
FLASH and the conversions are triggered at the cen-
ter of each high level of PWM wave. Three cores are
involved in the procedure alone. The upper part shows
the digital wave, and the lower part shows the analog
ones. In the upper part, each rectangle wave represents
a control register of PWM or ADC. PWM[1] is one of
the two PWM output tunnels. It is not difficult to find
that an ADC conversion will be triggered at the center
of each high level of PWM[1] . At first, conversion re-
quest signal, pwmcon, is set high. Once it is received by
the ADC control module, the ADC enable signal, EN-
ABLE, will be set high, and the conversion clock will be
activated. The conversion start signal, ADS, will then
be sent to MCU. At the end of each conversion, some
stable values can be read from D out [9:0] which is also
the conversion results.
In the lower part, v(in3) is the sine-wave stimulation
signal with the frequency of 5 kHz and the amplifica-
tion of 1.65 V. To compare the conversion results, D out
[9:0] is displayed in the form of analog waves. It could
be found in Fig.4 that the ladder wave varies regularly
with the way of v(in3). The glitches between two close
steps are caused by the successive approximation pro-
cess during each conversion. Two points (A and B) are
marked in the figure to check the conversion accuracy.
At point A, the value of the analog sampling signal is
2.570 V, while the value of its counterpart, A’, is 803
which corresponds to the analog value of 2.590 V. Sim-
ilarly, the sampling value at point B is 1.13 V and the
conversion value at point B’ is 343 which corresponds
352
to the analog value of 1.11 V. Deviations of both results
meet the needs of the requirements.
In Fig.6, details of the single conversion process at
point B are displayed. The variations of D out [9:0] at
each clock cycle and the entire successive approximation
process can be observed. When the conversion process
is finished, the value of D out [9:0] will be in a stable
Fig.5 Conversion process of ADC
Fig.6 Details of a successive approximation conversion period
Fig.7 Final tape-out of SHU-MV08
J Shanghai Univ (Engl Ed), 2010, 14(5): 349–353
state. At the same time, ADC will send the interrupt
request signal to MCU.
Figure 7 is the final tape-out picture of SHU-MV08.
The IP core in the up right corner is FLASH, and the
down left and down right IP cores are RAM (old IP
core) and ADC. The tests after the first tape-out have
proved the validity of our design.
3 Conclusions
The experience of the design of SHU-MV08 has been
shared in this paper. System establishment is realized
by integrating four different IP cores. PWM-ADC link-
age running mode is introduced which can improve the
reliability of the running of the automobile engine fan.
The using of NanoSim not only reduces the verification
time significantly but also ensures the stimulation accu-
racy. One of the verification results is presented which
involves three new IP cores. The final tests after tape-
J Shanghai Univ (Engl Ed), 2010, 14(5): 349–353
out have proved the validity of our design.
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(Editor JIANG Chun-ming)