2017 2nd International Conference on Integrated Circuits and Microsystems

A Unique Centralized-Management Methodology Block/Architecture and a Novel

Random Input Stimulus Controlled Variable Table Implementation for the Latest
Marvell Ethernet PHY UVM Verification Platform

Peter Wang
Marvell Semiconductor Inc.
5488 Marvell Lane, Santa Clara, USA
e-mail: peterw@marvell.com

Abstract—More than eighty different test environments need to
be created and maintained for debugging the Marvell Ethernet
PHY chip if the traditional industrial verification methodology
is being used. This can easily incite very complicated
debugging procedures and cause the problems and concerns of
a multitude of engineering resources.
The latest Marvell Ethernet PHY IC UVM verification
platform integrating with the Marvell selected IP vendor’s
UVM library has been developed. A unique centralized-
management methology block/architecture idea is brought in
to build this UVM verification platform for the latest Marvell
Ethernet PHY integrated circuit. All the eighty different test
modes can be tested and verified in the same single UVM
platform environment.
This UVM verification platform environment significantly
reduces the number of engineering resources needed to create
and maintain the test cases. It also greatly saves debugging
time and reduces chip development time.
In the meanwhile, a novel random input stimulus
controlled variables table idea is also implemented in this
UVM verification platform to manage and improve the
function coverage much more easily and efficiently.
Keywords-Marvell Ethernet PHY; integrated circuit
verification; UVM; UVM verification platform; systemverilog
testbench; RTL; code coverage; function coverage
I. INTRODUCTION
This paper presents a unique centralized management
methodology/block architecture which is used for the latest
Marvell Ethernet PHY integrated circuit verification
platform. It also presents a novel random input stimulus
controlled variable table implementation for the same UVM
verification platform to manage and improve the function
coverage much more easily and efficiently.
Both of the unique centralized-management methodology,
block/architecture, operational principles [1] and the novel
random input stimulus controlled variable table concept [2]
have been integrated with Marvell selected IP Vendor’s
UVM library to successfully build an Ethernet PHY UVM-
based integrated circuit verification platform for the latest
Marvell Ethernet PHY chip tape-out.
The latest Marvell Ethernet PHY IC needs to support
x different speeds from 100M, 1G, 2.5G, 5G, 10G,
25G, 40G, 50G to 100G, 200G;
x all the different Ethernet protocols and interfaces
such as MII, GMII, XGMII, X25GMII,XLGMII,
CGMII and others;
x all different clocks frequency setting and SERDES
interface lane numbers from 1, 2, 4 to 8, 16 lanes;
x all different registers setting for different test
modes through MDIO registers programming
This makes the total different combined test scenarios
very complicated and it may need to create more than eighty
different test cases to cover all the features. Because each test
mode works with a different speed, clock frequency,
interface connection, SERDES interface lane numbers, and
each test mode has different working settings, including the
MDIO registers programming setting, more than eighty
different test scenarios environments need to be created,
maintained, and supported to fully cover all of these different
test features if using the current traditional industrial IC
verification methodology.
Marvell actually did the verification environment work
for its previous Ethernet PHY chips using the traditional
industrial IC verification methodology. The verification work
was very laborious and the eighty different test scenarios
environments were difficult to maintain and debug.
A unique centralized-management methodology block
architecture is presented and implemented for the latest
Marvell Ethernet PHY IC verification platform with the
integration of Marvell selected IP vendor’s UVM library. All
the eighty different test modes can be tested and verified in
the same single UVM platform environment.
By adopting this platform, we can not only finish the full
functional verification for our latest Ethernet PHY IC more
efficiently, but also maintain all the test scenarios in the same
single environment more easily and shorten the entire
development period of our production.
Function coverage is also another important
measurement criterion for the Marvell Ethernet PHY
integrated circuit UVM verification platform. While the
traditional random variables generation randomly and
uncontrollably distributes in all the different sequences inside
the verification platform, this novel random input stimulus
control variables table idea is presented and brought into this
integrated circuit UVM verification platform to manage and
improve the function coverage much more easily and
efficiently. After integration with the Marvell selected IP

978-1-5386-3506-3/17/$31.00 ©2017 IEEE 

vendor’s Ethernet UVM library code coverage and function
coverage working flow, the function coverage of this UVM
verification platform can be much more easily traced,
monitored, and improved based on the different random
input stimuli in the random input controlled variables table.
In this technical paper, the scheme of the centralized-
management methodology, block/architecture, the operating
principles, and the random input stimulus controlled
variables table concept are introduced, and the UVM
verification platform environment, which implements this
centralized-management block, and a random input stimulus
controlled variable table are illustrated.
II. THE CENTRALIZED-MANAGEMENT METHODOLOGY
BLOCK /ARCHITECTURE FOR THE MARVELL ETHERNET PHY
UVM VERIFICATION PLATFORM INTEGRATING WITH THE
MARVELL SELECTED IP VENDOR’S ETHERNET UVM
LIBRARY
A. Marvell Ethernet PHY UVM Verification Block
Diagram
Fig. 1 in this paper presents the Marvell Ethernet PHY
integrated circuit UVM verification platform diagram. The
Ethernet PHY DUT has the host and line interface as the
main PHY link interfaces. The Ethernet sequence in this
UVM test platform controls the random packets generation
through the MAC-PHY interface. The transmitting and
receiving packets can be passed to the scoreboard and be
checked and compared on the scoreboard to give the packets
data match/mismatch information. The Ethernet protocol
checkers are also built into the platform to monitor and
report the Ethernet protocol violation through the assertion
methodology when the errors are hit in the simulation.
Figure 1. Marvell Ethernet PHY UVM integrated circuit verification
platform diagram.
Marvell selects its own IP vendor for providing the
Ethernet UVM library to build the verification platform. The

IP vendor’s Ethernet UVM library provides the MAC/PHY
BFM module, Ethernet protocol checker, clock module,
scoreboard module and UVM agents which can be selected
and integrated into this Marvell Ethernet PHY verification
platform to minimize the Marvell engineers’ development
time. The Marvell selected IP vendor’s Ethernet UVM
library allows the quick verification platform build to meet
the tight chip delivery schedule.
Since this latest Marvell Ethernet PHY integrated circuit
needs to support
x different speeds from 100M, 1G, 2.5G, 5G, 10G,
25G, 40G, 50G to 100G, 200G;
x all the different Ethernet protocols and interfaces
such as MII, GMII, XGMII, X25GMII,XLGMII,
CGMII and others;
x all different clock frequency and SERDES
interface lane numbers from 1, 2, 4 to 8, 16 lanes,
Based on the different test scenarios, the clock setting,
lane numbers, interface connection and MDIO registers
program for each test mode can be completely different. If
using the traditional verification methodology to build this
integrated circuit verification environment, more than eighty
different verification environments need to be created and
maintained to support all the chip features. This can easily
make the environment creating, maintaining and debugging
workload very heavy and difficult.
B. A Unique Centralized-Management Methodology Block
Architecture Implementation
A unique centralized-management methodology block
architecture was presented and implemented in the latest
Marvell Ethernet PHY integrated circuit verification
platform.
Figure 2. Centralized-management operational policy.
 Fig. 2 here in this paper presents the idea of a centralized-
management operational policy. It has one centralized-
management block sitting on the top-level environment to
manage, monitor, and sync up the detailed operation between
each class/agent in the UVM environment. The centralized-
management block also automatically manages the
information communication between each agent in the UVM
environment from the top-level. With the implementation of
this centralized-management methodology/block architecture,
the different clocking setting, interface connection, SERDES
interface lane numbers, and the registers programming
through MDIO serial port for each different test scenario can
be detected, loaded and set-up automatically in the
environment. With the application of this unique centralized-
management operational policy and architecture, all the
eighty different test scenario modes can be tested and
verified in the same UVM universal platform when the auto-
detection function and controlling function for different test
modes switching are turned on.
III. BRINGING IN RANDOM INPUT STIMULUS CONTROLLED
VARIABLE TABLE TO THE MARVELL ETHERNET PHY
VERIFICATION PLATFORM TO MANAGE AND IMPROVE THE
FUNCTION COVERAGE
A. Function Coverage in the Marvell Ethernet PHY
Integrated Circuit UVM Verification Platform
Function coverage is the measurement of how much
design functionality has been exercised and covered by the
UVM verification platform, which is defined in the form of a
functional coverage model.
In the UVM verification environment, the user defines
the mappings for each functional feature which need to be
tested and verified to be “cover points”. These cover points,
which are used in the verification platform environment,
usually have certain conditions defined by the integrated
circuit verification team based on the chip design
specification. The cover points can include conditions such
as ranges, defined transitions, cross boundaries, etc. to
complete in the simulation. All these conditions for a cover
point are defined in the form of “bin” in the coverage group.
Figure 3. Built functional coverage model for the Marvell Ethernet PHY
verification platform.

100% function coverage in the Marvell Ethernet PHY
integrated circuit verification platform is required for the
verification regression test.
During the regression test, when a certain conditions of
cover points hit, those bins are covered and give the
verification team the measurement of verification progress.
After executing all the test cases in the regression test, a
coverage report can be generated to analyze the functional
coverage report and a detailed chip test plan can be made to
cover up the holes which bins (conditions) were not hit in the
final chip regression test.
The number of cover points can be collected and
combined together under one “cover group”, and the
collection of multiple cover groups is usually called the
“functional coverage model” in the UVM verification
environment.
B. Implement a Novel Random Input Stimulus Controlled
Variables Table to Manage and Improve the Function
Coverage Much More Easily and Efficiently
The randomization of verification methodology enables
the verification environment to automatically generate the
random input stimulus for function coverage.
In the generic UVM environment, the stimulus variables
are randomly and uncontrollably distributed in each agent or
sequence generation class.
Figure 4. Random input stimulus controlled variables table in XLS format
for the Marvell Ethernet PHY integrated circuit verification platform.
In this latest Marvell Ethernet PHY integrated circuit
UVM verification platform, a novel random input stimulus
controlled variables table idea has been brought in and
implemented to map the excel format specification table into
the UVM random controlled input stimulus variables table
code in the top-level class or module.
 Since this random input stimulus controlled variables
table only needs to be implemented in the top-level class or
module, it can easily and flexibly sync up and control all the
stimulus variables which have been randomly distributed in
every agent and sequence from the top-level through this
table. With the control setting change of this random input
stimulus controlled variable table, the function coverage can
be much more easily managed and improved from the top-
level in the chip regression test. The random input stimulus
controlled variables table can also been easily managed by
RTL modules design engineers and verification managers to
collect and combine every single idea from designers or
verification engineers about all of the pontential possibilities
of random variables which should be added or covered in the
verification platform.
Figure 5. Random frame generation by the controlling of random input
stimulus controlled variables table.
Through the controlling of random frame type, random
data frame, random control frame, ip4, ip6 frame, random
packet address, random packet length, random frame header,
random frame gap and other variables, the test scenario case
can be eaily changed and re-configured to improve the
function coverage without detailed knowledge of each UVM
agent, sequence, or class from the Marvell selected IP
vendor’s Ethernet library, where all the stimulus variables
are randomly and uncontrollably distributed inside and made
it difficult to trace by the library users. The holes which the
random setting or range hasn’t hit can also be easily found
by designers and verification managers and can be easily
improved to be covered up in the new tests after the
comparing and checking of random stimulus controlled
variables table input with the simulation results in the
regression test.

Figure 6. Function coverage report for the Marvell Ethernet PHY
integrated circuit verification platform.
IV. SUMMARY
A unique centralized management methodology, block
architecture, operational principles and a novel random input
stimulus controlled variables table concept have been
successfully implemented and integrated with Marvell
selected IP vendor’s Ethernet UVM library in the latest
Marvell Ethernet PHY IC UVM verification platform.
The latest Marvell Ethernet PHY integrated circuit
UVM verification platform has the following features:
x Centralized-management methodology, block/
architecture, operational principles built in to sync
up all 80 different test scenario modes
x Novel random input stimulus controlled variable
table built in to manage and improve the function
coverage
x SystemVerilog UVM environment integrating with
the Marvell selected IP vendor’s UVM Ethernet
library
x All eighty test modes/scenarios are supported in
one single UVM platform environment
x Complete function coverage features built in
x Reduced simulation time and regression test time,
which saves development time to meet tight
schedule
ACKNOWLEDGMENT
Thanks to Marvell selected IP vendor’s AE team for
supporting Marvell UVM verification platform build work.
REFERENCES
[1] Peter Wang, "A new centralization-managed universal verification
platform architecture and methodology for the Ethernet PHY chip
verification”, the pending patent(IDF 10304) submitted through
Marvell Intellectual Property patents application channel, 2017
[2] Peter Wang, " implement a novel random input stimulus controlled patent(IDF 10375) submitted through Marvell Intellectual Property
variables table into the UVM verification platform to manage and patents application channel, 2017.
improve the Ethernet PHY chip function coverage”, the pending