7/10/2019 An insight into layout versus schematic | EDN

Advertisement Advertisement

DESIGN CENTERS TOOLS & LEARNING COMMUNITY EDN VAULT

About Us | Subscribe

Search

Sign In | Sign Up

Home > Integrated-circuit-design Design Center > How To Article

An insight into layout versus schematic

Rishabh Agarwal, Shailesh Kumar, Siddharth Sinha, and Vishant Gotra, Freescale Semiconductor
-July 15, 2013

Share Tweet

In the nanometer era, die areas are getting larger as the designs are getting more and more
complex. In order to ensure the correctness of the implemented design, bigger layout databases
needs to be checked during the physical verification stage in the same ambitious project time
frames as before. Any failure identified after the design is manufactured will result in expensive
mask changes and delays in getting the System on Chip (SOC) to market. Physical Verification is
performed to check whether the design layout is equivalent to its schematic and checks the layout
against process manufacturing guidelines provided by the semiconductor fabrication labs to
ensure it can be manufactured correctly. Physical verification includes:

Design rule check (DRC): It verifies whether the designed layout can be manufactured by
the fabrication lab with a good yield.
Layout versus schematic (LVS): It is a method of verifying that the layout of the design is
functionally equivalent to the schematic of the design.

It is important to note that DRC does not ensure the intended functionality of layout. DRC is only
limited to checking whether the given layout conforms to design rules provided by the fabrication
unit so as to ensure the faultless fabrication but without warranting whether the circuit will behave
in a way that it was intended to. The idea of LVS originated from this very requirement. In this
article, LVS flow is discussed followed by common issues and their debugging with the help of
appropriate illustrations.

How LVS works

ADVERTISING

https://www.edn.com/design/integrated-circuit-design/4418390/An-insight-into-layout-versus-schematic 1/7
7/10/2019 An insight into layout versus schematic | EDN

Replay

Learn more

A verification EDA tool performs LVS by taking a set of instructional code input, commonly known
as LVS rule deck, in the following two steps: extraction and comparison. The LVS rule deck
guides the verification tool by providing the instructions and identifying files which are needed for
LVS. Design inputs needed for running LVS are as follows:
Graphical database system (GDS) layout database of the design
Schematic netlist of the design
Cell definition file including Intellectual property files and standard cells
Pad reference file

A LVS rule deck is a set of code, which is written in Standard Verification Rule Format (SVRF) or
TCL Verification Format (TVF), which guides the verification tool to extract the devices and
connectivity of the integrated circuit. The LVS rule deck contains the layer definitions for the
identification of layers used in the layout file and matches description of a layer to the location of
the layer in the GDS file. This helps in the recognition of the electrically connected regions in the
layout, namely the nets. Nets are recognized from the layout shapes through analysis between
layout shapes in layers. LVS rule deck also contains device structure definitions.

Figure 1 LVS flow

The LVS flow is as follows:

The verification tool takes the GDS file as input and breaks it down into basic design devices like
transistors, diodes, capacitors, resistors etc. These devices are identified in the GDS file by
recognition of the layers and shapes that makes up the circuit or by the cell definition of the
devices/circuits provided in the cell definition file of the intellectual property blocks or in the LVS
rule deck itself. It also extracts the connectivity information between these devices from the GDS
file. The next step in connectivity extraction is uniquification of nets. Each electrical net is given a
unique node number for identification during the extraction process. Net names can also be
named based upon the presence of layout text objects or text statements in the control file. This
https://www.edn.com/design/integrated-circuit-design/4418390/An-insight-into-layout-versus-schematic 2/7
7/10/2019 An insight into layout versus schematic | EDN

device information along with their connectivity is written into a layout netlist file, generally called
layout extracted netlist. This process is known as extraction.

In the comparison phase, the verification tool compares the electrical circuits from the schematic
netlist and the layout extracted netlist. The netlist comparison process also uses the LVS rule
deck. After the successful comparison between layout and source netlist, a one-to-one
correspondence between the elements (instances, nets, ports, instance pins) of source netlist and
layout netlist is established. The intention of the layout designer is to implement the functionality
provided in the schematic into a geometrical representation of layout. Therefore, in order for the
verification process to complete without error, both layout and source netlist must match. If the
two netlists differ, discrepancies are reported in the form of a LVS result database which can be
used to debug LVS issues. Result database would contain the list of incorrect elements and the
reason of mismatch like incorrect nets, incorrect ports, and incorrect instances.

Commonly faced LVS issues and their debug

The source spice netlist which is a representation of the schematic of a circuit should match with
the spice netlist extracted from the layout. But, there may be several reasons due to which LVS
may fail. It is always suggested to check the following points in order to roughly find out the
reason of LVS failure.
LVS comparison includes the following points:
Number of devices in the schematic and its layout.
Type of devices in layout and schematic.
Number of nets in schematic and its layout.
Some of the common LVS issues and their debugging are explained in detail with appropriate
examples mentioned below:

1) Short
Short in a design occurs when in a particular layer of the GDS two polygons having different
layout text on them overlap and have a non-zero intersection. Alternatively, when two different
nets touch each other, it will result in a short. Presence of a short in a design may result in a chip
failure. In large designs, it is always suggested to run the short finding utility of the place and
route tool before running LVS to figure out the shorts in the early phase of the design cycle.
Presence of short in a design after running LVS can be identified as shown in the following
example. In case of a short, LVS tool always dumps a report file which contains the information of
the short.
Share Tweet

Next: Signal short

< Previous Page 1 of 3 Next >

SPONSORED CONTENT

24GHz XENSIV™ radar

demo kits: Choose the right
board to support your
application
Infineon provides three
industrial XENSIV™ radar
demo kits, supporting
different applications –
from basic movement
detection to advanced motion detection sensing. This
comparison video will present the features and benefits of
each of them: Sense2GoL, Distance2Go and Positiong2Go.
Now you can choose the right one for your application.
Sponsored By Infineon

https://www.edn.com/design/integrated-circuit-design/4418390/An-insight-into-layout-versus-schematic 3/7
7/10/2019 An insight into layout versus schematic | EDN

Write a Comment

Submit Comment
To comment
please Log In

EDN MOMENT
‘Father of modern
general relativity’
John Wheeler is
born July 9 1911

Funds credited in 48 hours*

Avail personal loan up to Rs.30
Lakhs @10.99%* p.a. Flexible
Repayment period. Apply now

PODCAST

PODCASTS / 25:43

Moore's Law and GaN

● Facial Recognition vs.
Privacy ● The Trade
War Soap Opera
This week: There will be
progress in the semiconductor
industry even after the demise
of Moore's Law. In some
circumstances, facial
recognition is really, really bad
at identifying faces. And what's
next in the U.S.-China trade
war?

VIEW ALL EPISODES

LISTEN

https://www.edn.com/design/integrated-circuit-design/4418390/An-insight-into-layout-versus-schematic 4/7
7/10/2019 An insight into layout versus schematic | EDN

PARTNER CONTENT

Upgrade your smart

home’s IQ with Z-
Wave 700 mesh
networking and augmented
edge intelligence
By Silicon Labs, 26.06.2019

Winbond supports
accelerated roll-out
of 5G CPE modems
with release of 2Gb+2Gb
NAND+LPDDR4x multi-chip
package
By Winbond, 22.06.2019

See how Taiwan’s

startups improve
human life with
advanced technology!
By Taiwan Tech Arena (TTA) ,
20.06.2019

Most Popular Most Commented

https://www.edn.com/design/integrated-circuit-design/4418390/An-insight-into-layout-versus-schematic 5/7
7/10/2019 An insight into layout versus schematic | EDN

Basics of multi-cycle & false

paths
Decode a quadrature encoder
in software
Choosing a mobile-storage
interface: eMMC or UFS
Gate level simulations:
verification flow and
challenges
Floorplanning: concept,
challenges, and closure
MBIST verification: Best
practices & challenges
Power integrity domains
Moving averager rejects noisy
outlier values
Modern ADCs improve CMOS
image sensors
Design planning for large SoC
implementation at 40nm - Part
2

FEATURED RESOURCES

Subscribe to RSS: or

DESIGN CENTERS MORE EDN

5G LEDs Blogs EDN TV
Analog Medical Design Ideas Events
Automotive PCB Tech Papers About Us
Components & Packaging Power Management Courses
Consumer Sensors Webinars
DIY Systems Design
IC Design Test & Measurement
https://www.edn.com/design/integrated-circuit-design/4418390/An-insight-into-layout-versus-schematic 6/7
7/10/2019 An insight into layout versus schematic | EDN

ASPENCORE NETWORK

EBN EDN EE Times EE Times Europe EEWeb Electronic Products Electronics-Tutorials Embedded Planet Analog

ElectroSchematics Power Electronics News TechOnline Datasheets.com Embedded Control Europe Embedded Know How
Embedded News IOT Design Zone Motor Control Design Electronics Know How IoT Times

GLOBAL NETWORK

EE Times Asia EE Times China EE Times India EE Times Japan EE Times Taiwan EDN Asia EDN China EDN Taiwan

EDN Japan ESM China

Working With Us: About | Contact Us | Media Kits

Terms of Service | Privacy Statement | Copyright ©2019 AspenCore All Rights Reserved

https://www.edn.com/design/integrated-circuit-design/4418390/An-insight-into-layout-versus-schematic 7/7