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Written Test:-
Total questions: 60
Section A – Aptitude (data interpretation linked questions, calendar, profit and loss,
average, allegations and mixture, time speed distance, finding the relationship and
reasoning type linked questions ) 20 questions in 20 minutes
Aptitude questions are like CAT level .practice more n more and be selective while
attempting because time is very less for this portion
Technical Round 1
Make OR , AND gate from 2:1 MUX
Make 3:8 decoder from two 2:4 decoders
What is setup time and hold time, how we can reduce it, what is the change in setup time
if frequency of clock is changed.
What is the use of grey code , its application
Write the Verilog code from 2:4 priority encoder
Write Verilog code for D ff
What is Schmitt trigger explain its working
What is the diff bw synthesizable and non-synthesizable task (Verilog)
Some questions from 8051 Microcontroller interrupt because my project is on it
Design a MOD 3 counter
What is the difference bw task and function
What is metastability and MTBF
Technical round 2-
Questions from my Mtech and btech project and thesis
What is diff bw RISC and CISC
What is the concept of pipelining how it is useful
What is setup time and hold time violation
Diff bw moore and mealy machines with some application where they are used
What is the use of shift registers
Explain the working of TTL Logic family
Sequence detector problem
Make LPF and HPF using OPAMP
HAMMING CODE encoder
Logical efforts in CMOS
Think and answer. Both Interview panels were very cool and calm. Take
your time to think and answer.
HR ROUND:-
Tell me about yourself.
Why Qualcomm?
How was ur interview experience today .
Do you have any problem if posting is given at Hyderabad.
Be confident and clear in your answers and proper explanation to it. Make
sure your basics are strong.