THEORY:

A Flip-Flop can store only one bit of data. If we want to store a group of bits, a series of
flip-flops are inter-connected in cascade. This cascaded group of flip-flop as a whole is
called a ‘Register’. The fundamental operations, which make a register very useful, are
its “Shift right” and “Shift left” operation. There are two methods for shifting binary
information into a register.

1. Shifting the information into a register one bit at a time in a series fashion and leads
to the development of a serial shift register.

2. Shifting all the bits into the register at a same time and leads to the development of
a parallel shift register.

Here, we have used IC74AS194. It is a 4-bit Universal Shift register. This bi-directional
shift register has four distinct modes of operation.

Figure 1: IC 74AS194

Parallel Shift Mode:

Applying the four bits of data and taking both mode control inputs, S 0 and S1 high,
accomplish synchronous parallel loading. The data are loaded into the associated flip-
flops and appears at the outputs after the positive transition of the clock input. During
loading, serial data flow is inhibited.
 Figure 2: Universal Shift Register with Parallel Load

INPUTS OUTPUTS
MODE SERIAL PARALLEL
CLEAR CLK QA QB QC QD
S1 S2 LEFT RIGHT A B C D
0 X X X X X X X X X 0 0 0 0
1 X X L X X X X X X QA0 QB0 QC0 QD0
1 1 1 H X X a b c d a b c d
1 0 1 H X 1 X X X X 1 QAn QBn QCn
1 0 1 H X 0 X X X X 0 QAn QBn QCn
1 1 0 H 1 X X X X X QBn QCn QDn 1
1 1 0 H 0 X X X X X QBn QCn QDn 0
1 0 0 X X X X X X X QA0 QB0 QC0 QD0

Shift Right Mode:

Shift right is accomplished synchronously with the rising edge of the clock pulse when
S0 is high and S1 is low. Serial data for this mode is entered at the shift right data input.

Shift Left Mode:

When S0 is low and S1 is high, 1 bit data shifts one position to the left synchronously and
new data is entered at the serial-left serial input at every clock pulse.

Inhibiting Mode:

Clocking of the flip-flops is inhibited when both mode control inputs are low.