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Model Question Paper

Programme : BTech Semester :
Course : Digital Logic Design Code : ECE 2003
Faculty : Slot :
Time : Three Hours Max. Marks : 100

PART – A (6 × 4 = 24 Marks)
Answer all the Questions

Sub
Q.No. . Question Description Marks
Sec.
1. Arnald(A), Betty(B),Cathy(C) and David(D) may attend a school dance, but will dance
only with opposite sex and then only under the following condition: Arnald will dance
with either Betty or Cathy. However, Cathy will dance with Arnald only if Betty is not 4
present at the dance. David will dance only with Betty. Obtain the logic expressions for
DA,DB,DC and DD representing the active state of dancing for A,B,C and D.
2. Convert the given decimal number (1148.26)D to
(i) Hexadecimal number with 2 digits after the hex point 4
(ii) Binary number
3. An 8:1 multiplexer has inputs A, B, and C connected to the selection inputs S2, S1, and S0,
respectively. The data inputs I0 through I7 are as follows: I1 = I2= 0; I3 = I7 = 1; I4 = I5= D 4
and I0 = I6 =D’. Determine the Boolean function that the multiplexer implements.
4. Write the Verilog code for synchronous and asynchronous D flip-flip. 4
5. a) A majority circuit is a combinational circuit whose output is equal to 1 if the input
variables have more 1’s than 0’s. The output is 0 otherwise.
b) 4
Design a 3-input majority circuit by finding the circuit’s truth table, Boolean equation,
and a logic diagram. Write a Verilog gate-level model of the circuit.
6. Find the simplified expression for F(A,B,C,D) = Π(1,3,5,11,15) using K-map. 4
7. a) Design a binary adder which can add two 4-bit numbers. Draw the block diagram and 8
write the structural Verilog code for your design.

b) Consider the design of a light for the staircase of a house. The light should be controlled
from both the bottom and the top of the staircase. The rule to be followed is that switching
either switch should change the state of the light, i.e, if the light was on it goes off, if it
was off it goes on, when either switch is switched. Develop a truth table for this function. 4

8. a) In a ternary number system there are three digits: 0, 1 & 2. Table 1 defines the ternary half
adder. Design a circuit that implements this half adder using binary-encoded signals, such
that two bits are used for each ternary digit. Use the following encoding: 00 = (0)3,
01 = (1)3, and 10 = (2)3. And let A=a1a0, B=b1b0, S=s1s0; note that carry is a single bit 12
binary signal. Modify the table accordingly and implement the design.

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 A B Carry Sum
0 0 0 0
0 1 0 1
0 2 0 2
1 0 0 1
1 1 0 2
1 2 1 0
2 0 0 2
2 1 1 0
2 2 1 1
Table 1

9. A kids gaming machine contains Red balls and White balls. A sucking machine pushes
one ball outside every time a button is pressed. A kid wins a chocolate if he/she gets one
Red ball, two white balls and then one red ball in four consequtive trials.Let logic ‘1’
12
represents red ball and logic ‘0’ represents white ball. Design a synchronous sequential
circuit for this machine. Draw the state diagram, state table and derive the circuit diagram.
Use D flip flop.
10. Design a counter that goes through the states 0-3-1-7-6-4 using JK flip flops. 12
11. Write the Verilog code for a 4-bit UP-DOWN counter. 12
12. a) Design a 4-bit magnitude comparator. Explain the logic equations and draw the circuit
diagram. 7
b) Using the above design as a basic block, design a comparator which compares two, 2-digit 2
BCD numbers.
c) Write the Verilog code for the above design in behavioural modelling. 7

Total 100
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