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1FEATURES DESCRIPTION
•
2 15 MHz Small Signal Bandwidth The LM118 series are precision high speed
operational amplifiers designed for applications
• Ensured 50V/μs Slew Rate requiring wide bandwidth and high slew rate. They
• Maximum Bias Current of 250 nA feature a factor of ten increase in speed over general
• Operates from Supplies of ±5V to ±20V purpose devices without sacrificing DC performance.
• Internal Frequency Compensation The LM118 series has internal unity gain frequency
• Input and Output Overload Protected compensation. This considerably simplifies its
application since no external components are
• Pin Compatible with General Purpose Op necessary for operation. However, unlike most
Amps internally compensated amplifiers, external frequency
compensation may be added for optimum
performance. For inverting applications, feedforward
compensation will boost the slew rate to over
150V/μs and almost double the bandwidth.
Overcompensation can be used with the amplifier for
greater stability when maximum bandwidth is not
needed. Further, a single capacitor can be added to
reduce the 0.1% settling time to under 1 μs.
The high speed and fast settling time of these op
amps make them useful in A/D converters, oscillators,
active filters, sample and hold circuits, or general
purpose amplifiers. These devices are easy to apply
and offer an order of magnitude better AC
performance than industry standards such as the
LM709.
The LM218-N is identical to the LM118 except that
the LM218-N has its performance specified over a
−25°C to +85°C temperature range. The LM318-N is
specified from 0°C to +70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM118-N, LM218-N, LM318-N
SNOSBS8C – MARCH 1998 – REVISED MARCH 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Electrical Characteristics
Parameter Conditions LM118-N/LM218-N LM318-N Units
Min Typ Max Min Typ Max
Input Offset Voltage TA = 25°C 2 4 4 10 mV
Input Offset Current TA = 25°C 6 50 30 200 nA
Input Bias Current TA = 25°C 120 250 150 500 nA
Input Resistance TA = 25°C 1 3 0.5 3 MΩ
Supply Current TA = 25°C 5 8 5 10 mA
Large Signal Voltage Gain TA = 25°C, VS = ±15V 50 200 25 200 V/mV
VOUT = ±10V, RL ≥ 2 kΩ
Slew Rate TA = 25°C, VS = ±15V, AV = 1
(2) 50 70 50 70 V/μs
(1) These specifications apply for ±5V ≤ VS ≤ ±20V and −55°C ≤ TA ≤ +125°C (lm118-n), −25°C ≤ TA ≤ +85°C (LM218-N), and 0°C ≤ TA ≤
+70°C (LM318-N). Also, power supplies must be bypassed with 0.1 μF disc capacitors.
(2) Slew rate is tested with VS = ±15V. The lm118-n is in a unity-gain non-inverting configuration. VIN is stepped from −7.5V to +7.5V and
vice versa. The slew rates between −5.0V and +5.0V and vice versa are tested and specified to exceed 50V/μs.
2 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated
Figure 1. Figure 2.
Figure 3. Figure 4.
Figure 5. Figure 6.
Figure 7. Figure 8.
AUXILIARY CIRCUITS
Slew and settling time to 0.1% for a 10V Figure 41. Overcompensation
step change is 800 ns.
TYPICAL APPLICATIONS
CF = Large
(CF ≥ 50 pF)
*Do not hard-wire as integrator or slow inverter; insert a 10k-5 pF network in series with the input, to prevent
oscillation.
Do not hard-wire as voltage follower (R1 ≥ 5 kΩ)
Figure 43.
ΔOutput zero.
*“Y” zero
+“X” zero
‡Full scale adjust.
Schematic Diagram
Pin Diagram
Pin connections shown on schematic diagram and typical applications are for TO-99 package.
TO-99 Package
(Top View)
See Package Number LMC (O-MBCY-W8)
REVISION HISTORY
www.ti.com 14-Jan-2019
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM118H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -55 to 125 ( LM118H, LM118H)
LM118H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS Call TI Level-1-NA-UNLIM -55 to 125 ( LM118H, LM118H)
& no Sb/Br)
LM318M NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LM
318M
LM318M/NOPB ACTIVE SOIC D 8 95 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 LM
& no Sb/Br) 318M
LM318MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 LM
& no Sb/Br) 318M
LM318N/NOPB ACTIVE PDIP P 8 40 Green (RoHS CU SN Level-1-NA-UNLIM 0 to 70 LM
& no Sb/Br) 318N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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