Types of Standard Cells:

 STDCELLS:

 Nothing But Base cells (Gates, flops).

 TAP CELLS: (Technology Dependant)

 Avoids Latch up Problem (Placing these cells with a particular distance).
 Tap cells are well-tied cells that bias the silicon infrastructure of n-wells or
p-wells.
 They are traditionally used so that Vdd or Gnd are connected to substrate
or n-well respectively.
 This is to Help TIE Vdd and Gnd which results in lesser drift and prevention
from latchup.
 Required by some technology libraries to limit resistance between Power
or Ground connections to well of the substrate.

 TIE CELLS :
 It is used for preventing Damage of cells; Tie High cell (Gate One input is
connected to Vdd, another input is connected to signal net); Tie low cells
Gate one input is connected to Vss, another input is connected to signal.
 Tie - high and Tie - low cells are used to connect the gate of the transistor
to either Power or Ground.
 In lower technology nodes, if the gate is connected to Power or Ground.
The transistor might be turned "ON/OFF" due to Power or Ground Bounce.
  These cells are part of the std cell library.
 The cells which require Vdd (Typically constant signals tied to 1) connect to
tie high cells.
 The cells which require Vss/Vdd (Typically constant signals tied to 0)
connect to tie low cells.

 END CAP CELLS: (Technology Dependant)

 To know the end of the row, and at the edges endcap cells are placed to
avoid the cells damages at the end of the row to avoid wrong laser
wavelength for correct manufacturing.
 You can add Endcap cells at both Ends of a cell row.
 Endcap cells surrounding the core area features which serve as second
poly to cells placed at the edge of row.
 The library cells do not have cell connectivity as they are only connected to
Power and Ground rail,
 Thus ensure that gaps do not occur between "WELL" and "IMPLANT
LAYER" and to prevent the DRC violations by satisfying "WELL TIE -
OFF" requirements for core rows we use End cap cells.
 Usually adding the "Well Extension" for DRC correct designs.
 End caps are a "POLY EXTENSION" to avoid drain source SHORT

 DECAP CELLS:
  De cap cells are temporary capacitors added in the design between power
and ground rails to counter functional failures due to dynamic IR drop.
 Dynamic I.R. drop happens at the active edge of the clock at which a high
percentage of Sequential and Digital elements switch.
 Due to this simultaneous switching a high current is drawn from the power
grid for a small duration.If the power source is far away from a flop the
chances are that this flop can go into a metastable state due to IR Drop.
 To overcome this decaps are added. At an active edge of clock when the
current requirement is high , these decaps discharge and provide boost to
the power grid.
 One caveat in usage of decaps is that these add to leakage current.
 De caps are placed as fillers.
 The closer they are to the flop’s sequential elements, the better it is.

 FILLER CELLS:
 Filler cells are used to connect the gaps between the cells after placement.
 Filler cells are used to establish the continuity of the N-Wells and the
IMPLANT LAYERS on the standard cells rows, some of the cells also don't
have the Bulk Connection (Substrate connection) Because of their small
size (thin cells).
 In those cases, the abutment of cells through inserting filler cells can
connect those substrates of small cells to the Power/Ground nets.
I.e. those tin cells can use the Bulk connection of the other cells (this is one
of the reason why you get stand-alone LVS check failed on some cells)
 ICG CELLS:
 Clock gating cells, to avoid Dynamic power Dissipation.
 Register banks disabled during some clock cycles.
 During idle modes, the clocks can be gated-off to save Dynamic power
dissipation on flip-flops.
 Proper circuit is essential to achieve a gated clock state to prevent false
glitches on the clock paths

 POWER GATING CELLS:

 In Power gating to avoid static power Dissipation.
Power Gating Cells:
 Power switches
 Level Shifters
 Retention registers
 Isolation cells
 Power controller

 PAD CELLS:
 To Interface with outside Devices; Input to of Power, Clock, Pins are
connected to pad cells and outside also.

 CORNER CELLS:
 Corner Pads are used for Well Continuity.
  To lift the chip.

 MACRO CELLS:
 Memories.
 The memory cells are called Macros.
 To store information using sequential elements takes up lot of area.
 A single flip-flop could take up 15 to 20 transistors to store one bit store
the data efficiently and also do not occupy much space on the chip
comparatively by using macros.

 SPARE CELLS:
 Used at the ECO.
 Spare cells are standard cells in a design that are not used by the netlist.
 Placing the spare cells in your design provides a margin for correcting
logical error that might be detected later in the design flow, or for
adjusting the speed of your design.
 Spare cells are used by the fix ECO command during ECO process.

 PAD FILLER CELLS:

 Used for Well Continuity, Placed in between Pads.

 JTAG CELLS:
 These are used to check the IO connectivity.
Flavours Of Cells:

1. Different Drive Strengths and Vt:

 The purpose of logic gate is to propagate the effect of logic value

available at its input to the output. Based upon whether '0' or '1' is to be
propagated to the output.
 The corresponding is achieved by charging and discharging of the output
load capacitance. Propagating a logic '0' will mean discharging of the load
capacitance, and vice-versa.

 Drive strength of the logic gate is the its relative capability to

charge/discharge the capacitance present at its output. Now, the time
constant, and hence, delay of the circuit is "RC".

 So, for a cell with higher drive strength, corresponding "R" is lesser than
the one with lower drive strength. So that for same load capacitance "C",
delay is lower for a cell with higher drive strength as it can charge the
capacitance in lesser time.

 From another point of view, it is just the strength required to

charge/discharge the capacitance at the output to the required value.
Greater the drive strength, higher current can be drawn from the supply
 and the output capacitors can be charged quickly, if drive strength is low,
then the current is less and the output capacitance takes time to
charge/discharge.

How drive strength varies with size of a cell: Let us talk in terms of MOSFETs,
although this is valid in terms of every device in general. We know that for a
given technology standard cell library, length of all transistors is kept constant.

For instance, 90 nm technology will have gate length of all transistors as ~90
nm. And channel resistance of the MOSFET is inversely proportional to "W/L" of
the transistor. So, a simple way to decrease channel resistance is to increase
"W" of the transistor.

So, a transistor with more area will have lesser resistance. Or we can say that a
logic gate with bigger transistors will have more drive strength.

What is unit drive strength: In a standard cell library, we generally see cells
labelled as "1X", "2X" and so on. But what is meant by the number that you see
with drive strength?

In general, the lowest size logic gate is labelled as unit drive strength. The drive
strength numbers of other cells are laelled relative to unit drive strength cell.
2. Different Architectures:
The standard cell libraries provide three separate architectures, high-speed
(HS), high-density (HD), and ultra high-density (UHD), to optimize circuits for
performance, power and area tradeoffs.