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WHAT IS A CLOCK AND WHAT ARE THE

DIFFERENT TYPES OF CLOCKS DEFINED FOR
TIMING ANALYSIS ?
AUGUST 20, 2013 | GAYATHRI | 1 COMMENT

What is a clock and what are the different types of clocks de ned for Timing Analysis ?

Clock is a signal used for synchronization when the data passes through the storage elements like ip-
ops and latches. It is to ensure that the correct data is captured in each sequential element. The
waveform of a basic clock is as shown below.

Clock sources

In an ASIC design, clock can be generated from sources like PLLs or Crystal Oscillators. PLL or Phase
Locked Loop is a circuit which generates the clock signal with reference to an input signal. It has a
circuitry to compare between the reference and the feedback signal to keep the output phase locked to
the input. Crystal Oscillator uses the mechanical resonance of a vibrating crystal to generate an output
clock signal. The output from a crystal oscillator is precise.

Clock Tree

Clocks are distributed to the sink points. They are sequential elements through clock trees or clock
distribution networks. Clock tree is a collection of buffers or inverters. An ideal clock tree has the same
number of levels of buffers/inverters from the source to the sinks. This promises equal delay of the clock
from a single source to all sinks, which means zero clock skew. A clock tree gives balanced fanout too.

Clock Types

Master clocks: These are clocks which get de ned at the main clock source like oscillator/PLL. In a chip
master clock can be de ned at some clock input ports too. When we de ne these master clocks, proper
frequency and source information should be given. Uncertainty also should be speci ed.
Generated clocks: These are divider/multiplier clocks which get generated from a master clock. Mostly
these are de ned at the output of a clock divider like ip op or mux. When we de ne a generated clock,
its source clock, the generation point, division ratio and uncertainty value should be provided.
Generated clocks can be also de ned at any point, if we need to de ne some exception wrt this clock.

Virtual clocks : These are clocks used to time the input/output port. These are imaginary clocks de ned
only with the clock waveform and not having any source/generation point.

For more details kindly refer my post on Virtual Clocks.

Clock Relationships

The relationship between different clocks should be speci ed correctly for accurate timing analysis.

Synchronous clocks: These are clocks those interact each other. They should be ideally generated from
the same clock source and should have related waveforms.

Asynchronous clocks: These are clocks those don’t interact each other. They will be generated from
different clock sources or will be having non related clock waveforms/frequencies.

Logically Exclusive clocks: These are clocks which are asynchronous to each other, but which will be
present physically at the same time.

Physically Exclusive clocks: These are clocks those are asynchronous to each other which will not be
physically present together at the same time.

For ef cient timing analysis accurate de nition of clocks is very important. Always review your clock
de nitions before proceeding to Timing Analysis. If we miss some clock de nition it can be gured out
from the no clock point analysis. But if we code the wrong clock frequency in the constraints, only
review can catch the mistake.
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Ramanji Reddy • 5 months ago

Hi sir This is ram i am finding very interesting information in your blog i need all this info can u share it
to me sir for this mail regards STA and Synthsis Wireload Model
ramanjineyareddy.t.v@gmail.com
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