Introduction Zynq

Lecture 1 Andreas Habegger

Introduction Zynq
Introduction Zynq Introduction

Zynq PS vs. PL Processing System

Processor Peripherals
Data Buses
AXI Bus

Conclusion

BTE5380 - Embedded Systems

Octobre 2014

Andreas Habegger
Bern University of Applied Sciences
Rev. – 1.1
Zynq: A Programmable SoC Introduction Zynq

Andreas Habegger

Zynq-7000 family is an APS O C from Xilinx

Complete ARM-based processing system
application processor unit (APU)
Introduction
fully integrated memory controllers
Processing System
I/O peripherals Processor Peripherals
Tightly integrated programming logic AXI Bus

used to extend the processing system Conclusion

scalable density and performance

Flexible array of I/O
wide range of external multi-standard I/O
high-performance integrated serial transceivers
analog-to-digital converter inputs

The slides are based on Xilinx Tutorials.

Rev. – 1.2
Zynq SoC Block Diagram Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.3
Processor and Hardware Logic Introduction Zynq

Andreas Habegger

The Zynq-7000 S O C architecture consists of two major

sections:
PS: processing system
dual ARM Cortex-A9 processors, 866MHz to 1GHz
frequency
Introduction
multiple peripherals
Processing System
hard silicon core
Processor Peripherals
PL: programmable logic
AXI Bus
shares the same F PGA series 7 programmable logic
Conclusion
logic cells: 28k - 444k (430k to 6.6M gates)
flip-flops: 35k - 554k
D SP /M AC: 80 - 2020
peak D SP performance: 100 - 2622 GMACs
AD converter: two 12bits

Rev. – 1.4
ARM Processor Architecture Introduction Zynq

Andreas Habegger

A RM Cortex-A9 processor implements the A RMv7-A

architecture
A RMv7 is the A RM instruction set architecture I SA
A RMv7-A: application set that includes support for a M MU
A RMv7-R: real-time set that includes support for a memory Introduction

protection unit M PU Processing System

A RMv7-M: microcontroller set that is the smallest set Processor Peripherals

AXI Bus
A RMv7 I SA includes the following types of instructions (for
Conclusion
backward compatibility)
Thumb instructions: 16 bits, Thumb-2 instructions: 32 bits
N EON: A RMs single instruction multiple data instructions
A RM advanced microcontroller bus architecture (A MBA)
protocol
A XI 3: third-generation A RM interface
A XI 4: adding to existing A XI definitions (extended bursts,
subsets)
Cortex is the new family of processors

Rev. – 1.5
ARM Cortex-A9 Processor Power Introduction Zynq

Andreas Habegger

dual-core processor cluster

2.5 D MIP/MHz per processor
Harvard architecture
Introduction
self-contained 32KB L1 caches for instruction and data Processing System

external memory based 512KB L2 cache Processor Peripherals

AXI Bus
automatic cache coherencey between processor cores Conclusion

1 GHz operation (fastest speed grade)

Rev. – 1.6
Cortex-A9 Processor Micro-Architecture (1) Introduction Zynq

Andreas Habegger

instruction pipeline
supports out-of-order
instruction issue and
completion Introduction

Processing System
register renaming to Processor Peripherals
enable execution AXI Bus

speculation Conclusion

non-blocking
memory system with
load-store forwarding
fast loop mode in
instruction pre-fetch
to low power
consumption

Rev. – 1.7
Cortex-A9 Processor Micro-Architecture (2) Introduction Zynq

Andreas Habegger

variable length, out-of-order, eigth-stage, super-scalar

instruction pipeline
Introduction
advanced pre-fetch with parallel branch pipeline enabling
Processing System
earlier branch prediction and resolution
Processor Peripherals
speculative execution AXI Bus

supports virtual renaming of A RM physical registers to Conclusion

remove pipeline stall due to data dependencies

increased processor utilization and hiding of memory
latencies
increased performance by hardware unrolling of code loops
reduced interrupt latency via speculative entry to Interrupt
Service Routine I SR

Rev. – 1.8
Processor System Components Introduction Zynq

Andreas Habegger

application processing unit (A PU)

I/O peripherals (I OP)
Introduction
multiplexed I/O (M IO), extended multiplexed I/O (E MIO) Processing System

memory interfaces Processor Peripherals

AXI Bus
PS interconnect
Conclusion
D MA
timers
general interrupt controller G IC
on-chip memory (O CM): R AM
debug controller: CoreSight

Rev. – 1.9
Processor System Interconnect (1) Introduction Zynq

Andreas Habegger

programmable logic
to memory
two ports to D DR
one port to O CM
S RAM
Introduction

central interconnect Processing System

enables other Processor Peripherals

AXI Bus
interconnects to
Conclusion
communicate

peripheral master
U SB, GigE, S DIO
connects to D DR
and PL via the
central
interconnect

peripheral slave
C PU, D MA, and
PL access to I OP Rev. – 1.10
Processor System Interconnect (2) Introduction Zynq

Andreas Habegger

processing system
master
two ports from the
processing
system to
programmable Introduction

logic Processing System

connects the C PU Processor Peripherals

block to common AXI Bus

peripherals Conclusion

through the
central
interconnect

processing system
slave
two ports from
programmable
logic to the
processing
system
Rev. – 1.11
Memory Map Introduction Zynq

Andreas Habegger

the Cortex-A9 processor

uses 32-bit addressing
Introduction
all PS and PL peripherals Processing System

are memory mapped to the Processor Peripherals

Cortex-A9 processor cores AXI Bus

Conclusion
all slave PL peripherals will
be located between:
40000000 and 7FFFFFFF
(connected to GP0) and
80000000 and BFFFFFFF
(connected to GP1)

Rev. – 1.12
Memory Resources Introduction Zynq

Andreas Habegger

on-chip memory (O CM) Introduction

Processing System
R AM
Processor Peripherals
boot R OM
AXI Bus
D DRx dynamic memory controller Conclusion
supports L PDDR 2, D DR 2, D DR 3
flash/static memory controller
supports S RAM, Q SPI, N AMD /N OR flash

Rev. – 1.13
PS Boots First Introduction Zynq

Andreas Habegger

C PU 0 boots from O CM R OM; C PU 1 goes into a sleep state

on-chip boot loader in O CM R OM (stage 0 boot)
processor loads First Stage Boot Loader (F SBL) from Introduction

Processing System
external flash memory
Processor Peripherals
N OR
AXI Bus
N AND Conclusion
Quad S PI
SD card
J TAG: not a memory device - used for development/debug
only
boot source selected via package bootstrapping pins
optional secure boot mode allows the loading of encrypted
software from the flash boot memory

Rev. – 1.14
Configuring the PL Introduction Zynq

Andreas Habegger

the programmable logic is configured after the PS boots

Introduction
performed by application software which is accessing the
Processing System
hardware device configuration unit
Processor Peripherals
bitstream image transfered AXI Bus
100MHz, 32-bit P CAP stream interface Conclusion
decryption/authentication hardware option for encrypted
bitstream (in secure boot mode, this option can be used for
software memory load)
built-in D MA allows simultaneous PL configuration and OS
memory loading

Rev. – 1.15
Input/Output Peripherals Introduction Zynq

Andreas Habegger

two GigE
two U SB
two S PI Introduction

two S D /S DIO Processing System

Processor Peripherals
two C AN
AXI Bus
two I2 C Conclusion

two UART
four 32-bit G PIO
static memories
N AND,
N OR /S RAM, Quad
S PI
trace ports

Rev. – 1.16
Multiplexed I/O (MIO) Introduction Zynq

Andreas Habegger

external interface to PS I/O

peripheral ports Introduction

Processing System
54 dedicated package
Processor Peripherals
pins available
AXI Bus
software configurable
Conclusion
automatically added to
bootloader by tools
not available for all
periphery ports
some ports can only
use E MIO

Rev. – 1.17
Extended Multiplexed I/O (EMIO) Introduction Zynq

Andreas Habegger

extended interface to PS
I/O peripheral ports
E MIO: peripheral port to Introduction

Processing System
programmable logic
Processor Peripherals
alternative to use M IO
AXI Bus
mandatory for some
Conclusion
peripheral ports
facilitates
connection to
peripheral in
programmable logic
use of general I/O pins
to supplement M IO pin
usage

Rev. – 1.18
PS-PL Interfaces (1) Introduction Zynq

Andreas Habegger

A XI high-performance slave
ports (HP0-HP3)
configurable 32-bit or 64-bit
data width
access to O CM and D DR only Introduction

conversion to processing Processing System

Processor Peripherals
system clock domain
AXI Bus
A XI F IFO interface (A FI) are
Conclusion
F IFOs (1KB) to smooth large
data transfers
A XI general-purpose ports
(GP0-GP3)
two masters from PS to PL
two slaves from PL to PS
32-bit data width
conversation and sync to
processing system clock
domain

Rev. – 1.19
PS-PL Interfaces (2) Introduction Zynq

Andreas Habegger

one 64-bit accelerator coherence port (ACP) A XI slave

interface to C PU memory
D MA, interrupts, event signals
Introduction
processor event bus for signaling event information to the Processing System
C PU Processor Peripherals
PL peripheral IP interrupts to the PS general interrupt AXI Bus
controller (G IC) Conclusion
four D MA channel R DY /ACK signals
extended multiplexed I/O (E MIO) allows PS peripheral
ports access to PL logic and device I/O pins
clock and resets
four PS clock outputs to the PL with enable control
four PS reset outputs to the PL
configuration and miscellaneous

Rev. – 1.20
PL Clocking Sources Introduction Zynq

Andreas Habegger

PS clocks
PS clock source from external package pin
PS has three P LLs for clock generation Introduction
PS has four clock ports to PL Processing System
PL has 7 series clocking resources Processor Peripherals

PL has a different clock source domain compared to the PS AXI Bus

the clock to PL can be sourced from the external clock Conclusion

capable pins
one of the four PS clock sources can be used for the PL
PS architecture synchronizes the clock between PL and
PS
PL cannot supply clock source to PS
GUI interface for PL and PS clock definition

Rev. – 1.21
Clocking the PL Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.22
Zynq Resets Introduction Zynq

Andreas Habegger

internal resets
power-on-reset (P OR) Introduction

watchdog resets from the three watchdogs timers Processing System

secure violation reset Processor Peripherals

AXI Bus
PS resets
Conclusion
external resets: PS_SRST_B
warm reset: SRSTB
PL resets
four reset outputs from PS to PL
FCLK_RESET[3:0]

Rev. – 1.23
AXI is Part of ARM’s AMBA Bus Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.24
Basic AXI Signaling - 5 Channels Introduction Zynq

Andreas Habegger

1. read address channel Introduction

Processing System
2. read data channel
Processor Peripherals

AXI Bus

Conclusion

3. write address channel

4. write data channel
5. write response channel

Rev. – 1.25
The AXI Interface - AXI4-Lite Introduction Zynq

Andreas Habegger

no burst
Introduction
data width 32 or 64 Processing System
Xilinx IP only Processor Peripherals
suppports 32-bits AXI Bus

very small footprint Conclusion

bridging to AXI4
handled
automatically by
AXI_Interconnect

Rev. – 1.26
The AXI Interface - AXI4 Introduction Zynq

Andreas Habegger

sometimes called
"Full AXI" or
"memory mapped" Introduction

not Processing System

A RM-sanctioned Processor Peripherals

names AXI Bus

Conclusion
single address
multiple data
burst up to 256
data beats
data width
parameterizable
1024 bits

Rev. – 1.27
The AXI Interface - AXI4-Stream Introduction Zynq

Andreas Habegger

no address channel, no
read and write, always
just master to slave
effectively and A XI4 Introduction
"write data" channel Processing System

unlimited burst length Processor Peripherals

AXI Bus
A XI4 max 256
Conclusion
A XI4-Lite does not burst
virtually same signaling
as A XI data channels
protocol allows
merging, packing, width
conversion
supports sparse,
continuous, aligned,
unaligned streams

Rev. – 1.28
The AXI Interface -Streaming Applications Introduction Zynq

Andreas Habegger

may not have packets

Introduction
e.g: digital up converter:
Processing System
no concept of address
Processor Peripherals
free running data (in this case)
AXI Bus
A XI4-stream would optimize to a very simple interface (in
Conclusion
this case)
may have packets
e.g: P CIe:
their packets may contain different information
typically bridge logic of some sort is needed

Rev. – 1.29
Conclusion Introduction Zynq

Andreas Habegger

the Zynq-7000 processing platform is a system-on-chip

S O C processor with embedded programmable logic
the processing system (PS) is a hard silicon dual core
consisting of
an application processor unit Introduction

two A RM Cortex-A9 processors Processing System

N EON co-processor Processor Peripherals

general interrupt controller AXI Bus
general and watchdog timers Conclusion

I/O peripherals
external memory interfaces
the programmable logic (PL) consists of 7 series devices
high performance A XI4 point-to-point interface
tightly coupled A XI4 ports interfacing PS and PL
PS boots from a selection of external memory devices
PL is configured by and after PS boots
PS provides clocking resources to PL
Rev. – 1.30