Standard Library Cell Design using 45nm Technology

FRAMEWORK

The increasing demand for system integration by combination of transistors

along with less power dissipation has been in development with the CMOS
technology. The recent usage of deep sub-micron tenure was due to the rise in
demand for integration of much more components on to a single chip for better
performance with less power consumption.
ASIC consists of logic blocks which are pre-designed and pre-verified in
system library functions which lead to the success for the rapid increase of integrated
system. This further helped designers to reduce the time for product development
and to manage ramifications by adding more and more transistors.
Standard cell methodology is a phenomenon of designing ASICs (Application
Specific Integrated Circuits) that is used in designing semiconductors with digital-
logic features. It is shown as an example of design consideration by enclosing the
low-level VLSI-layout into an abstract logic representation.
A NOR 2 input and NAND 2 input function is adequate to design a random
Boolean function set. But in present ASIC design, standard library cell methodology
is exercised with a scalable library cells which has many implementations of similar
logic function, with varying speed and area. This variety embellishes the drastic
amount of efficiency of placement and routing (PNR), automated synthesis tools.
A technology library is formed by a complete group of standard cell
descriptions. The choice of library decides the efficiency and economic
accomplishment of ASIC design. Hence the design requirement is fulfilled. There is
an unlimited number of products like mobiles, processors, televisions etc. that uses
characterized IC components.
A digital IC can be fabricated using similar basic steps with the help of different
methodologies. Fabrication steps starts with transistors, wiring etc., which is
designed using Computer Aided Design (CAD) tools. This helps in physically
realising the chip. Depending upon the requirements, we have three different design
approaches.

Full custom design is the process of developing the layout from the scratch. Designs
can be altered for increase in speed, capacitive load, area etc. All the wires in layout
are placed manually. The designer has the freedom to properly optimise his designs

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 Standard Library Cell Design using 45nm Technology

based on the requirements. There is an accessible advantage in the layout so that it

can be created very precisely.
Semi-Custom design is the process of importing cells from already available
standard library cells to complete the design. A supplier creates gates such as buffer,
NAND, NOR etc. and distributes them as library cell which can be further used by
the designer. The designer will place logic blocks in the layout as per the desired
specification. The advantage in this approach is the decrease in the required time.
the combination of semi-custom and full-custom is a very good approach to create
the logic gates manually and optimize.
Automatic Design is a process that generates layouts automatically and checks the
circuits by comparing them with the created library cell. The design can be created
using HDL (Hardware Description Languages) like VHDL or Verilog. In order to
meet the required constraints, optimisation of the generated layouts are performed
through CAD tools. Though the optimisation can be performed in different ways,
the designer doesn’t have any control over the layout generation. Using this design
less optimised layouts are designed when compared with other two designs.
However, automatic design is a very useful tool when the design to be created does
not have very strict requirements and when the time to market is more important
than a fully optimized design.

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INTRODUCTION

A Boolean logic or a storage function can be implemented using a standard

library cell which consists of a set of transistors. A NAND or a NOR gate can be
used to generate any Boolean function. The design’s area can be reduced by using
other logic gates. The basic gates such as Buffer, Inverter, AND, OR, etc. universal
gates such as NAND and NOR and other gates such as XOR and memory cells are
the components found in any standard library. Complex libraries consist of several
other cells such as adders and multipliers.
Initially, the standard cell is designed by implementing the functionality of
the cell at a transistor level. It is done by drawing a schematic. Simulation and
debugging is done to ensure proper operation. The representation of the schematic
of a cell is done using a symbol which is composed of the input and output ports of
the cell. Text information can also be included in it.
For simulation purposes, the netlist is useful. Hence it is required to design
the layout view. Although it is not used for fabrication it is compulsory. Many base
layers are combined to form a layout which basically consists of interconnect lines
and transistor structures. The layout of a cell represents what will be physically
placed on a chip. Though there are many CAD tools that assists the procedure of
design, we still face challenges in designing efficient layouts that could meet the
required constraints.
The designed layouts are repeatedly checked to ensure that the design rules
are not violated (called as Design Rule Check). In order to check the consonance of
the layout with its corresponding schematic, Layout vs. Schematic (LVS) is
performed. After the parasitic extraction, post layout simulation is performed. The
placement-and-routing tools are given details about the height and width of cells
along with dimension and location of their input and output pins. The layouts are
directed to the Abstract Generator, where the Library Exchange Format (LEF) file
is produced. LEF files also give information about the technology’s spacing and
thickness and the minimum width of the layers present. The layout information of
the schematics that we create is available as a GDS (Graphic Database System) file
which can be sent for fabrication purposes.

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Standard cell definition:

 Standard cell is specific design for each gate. Using the standard cell we can
increase the performance and reducing the time to design. Standard cell are
the area minimize element.
Why standard cell?
 Standard cells usually refer to blocks of logic that are arranged into a library
of elements. This is the library you buy from a fabrication facility (FAB) when
you order their services for chip fabrication. These "cells" are coming fully
validated and characterized by the vendor for each particular fabrication node,
with all timing and power consumption etc.
Advantages of using standard cells:
1. The gate count is high
2. The quantity required is high
3. The circuit design is firm
4. The turnaround time needed is short

Vertical and Horizontal Routing Grids:

 Cell pins, with the exception of abutment pins (VDD and GND) must be
placed on the intersections of the vertical and horizontal routing grids.
 Vertical and horizontal routing grids may be offset with respect to the cell’s
origin, provided that the offset distance is exactly one-half of the grid spacing.
 The cell height must be a multiple of the horizontal grid spacing; the cell width
must be a multiple of the vertical grid spacing.
 All cells must have the same height, but some complex cells can be designed
with double height.
 Routing grids are used by the CAD tools to route wires over the standard cells
placed in the design Some CAD tools can route off grid, however most are
optimal when they route on grid

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 Standard Library Cell Design using 45nm Technology

What are Routing Grids For?

 The routing grids are where the over-the-cell metal routing will be
routed.
 The pins of your standard cells should always lie on the intersections of
the horizontal and vertical routing grids. Although some CAD tools will
route to off-grid pins, this may cause some other complications.

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Pin routing styles:

 During the pin routing the metal should be on track and metal jogs
should be avoided.

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 Standard Library Cell Design using 45nm Technology

 Metal 1 can be routed both vertically and horizontally and should be on

track.
 Metal 2 can be routed horizontally and should be on track.

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 Standard Library Cell Design using 45nm Technology

STICK DIAGRAM

The physical mask layout of any circuit to be manufactured using particular

process must obey a set of geometric constraints referred to as layout design rules.
These rules specify the minimum allowable line widths, component dimensions and
separation on-chip. The design rule objective is to achieve an overall high yield with
reliability for any circuit manufactured with a particular process using the smallest
possible silicon chip. However violation to any specified rule, which is imminent in
a VSLI layout design, due to its complexity, would mean a low yield and therefore
un-manufacturability of the product. In the early days of CMOS integrated circuit, it
was observed that when a chip was illuminated with a source of white light, each
conducting layer had a unique colour associated with it when viewed under the
microscope. This observation apparently provided the basis for the development of
the stick diagram technique. Oxide layers appeared transparent (crystalline), hence
not shown in a stick diagram. A stick diagram is paper and pencil tool that is used to
plan layout of a cell. It resembles the actual layout but uses “sticks” or lines to
represent the devices and components. It is a schematic representation of a circuit at
the physical design level with each conducting component layer represented by a
line of distinct colour, used for planning the layout and routing of integrated circuit.
The stick diagram is an abstract representation of layout which can help us
understand the circuit function and its geometrical location relative to other circuit
block. The stick diagram shows all components in their relative rather than exact
positions. The sizes of the component (e.g. transistor) are not drawn to scale. The
wires are drawn as stick figures with no width. The VLSI is a 3-dimensional set of
patterned material layers, whose designs aims at translating circuit concept onto
silicon chip or wafer. The stick diagram provides a top view of the patterns.
A stick diagram is a kind of diagram which is used to plan the layout of a transistor
cell. The stick diagram uses “sticks” or lines to represent the devices and conductors.
 VLSI design aims to translate circuit concepts onto silicon.
 Stick diagrams are a means of capturing topography and layer information
using simple diagrams.
 Stick diagrams convey layer information through color codes (or
monochrome encoding).
 Acts as an interface between symbolic circuit and the actual layout.

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 Does show all components/via.

 It shows relative placement of components.
 Goes one step closer to the layout
 Helps plan the layout and routing
 Does not show
 Exact placement of components
 Transistor sizes
 Wire lengths, wire widths, tub boundaries.
 Any other low level details such as parasitic.
Stick diagram: Rules
Rule 1.
When two or more ‘sticks’ of the same type cross or touch each other that
represents electrical contact.
Rule 2.
When two or more ‘sticks’ of different type cross or touch each other there is
no electrical contact. (If electrical contact is needed we have to show the connection
explicitly).

Rule 3.
When a poly crosses diffusion it represents a transistor.

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Rule 4

In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff.

All pMOS must lie on one side of the line and all nMOS will have to be on the other
side.

They act as an interface or communication link between the circuit designer

and the process engineer during the manufacturing phase. The objective associated
with layout rules is to obtain a circuit with optimum yield (functional circuits versus
non-functional circuits) in as small as area possible without compromising reliability
of the circuit. In addition, Design rules can be conservative or aggressive, depending
on whether yield or performance is desired. Generally, they are a compromise
between the two. Manufacturing processes have their inherent limitations in
accuracy. So the need of design rules arises due to manufacturing problems like –
• Photo resist shrinkage, tearing.

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• Variations in material deposition, temperature and oxide thickness.

• Impurities.
• Variations across a wafer.
These lead to various problems like:
• Transistor problems: Variations in threshold voltage: This may occur due to
variations in oxide thickness, ion-implantation and poly layer. Changes in
source/drain diffusion overlap. Variations in substrate.
• Wiring problems: Diffusion: There is variation in doping which results in variations
in resistance, capacitance. Poly, metal: Variations in height, width resulting in
variations in resistance, capacitance. Shorts and opens.
• Oxide problems: Variations in height. Lack of planarity.
• Via problems: Via may not be cut all the way through. Undersize via has too much
resistance. Via may be too large and create short. To reduce these problems, the
design rules specify to the designer certain geometric constraints on the layout
artwork so that the patterns on the processed wafers will preserve the topology and
geometry of the designs. This consists of minimum-width and minimum-spacing
constraints and requirements between objects on the same or different layers. Apart
from following a definite set of rules, design rules also come by experience.

Types of Design Rules

The design rules primary address two issues:
1. The geometrical reproduction of features that can be reproduced by the mask
making and lithographical process, and
2. The interaction between different layers.
There are primarily two approaches in describing the design rules.
1. Linear scaling is possible only over a limited range of dimensions.
2. Scalable design rules are conservative .This results in over dimensioned and less
dense design.
3. This rule is not used in real life.
1. Scalable Design Rules (e.g. SCMOS, λ-based design rules): In this approach, all
rules are defined in terms of a single parameter λ. The rules are so chosen that a
design can be easily ported over a cross section of industrial process, making the
layout portable .Scaling can be easily done by simply changing the value of.

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The key disadvantages of this approach are:

2. Absolute Design Rules (e.g. μ-based design rules): In this approach, the design
rules are expressed in absolute dimensions (e.g. 0.75μm) and therefore can exploit
the features of a given process to a maximum degree. Here, scaling and porting is
more demanding, and has to be performed either manually or using CAD tools .Also,
these rules tend to be more complex especially for deep submicron. The fundamental
unity in the definition of a set of design rules is the minimum line width .It stands
for the minimum mask dimension that can be safely transferred to the semiconductor
material .Even for the same minimum dimension, design rules tend to differ from
company to company, and from process to process. Now, CAD tools allow designs
to migrate between compatible processes. Layer Representations With increase of
complexity in the CMOS processes, the visualization of all the mask levels that are
used in the actual fabrication process becomes inhibited. The layer concept translates
these masks to a set of conceptual layout levels that are easier to visualize by the
circuit designer.
From the designer's viewpoint, all CMOS designs have the following entities:
• Two different substrates and/or wells: which are p-type for NMOS and n-type for
PMOS.
• Diffusion regions (p+ and n+): which defines the area where transistors can be
formed. These regions are also called active areas. Diffusion of an inverse type is
needed to implement contacts to the well or to substrate. These are called select
regions.
• Transistor gate electrodes: Polysilicon layer
• Metal interconnect layers
• Interlayer contacts and via layers. The layers for typical CMOS processes are
represented in various figures in terms of: • A colour scheme (Mead-Conway
colours). • Other colour schemes mended to differentiate CMOS structures. Example
of layer representations for CMOS inverter using above design rules is shown below.
In this, the designer draws a freehand sketch of a layout, using coloured lines to
represent the various process layers such as diffusion, metal and polysilicon .Where
polysilicon crosses diffusion, transistors are created and where metal wires join
diffusion or polysilicon, contacts are formed. This notation indicates only the
relative positioning of the various design components. The absolute coordinates of
these elements are determined automatically by the editor using a compactor. The

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compactor translates the design rules into a set of constraints on the component
positions, and solve a constrained optimization problem that attempts to minimize
the area or cost function. The advantage of this symbolic approach is that the
designer does not have to worry about design rules, because the compactor ensures
that the final layout is physically correct. The disadvantage of the symbolic approach
is that the outcome of the compaction phase is often unpredictable. The resulting
layout can be less dense than what is obtained with the manual approach. In addition,
it does not show exact placement, transistor sizes, wire lengths, wire widths, tub
boundaries.

The standard cell methodology

VDD and GND should abut (standard height), adjacent gates should satisfy design
rules, nMOS at bottom and pMOS at top all gates include well and substrate contacts
one of the large industry suppliers is ARM (which purchased ARTISAN).

Wiring Track is the space required for a wire Example, 4λ width, 4λ spacing from
neighbour = 8λ pitch Transistors also consume one wiring track.

well spacing: wells must surround transistors by 6λ Implies 12λ between opposite
transistor flavours Leaves room for one wire track

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 Standard Library Cell Design using 45nm Technology

Estimate area by counting wiring tracks Multiply by 8 to express in λ Estimating

area of O3AI Sketch a stick diagram and estimate area.

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ARCHITECTURE OF STANDARD CELLS

Height of standard cells -

Why is a standard cell’s height fixed in a layout?

Standard cells do come in difference heights. Single height cells, double height cells.
But this is again mostly limited to few variants. Primary reason is the combination
of site row, unit tile, and power rail alignments.

Standard cells have PG rails on top, bottom of cell so that cells sitting on
top/bottom of existing std cell can be flipped to make use of single power rail to
connect two sets of std cell rows. Let’s say double height cell sits adjacent to single

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 Standard Library Cell Design using 45nm Technology

height cell, then double height cell center would have a dummy pg rail just to abut
to the cells sitting around without creating shorts or drc.

Track
Track is generally used as a unit to define the height of the std cell.
The Track number quantifies the distance in M1 pitch lengths between VSS and
VDD for the used standard cell. So this is the "height" of the cell perpendicular to
the Poly Gates.
High density cells are mainly used where we are considering area into
consideration and we are ready to compromise for the performance. So usually the
high density cells have less number of tracks when compared to height performance
cells.
A 12 track cell will be taller than a 9 track cell. A 12 track std cell will be
taller, that means more metal 1 routing space is available within the cell, hence cells
will be faster. Where as in a 9 track cell, the cell will be compact, but speed is less
compared to 12 track.

9track, less area, less speed compared to 12 track.

12tarck, more area, more speed compared to 9 tracks.

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Pitch

It is the center to center distance of between the metals having Minimum width and
minimum spacing. The minimum width & min spacing could be different. it is
usually decided by the manufacturing fabs capability to make the accurate
geometries without errors / issues.

Routing Grids
Vertical and Horizontal Routing Grids:
Both vertical and horizontal routing grids need to be defined
HVH or VHV routing is defined for alternating metals layers
All standard cell pins should ideally be placed on intersection of horizontal and
vertical routing grids
Exceptions are abutment type pins (VDD and GND)
Grids are defined wrt the cell origin
Grids can be offset from the origin, however by exactly half the grid spacing
The cell height must be a multiple of the horizontal grid spacing

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All cells must have the same height, but some complex cells can be designed with
double height
The cell width must be a multiple of the vertical grid spacing
However, limited routing tracks are the bottleneck even with wider cells
- Cell pins, with the exception of abutment pins (VDD and GND) must be
placed on the intersections of the vertical and horizontal routing grids.
- Vertical and horizontal routing grids may be offset with respect to the cell’s
origin, provided that the offset distance is exactly one-half of the grid spacing.
- The cell height must be a multiple of the horizontal grid spacing; the cell width
must be a multiple of the vertical grid spacing.
However, limited routing tracks are the bottleneck even with wider cells

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Beta-Ratio-Effects
When Vin = Vout the switching threshold or gate threshold Vm can be pointed out
in VTC curve and obtained graphically from the intersection of the VTC with the
line given by Vin = Vout as shown in Fig below In this region both PMOS and
NMOS are always saturated. As,

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Thus the gate threshold voltage is dependent on the βp/βn ratio. If we want to change
this Beta ratio we have to change the dimensions of the transistor from the Figure
below, it is clear that as the ratio βp/βn is changed the transitions region shifts.

How device width and length of MOSFET is decided?

The gate length specified for a MOSFET technology means the MINIMUM
length. In design it can be larger than the minimum length.

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The W/L ratio is linked to the trans-conductance and the current capability,
together with the multiplicity factor m. A higher w/l ratio increases the current gain
and subsequently a higher current for a given Vg. The same is for a higher m that
means m·W/L.
In practice, for the gain stages are useful large transistors, i.e. large W/L ratios
or/and large m. As example, the differential input stage of OpAmps needs high gain.
However, the good matching of the input differential stage has to be considered as
well.
In general, a larger transistor ensures a better matching because it minimizes
the edge effects, but this is paid with a significant area price.

Hit Points
Figure: inverter showing hit points

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v
Hit point is a metal connected to a contact which covers number of tracks, the more
the number of hit points easier to route the cell. It is better to consider minimum 2
hit points to each contact to ease the routing process.
In the figure show below it is observed that input contact covered 5 hit points and
output covered 3 hit points.

Staggered hit points

If we place more number of metals connected to different contacts parallel on the
same track it is difficult to route middle contact some contacts might be missed to
route, it is solved by implementing staggering of hit points.

Figure: staggered hit points.

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Feed through
Feed through is a keeping a track free to which no metals or hit points should meet
that track, feed through is provided to pass signal from previous cell to next cell.
While creating standard cell we need to give first priority to hit points to contain
minimum hit points, then next priority is to provide feed through.
Following figure shows the feed through.

Figure: feed through

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DRIVE STRENGTH AND STAGE RATIO

What is meant by drive strength of a standard cell?

As we know that cell delay is a function of output load capacitance. The most
simplistic equivalent circuit of a logic gate driving an output can be assumed as given
in below figure

The purpose of logic gate is to propagate the effect of logic value available at its
input to the output. Based upon whether '0' or '1' is to be propagated to the output.
The corresponding is achieved by charging and discharging of the output load
capacitance. Propagating a logic '0' will mean discharging of the load capacitance,
and vice-versa. Drive strength of the logic gate is the its relative capability to
charge/discharge the capacitance present at its output. Now, the time constant, and
hence, delay of the circuit is "RC".
So, for a cell with higher drive strength, corresponding "R" is lesser than the one
with lower drive strength. So that for same load capacitance "C", delay is lower for
a cell with higher drive strength as it can charge the capacitance in lesser time.

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How drive strength varies with size of a cell:

Let us talk in terms of MOSFETs, although this is valid in terms of every device in
general. We know that for a given technology standard cell library, length of all
transistors is kept constant. For instance, 45 nm technology will have gate length of
all transistors as ~45 nm. And channel resistance of the MOSFET is inversely
proportional to "W/L" of the transistor. So, a simple way to decrease channel
resistance is to increase "W" of the transistor. So, a transistor with more area will
have lesser resistance. Or we can say that a logic gate with bigger transistors will
have more drive strength.

What is unit drive strength?

In a standard cell library, we generally see cells labelled as "1X", "2X" and so on.
But what is meant by the number that you see with drive strength? In general, the
lowest size logic gate is labelled as unit drive strength. The drive strength numbers
of other cells are labelled relative to unit drive strength cell.

The above figure shows the 8X drive strength of an inverter

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How delay of a standard cell changes with drive strength

A standard cell (let us say a buffer) can be represented as shown in figure below,
where
R = Channel resistance
Cds = Drain-to-source capacitance (internal capacitance of cell)
Cload = Load capacitance

So, RC time constant can be represented as "R * (Cds + Cload)".

What happens on increasing the drive strength?

We discussed that the drive strength of a standard cell increases when we
increase the size of its transistors. So, basically, a cell with drive strength 2X will
have twice of width as compared to the one with 1X drive strength.
And we know that
Channel resistance decreases with "W".
Drain-to-source capacitance increases with "W".

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So, upon increasing the drive strength, its internal capacitance will increase and
channel resistance will reduce by same amount. The same is depicted in figure
below.

Time constant of "1X" buffer = R * (Cds + Cload)

Time constant of "2X" buffer = R/2 * (2Cds + Cload)

STAGE RATIO
1 The gate length specified for a MOSFET technology means the MINIMUM
length. In design it can be larger than the minimum length.
2. The W/L ratio is linked to the trans-conductance and the current capability,
together with the multiplicity factor m. A higher w/l ratio increases the current gain
and subsequently a higher current for a given Vg. The same is for a higher m that
means m*W/L.
3. In practice, for the gain stages are useful large transistors, i.e. large W/L ratios
or/and large m. As example, the differential input stage of OpAmps needs high gain.
However, the good matching of the input differential stage has to be considered as
well.

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4. In the current mirrors, a higher transistor gate length is beneficial, for a better
matching of the mirror’s currents. You can play with these parameters in simulations
to observe the impact of the length on the mirrors current matching.
5. In general, a larger transistor ensures a better matching because it minimizes
the edge effects, but this is paid with a significant area price.
In the below figure we are increasing the drive capability of an OR gate of 12X using
1:4 ratio. As you see for this ratio to drive the load we need to increase the width of
4 times. And here we have considered the width of PMOS and NMOS to be
maximum and taking 4 fingers for each input signal and which is given to the inverter
of 12X drive at the end.

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MULTIPLIERS AND FINGERS

Multiplier is a single transistor which is having a maximum width which is
basically called as the signal which is multiplied n number of times with the width
not varying. In a cell the same width transistors repeatedly appears then it’s a
multipliers and in this multiplier if the whole transistor is not been able to be placed
then it is divided into many number of polysilicon and are shorted which are called
as Fingers.

Let us consider an example a schematic instance M0 with total_width=6u,

length=1u, fingers=3 finger_width=2u m=5le

The above list can be diagrammatically explained as below

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METHODOLOGY
The process flow for creating a library cell is shown below. The creation of standard
cell started with schematic diagrams of the circuits which were then converted to
their respective symbols. Using the schematics, the layout structure is designed
according to the Lambda (λ) rules from transistor level. After the completion of
layout, DRC (Design Rule Check) is done to check for errors. In order to ensure that
the layout and schematic of circuits are identical, LVS is performed. The simulation
for the layout is carried out using an inbuilt cadence tool to notify the operation of
each circuit. This software also helps us in calculating the necessary parameters like
rise and fall time. After verification the node extraction is done and characterization
of each cells are performed. Finally, the Standard Cell Library is created by dumping
all the cells.

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TYPES OF STANDARD CELLS

STD CELLS:
 Nothing But Base cells (Gates, flops).
 TAP CELLS: (Technology Dependant)
 Avoids Latch up Problem (Placing these cells with a particular distance).
 Tap cells are well-tied cells that bias the silicon infrastructure of n-wells or p-
wells.
 They are traditionally used so that Vdd or Gnd are connected to substrate or
n-well respectively.
 This is to Help TIE Vdd and Gnd which results in lesser drift and prevention
from latchup.
 Required by some technology libraries to limit resistance between Power or
Ground connections to well of the substrate.

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TIE CELLS:
 It is used for preventing Damage of cells; Tie High cell (Gate One input is
connected to Vdd, another input is connected to signal net); Tie low cells Gate
one input is connected to Vss, another input is connected to signal.
 Tie - high and Tie - low cells are used to connect the gate of the transistor to
either Power or Ground.
 In lower technology nodes, if the gate is connected to Power or Ground. The
transistor might be turned "ON/OFF" due to Power or Ground Bounce.
 These cells are part of the std cell library.
 The cells which require Vdd (Typically constant signals tied to 1) connect to
tie high cells.
 The cells which require Vss/Vdd (Typically constant signals tied to 0) connect
to tie low cells.

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END CAP CELLS: (Technology Dependant)

 To know the end of the row, and at the edges end cap cells are placed to avoid
the cells damages at the end of the row to avoid wrong laser wavelength for
correct manufacturing.
 You can add End cap cells at both Ends of a cell row.
 End cap cells surrounding the core area features which serve as second poly to
cells placed at the edge of row.
 The library cells do not have cell connectivity as they are only connected to
Power and Ground rail,
 Thus ensure that gaps do not occur between "WELL" and "IMPLANT
LAYER" and to prevent the DRC violations by satisfying "WELL TIE -
OFF" requirements for core rows we use End cap cells.
 Usually adding the "Well Extension" for DRC correct designs.
 End caps are a "POLY EXTENSION" to avoid drain source SHORT

DECAP CELLS:
 De cap cells are temporary capacitors added in the design between power and
ground rails to counter functional failures due to dynamic IR drop.

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 Dynamic I.R. drop happens at the active edge of the clock at which a high
percentage of Sequential and Digital elements switch.
 Due to this simultaneous switching a high current is drawn from the power
grid for a small duration. If the power source is far away from a flop the
chances are that this flop can go into a metastable state due to IR Drop.
 To overcome this decaps are added. At an active edge of clock when the
current requirement is high, these decaps discharge and provide boost to the
power grid.
 One caveat in usage of decaps is that these add to leakage current.
 De caps are placed as fillers.
 The closer they are to the flop’s sequential elements, the better it is.

FILLER CELLS:
 Filler cells are used to connect the gaps between the cells after placement.
 Filler cells are used to establish the continuity of the N-Wells and the
IMPLANT LAYERS on the standard cells rows, some of the cells also don't
have the Bulk Connection (Substrate connection) Because of their small size
(thin cells).
 In those cases, the abutment of cells through inserting filler cells can connect
those substrates of small cells to the Power/Ground nets.
I.e. those tin cells can use the Bulk connection of the other cells (this is one of the
reason why you get stand-alone LVS check failed on some cells)

ICG CELLS:
 Clock gating cells, to avoid Dynamic power Dissipation.
 Register banks disabled during some clock cycles.

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 During idle modes, the clocks can be gated-off to save Dynamic power
dissipation on flip-flops.
 Proper circuit is essential to achieve a gated clock state to prevent false
glitches on the clock paths

POWER GATING CELLS:

 In Power gating to avoid static power Dissipation.
 Power switches
 Level Shifters
 Retention registers
 Isolation cells
 Power controller

PAD CELLS:
 To Interface with outside Devices; Input to of Power, Clock, Pins are
connected to pad cells and outside also.

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CORNER CELLS:
 Corner Pads are used for Well Continuity.
 To lift the chip.

MACRO CELLS:
 Memories
 The memory cells are called Macros.
 To store information using sequential elements takes up lot of area.
 A single flip-flop could take up 15 to 20 transistors to store one bit store the
data efficiently and also do not occupy much space on the chip comparatively
by using macros.

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SPARE CELLS:
 Used at the ECO.
 Spare cells are standard cells in a design that are not used by the netlist.
 Placing the spare cells in your design provides a margin for correcting logical
error that might be detected later in the design flow, or for adjusting the speed
of your design.
 Spare cells are used by the fix ECO command during ECO process.

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PAD FILLER CELLS:

 Used for Well Continuity, Placed in between Pads.

JTAG CELLS:
 These are used to check the IO connectivity.

An Example placement of different cells:

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FLAVOURS OF CELLS

1. Different Drive Strengths and Vt:

 The purpose of logic gate is to propagate the effect of logic value available at
its input to the output. Based upon whether '0' or '1' is to be propagated to the
output.
 The corresponding is achieved by charging and discharging of the output load
capacitance. Propagating a logic '0' will mean discharging of the load
capacitance, and vice-versa.
 Drive strength of the logic gate is the its relative capability to charge/discharge
the capacitance present at its output. Now, the time constant, and hence, delay
of the circuit is "RC"
 So, for a cell with higher drive strength, corresponding "R" is lesser than the
one with lower drive strength. So that for same load capacitance "C", delay is
lower for a cell with higher drive strength as it can charge the capacitance in
lesser time.
 From another point of view, it is just the strength required to charge/discharge
the capacitance at the output to the required value. Greater the drive strength,
higher current can be drawn from the supply and the output capacitors can be
charged quickly, if drive strength is low, then the current is less and the output
capacitance takes time to charge/discharge.

How drive strength varies with size of a cell: Let us talk in terms of MOSFETs,
although this is valid in terms of every device in general. We know that for a given
technology standard cell library, length of all transistors is kept constant.
For instance, 90 nm technology will have gate length of all transistors as ~90 nm.
And channel resistance of the MOSFET is inversely proportional to "W/L" of the
transistor. So, a simple way to decrease channel resistance is to increase "W" of the
transistor.

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So, a transistor with more area will have lesser resistance. Or we can say that a logic
gate with bigger transistors will have more drive strength.

What is unit drive strength: In a standard cell library, we generally see cells labelled
as "1X", "2X" and so on. But what is meant by the number that you see with drive
strength?
In general, the lowest size logic gate is labelled as unit drive strength. The drive
strength numbers of other cells are labelled relative to unit drive strength cell.

HVT, SVT and LVT:

To define which MOSFETS are HVT, LVT or SVT, we overlap the regular P-imp
and N-imp layers with their corresponding HVT or LVT layers i.e P-imp can be
overlapped with Phvt and Plvt and N-imp can be overlapped with Nhvt and Nlvt to
define HVT and LVT MOSFETS.

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 Standard Library Cell Design using 45nm Technology

Examples:
NOR2_X2:

OR6_X1:

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 Standard Library Cell Design using 45nm Technology

OR2_12X with 1:4 Stage Ratio:

2. Different Architectures:
The standard cell libraries provide three separate architectures, high-speed (HS),
high-density (HD), and ultra-high-density (UHD), to optimize circuits for
performance, power and area trade-offs.

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 Standard Library Cell Design using 45nm Technology

METAL2 USAGE

Whenever there are complex circuits that needs to be fabricated, then there
occurs the connection between different instances and sometimes these connection
becomes so messy that if we connect all of them using a single metal 1 layer, there
is a chance that the wires may short... so we need to switch to higher layer and higher
layer as the demand arises.
This is one of the reasons..
Usually the resistivity of metal layer decreases as we move to higher layers
(This has to do with Crystal structure of metal and semiconductors). So global
signals(generally which travels much longer length) are generally allowed to run on
higher layers but not blindly to a higher layer available, this is done in order to
maintain the signal integrity and good slew.
Today we are at a stage where we have designs with 11 metal layers (including
power routing) and are still struggling with routing issues such as congestion and
shorts!
Primarily to get the best advantage out of technology scaling (which is
reducing the transistor gate length progressively, to the uninitiated in VLSI: P)
companies are packing more and more transistors into a single block. While this
definitely adds to the competitive edge (as more capabilities are introduced into a
smaller die area at a lesser cost) , it makes routing all of these instances a real
challenge.
The fact that we have a more complex design rule deck (DRC’s) and other
added constraints like Double patterning (DPT) and Triple Patterning (TPT) at
technology nodes like 10nm, 14nm and below, the more routing resources we have
the better.
While we are on the topic of routing layers I wanted to add info here. Opening
another routing layer in the design actually adds to the cost of manufacturing the
chip as the fab will have to make additional masks for each layer you use and each
mask comes at a hefty price. So adding additional layers to routing although is very
much needed in today’s designs it can’t be done unscrupulously and is a careful

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 Standard Library Cell Design using 45nm Technology

consideration between design complexity and the cost at which you want to make
your chip.
Generally you should use one of our top metals for power routing at chip level
in order to minimise IR drops. What metals you choose depends on the metal stack
available to you have 7 layers with three thick layers you may choose to route vdd
in metal7 from pad to cells and route gnd underneath it in metal 6, saving space for
routing channels and giving yourself a little decoupling .if you only have three layers
then that is unlikely to be an option.
At cell level I generally route both VDD and GND in metal1 horizontally
,this means I can tap directly into my current mirrors, guard rings etc. then use metal
2 exclusively for vertical routing and metal 3 for horizontal. It would be nice to use
metal 1 but the prevalence of guard rings etc. generally makes that an awkward
strategy. It is worth remembering these are only guidelines, ultimately the decision
will come down to
-block function (high currents / high frequency will require thick stack metals)
-metallisation option
- Top level requirements.

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 Standard Library Cell Design using 45nm Technology

COMMON ERROR AND MISTAKE

TECHNOLGY FILE
 Technology File is the most critical input for physical design tools. If you
want to start any further steps or create a mw lib to start any further in physical
design? You must have tech file ready in your hand.
 There is many technology file available. The technology files are differ to
each other by their functionality.
 It provides technology-specific information like the names and physical and
electrical characteristics of each metal/via layers and the routing design rules.
It guides physical design tool on below list of information:
 Unit tile definitions that can be used in site rows so that placement engine can
guide placement of cells?
 List of metals available for routing?
 Metal widths, spacing & pitch info etc... ?
 Design rules between same metal layer spacing?
 What are all the via types/via masters available?
 Units of length, cap, power, resistance & technology precision etc... ?
DRC rule (design check rule)
 It is performed in Calibre using the DRC rule file.
 If you have errors in DRC, you should modify your layout design according
to the error message.
 The error messages include information about the location and the source of
the trouble.
 The ruler (type k in the layout window) is very useful.

RULES:
 Minimum width and spacing for metal
 Minimum width and spacing for via
 Minimum Metal contact enclosure

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 Standard Library Cell Design using 45nm Technology

 End of Line spacing

 Minimum area
 The spacing between the active area to the implantation
 Wide metal jog
 Misaligned Via wire
 The contact must be covered by the metal.
 Poly to ploy min space
 Contact to active area spacing

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 Standard Library Cell Design using 45nm Technology

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 Standard Library Cell Design using 45nm Technology

MISTAKES
 Avoid metal jogs if it’s not necessary.
 Decrease the poly connection as they are highly resistive.
 We should use more contacts instead of few contacts to increase the drive
strength.
 Use stage ratio for increase the width of std cell to get the high driving
strength where this rule is applicable.
 We should place metal and gate contact at the center of the track for a good
routing purpose.

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 Standard Library Cell Design using 45nm Technology

TAP CELLS AND TAPLESS CELLS

TAP CELLS
 Tap cells are used to limit resistance between power or ground connections to
wells of the substrate. Taps are traditionally used so that the VDD and GND
are connected to substrate and n-wells respectively.
(WHEN LATUCH-UP OCUURE: A: The transistor current gain product of the two
parasitic transistors is greater than 1
B: Both emitter-base junctions of the parasitic transistors are forward
biased)

 Avoids Latch up Problem (Placing these cells with a particular distance).

 Cells are physical-only cells that have power and ground pins and don’t have
signal pins.
 Tap cells are well-tied cells that bias the silicon infrastructure of n-wells or p-
wells.
 They are traditionally used so that Vdd or Gnd are connected to substrate or
n-well respectively.
 This is to Help TIE Vdd and Gnd which results in lesser drift and prevention
from latchup.
 Required by some technology libraries to limit resistance between Power or
Ground connections to well of the substrate.

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 Standard Library Cell Design using 45nm Technology

The cell placement would now appear as below:

Tap-less cell:

As it can be seen that ‘WELL TIES’ are needed to tie N-WELL and P-WELL to a
known potential. The layout in figure suggests that they are a part of each and every
CMOS standard cell. However, the stdcells are placed in well-defined rows of
uniform height where wells are continuous and thus, standard cells placed in a row
can share these ‘WELL TIES’. This topology reduces the standard cell size and

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 Standard Library Cell Design using 45nm Technology

allows the SoC to accommodate more standard cells. This type of standard cell
library is called Tap-Less library. To provide the much required well connections,
cells known as ‘Well Taps’ are placed at uniform interval. The spacing between
these ‘Well Taps’ should not be too high as this would increase the resistance R1
and R2 and this could make the circuit susceptible to latch-up.

Refer this figure for a typical CMOS device for Tap-Less library.

Exemplifies symbolic representation and layout implementation of a standard cell

in Tap-Less library. PUN stands for Pull up Network consisting PMOS devices and
PDN stand for Pull down Network consisting NMOS devices.

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 Standard Library Cell Design using 45nm Technology

AUTHORS

 Definition of Standard cell, where it is used, why it is used, how can it be

utilized in PD and Pin routing styles - Tanveer Mustafa

 Architecture of a Standard cell and Hit points – Sagar Angadi

 Drive strength, Stage ratio, Fingers & multipliers and Methodology – Rohith
Prasad K M

 Types of cells and Flavors of cells – Amrut Grampurohit

 Stick diagram & techniques and Metal 2 usage in Std cell design – Prema F

 TAP cells and TAPLESS cells, Common mistakes and errors caused in
designing a Std cell – Hiral Gohil

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