Emt

ELECTRONICS & COMMUNICATION ENGINEERING
1. COMMON EMITTER AMPLIFIER

Aim
1. Design a COMMON - EMITTER amplifier for given specifications.

2. Simulate the designed amplifier.
3. Develop the hard ware for designed amplifier.
4. Compare simulated results with practical results.
Apparatus
S.No Name of The Component/ Specifications Qty
Equipment
Icmax=100mA
1 Transistor (BC-107) PD=300mw 1
Vceo=45V
Vbeo=50V
2 Capacitors(designed values) Electrolytic type, 3
Voltage rating=
1.6v
3 Resistors (designed values) Power rating=0.5w 4
Carbon type
4 Function Generator 0 -1MHZ 1
5 Cathode Ray Oscilloscope 20MHZ 1
6 Regulated Power Supply 0-30V,1Amp 1
Theory: Common Emitter amplifier has the emitter terminal as the common
terminal between input and output terminals. The emitter base junction is forward
biased and collector base junction is reverse biased, so that transistor remains in
active region throughout the operation. When a sinusoidal AC signal is applied at
input terminals of circuit during positive half cycle the forward bias of base emitter
junction VBE is increased resulting in an increase in IB ,The collector current Ic is
increased by β times the increase in IB, VCE is correspondingly decreased. i.e output
voltage gets decreased. Thus in a CE amplifier a positive going signal is converted
into a negative going output signal i.e..180o phase shift is introduced between output
and input signal and it is an amplified version of input signal.
Characteristics of CE amplifier
1. Large current gain (AI )
2. Large voltage gain (AV)
3. Large power gain(AP=AI .AV)
4. Phase shift of 180o
5. Moderate input & output impedances.
ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 1

Circuit Diagram
Fig. 1 Common Emitter Amplifier circuit diagram
Design Equations
Given Data
VCC =12V, VCE = 6V, IE =2mA, β=500, S ≤ 5.
1) For fixing the optimum operating point Q, mark the middle of the d.c load line
and the corresponding VCE (Q) and ICQ values are determined.
VCE (Q) = VCC/2
2) Applying Kirchoff’s voltage law to the collector circuit in the diagram
VCC ≥ ICQ(RC+RE) +VCE(Q)
3) By choosing drop across RE as 0.1 VCC
VE = VCC/10
4) In transistor since base current is very small, so IE is approximately equal to
IC ( IE = IC) , IERE
5) RC
6) The voltage across R2 is

VR2 = VBE+IERE
VCC. R2/(R1+R2)
R1/(R1+R2)= ----------------------------- (a)

7) S = (1+ β) / (1+ βRE/(RE+RB))

5= 101/ (1+(100 X 600/(600+RB)))
RB=
R1R2 / (R1+R2) = ------------------- (b)
From (a) & (b)
R1 = _______ R2 = ________
Capacitor Calculations
To provide low reactances almost short circuit at the operating frequency
f=1KHZ.
XCi = 0.1RB , Xco =0.1 RC, XcE =0.1 RE
Standard values of Resistors and capacitors R1_____, R2=____ RC=_____, RE=____,

Ci = Co = _______, CE=______
Procedure
1. Connect the circuit as per the circuit diagram Fig. 1.
2. Apply the supply voltage , VCC=12V
3. Make sure that the transistor is operating point in active region by keeping
VCE half of VCC.
4. Now feed an ac signal of 20mV at the input of the amplifier with different
frequencies ranging from 100HZ to 300 MHZ and measure the amplifier
output voltage.
5. Now calculate the gain in decibels at various input signal frequencies.
6. Draw a graph with frequencies on X-axis and gain in dbs on Y-axis. From
the graph calculate Bandwidth.

Tabular form
Simulation
Input AC voltage, ______ mV (peak-peak)
Frequency Output Voltage(Vo) Gain in decibels

S.No
(HZ) (Volts-p-p) AV=20 log (Vo / Vi)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Practical
Input AC voltage, VI= _____ mV (peak-peak)
Output Voltage (Vo) Gain in decibels

S.No Frequency (HZ)
(Volts-p-p) AV=20 log (Vo/ VI)
1
2
3
4
5
6
7
8
9
10
11
12

Model graph
Observations
Simulated Practical
Maximum gain (Av) =

Lower cutoff frequency (FL) =
Upper cutoff frequency (FH) =
Band width (B.W) = (FH – FL) =
Gain bandwidth product = Av (B.W) =
Precautions
1. Connections must be given very carefully.
2. Readings should be noted without any parallax error.
3. The applied voltage, current should not exceed the maximum rating of the
given transistor.
Inferences
Result

Questions
1. What are the characteristics of C.E amplifier?

2. What is the main application of CE amplifier?
3. What is meant by Bandwidth of an amplifier?
4. Find the phase relation b/w input and output?
5. Measure Ri, RO and Ai of a circuit?
6. Define operating point?
7. Proof for the circuit/BJT is in active region operation?
8. Which component in the circuit effects the gain and bandwidth of an amplifer?

2. COMMON COLLECTOR AMPLIFIER

Aim
1. To design a COMMON – COLLECTOR amplifier for given specifications.

Apparatus
S.No Name of The Component/ Specifications Qty
Equipment
Icmax=100mA
1 Transistor (BC-107) PD=300mw 1
Vceo=45V
Vbeo=50V
2 Capacitors(designed values) Electrolytic type, 3
Voltage rating=
1.6v
Carbon type
Theory
Common Collector amplifier has the collector terminal as the common terminal
between input and output terminals. The emitter base junction is forward biased and
collector base junction is reverse biased, so that transistor remains in active region
throughout the operation. The collector base junction acts as input and emitter base
junction acts as output. Thus the output taken across the emitter, it exactly follows
the input voltage variation. Hence it is named as emitter follower. An external load
resistor RL is capacitor coupled to the emitter terminal of the transistor. Bias voltage
VB is derived from Vcc by means of potential divider R 1 and R 2 .So circuit employs
emitter current bias. No resistor is connected in series with the transistor collector
terminal, and no emitter bypass capacitor is employed. The capacitors C 1 and C 2
acts as input and output coupling capacitors.CC-amplifier circuit provides current
gain and power gain but no voltage gain. It has high input impedance and very low
output impedance. The voltage gain of emitter follower is unity, thus it is used as
buffer amplifier. It is also used as impedance matching network.

Characteristics of CC amplifier
1. High input impedance

2. Low output impedance
3. High current gain(Ai)
4. Large power gain(AP=AI .AV)
5. Voltage gain is unity.
Circuit Diagram
Fig. 1 Common Collector Amplifier Circuit Diagram
Design Equations
Given Data:
VCC =12V, IE =2mA, β=500, S ≤ 5,f=1KHZ
1. For fixing the optimum operating point Q, mark the middle of the d.c load
line and the corresponding VCE (Q) and ICQ values are determined.
VCE (Q) = VCC/2 =
2. Applying Kirchoff’s voltage law to the collector circuit in the diagram
VCC ≥ IERE +VCE(Q)
RE=

3. S = (1+ β) / (1+ βRE/(RE+RB))

RB=
RB = R1R2 / (R1+R2) =
4. VR2 =VBE+VE =0.7+IERE
VR2=
5. VR2= Vcc (R2)/(R1+R2)
R2/(R1+R2)=
R1=
R2=
Capacitor Calculations
f=1KHZ.
XCi = 0.1RB
6. XCi =
Ci =
7. Xco = RE/10
Co =1/ (2πfXco)=
Procedure

2. Apply the supply voltage , VCC=12V
3. Make sure that the transistor is operating point in active region by keeping
VCE half of VCC.
4. Now feed an ac signal of 1V at the input of the amplifier with different
output voltage.
6. Draw a graph with frequencies on X-axis and gain in dbs on Y-axis. From
the graph calculate Bandwidth.

Tabular form
Simulation
Input AC voltage, VI= ______ V (peak-peak)
Frequency Output Voltage(Vo) Gain in decibels

S.No
(HZ) (Volts-p-p) AV=20 log (Vo / Vi)
Practical
Input AC voltage, VI= ______ V (peak-peak)
Output Voltage (Vo) Gain in decibels

S.No Frequency (HZ)
(Volts-p-p) AV=20 log (Vo/ VI)

Model graph
Observations
Simulated Practical
Maximum gain (Av)

Lower cutoff frequency (FL)
Upper cutoff frequency (FH)
Band width (B.W) = (FH – FL)
Gain bandwidth product = Av (B.W)
Precautions
1. Connections must be given very carefully.
3. The applied voltage, current should not exceed the maximum rating of
the given transistor.
Inferences:
Result .
Questions
1. What are the characteristics of CC amplifier?
2. What is the main application of CC amplifier?
3. What is meant by Bandwidth of an amplifier?

3. TWO STAGE RC COUPLED AMPLIFIER
Aim:
1. Design two stage RC coupled amplifier for given specifications.
4. Compare practical results with theoretical results.
Apparatus
S.No Name of The Specifications Qty

Component/equipment
1 Transistor (BC-107) Icmax=100mA
PD=300mw 02
Vceo=45V
Vbeo=50V
2 Capacitors(designed values) Electrolytic type 05
Voltage rating= 1.6v
Carbon type
Theory
When two amplifiers are connected, in such a way that the output signal of
first serves as the input signal of second, the amplifiers are said to be connected in
cascade. Cascading is done to increase the gain of the amplifier.
Each stage of the cascade amplifier should be biased at its designed
level. It is possible to design a Multistage cascade in which each stage is separately
biased and coupled to the adjacent stage using blocking or coupling capacitors. In
this circuit each of the two capacitors c1 & c2 isolate the separate bias network by
acting as open circuits to dc and allow only signals of sufficient high frequency to
pass through cascade.

Circuit Diagram
Fig. 1 Two Stage Common Emitter Amplifier Circuit Diagram.
Design equations
Given Data:
hfe1 = hfe2= 200, RL =10Ω,IE1 = IE2 =1mA, s1 = s2 =8, f=100HZ, VCC=12v
1) For fixing the optimum operating point Q, mark the middle of the d.c load line
and the corresponding VCE (Q) and ICQ values are determined.
VCE (Q) = VCC/2
VE = VCC/10
3) In transistor since base current is very small, so IE is approximately equal to
IC ( IE = IC) , IERE = ; ICRE =
RE = VE / IE =
RC = (VCC – VCE – VE) / IC = (
5) The voltage across R2 is
VBB = VCC * R2 / (R1 + R2) --------------- (1)
VBB = VBE + IERE -------------------- (2)
Substitute (2) in (1)
1.8 = 12 R2 / (R1+R2)
R2 = 0.1761 R1 ------------------ (a)

6) S=1+ R1R2/ (R1+R2) RE -----------------(b)

By solving (a) and (b) we get
R1 = _________ R2 = ________
Capacitor calculations:
f=100HZ.
X cE = 0.1RE , Xci =0.1 Zi, Xco =0.001 Z0
7) X cE << RE,
X cE =RE/10
=> CE=
8) XCi=Zi/10 Where Zi=hie//RE =
=> Ci =
9) XCo= ZO/1000
ZO=RL//RC =
=> CO =
Standard values
R11= R12= R1=______, R21 = R22 =R2 = _______, RE1 =RE2 =RE =_______
RC1 =RC2 =RC=_______, RL=______,Ci=_____,CC= _____,CE = _____ C0= _______
Procedure
2. Apply supply voltage, Vcc= 12V.

3. Make sure that the transistor is operating in active region by keeping Vce half
of Vcc.
4. Now feed an ac signal of 20mV at the input of the amplifier with different
frequencies ranging from 100Hz to 1MHz and measure the amplifier output
voltage, Vo.
5. Now calculate the gain in db at various input signal frequencies.
6. Draw a graph with frequencies on X- axis and gain in db on Y- axis. From
graph calculate bandwidth.

Tabular Form
Simulation
Input AC voltage, Vi = ______mV (peak-peak)
Output voltage Vo Gain in decibels

S.No Frequency (Hz)
(mv) (peak-peak) AV=20 log (Vo / Vi)
Practical
Input AC voltage, Vi = _______mV (peak-peak)
Output voltage Vo Gain in decibels

S.No Frequency (Hz)
(mv) (peak-peak) AV=20 log (Vo / Vi)

Observations
Simulation Practical
Maximum gain (Av)
Lower cutoff frequency (fL)
Model graph
Precautions
1. Connections must be done very carefully.

3. The applied voltage and current should not exceed the maximum
ratings of the given transistor.
Inferences
Result
Questions
1. Why RC coupled amplifiers widely used as voltage amplifiers?
2. Why the voltage gain of RC coupled amplifier falls in low frequency range?
3. Why the voltage gain of RC coupled amplifier falls at high frequency range?

4. WIENBRIDGE OSCILLATOR
Aim
1. Design a WIEN BRIDGE OSCILLATOR for given specifications.
2. Simulate the designed oscillator.

3. Develop the hard ware for designed oscillator.
4. Compare practical results with theoretical results.
Apparatus
S.No Name of The Component/Equipment Specifications Qty
1 Transistor (BC-107) ICMAX=100mA
PD=300mw 2
VCEO=45V
VBEO=50V
2 Capacitors(designed values) Voltage rating= 5
1.6v Electrolytic
type
3 Resistors (designed values) Power 10
rating=0.5w
Carbon type
Theory
The circuit diagram of Wien bridge oscillator is given in figure .The circuit
consists of a two stage RC coupled amplifier which provides a phase shift of 360 or
0. A balanced bridged is used as the feedback network which has no need to provide
any additional phase shift. The feedback network consists of lead-lag network(R 1 -C 1
and R 2 -C 2 ) and a voltage divider (R 3 -R 4 ). The lead–lag network provides positive
feedback to the input of first stage and the voltage divider provides a negative
feedback to the emitter of Q 1 .If the bridge is balanced,
R3/R4=(R1-jXc1)/(R2)(-jX2)/(R2-jXc2)).
Where Xc1 and Xc2 are the reactances of the capacitors.
By simplifying and equating the real and imaginary parts on both sides,we get the
frequency of oscillation as,
fo= 1/ ( 2π√R1R2C1C2)
=1/(2πRC), if R1=R2=R3 and C1=C2=C.

The ratio of R3 to R4 being greater than 2 will provide a sufficient gain for the circuit
to oscillate at the desired frequency. This oscillator is used in commercial audio
signal generator.
Circuit Diagram
Fig. 1 Wienbridge Oscillator Circuit Diagram
Design Equations
Given data:
VCC =15v, VCE =8v, IC=2mA, β=100, VBE =0.6v,

VCC = VCE+ ICRC
Rc = (Vcc -Vce)/Ic
IB= IC/β =
2) Applying Kirchoff’s voltage law to the base circuit in the diagram
Vcc = IBRB+ VBE => Rb =
Current through R5,R6
I1 = 10IB
But I1= Vcc/(R5+ R6)
R5 + R6 =
But V6 = VBE + VE
VE =
V6 =
I1 (R6 )=

R6 =
R5 + R6 =
R5=
Ve = IERE=> RE=
XCO=RC/10=(3.5k)/10
f=1KHZ
CO=1/(2πfRC/10)=
CF=
Practical Values
Time period=
%error = (|Theoritical-Practical|/ Theoritical) x100
Procedure
1. Connections are made as per the circuit diagram.

2. Switch on power supply.
3. Connect the CRO at output of the circuit.
4. Adjust potentiometer for distortion free wave form.
5. Measure the output frequency and amplitude on CRO and compare the
theoretical and practical frequencies.
6. Repeat the procedure for different values of capacitor.
Tabular form
Simulation
S.No Amplitude(V) (Peak-Peak) Frequency(KHZ) % Error
Practical
S.No Amplitude(V) Peak- Frequency(KHZ) % Error

peak

Model Graph
Inferences
Result .
Questions
1. What is oscillator?
2. What are BHARKHAUSEN conditions of oscillators?
3. Which type of feedback is used in wein bridge oscillator?
4. What is the application of wein bridge oscillator?

5. RC PHASE SHIFT OSCILLATOR

Aim
1. To design RC phase shift oscillator for given specifications.
2. Simulate the designed circuit.
3. Compare the theoretical and practical values.

Apparatus
S.No Name of The Specifications Qty

Component/equipment
1 Transistor (BC -107) Icmax=100mA
PD=300mw 1
Vceo=45V
Vbeo=50V
2 Capacitors(designed values) Electrolytic type 3
Voltage rating= 1.6v
Carbon type
Theory
RC phase shift oscillators are more suitable oscillators as they occupy less
space. RC phase shift oscillator can be achieved by two means,
1. RC phase shift oscillator using cascade of high pass filters.
2. RC phase shift oscillator using cascade of low pass filters.
If values of R and C are chosen that every RC section provides a phase shift of 60o.
thus theoretically RC ladder network produces a total phase shift of 1800 between
input and output voltages for the given frequency. Therefore at a specified frequency
fr the total phase shift from base of transistor around and back to the base will be
3600 or 00, there by Barkausen condition of oscillation, the frequency of oscillations is
given by
f=1/2πRC (6+4K)1/2 Where C1=C2=C3=C,
K=RC/R,
R1=R2=R3=R

Circuit Diagram
Fig.1 RC Phase Shift Oscillator Circuit Diagram
Design Equations
Given data: VCC =12v, IC =1mA, β = 100, VBE =0.3v, VCE =8v,f = 1KHZ
1) The d.c current gain is defined as the ratio of collector current (IC) to the base
current (IB) βdc = IC/ IB
IB = IC /β =
2) The voltage across the base resistor is
VCC = VB + VBE = IB RB + VBE
RB =
VRE = VCC / 10 = ICRE
RE =
VCC ≥ ICQ(RC+RE) +VCE(Q)
RC+RE =
RC =

Capacitor calculations
f=1KHZ.
XCE = 0.1RE , XcO =0.1 RO
5) XCO= RO/10 , CO=1/(2πf RO) =
6) XcE = RE / 10 ,CE =1/(2πf RE) =
Theoretical Values
Assume f=1k HZ, C=0.01µ F
f=1/(2πRC)((6+4k))1/2 where k=RC/R, R=
Procedure
1. Connections are made as per circuit diagram Fig. 1.
2. Switch on the power supply.
3. Connect the CRO at the output of the circuit and apply supply voltage of
VCC =12v.
4. Compare the simulation frequency and practical frequency values.
5. Plot the graph for amplitude versus frequency.
Observations
Time period, T of the AC signal available at the output =
The frequency of Oscillations, f = 1 / T =
Tabular Form
Simulation
S.NO Amplitude(v) p-p Frequency (KHZ) % Error
Practical
S.NO Amplitude(v) p-p Frequency (KHZ) % Error

Model Graph
Precautions
1. Connections must be done very carefully.
3. The applied Voltage and current should not exceed the maximum ratings of the
given transistor.
Inferences
Result:
Questions
1. Which type of feedback is used in RC phase shift oscillator?
2. How many RC networks are used in RC phase shift oscillator?
3. What must be the gain of the internal amplifier in the general RC phase shift
oscillator?
4. What is the effect of VCC, R & C values on output?
5. How to vary the frequency in worse and fine ways?

6. CLASS-A POWER AMPLIFIER

Aim
1. Design a class-A inductor coupled power amplifier to deliver 4W power to 10
Ohms load resistor.
4 Compare practical results with theoretical results.
Apparatus
S.No Name of the Component Specifications Qty

/equipment
1 Power transistor (BD139) VCE =60V, VBE = 100V 1
IC = 100mA hfe = 40 to160
2 Resistor (designed values) Power rating=0.5w 4
Carbon type
3 Capacitors(designed values) Electrolytic type Voltage 3
rating= 1.6v
7 Inductor(designed values) Operating 1
temperature=ambient
Theory
The power amplifier is said to be class A amplifier if the Q point is selected in
such a way that output signal is obtained for a full input cycle. For class A power
amplifier position of Q point is at the centre of mid point of load line. For all values of
input signals the transistor remains in the active region and never enters into the cut
off or saturation region. When an ac signal is applied, the collector current flows for
3600 of the input cycle. In other words, the angle of collector current flow is 3600 i.e...
One full cycle. Here signal is faithfully reproduced at the output without any distortion.
This is an important feature of class A operation. The efficiency of class A operation
is very low with resistive load and is 25%. This can be increased to 50% by using
inductive load. In the present experiment inductive load is used.

Circuit Diagram
Fig. 1 Class-A Power Amplifier Circuit Diagram
Design Equations
Given data: RL= 10Ω, PL max= 4W, f=1KHZ

1) Selection of L:
ωL>>RL
L>>RL/2πfL =
2) Selection of VCC:
The maximum power which can be delivered is obtained for Vm = VCC
(if vmin=0)
PL max ≤ VCC ² /2RL
VCC ² ≥PLmax X 2RL, VCC =
3) Selection of RE:
ICQ = (PC max /RL)1/2 =
ICQ=VCC/(Rac+Rdc) where Rac= RL, Rdc= RE
ICQ=VCC/(RL+RE) , RE = (VCC /ICQ) - RL , RE =
4) Selection of biasing resisters R1 & R2:
VBB= VBE+VE
VE = ICQ*RE =
VBB=

The voltage across R2 is

VBB=VCCR2/(R1+R2)
RB= R1R2/(R1+R2)
R1 =______ , R2 , = _________
f=1KHZ. XCE = 0.01RE , Xci =0.1 RB ,Xc0 =0.1 RL
5) Selection of CE:
XcE= RE/100 CE = _______
6) Selection of Ci& C0:
Xci≈RB/10=
Ci = _______
7) Xc0≈RL/10 =____, C0 = _______
Procedure
1. Connect the circuit as shown Fig. 1 and supply the required DC voltage 2.
Feed an AC signal at the input and keep the frequency at1 KHZ and
amplitude 5V.Connect a power o/p meter at the o/p.
2. Change the o/p impedance in steps for each value of impedance and note
down the o/p power.
3. Plot a graph between o/p power and load impedance. From this graph find
the impedance for which the o/p power is maximum. This is the value of
optimum load.
4. Select load impedance which is equal to 0V or near about the optimum load.
See the wave form of the o/p of the C.R.O.
5. Calculate the power sensitivity at a maximum power o/p using the relation.
Power sensitivity = output power / (rms value of the signal)2

Tabular Form
Simulation
Input Power=VCC x ICQ=_______
S.No RL(Ohm) D.C.Input Output Power Efficiency =

Power Pin (W) Pout (W)
pout/pin*100(%)
Practical
S.No RL(Ohm) D.C Input A.C output η=(Pac)/(Pdc)*100

Power Pin (W) Power Pout (W)
Model Graph

Precautions
1. Connections should be done care fully.
2. Take the readings with out any parallax error.
Inferences
Result
Questions
1. What is power amplifier?
2. Why power amplifiers are called as large signal amplifiers?
3. What is the maximum collector efficiency of transformer load class A
power amplifier?
4. What is the maximum collector efficiency of resistive load class A
power amplifier?

7. CLASS-B POWER AMPLIFIER

Aim
1. Design a class B push pull amplifier to deliver 5W to 10 Ohm load resistor

2. Simulate the designed regulator.
3. Develop the hardware for designed Regulator.
4. Compare the practical values with theoretical values.
Apparatus
S.No Name of the component Specifications Qty

/Equipment
1 Power transistors Pcmax =12.5W 2
BD 138, BD139 Icmax=1.5A
Vcemax=80V,hfe=100
2 I/P Transformer Turns Ratio 1:1 1
3 O/P Transformer Turns Ratio 4:1 1
Carbon type
Theory
The two transistors are biased to work in class-B operation. This increases
the power efficiency of the circuit. When the signal is applied, the transformer Q1
works as a phase splitter. It produces two signals (for the two transistors) which are
equal in magnitude but opposite in phase. During positive half-cycle of the input
signal, the base of the transistor Q1 is driven positive. So, it will be in the conducting
state. The base of the transistor Q 2 is driven negative. It remains cut-off. Current ic1
flows, but ic2 is zero. During the negative half cycle of the input signal, the opposite
happens. Q 2 conducts, but Q 1 does not.

Circuit diagram
Fig.1 Class-B Power Amplifier Circuit Diagram
Design Equations
Given data: PL (max) = 5W, PC (max) = 12.5 W, IC (max) = 1.5A, V CC (max) = 80V,
S=8
1. Selection of Vcc:
PL (max) =VCC X IC (MAX) / 2
Vcc=
2. Selection of RL
IC (max) =VCC / N ² X RL
RL =______
3. Selection of RE :
RE << RL
RE=RL/10
4. Selection of R1 & R2:
VE= ICQ X RE
ICQ=PC (max) / VCE
S=RB // RE=R1 // R2 // RE
R2 =
VE = Vcc X R1 / (R1+R2)
R1 = ______ R2= _______

Procedure
1. Connect the circuit as per the circuit diagram shown in Fig. 1
2. Connect the required supply from the regulated R.P.S

3. Feed the AC signal at the I/p and keep the frequency at 1 KHz . connect the
power o/p meter at the o/p. Change the o/p impedance in steps for each
value of impedance and note down the o/p power.
4. Plot a graph between o/p power and load impedance. From this graph find
the impedance for which the output power is maximum. This is the value of
optimum load.
5. Select load impedance which is equal to optimum load. See the wave form of
the output on C.R.O.
6. Calculate the conversion efficiency..
Tabular form
Simulation
S.NO Load resistance Pac (W) Pdc (W) % η = ((Pac)

RL (Ohms) / (Pdc))*100
Practical
S.NO Load resistance Pac (W) Pdc (W) % η = ((Pac)
RL (Ohms) / (Pdc))*100

Model Graph
Precautions
1. Connections should be made carefully.
2. Take the readings without parallax error.
Inferences
Result
Questions
1. What are the advantages of class B power amplifier?
2. What is the period of conduction in class B power amplifier?
3. How is the cross over distortion eliminated?

8. CLASS B COMPLEMENTARY SYMMETRY

POWER AMPLIFIER
Aim
1. Design a complementary symmetry power amplifier to deliver maximum
power to 10 Ohm load resistor.
2. Simulate the design circuit.
3. Develop the hard ware for design circuit.
4. Compare the practical results with theoretical values.
Apparatus
Sl.No Name of the Component Specifications Qty

/equipment
1 Power transistor (BD139) VCE =60V VBE = 100V 1
IC = 100mA hfe = 40 -160
Carbon type
3 Capacitors(designed values) Electrolytic type Voltage 3
rating= 1.6v
4 Inductor(designed values) Operating temp =ambient 1

Theory
In complementary symmetry class B power amplifier one is p-n-p and other
transistor is n-p-n. In the positive half cycle of input signal the transistor Q1 gets
driven into active region and starts conducting. The same signal gets applied to the
base of the Q2. it ,remains in off condition, during the positive half cycle. During the
negative half cycle of the signal the transistor Q2 p-n-p gets biased into conduction.
While Q1 gets driven into cut off region. Hence only Q2 conducts during negative half
cycle of the input, producing negative half cycle across the load.

Circuit Diagram
Fig. 1 Class-B Complementary Symmetry Power Amplifier Circuit Diagram
Design Equations:
Given data: PL (MAX) =5 W, RL= 10Ω, f = 1KHZ
1. Selection of VCC:-
PL (MAX) = VCC ² / 2RL
VCC ² = PL (MAX) 2RL
VCC =
2. Selection R and RB:-
VBB = VBE = 0.6V , assume R = 150Ω
VBB=VCC.R / (R+RB)
RB =
f=1KHZ.
XCC1 = XCC2 = (R \\ RB) / 10
CC1 = CC2 = 1/ 2 π f XCC1 =

Procedure
1. Connect the circuit diagram as shown in Fig. 1 and supply the required
DC supply.
2. Apply the AC signal at the input and keep the frequency at 1 KHz and
connect the power o/p meter at the output. Change the Load resistance in
steps for each value of impedance and note down the output power.
3. Plot the graph between o/p power and load impedance. From this graph
find the impedance for which the output power is maximum. This is the
value of optimum load.
4. Select load impedance which is equal to 0V or near about the optimum
load. See the wave form of the o/p of the C.R.O.
5. Calculate the power sensitivity at a maximum power o/p using the relation.
Tabular Form
Simulation
Input power = 2 VCC2 / (πRL) =
S.No O/P Impedance (Ω) I/P Power O/P N=(Po)/( Pi)*100

(pi) (W) Power(po)
(W)
Practical
Input power = _____mW
S.NO O/P Impedance I/P Power(pi ) O/P Power(po) η=(Pac)/(Pdc)*100

(Ω) (mW) (mW)

Model Graph
Precautions
1. Connections should be made care fully.
2. Take the readings with out parallax error.
3. Avoid loose connections.
4. Simulation switch must be off while changing the values.
Inferences
Result
.
Questions
1. What is the use of Heat sinks in power amplifiers?
2. What is cross over distortion?
3. What is the maximum efficiency of Class B complementary symmetry
Power amplifier?
4. What are the advantages of Class B complementary symmetry amplifier?

9. SINGLE TUNED VOLTAGE AMPLIFIER

Aim
To design a class c tuned voltage amplifier for the input signal frequency of
5 kHz
Apparatus
Sl.No Name of the Specifications Qty

Component / equipment
1 Power transistor Icmax=100mA
pDmax=300mw
Vceo(max)=45v 1
Vcbo(max)=50v
2 capacitor(designed values) Max temp : 65c
Electrolytic type 3
capacitor
3 Resistors(designed values) Power rating=0.5w
Carbon type 2
4 Inductors(designed values) Internal resistance=∞ 1
Operating point :
Ambient
Theory
In class C amplifier, the Q point and input signal are selected such that the
output signal is obtained for less than a half cycle, for a full wave input. Due to such a
selection of Q point, transistor remains active , for less than a half cycle, For
remaining cycle of input cycle, the transistor remains cut off and no signal is
produced at the output. When a class C amplifier is connected to a parallel tuned
circuit, there fore the output voltage is maximum at the resonant frequency. The
resonant frequency for parallel tuned circuit is given by fr = 1/2 Π LC .

Tuned Amplifiers are used at radio frequencies. The amplifier consists of LC
Circuit for tuning certain frequency. The resonant frequency of lc circuit is equal to
input frequency.

Circuit diagram
Fig. 1 Single Tuned Voltage Amplifier Circuit Diagram
Design equations
Given data:
fr=5KHz , C=0.01µF,RB=1KHz,RL=1MΩ
1. selection of L:
fr = 1/2 Π LC
L=
f=5KHZ.
XC1 = 0.1RB , XC2 =0.1 RL,
2. selection of capacitor c 1 :
XC1=RB / 10
C1=
selection of capacitor c 2 :
Xc2 = RL/10
C2=

Procedure
1. Connect the circuit as per the circuit diagram shown in Fig. 1.
2. Apply input signal of some fixed amplitude.
3. Set input signal frequency at some frequency (say 100 KHz).
4. Increase the frequency in steps of KHz and observe the output.
5. Measure the output voltage for each value of input frequency.
6. Find the frequency at which maximum output is obtained.
7. Tabulate the readings and find voltage gain.
8. Draw the graph between frequencies vs. gain.
9. Locate two points on either side of the amplitude peak value on the graph at
which the gain is 70.7% of maximum gain.
Tabular Form
Simulation
Input voltage = _____V (peak-peak)
S.No Frequency Output Voltage (Vo) Gain in dB AV=20
(KHZ) (peak-peak) volts log (Vo / Vi)
Practical
Input voltage = _____V (peak-peak)
S. No Frequency Output Voltage (Vo) Gain in dB =

(KHZ) (volts p-p) 20log (Vo/Vi)

Model graph
Precautions
1. Connections should be made care fully.

2. Take the readings with out parallax error
Inferences
Result
Questions
1. What are the applications of Tuned amplifiers?
2. What are the requirements of tuned amplifiers?

3. What is Q-factor?

10. SERIES VOLTAGE REGULATOR

Aim
1. Design series voltage regulator to operate on supply of 15v.
2. Simulate the design of regulator.
3. Develop the hardware for design of voltage regulator.
4. Compare the practical results with theoretical results.
Apparatu:
S.No Name of the Specifications Qty

component/equipment
1 Zener diode (Bz6.5) Vz=6.5v 1
2 Transistors (BC 107) I c max =100ma, 1

VCEO =45v,
Pd(min) =300mw
3 Resistors(designed values) Power dissipation=0.5w 1
Carbon type Tolerance ±5%
4 Regulated power supply 0-30 V,1Amp 1
Theory
A regulator is an electronic circuit which maintains a constant output irrespective
of change in input voltage, load resistance and change in temperature. Series
voltage regulator is one type of regulator. If in a voltage regulator circuit , the control
element is connected in series with the load ,then the circuit is called series voltage
regulator circuit. The unregulated d.c voltage is the input to the circuit. The control
element controls the input voltage, that gets to the output. The sampling circuit
provides the necessary feed back signal. The comparator circuit compares the feed
back with the reference voltage to generate appropriate control signal. In a
transistorized series feedback type regulator the output voltage is given by
Vo = (1+R1/R2) (VBE2+Vz)

Circuit Diagram
Fig. 1 Series Voltage Regulator Circuit Diagram
Design Equations
Given data
VL= 9V, IL = 40mA, IZ = 1mA, VZ = 6.5V Vi =15V, IB =1mA, hfe=100
1. Assume the current flowing through the resistor R1 & R3 is 1/10 of the IL
I1=I3=IL/10 =40mA / 10 =
2. IE1=I1+I3+IL =
3. RL=VL/IL = 9/(40 X 10-3) =
4. VO=VL=R3I3+VZ
R3=VL-VZ/I3 =
5. R1I1+VBE2+VZ=VO
R1=VO-(VBE2+VZ)/I1 =
4 R2I2 = VBE2 + VZ
hfe = 100, IC2 =
5 I2 = I1-IB2 ( Since hfe = IC2/IB2 )
I2=
6 I4= IB1 + IC2
IB1 = IC1 / hfe1 (IC1 = IE1)
I4 = 3
7 Vi = I4R4 + VBE1 + VO
R4 =

Procedure
1. Connect the Circuit diagram as shown in the Fig. 1.
2. Apply the input voltage of 15V
3. Keep the input Voltage constant. Vary the load resistance and measure the
output Voltage and output current
4. Tabulate the readings
5. Plot the graph between Load current versus Load Resistance and Output
Voltage versus Load resistance.
Tabular forms
Simulation
S.No Load resistance Output Voltage (v) Output Current

RL (Ohms) IL (mA)
Practical
S.No Load resistance Output Voltage (v) Output Current

RL (Ohms) IL (mA)

Model graph
Precautions
1. Connections should me made care fully.

Inferences
Result
Questions
1. What is voltage regulator?
2. Why series regulators are called as linear voltage regulators.
3. What are the applications of series voltage regulator?
4. What are the characteristics of series voltage regulator?
5. How the regulation is obtained in series regulator.
6.What is the effect of output short on circuit operation?
7.What is the range of input voltage for which output is constant?
8. Define line and load regulations?

11. SHUNT VOLTAGE REGULATOR
Aim
1. Design a Voltage Shunt regulator for a supply of 15V to provide an o/p of 7V with
load current 40 mA.
2. Simulate the designed regulator.
3. Develop the hardware for designed Regulator.
4. Compare the practical values with theoretical values.
Apparatus
S.No Name of the component Specifications Qty

/Equipment
1 Resistors ( designed values) 0.5w , Tolerance ±5% 1
2 Transistor (BC107) ICmax=100mA, Vce = 5V 1

Vceo=45v,Pd(min)=300mw,
hfe=100
3 Zener diode(BZ6.5) 6.5V 1
Theory
The heart of any regulator circuit is a control element. If such a control
element is connected in shunt with the load, the regulator is called shunt voltage
regulator. The unregulated input voltage Vm tries to provide the load current but path
of current is taken by the control element to maintain the constant voltage across the
load. The control element remains constant voltage by shunting the current. Hence
regulated power supply is called voltage shunt regulated circuit. The output voltage
and output current of emitter follower series regulator is
VL = Vz + VBE ------1
IL = VL/RL ------ 2.

Circuit Diagram
Fig. 1 Shunt Voltage Regulator Circuit Diagram.
Design Equations
Given data : VL= 7V, IL = 40mA, IZ = 1mA, VZ = 6.5V Vi =15V, IB =1mA, hfe=100
1) RL = VL / IL=
2) By applying kirchoff’s current law
IS = IZ+IC+IL ; where IC = hfe IB =100*1mA=100mA
3) Choose the zener breakdown voltage as less (0.5v-1v) than the
required output voltage.
VL= VZ+VBE
VZ = VL- VBE
4) RS = (Vi – VL) / IS =
Procedure
1) Connect the circuit as per the circuit diagram shown in Fig. 1.

2) Keep the input voltage constant vary the load resistance Rl and
measure the o/p voltage and o/p current.
3) Plot the graph between VO and IL.
4) Plot the graph between IL and RL.

Tabular forms
Simulation
S.No Load resistance RL O/P Voltage Vo Load Current IL

(ohms) (volts) (mA)
Practical
S.No Load resistance RL O/P Voltage Vo Load Current IL

(ohms) (volts) (mA)
Model Graph

Precautions
1. Connections should me made care fully.

3. Avoid loose connections
Inferences
Result
Questions
1. What are the applications of shunt voltage regulator?
2. What are the characteristics of shunt voltage regulator?
3. How is the regulation obtained in shunt regulator?
4. What is the effect of output short on circuit operation?
5.What is the range of input voltage for which output is constant?
6.Define line and load regulations?

PULSE AND DIGITAL CIRCUIT

EXPERIMENTS

1. LINEAR WAVE SHAPING

Aim
i) To design a low pass RC circuit for the given cutoff frequency and obtain its
frequency response.
ii) To observe the response of the designed low pass RC circuit for the given
square waveform for T<<RC,T=RC and T>>RC.
iii) To design a high pass RC circuit for the given cutoff frequency and obtain
its frequency response.
iv) To observe the response of the designed high pass RC circuit for the given
square waveform for T<<RC,T=RC and T>>RC.
Apparatus Required
Name of the
Specifications Quantity
Component/Equipment
1KΩ 1
Resistors
2.2KΩ,16 KΩ 1
Capacitors 0.01µF 1
CRO 20MHz 1
Function generator 1MHz 1
Theory
A linear network is a network made up of linear elements only. When we transmit
a sinusoidal signal through the linear network it preserves its shape .No other period
signal like square, pulse, ramp and exponential signal preserve its shape when
transmitted through a linear network.
The process whereby the form of a non sinusoidal signal is altered by
transmission through a linear network is called “linear wave shaping”
Low Pass RC Circuit
An ideal low pass circuit is one that allows all the input frequencies below a
frequency called cutoff frequency f c and attenuates all those above this frequency.
A practical low pass circuit as shown in (Fig.1)
At zero frequency the reactance of the capacitor is infinity(because the capacitor
acts as an open circuit) so the entire input is appear at the output ,

i.e .the input is transmitted to output with zero attenuation. So the output is same as
input. So the gain is unity.
As the frequency increase the capacitor reactance (Xc=1/2πfC) decrease and so
the output decreases. At very high frequencies the capacitor virtually acts as a short
–circuit and the out becomes zero. So the circuit is called “Low pass filter”.
High Pass RC Circuit
An ideal high pass circuit is one that allows all the input frequencies above a
frequency called cutoff frequency f c and attenuates all those below the cutoff
frequency. A practical high pass circuit as shown in (Fig.2)
At zero frequency the reactance of the capacitor is infinity (because the capacitor
acts as an open circuit) and so it blocks the entire input and hence the output is zero.
As the frequency increase the capacitor reactance (Xc=1/2πfC) decrease and
hence the output and gain increases. At very high frequencies the capacitor
reactance is very small so the output is equal to input and the gain is equal to 1. So
the circuit is called “High pass filter”.
Circuit Diagram
Fig. 1 Low Pass RC Circuit
Fig. 2 High Pass RC Circuit

Design equations
f=1/2πRC
for the given cutoff frequency choose R value and calculate C
Procedure
A) Frequency response characteristics
1 .Connect the circuit as shown in Fig.1 and apply a sinusoidal signal of
amplitude of 2V p-p as input.
2. Vary the frequency of input signal in suitable steps of 100 Hz to 1 MHz and
measure the peak to peak amplitude of output signal.
3. Obtain frequency response characteristics of the circuit by calculating the gain
at each frequency and plotting gain in dB vs frequency in hertzs.
4. Find the cut off frequency fc by noting the value of f at 3 dB down from the
maximum gain
B) Output response
If the time constant of the circuit RC= 0.0198 ms
1. Apply a square wave of 2v p-p amplitude as input.
2. Adjust the time period of the waveform so that T>>RC, T=RC, T<<RC and observe
the output in each case.
3. Draw the input and output wave forms for different cases.
Readings
Table 1 Low Pass RC Circuit
Input Voltage, Vi=_____ V(p-p)

Frequency O/P Voltage, Vo Gain = 20log(Vo/Vi)
S.No
(Hz) (V) (dB)

Table 2 High Pass RC Circuit
Input Voltage, Vi=______ V(p-p)

Frequency O/P Voltage, Vo Gain = 20log(Vo/Vi)
S.No
(Hz) (V) (dB)
Model Graphs and Wave forms
Fig. 5 Output response of Low Pass RC circuit for different time constants

Fig. 6 Output response of high Pass RC circuit for different time constants
Precautions
2. Verify the circuit connections before giving supply.

3. Take readings without any parallax error.
Result:
Inference
Questions
1. Define linear wave shaping?
2. When does the low pass circuit act as integrator?
3. When does the high pass circuit acts as a differentiator?

2. NON LINEAR WAVE SHAPPING-CLIPPERS&

CLAMPERS
Aim
i) To obtain the output and transfer characteristics of various diode clipper

circuits.
ii) To verify the output response of different diode clamping circuits
Apparatus required
Name of the
Component/Equipme Specifications Quantity
nt
Resistors 1KΩ 1
Diode 1N4007 1
CRO 20MHz 1
DC Regulated power 1
0-30V,1A
supply
Theory
The circuits for which the outputs are non-sinusoidal for sinusoidal inputs are called
“Nonlinear wave shaping circuits”. Examples for nonlinear wave shaping circuits are
clipper and clamping circuits.
Clippers
Clipping means cutting or removing a part. The basic action of a clipper circuit is
to remove certain portions of the waveform, above or below certain levels as per the
requirements. Thus the circuits which are used to clip off unwanted portion of the
waveform, without distorting the remaining part of the waveform are called “Clipper
circuits or Clippers”.
The half wave rectifier is the best and simplest type of clipper circuit which clips
off the positive/negative portion of the input signal. The clipper circuits are also called
voltage or current limiters, amplitude sectors or slicers.
The clippers are mainly classified into two types based on level of clipping.

1) Single level clippers: In this a single diode is used to perform single-ended

limiting at one independent level.
2) Two level clippers: In this a pair of diodes is used to perform double-ended
limiting at two independent levels. A parallel, a series, or a series-parallel
arrangement may be used.
Single level clippers may be

a) series diode clippers with or without reference
b) shunt diode clippers with or without reference
Applications of clippers includes
i) Sine to square wave converters
ii) Voltage comparators
iii) Noise eliminating circuits
Circuit diagrams
Fig. 1 Positive peak clipper with reference voltage, V=2V
Fig. 2 Positive Base Clipper with Reference Voltage, V=2V

Fig. 3 Negative Base Clipper with Reference Voltage, V=-2V
Fig. 4 Negative peak clipper with reference voltage, V=-2v
Fig. 5 Slicer Circuit

Procedure
1. Connect the circuit as per circuit diagram shown in fig.1. Obtain a sine wave of
constant amplitude 8Vp-p from function generator and apply as input to the circuit.
2. Observe the output waveform and note down the amplitude at which clipping
occurs.
3. Draw the observed output waveforms.
4. To obtain the transfer characteristics apply dc voltage at input terminals and vary
the voltage insteps of 1V up to the voltage level more than the reference voltage
and note down the corresponding voltages at the output.
5. Plot the transfer characteristics between output and input voltages.
6. Repeat the steps 1 to 5 for all other circuits.
Readings
Table 1 Positive peak clipper: Reference voltage, V=___v
I/p voltage O/p voltage

(v) (v)
Table 2 Positive base clipper: Reference voltage V= ____v
I/p voltage(v) O/p voltage(v)

Table 3 Negative base clipper: Reference voltage V=___v
I/P voltage(v) O/Pvoltage(v)
Table 4 Negative peak clipper: Reference voltage V= _____v
I/P voltage(v) O/P voltage(v)
Table 5 Slicer Circuit
I/p voltage(v) O/p voltage(v)

Theoretical calculations
Positive peak clipper

Vr=2V, Vγ=0.6V
When the diode is forward biased Vo =Vr+ Vγ = 2.6v
When the diode is reverse biased the Vo=Vi
Positive base clipper
Vr=2V, Vγ=0.6V
When the diode is forward biased Vo=Vr –Vγ = 1.4v
When the diode is reverse biased Vo=Vi .
Negative base clipper
Vr=2V, Vγ=0.6V
When the diode is forward biased Vo = -Vr+ Vγ = -1.4v
Negative peak clipper
Vr=2V, Vγ=0.6V
When the diode is forward biased Vo= -(Vr+ Vγ) =-2.6v
Slicer
When the diode D1 is forward biased and D2 is reverse biased Vo= Vr+ Vγ
=2.6V
When the diode D2 is forward biased and D2 is reverse biased Vo=-(Vr+ Vγ)
=-2.6V
When the diodes D1 &D2 are reverse biased Vo=Vi .
Model Graphs
Output response Transfer Characteristics
Fig. 6 Positive peak clipper: Reference voltage V=----V

Fig. 7 Positive base clipper: Reference voltage V=-----V
Fig. 8 Negative base clipper: Reference voltage V=----V

Fig. 9 Negative peak clipper: Reference voltage V=----V
Fig. 10: Slicer Circuit
Precautions
2. Verify the circuit before giving supply.

Result
Inference
Questions
1. In the fig.1 if reference voltage is 0v then what will be the output?
2. What are the other names for the clippers?

CLAMPERS
Apparatus Required
Name of the Specifications Quantity
Component/Equipment
Resistors 10KΩ 1
Capacitor 100uF, 100pF 1
Diode 1N4007 1
CRO 20MHz 1
Theory
Clampers
Clamping circuits are the circuits, which are used to clamp or fix the extremity of
a period wave form to some constant reference level Vr .These are also use.d to add a
d.c level as per the requirement to the a.c signals. Capacitor, diode, resistor are the
three basic elements of a clamper circuit.
The Clamping Circuit Theorem
When a signal is transmitted through a capacitive coupling network (RC high –
pass circuit), it looses its dc component, and a clamping circuit may be used to introduce
a dc component by fixing the positive or negative extremity of that waveform to some
reference level. For this reason, the clamping circuit is often referred to as dc restorer
or dc reinserter.
Classification: Basically clampers are classified in to
1. Negative clampers: In negative clamping, the positive extremity of the
waveform is fixed at the reference level and the entire waveform appears below the
reference level, i.e. the output waveform is negatively clamped with reference to the
reference level.
2. Positive clampers: In positive clamping, the negative extremity of the
waveform is fixed at the reference level and the entire waveform appears above the
reference level, i.e. the output waveform is positively clamped with reference to the
reference level.

The capacitor is essential in clamping circuits. The difference between the

clipping and clamping circuits is that while the clipper clips off an unwanted portion of the
input waveform, the clamper simply clamps the maximum positive or negative peak of
the waveform to a desire level. There will be no distortion of waveform.
Circuit Diagrams
Fig. 11 Positive peak clamping to 0V
Fig. 12 Positive peak clamping to Vr=----

Fig. 13 Negative peak clamping to Vr=0v
Fig. 14 Negative peak clamping to Vr= -2v
Procedure
1. Connect the circuit as per circuit diagram Fig. 11
2. Obtain a constant amplitude sine wave from function generator of 6 Vp-p, frequency
of 1 KHz and give the signal as input to the circuit.
3. Observe and draw the output waveform and note down the amplitude at which
clamping occurs.
4. Repeat the steps 1 to 3 for all circuits.

Model waveforms
Fig. 15 Positive peak clamping to 0V:
Fig. 16 Positive peak clamping to Vr=2V
Fig. 17 Negative peak clamping to 0V

Fig. 18 Negative peak clamping to Vr= -2V
Precautions
2. Verify the circuit before giving supply.
Result
Inference
Questions
1. What is a clamper?
2. Give some practical applications of clamper.
3. What is the purpose of shunt resistance in clamper?

3. LOGIC GATES WITH DISCRETE COMPONENTS

Aim
To construct the basic and universal gates using discrete components and Verify their
truth tables
Apparatus required
Name of the
Component/Equipment
Transistor BC 107 1
Diode IN4007 1
4.7KΩ 2
Resistors
100KΩ 1
LED - 1
Bread Board - 1
Regulated Power Supply 0-30V, 1A 1
Theory
1. OR-GATE
OR gate has two or more inputs and a single output and it operates in
accordance with the following definitions.
• The output of an OR gate is high if one or more inputs are high. When all the
inputs are low then the output is low.
• If two or more inputs are in high state then the diodes connected to these inputs
conduct and all other diodes remain reverse biased so the output will be high and
OR function is satisfied.
2. AND-GATE
AND gate has two or more inputs and a single output and it operates in
accordance with the following definitions.
• The output of an AND gate is high if all inputs are high.
• If Vin is chosen i.e. more positive than Vcc then all diodes will be conducting upon
a coincidence and the output will be clamped to ‘1’.

• If Vr is equal to Vcc then all diodes are cut-off and output will raise to the voltage
Vr if not all inputs have same high value then the output of AND gate is equal to
Vi (min0).
3. NOT-GATE
The NOT gate circuit has a single input input and a single input and perform the
operation of negation in accordance with definition, the output of a NOT gate is high if
the input is low and the output is low or zero if the input is high or 1.
4. NOR-GATE
A negation following on OR is called as NOT-OR gate or NOR gate. As shown in

figure if Vo is applied as input signal to the diodes then both diodes are forward biased.
Hence no voltage is applied to emitter base junction and total current is passed through
the LED and it glows which indicate high or one state.
5. NAND-GATE
The NAND gate can be implemented by placing a transistor NOT gate after the
AND gate circuit with diodes. These gates are called diode-transistor logic gates.
If Vo is applied to input of the diode then the diode D1 and D2 will be forward biased.
Hence no voltage applied across base-emitter junction and this junction goes into cut-off
region. Hence total current from source Vce will flow through LED and it flows which
indicate the one state or high state.
Circuit diagrams
Fig. 1 OR GATE

Fig. 2 AND GATE
Fig. 3 NOT GATE

Fig. 4 NOR GATE
Fig. 5 NAND GATE

Truth tables
Table 1 AND GATE Table 2 OR GATE
Inputs Output Inputs Output
A B Y=AB A B Y=A+B
0 0 0 0 0 0
1 0 0 1 0 1
0 1 0 0 1 1
1 1 1 1 1 1
Table 3 NOT GATE Table 4 NAND GATE
Input Output Inputs Output
A Y= A B Y=
0 0 1
0 1
1 0 1
1 0 0 1 1
1 1 0
Table 5 NOR GATE
Inputs Output
A B Y=
0 0 1
1 0 0
0 1 0
1 1 0

Procedure
1. Connect the circuit as per the circuit diagram Fig.1
2. Apply 5V from RPS for logic 1and 0V for logic 0.
3. Measure the output voltage using digital multimeter and verify the truth table.
4. Repeat the same for all circuits.
Result
Inference
Questions
1. What are the universal gates? Why they are called universal gates?
2. What is the other name of the EX-NOR gate?

4. BISTABLE MULTIVIBRATOR
Aim
To observe the stable state voltages of Bistable Multivibrator.
Apparatus required
Name of the
Component/Equipment
Transistor BC 107 2
2.2KΩ 2
Resistors
12KΩ 2
Digital multi meter 3 ½ digit display 1
Theory
Multivibrator
Multi means many ; vibrator means oscillator. A circuit which can oscillate at a
number of frequencies is called a Multivibrator. Each multivibrator has two states.
Bistable Multivibrator
A bistable multivibrator has two stable states. Each multivibrator is having
two coupling elements. In bistable multivibrator circuit both the coupling elements are
resistors (i.e. dc couplings). It requires a triggering signal to change from one stable state
to another, and another triggering signal for the reverse transition.
A bistable multivibrator is also called as a multi, Eccles-Jordan circuit, trigger
circuit, scale –of-two toggle circuit, flip-flop, and binary.
Circuit Operation
The circuit diagram of a fixed bias bistable multivibrator using transistors is as
shown in fig. 1. The output of each amplifier is direct coupled to the input of the other
amplifier. In one of the stable states transistor Q1 and Q2 is off and in the other stable
state. Q1 is off and Q2 is on even though the circuit is symmetrical; it is not possible for
the circuit to remain in a stable state with both the transistors conducting simultaneously
and caring equal currents. The reason is that if we assume that both the transistors are
biased equally and are carrying equal currents i1 and i2 suppose there is a minute
fluctuation in the current i1-let us say it increases by a small amount .Then the voltage at
the collector of Q1 decreases. This will result in a decrease in voltage at the base of Q2.

So Q2 conducts less and i 2 decreases and hence the potential at the collector of q2
increases. This results in an increase in the base potential of Q1. So Q1 conducts still
more and i1 is further increased and the potential at the collector of Q1 is further
decreased, and so on. So the current i1 keeps on increasing and the current i 2 keeps on
decreasing till Q1 goes in to saturation and Q2 goes in to cut-off. This action takes place
because of the regenerative feed –back incorporated into the circuit and will occur only if
the loop gain is greater than one.
Applications of Bistable Multivibrator
1) It is used as a basic memory element
2) It is used to perform many digital operations such as counting, storing of binary
data.
3) It is also used in the generation & processing of pulse type waveform.
.
Circuit Diagram
Fig.1 Bistable Multivibrator

Procedure
1. Connect the circuit as shown in Fig.1
2. Verify the stable state by measuring the voltages at two collectors by using
multimeter.
3. Note down the corresponding base voltages of the same state (say state-1).
4. To change the state, apply negative voltage (say-2v) to the base of on
transistor or positive voltage to the base of transistor (through proper
current limiting resistance).
5. Verify the state by measuring voltages at collector and also note down
voltages at each base.

Observations
Before Triggering
Q1 Q2
VBE1= VBE2=
VCE1= VCE2=
After Triggering
Q1 Q2
VBE1= VBE2=
VCE1= VCE2=
Precautions
2. Note down the parameters carefully.
3. The supply voltage levels should not exceed the maximum rating of the transistor.
Inference
Result
Questions
1. What do you mean by a bistable circuit?
2. What are the other names of a bistable multivibrator?
3. What do you mean by triggering signal?

5. ASTABLE MULTIVIBRATOR
Aim
To observe the ON & OFF states an Astable Multivibrator.
Apparatus required
Name of the
Component/Equipment
Transistor BC 107 2
3.9KΩ 2
Resistors
100KΩ 2
Capacitor 0.01µF 2
Theory
Multivibrator
Multi means many ; vibrator means oscillator. A circuit which can oscillate at a
number of frequencies is called a Multivibrator. Each multivibrator has two states.
Astable Multivibrator
An astable multivibrator has no stable state. And it is having two quasi stable
states. In astable multivibrator circuit both the coupling elements are capacitors (i.e. ac
couplings). And it keeps on switching between these two states by itself. No external
triggering signal is needed. The astable multivibrator cannot remain indefinitely in any
one of the two states .The two amplifier stages of an astable multivibrator are
regenerative across coupled by capacitors. The astable multivibrator may be to
generate a square wave of period,1.38RC. The astable multivibrator circuit is used as a
master oscillator to generate square waves. It is often a basic source of fast waveforms.
It is a free running oscillator. It is called a “Square wave generator”. It is also termed a
“Relaxation oscillator”.
Circuit Operation
The circuit diagram of the collector – coupled astable multivibrator using
transistors as shown in fig.1. The collectors of both the transistors Q1 & Q2 are connected
to the bases of the other transistors through the coupling capacitors C1 & C2. Since both

are ac couplings, neither transistor can remain permanently at cut-off. Instead, the circuit
has two quasi-stable states, and it makes periodic transistors between these states.
Hence it is used as a master oscillator. No triggering signal is required for this
multivibrator. The component values are selected such that, the moment it is connected
to the supply, due to supply transients one transistor will go into saturation and the other
into cut-off, and also due to capacitive coupling it keeps on oscillating between its two
quasi stable states.
Applications of Astable Multivibrator
1) It is used in Square wave generators
2) It is also used in voltage to frequency converters.
Circuit Diagram
Fig.1 Astable Multivibrator

Procedure
1. Calculate the theoretical frequency of oscillations of the circuit.
2. Connect the circuit as per the circuit diagram.
3. Observe the voltage wave forms at both collectors of two transistors
simultaneously.
4. Observe the voltage wave forms at each base simultaneously with
corresponding collector voltage.

5. Note down the values of wave forms carefully.

6. Compare the theoretical and practical values.
Calculations
Theoretical Values
RC= R1C1+ R2C2
Time Period, T = 1.368RC
= 1.368x100x103x0.01x10-6
= 93 µ sec
Frequency, f = 1/T = 10.75kHz
Model waveforms
Fig. 2 Output response of Astable Multivibrator
Precautions
2. Readings should be noted without parallax error.
Result

Inference
Questions
1.Define stable state ?
2.Define quasi stable state ?

6.MONOSTABLE MULTIVIBRATOR
Aim
To observe the stable state and quasi stable state voltages of monostable multivibrator.
Apparatus Required
Name of the
Component/Equipment
BC 107 2
Transistor
1.5KΩ 1
2.2KΩ 2
Resistors
68KΩ 1
1KΩ 1
Capacitor 1µF 2
Diode 0A79 1
CRO 20MHz 1
Theory
Multi means many ; vibrator means oscillator. A circuit which can oscillate at a number of
frequencies is called a Multivibrator. Each multivibrator has two states.
Monostable Multivibrator
A monostable multivibrator on the other hand compared to astable, bistable has
only one stable state, the other state being quasi stable state. Normally the monostable
multivibrator is in stable state and when an externally triggering pulse is applied, it
switches from the stable to the quasi stable state. It remains in the quasi stable state for
a short duration, but automatically reverse switches back to its original stable state
without any triggering pulse.
The monostable multivibrator is also called as ‘one shot’ or ‘uni vibrator’ since
only one triggering signal is required to reverse the original stable state. The duration of
quasi stable state is termed as delay time (or) pulse width (or) gate time. It is denoted
as ‘t’
Circuit Operation
Under quiescent conditions, the monostable multivibrator will be in its stable
state only. A triggering signal is required to induce a transition from the stable state to

the quasi stable state. Once triggered properly the circuit may remain in its quasi stable
state for a time which is very long compared with the time of transition between the
states, and after that it will return to its original state. No external triggering signal is
required to induce this reverse operation. In monostable multivibrator one coupling
element is a resistor & another coupling element is capacitor.
When triggered, since the circuit returns to its original state by itself after a time T,
it is known as a one shot, single-step, or a univibrator. Since it generates a rectangular
waveform which can be used to gate other circuits, it is also called a gating circuit.
The circuit diagram for monostable multivibrator is as shown in fig 1. The R1C1
combination is differentiating circuit. Let the pulse width of the triggering signal be tp =1
µs.
Circuit diagram
Fig.1 Monostable Multivibrator

Procedure
1. Connect the circuit as per the circuit diagram as shown in Fig. 1.
2. Verify the stable states of Q1 and Q2
3. Apply the square wave of 2Vp-p , 1KHz signal to the trigger circuit.
4. Observe the wave forms at base of each transistor simultaneously.
5. Observe the wave forms at collectors of each transistor simultaneously.
6. Note down the parameters carefully.

7. Note down the time period and compare it with theoretical values.
8. Plot wave forms of VB1, VB2, VC1 & VC2 with respect to time .
Model waveforms
Fig. 2 Output response of Monostable Multivibrator

Calculations
Theoretical Values
Time Period, T = 0.693RC
= 0.693x68x103x0.01x10-6
= 47µ sec
= 0.047 m sec
Frequency, f = 1/T = 21 kHz

Precautions
2. Note down the parameters without parallax error.
3. The supply voltage levels should not exceed the maximum rating of the transistor.
Inference
Result
.
Questions
1. What are the other names of Mono Stable multivibrator ?
2. Which type of triggering is used in mono stable multi vibrator ?
3. Define transition time?

7. SCHMITT TRIGGER
Aim
To observe the output response and transfer characteristics of Schmitt Trigger
Apparatus Required
Name of the
Values/Specifications Quantity
Component/Equipment
Transistor BC 107 2
100Ω 1
6.8KΩ 1
Resistors
3.9KΩ 1
2.7KΩ 1
2.2KΩ 1
Capacitor 0.01µF 1
CRO 20MHz 1
Regulated Power Supply 30V 1
Theory
Schmitt trigger is an emitter coupled bistable circuit and the existence of only two
stable states results from the fact that positive feedback is incorporated into the circuit
and from the further fact that the loop gain of the circuit is greater than unity. There are
several ways to adjust the loop gain. One way of adjusting the loop gain is by varying
Rc1. Under quiescent conditions Q1 is OFF and Q2 is ON because it gets the required
base drive from Vcc through Rc1 and R1. So the output voltage is Vo=Vcc-Ic2Rc2 is at its
lower level. Until then the output remains at its lower level.
With Q2 conducting, there will be a voltage drop across RE = (Ic2+IB2)RE, and this
will elevate the emitter of Q1. As the input v is increased from zero, the circuit will not
respond until Q1 reaches the cut-in point (at Vi =V1). Until then the output remains at its
lower level. With Q1 conducting (for Vi>V1) the circuit will amplify because Q2 is already
conducting and since the gain ∆Vo/ ∆Vi is positive, output will rise in response to the rise
in input. As Vi continues to rise, C1 and hence B2 continue to fall and E2 continues to rise.

Therefore a value of Vi will be reached at which Q2 is turned OFF. At this point

Vo=Vcc and the output remains constant at this value of Vcc, even if the input is further
increased.
Applications of Schmitt Trigger
1) It is used as an amplitude comparator.
2) It is also used as a squaring circuit.
Circuit diagram
Fig.1 Schmitt Trigger

Procedure
2. Apply a sine wave of peak to peak amplitude 10V, 1 KHz frequency wave as
input to the circuit.
3. Observe input and output waveforms simultaneously in channel 1 and channel 2
of CRO.
4. Note down the input voltage levels at which output changes the voltage level.
5. Draw the graph between voltage versus time of input and output signals.
6. To obtain transfer characteristics apply a dc signal at the input and vary in steps
of 1V from 0V to 10V both in forward and reverse direction
7. Identify UTP and LTP from the readings
8. Plot output response and transfer characteristics separately

Model Graph
Fig.2 Output response of Schmitt Trigger
Fig.3 Transfer characteristics of Schmitt Trigger

Precautions
2. Readings should be noted carefully without any parallax error.

Result
Inference
Questions
1. What is the other name of the Schmitt trigger?
2. What are the applications of the Schmitt trigger?
3. Define the terms UTP & LTP?

8. UJT RELAXATION OSCILLATOR

Aim:
To observe the output response of UJT Relaxation Oscillator.
Apparatus Required
Name of the
Component/Equipment
UJT 2N 2646 1
220Ω 1
Resistors 68KΩ 1
120Ω 1
0.1µF 1
Capacitor 0.01µF 1
0.001µF 1
Diode 0A79 1
Inductor 130mH 1
CRO 20MHz 1
Regulated Power Supply (0-30V),1A 1
Theory
Many devices such as BJT, UJT, FET can be used as a switch. Here UJT is used as a
switch to obtain the sweep voltage. Capacitor C charges through the resistor, R towards
supply Voltage, Vbb. As long as the capacitor voltage is less than peak Voltage, Vp, the
emitter appears as an open circuit.
Vp =η Vbb + Vγ where,η = Intrinsic standoff ratio of UJT,
Vγ = Cut in voltage of diode.
When the capacitor voltage Vc exceeds voltage Vp, the UJT fires. The Capacitor starts
discharging through R1+Rb1. Where, Rb1 is the internal base resistance. As RB1 is
assumed negligible and hence capacitor discharges through R 1 .
Due to design of R1, this discharge is very fast, and is produces a pulse across R 1 .
When the capacitor voltage falls below Vv i.e. Vc=VE=Vv, the UJT gets turned OFF. The
capacitor starts charging again. This process is repeated until the power supply is
available.

Circuit diagram
Fig.1 UJT relaxation oscillator

Design equations
Theoretical Calculations
Vp = Vγ+(R1/ R1 R2 )Vbb
=0.7+(120/120+220)10
=8.57V
1. When C=0.1µF
Tc =RC ln(Vbb- Vv/ Vbb- Vp)
=(68K) (0.1µF) (12/12-8.57)

= 3.6ms
Td =R1C=(120)( 0.1µ)=12 µsec.
2. When C=0.01µF
=(68K) (0.01µF) (12/12-8.5)

= 365µs
Td =R1C=(120)( 0.01µ)=1.2 µsec.
3. When C=0.001µF
=(68K) (0.001µF) (12/12-8.5)

= 36.5µs
Td =R1C=(120)( 0.01µ)=0.12 µsec

Table 1: Comparison of theoretical and practical values

Capacitance value Theoretical time Practical time
S.NO
(µF) period period
1 0.1
2 0.01
3 0.001
Model graph
Fig. 2 Voltage across the capacitor

Procedure
Procedure
1. Connect the circuit as shown in Fig.1.
2. Observe the voltage waveform across the capacitor, C.
3. Change the time constant by changing the capacitor values to 0.1µF and 0.001 µF
and observe the wave forms.
4. Note down the parameters, amplitude, charging and discharging periods of the wave
forms
5. Compare the theoretical and practical time periods.
6. Plot the graph between voltage across capacitor with respect to time
Precautions
1. Connections should be given carefully.
2. Readings should be noted without parallox error.

Result
Inference
Questions
1. What do you mean by a) voltage time base generator, b) a current time bas generator.
2. What are the applications of time base generator?
3. What are the methods of generating a time base waveform?

9. BOOT STRAP SWEEP CIRCUIT

Aim
To observe the output response of a boot strap sweep circuit.
Apparatus Required
Name of the
Component/Equipment
Transistor BC 107 2
220Ω 1
1KΩ 1
Resistors
470 Ω 1
10Ω 1
100µF 2
Capacitor 1µF 1
0.001µF 1
Diode 2N2222 1
CRO 20MHz 1
Regulated Power 1
0-30V,1A
Supply
Theory
Boot strap sweep generator is a technique used to generate a sweep with
relatively less slope error when compared to the exponential sweep. This is achieved
by maintaining a constant current through a resistor, by maintain a constant voltage
across it.
The circuit shown in Fig. 1, is a transistor bootstrap time – base generator.
The input to transistor Q1 is gating waveform a monostable multivibrator and the Q1
acts as a switch which should be opened to initiate the sweep. Voltage across
resistor is maintained constant (Vce) hence a constant current (Vcc/R) will charge the
capacitor C. Transistor Q2 will act as an amplifier with high input impedance and
voltage gain ‘1’ (emitter follower). Hence the same sweep which is generated across
C will also appear at the output.

Circuit diagram
Fig. 1 Bootstrap sweep circuit

Wave forms
Fig. 2 Output response of Bootstrap sweep circuit

Design equations
TS(max)=RC
Assume ‘C’ and find ‘R’ for given maximum sweep
Select Rb to provide enough bias for switching transistor Q1
Procedure
1. Connect the circuit as shown in the Fig.1.
2. Apply the square wave input to the circuit (which is generated in the module itself).
3. Observe the output wave form.
4. By varying the input frequency observe the variations in the output.
5. Note the maximum value of sweep and starting voltage.
6. Note the sweep time Ts.
Precautions
1. Connections should be given carefully.
2. Readings should be noted without parallox error.
Result
Inference
Questions
1 .What are the other methods of sweep generator?
2. Compare bootstrap and miller sweep generator?

10. SAMPLING GATES

Aim
To observe the output response of a bidirectional sampling gate.
Apparatus Required
Name of the
Component/Equipment
Transistor BC 107 1
220KΩ 1
Resistors
5.6KΩ 1
CRO 20MHz 1
Theory:
Sampling gate is a transmission network in which the output is an exact reproduction of
the input during a selected time interval and is zero otherwise. The time interval for
transmission is selected by an externally impressed signal which is called the gating
signal and is usually rectangular in wave shape.
Sampling gates are of two types
1. Unidirectional sampling gates: Unidirectional sampling gates are those which
transmit signals of only one polarity.
2. Bidirectional sampling gates: Bidirectional sampling gates are those which transmit
signals of both polarities.
When gating signal is at it’s lower level transistor is well cutoff and output is Vcc.
When gating signal is at its higher level transistor goes into active region so input signal
is sampled and appears at output.
Sampling gates are also called linear gates, transmission gates or selection circuits.
Sampling gates are different from the logic gates. In logic gates there can be any
number of inputs and the inputs and output of the logic gates are either pulses or voltage
levels and the output is not a reproduction of the input. The output of a sampling gate is
an exact reproduction of the input during the selected time interval. The input may be a
pulse, square wave, sine wave or any other waveform.

Circuit diagram
Fig. 1 Bidirectional Sampling gate using transistor

Procedure
1. Connect the circuit as per shown in Fig.1.
2. Generate a control voltage Vc of 4V peak to peak voltage 1KHz and apply it to the
circuit.
3. Apply the input signal with a small peak to peak voltage.
4. Observe the output wave form and control voltage, VC simultaneously and note
down the parameters of waveforms.
5. Plot the graph between VS, VC and output waveform with respect to time
Model wave forms
Fig. 2 Input and output wave forms of Bidirectional Sampling gate

Precautions
1. Connections must be done carefully.
2. Observe the output waveforms with out parallax error
Result
Inference
Questions
1. What are the other names of sampling gates?
2. What do you meant by pedestal?
3. What are the applications of sampling gates?

ADDITIONAL LAB EXPERIMENTS

1. ATTENUATORS
Aim
To design an attenuator circuit and observe different types of compensations
for different values of capacitors.
Apparatus Required
Name of the
Component/Equipment
Resistor 1kΩ 2
Capacitor 0.1µF, 0.01µF, 1µF 2
CRO 20MHz 1
Regulated Power Supply

(0-30)V,1A 1
Theory
Attenuators are resistive networks, which are used to reduce the amplitude of
the input signal. The simple resistor combination if Fig.1 in the circuit diagram would
R2
multiply the input signal by the ratio α = R1 + R2
independently of the frequency. If the
output of the attenuator is feeding a stage of amplification , the input capacitance C 2
of the amplifier will be the stray capacitance shunting the resistor R 2 of the
attenuator and the attenuator will be as shown in Figure. And the attenuation now is
not independent of frequency.
Circuit Diagram
Fig. 1 Simple Attenuator

Fig. 2 Compensated Attenuator

Design Equations
Theoretical Calculations
a) Perfect Compensation
Vo (0+)=Vi C1/C1+C2
=5(0.1/0.1+0.1)
=2.5V
Vo (∞)=Vi R1/R1+R2
=5(1/1+1)
=2.5V
b) Over Compensation
Vo (0+)=Vi C1/C1+C2
=5(1µ/1µ+0.1µ)
=4.54V
Vo (∞)=Vi R1/R1+R2
=5(1/1+1)
=2.5V
c) Under Compensation
Vo (0+)=Vi C1/C1+C2
=5(0.01µ/0.01µ+0.1µ)
=0.45V
Vo (∞)=Vi R1/R1+R2
=5(1/1+1)
=2.5V

Procedure
1. Connect the circuit diagram as shown in Fig.1
2. Apply input voltage, VPP from the function generator to the circuit.
3. Observe the output wave form and note down the parameters
4. Connect the circuit diagram as shown in fig.2
5. Apply input voltage, VPP from the function generator to the circuit.
6. Keep the value of C1 = 0.1µF constant.
7. Now keep the value of C1 at 0.1µF for perfect compensation, at 1µF for over
compensation and at 0.01µF for under compensation.
8. Observe the output waveforms for each case and note down the values of
V0( ∞ ) and V0 (o+).
9. Compare the theoretical and practical values of each case.
10. Draw the graphs for perfect, over and under compensation network.
Model Graphs
Fig. 3 Perfect Compensation
Fig. 4 Over Compensation

Fig. 5 Under Compensation
Precautions
1. Check the connections before giving the power supply
2. Observations should be done carefully
Result:
Inference
Questions
1. What is the purpose of C1
2. What is the condition for perfect compensation?

2. TRANSISTOR AS A SWITCH
Aim
To verifying the switching action of a transistor.
Apparatus Required
Name of the
Component/Equipment
Transistor BC 107 1
10K 2
Resistors
5.6KΩ 2
Capacitor 100pF 1
CRO 20MHz 1
Theory
Transistors are widely used in digital logic circuits and switching applications. In
these applications the voltage levels periodically alternate between a “LOW” and a
“HIGH” voltage, such as 0V and +5V.
In switching circuits, a transistor is operated at cutoff for the OFF condition, and
in saturation for the ON condition. The active linear region is passed through abruptly
switching from cutoff to saturation or vice-versa. In switching applications, the active
region is of no interest.
In cutoff region, both the transistor junctions between Emitter and Base and the
junction between Base and Collector are reverse biased and only the reverse current
which is very small and practically neglected, flows in the transistor.
In saturation region both junctions are in forward bias and the values of Vce(sat)
and Vbe(sat) are small. Saturation voltages range from a few tenths of a volt to a volt,
depending on the transistor type. In saturation condition, the collector current is
comparatively large, and is controlled by the external resistance connected in the
collector circuit. The basic transistor circuit used in switching operations is called an
“Inverter”.

Circuit Operation
When the transistor acts as a switch, it is either in cut-off or in saturation. To
consider the behavior of the transistor as it makes transitions from one state to other,
consider the circuit shown in Fig. 1 which is driven by the pulse waveform. The pulse
waveform makes transitions between the voltage levels V2 and V1. At V2 the transistor is
at cut-off and at V1 the transistor is in saturation. The input is applied between base and
emitter through a resistor.
Circuit Diagram
Fig.1 Transistor as a switch
Procedure
2. Obtain a constant amplitude square wave from function generator of 5V p-p
and give the signal as input to the circuit.
3. Observe the output waveform and note down its voltage amplitude levels.
4. Draw the input and output waveforms

Model graph
Fig.2 Input and output wave forms
Theoretical calculations
When Vi= +2.5v, the transistor goes into saturation region.
So VO=Vce sat=0.3V.
When Vi=-2.5v, the transistor is in cutoff region so Vo=Vcc=5v
Precautions
2. Verify the circuit before giving supply voltage.

Result
Inference
Questions
1. What are the limitations of transistor switch?
2. What is the turn on time of a transistor?

3.COMMON SOURCE AMPLIFIER
Aim
1. To design a COMMON - SOURCE amplifier for given specifications.
Apparatus
S.No Name Of The Specifications Qty

Component/Equipment
1 Field Effect Transistor IGS=10mA
(BFW10) PD=300mw 1
VGS= -30V
VDG=-30V
2 Capacitors(designed Electrolytic type 3
values) Voltage rating=
1.6v
3 Resistors (designed Power rating=0.5w 4
values) Carbon type
Theory
In common source amplifier circuit source terminal is made common to the
other two terminals. In common source amplifier circuit input is applied between gate
and source and output is taken from drain and source. The coupling capacitors C1
and C2 are used to isolate the D.C biasing from the applied ac signal, and acts as
short circuit for the ac analysis. The high frequency characteristics of the FET
amplifier are determined by the interelectrode and wiring capacitance.
The CS amplifier which provides good voltage amplification is most
frequently used. In cascade amplifier input impedance of the second stage acts as
shunt across output of first stage and Rd is shunted by Ci. Since the reactance
decreases with increasing frequencies, the output impedance will be low at high
frequencies, this will result in decreasing the gain at high frequencies.

Circuit Diagram
Fig.1 Common Source Amplifier circuit diagram
Design Equations
Given data:
µ = 50,rd = 46KΩ , gm = 2 m mho, ID = 4 mA, VDs = 8V , VGs = -2V , VDD= 30V ,
Vgn = 12V
1) To calculate RD&RS
Applying Kirchoff’s voltage law to the drain circuit in the diagram

VDD = IDRD+VDS+VS
VDD = ID (RD+RS)+(VDD/2) (since VDs = IDRs so =VDD/2)
RD+RS =
Assume Rs = 1KΩ
RD =
2) As voltage divider bias in the circuit
RGS = R1// R2
f=1KHZ. XCs = 0.1Rs , Xci =0.1 Rgs, Xco =0.1 Rd

3) Xcs = (Rs/10)
CS = 1/(2πfXcS)
4) Xci = Rgs/10
Ci = 1/(2πfXc1)
5) Xco = Rd/10 =
Co = 1/(2πfXc2) =
Standard values
RD=____ , Rs = _____ ,RG=_____ , Ci=_____, Co= _____, Cs= ______
Procedure
1. Connect the circuit as per the circuit diagram as shown in Fig.1.
2. Apply supply voltage, VDD of 12V.
3. Now feed an AC signal 20mV at the input of the amplifier with different
output voltage.
5. Draw a graph with frequency on X- axis and gain in dB on Y- axis. From
graph calculate bandwidth.
Tabular Form
Simulation
ac Input voltage VI =_______mV (peak-peak)
Output Voltage(Vo) Gain in decibels

S.No Frequency (Hz)
(Volts-p-p) AV=20 log (Vo/ Vi)

Practical
ac Input voltage VI =______mV (peak-peak)
Output Voltage(Vo) Gain in decibels

S.No Frequency (Hz)
(Volts-p-p) AV=20 log (Vo / Vi)
Model Graph
Observations
Simulated Practical
Maximum gain (Av)

Lower cutoff frequency (fL)

Precautions
1. Connections must be made very carefully.
3. The applied voltage and current should not exceed the maximum ratings of
the given transistor.
Inferences
Result
Questions
1. What is meant by Transconductance with respect to JFET?
2. What are the characteristics of CS amplifier?
3. What is Amplification Factor (µ)?
4. Define operating point?
5. Which component in the circuit effects the gain and bandwidth of an amplifer?

APPENDIX
Name of The Component Specifications/Pin Diagrams
* operating point temp-65o to 200o

* IC(max)= 0.2 Amp
Transistor
(BC 107) * hfe (min) = 40
* hfe (max) = 450
Ic 2.0A(Pulsed)
Vce 30V
Uni Junction Transistor PDISS 300mW@TC=25ºC
(2N2646) TSTG -65ºC to +150ºC
TJ -65ºC to +125ºC
өJC 33ºC/W
Diodes
Type No 1N4001 1N4007

Max. Peak Inverse Volts 50 1000
Max RMS Supply Volts 35 700
Maximum Forward Voltage 1.1 Volts,Peak
@ 1Ampere, DC @ 75 0 C
Maximum Reverse DC Current 10µA
@PIV @ 250 C
Maximum Dynamic Reverse Current 30µA,Average
@PIV @750 C

References:
1. Electronic Devices and circuit theory –Robert L. Boylestad and Louis

Nashelsky,Pearson/Printice hall
2. Microelectronic circuits- serda A.S. and K.C. Smith,Oxford University Press
3. Microelectronic circuits analysis analysis and design – M.H. Rashid, PWS
Publications
4. Principles of Electronics circuits – S.G .Burns and P.R Bond
5. Pulse and digital circuits- J.Milliman and H.Taub, McGraw-Hill
6. Solid State Pulse circuits-David A.Bell, PHI
7. Pulse and Digital Circuits-A.Anand Kumar, PHI
websites:
1. www.google.com
2. www.discovercircuits.com
3. www.datasheetcatlog.com
4. www.dmoz.com
5. www.analog.com/pdc
6. www.datasheetarchive.com
7. www.ti.com

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ELECTRONICS & COMMUNICATION ENGINEERING

1. COMMON EMITTER AMPLIFIER

1. Design a COMMON - EMITTER amplifier for given specifications.

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 1

Fig. 1 Common Emitter Amplifier circuit diagram

6) The voltage across R2 is

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 2

7) S = (1+ β) / (1+ βRE/(RE+RB))

Standard values of Resistors and capacitors R1_____, R2=____ RC=_____, RE=____,

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 3

Frequency Output Voltage(Vo) Gain in decibels

Input AC voltage, VI= _____ mV (peak-peak)

Output Voltage (Vo) Gain in decibels

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 4

Maximum gain (Av) =

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 5

1. What are the characteristics of C.E amplifier?

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 6

2. COMMON COLLECTOR AMPLIFIER

1. To design a COMMON – COLLECTOR amplifier for given specifications.

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 7

1. High input impedance

Fig. 1 Common Collector Amplifier Circuit Diagram

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 8

3. S = (1+ β) / (1+ βRE/(RE+RB))

1. Connect the circuit as per the circuit diagram Fig. 1.

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 9

Frequency Output Voltage(Vo) Gain in decibels

Input AC voltage, VI= ______ V (peak-peak)

Output Voltage (Vo) Gain in decibels

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 10

Maximum gain (Av)

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 11

3. TWO STAGE RC COUPLED AMPLIFIER

2. Simulate the designed amplifier.

3. Develop the hard ware for designed amplifier.

4. Compare practical results with theoretical results.

S.No Name of The Specifications Qty

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 12

Fig. 1 Two Stage Common Emitter Amplifier Circuit Diagram.

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 13

6) S=1+ R1R2/ (R1+R2) RE -----------------(b)

2. Apply supply voltage, Vcc= 12V.

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Output voltage Vo Gain in decibels

Output voltage Vo Gain in decibels

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 15

1. Connections must be done very carefully.

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 16

2. Simulate the designed oscillator.

and R 2 -C 2 ) and a voltage divider (R 3 -R 4 ). The lead–lag network provides positive

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 17

Fig. 1 Wienbridge Oscillator Circuit Diagram

1) Applying Kirchoff’s voltage law to the collector circuit in the diagram

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 18

1. Connections are made as per the circuit diagram.

S.No Amplitude(V) (Peak-Peak) Frequency(KHZ) % Error

S.No Amplitude(V) Peak- Frequency(KHZ) % Error

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 19

2. What are BHARKHAUSEN conditions of oscillators?

3. Which type of feedback is used in wein bridge oscillator?

4. What is the application of wein bridge oscillator?

ELECTRONIC CIRCUITS AND PULSE AND DIGITAL CIRCUITS 20

Standard values of Resistors and capacitors R1___, R2= RC=_, RE=__,