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A CONTROL ARCHITECTURE PROPOSAL FOR SIRIUS BEAMLINES
M. A. L. Moraes†, H. D. Almeida, R. M. Caliari, R. R. Geraldes, G. B. Z. L. Moreno, J. R. Piton,
L. Sanfelici, LNLS, Campinas, Brazil
† marcelo.moraes@lnls.br tion for latency reduction, but the FPGA module for PXI
THPHA215
Hardware Technology 1947
16th Int. Conf. on Accelerator and Large Experimental Control Systems ICALEPCS2017, Barcelona, Spain JACoW Publishing
ISBN: 978-3-95450-193-9 doi:10.18429/JACoW-ICALEPCS2017-THPHA215
Content from this work may be used under the terms of the CC BY 3.0 licence (© 2017). Any distribution of this work must maintain attribution to the author(s), title of the work, publisher, and DOI.
is expensive enough to be considered feasible only for servo axes at significantly lower cost. Indeed, simple
specific applications, not as a standard platform. Without instruments, based on average-performance drivers and
FPGA, latency is limited by the RT OS. Finally, since the actuators, controlled via PID, notch and low-pass filters
general-purpose Linux OS (non-RT) can’t be changed, [14], make most of the motion applications. Galil 4183
there are limitations about reusing IOCs (input/output controller not only offers such functionalities [15] at a
controllers), due to incompatibilities as, for instance, the reasonable cost, but it has also been satisfactory used for
version of the compiler or the system architecture (x86). some years. Therefore, it will be kept as standard motion
Facing these points, HYPPIE is insufficient for ad- controller. In addition to it, a few controllers that may be
vanced applications. Thus, keeping it for general-purpose linked with specific third-party motors and actuators will
systems would lead to a more heterogeneous standard also be inevitably present in a smaller amount. Finally,
architecture. Although, NI PXI is a powerful platform that customized controller implementations shall be catego-
can achieve Sirius’ requirements with FPGA modules, it rized as advanced control solutions, due to requirements
would demand high investments and, even the earlier of plant identification, bandwidth and fast I/O.
versions, could not run Linux natively [11]. Hence, the
new standard control system needs another solution. cRIO-Linux Project
The motivation for the HYPPIE project was the integra- cRIO-Linux is a multi-layer solution for integrating
tion of robust hardware and Linux environment. In paral- cRIO I/O to EPICS, minimizing latency and maximizing
lel with this implementation with the PXI at LNLS, NI throughput. The first phase of the project consists in de-
announced in 2013 a completely redesigned cRIO with fining the complete architecture. The second phase is the
built-in Linux RT OS [11]. This is a very convenient op- implementation of read/write hardware features that go
tion because cRIO is a rugged platform designed for in- from basic to advanced implementations.
dustry and widely used around the world. With a built-in The proposed features to cover all general-purpose con-
Linux RT, it is a robust base for integrating hardware and trol systems that use the cRIO platform are:
EPICS. Table 1 presents a comparison between HYPPIE 1. Digital read/write (arrays, FIFO);
and cRIO, with the purpose of emphasizing the features 2. Analog read/write (arrays, FIFO);
of interest for the new standard definition. Despite the 3. Scaler;
unfairness of comparing recent technology like the TSN 4. Encoder in;
(Time Sensitive Network) [12] with a 5-year-old system, 5. Stepper motor out;
deterministic network is an interesting feature for ad- 6. RS232/RS485 2-wires/RS485 4-wires Serial Port;
vanced applications. 7. EtherCAT devices;
Table 1: Comparison between HYPPIE and cRIO 8. Triggering.
Feature PXI AND cRIO1 Architecture Figure 1 presents the architecture of a
HYPPIE general-purpose control system on cRIO platform. Con-
sidering that this project consists in hardware migration, it
RT OS Phar Lap NI Linux RT [11]
is possible to reuse the existing GUI structure. The high-
ETC [11]
level layers are based in Python, whose implementation is
that cannot
detailed in [16]. Although the architecture is represented
be upgraded
from hardware to GUI, the object of study of this paper
EPICS Additional Compatible with ends in the EPICS layer.
Virtual Ma- native RT OS cRIO-Linux Project is composed by four layers: FPGA,
chine with Real-time, Cpp libraries and Device support (green
non-RT OS blocks). In cRIO architecture, every hardware is accessed
TSN [12] - Compatible through FPGA, and there are tools for access to FPGA
and Real-Time applications, as well. LabVIEW FPGA C
FPGA Expensive In-built
API [17] is a solution for direct access to FPGA via C
modules
code, whereas LabVIEW Real-Time applications can
Scalability Limited by Scalable interact with external applications via POSIX IPC [18].
virtualization This way, all requirements for cRIO-Linux Libraries
technology (Libs) layer development are satisfied. The chosen lan-
Hot swappable No Yes guage is Cpp, for object-oriented implementation.
[13] Development Status The first phase is finished and
Unlike the relevant effort of creating a standard control the second phase is in progress, having the digital read
system by migrating HYPPIE tasks to cRIO, restricting array already successfully implemented in all layers. The
the options for motion controllers might be unwise or development has been done by feature, which means that,
unfeasible. General-purpose motion controllers can offer according to the architecture in Figure 1, the architecture
a satisfactory solution for a large volume of stepper and has been vertically iterated for each feature until conclu-
1
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THPHA215
1948 Hardware Technology
16th Int. Conf. on Accelerator and Large Experimental Control Systems ICALEPCS2017, Barcelona, Spain JACoW Publishing
ISBN: 978-3-95450-193-9 doi:10.18429/JACoW-ICALEPCS2017-THPHA215
Content from this work may be used under the terms of the CC BY 3.0 licence (© 2017). Any distribution of this work must maintain attribution to the author(s), title of the work, publisher, and DOI.
achieved via deterministic networks like TSN – built-in
for some cRIO models. Hence, the cRIO flexibility makes
it eligible as the standard platform for hosting also the
advanced applications.
HD-DCM
Figure 2 shows the HD-DCM and its dynamic concept,
aiming at a higher stability performance [14]. The sche-
matic shows the first set of crystals attached to the Me-
trology Frame (MeF1), and the second set of crystals in
the Short-Stroke (ShS). The motion system that controls
the Bragg angle, parallelism and gap is composed by the
actuators and sensors presented in
Table 2. The Goniometer Frame (GoF) motion defines
the Bragg angle, the Long-Stroke (LoS) performs coarse
gap movement and the ShS guarantees fine gap and paral-
lelism.
THPHA215
1950 Hardware Technology
16th Int. Conf. on Accelerator and Large Experimental Control Systems ICALEPCS2017, Barcelona, Spain JACoW Publishing
ISBN: 978-3-95450-193-9 doi:10.18429/JACoW-ICALEPCS2017-THPHA215
Content from this work may be used under the terms of the CC BY 3.0 licence (© 2017). Any distribution of this work must maintain attribution to the author(s), title of the work, publisher, and DOI.
Conveniently enough, cRIO offers a set of motion con- because they are not tied to a specific commercial control-
trol solutions (NI SoftMotion [28], dedicated 3rd party ler.
I/O modules) that covers trajectory generation, interpola-
tion, velocity calculation, among other features for con-
trolling stepper and servo motors. SoftMotion Service ACKNOWLEDGEMENTS
manages both FPGA and RT layers and will be used as The authors would like to gratefully acknowledge the
the standard solution for customizable controllers. funding by the Brazilian Ministry of Science, Technology,
Development Status SoftMotion configuration is in Innovation and Communication and the contribution of
progress, whereas the I/O drivers and the ShS control the LNLS team, the National Instruments team, the MI-
loop with kinematics transformations are already finished. Partners team, and those of the synchrotron community
Thanks to the FPGA implementation, the ShS controller who directly or indirectly built the path to this develop-
could reach 1 MHz. The analog output module (NI 9264), ment.
however, limits the rate to 25 kHz. Therefore, the hard-
ware limitation target was achieved. REFERENCES
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THPHA215
Hardware Technology 1951
16th Int. Conf. on Accelerator and Large Experimental Control Systems ICALEPCS2017, Barcelona, Spain JACoW Publishing
ISBN: 978-3-95450-193-9 doi:10.18429/JACoW-ICALEPCS2017-THPHA215
Content from this work may be used under the terms of the CC BY 3.0 licence (© 2017). Any distribution of this work must maintain attribution to the author(s), title of the work, publisher, and DOI.
THPHA215
1952 Hardware Technology