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Logic states can be referred to as: 1 and 0; True and False; On and Off. All are equivalent to each other,
but we tend to use 1 and 0 in this strand.
There are two representation conventions: positive logic and negative logic.
In positive logic, 5V is logic 1 and 0V is logic 0. In negative logic, the inverse is true; 5V is logic 0 and
0V is logic 1. In this strand, we tend to use the positive logic convention. Voltages are in respect to earth.
High is considered to be logic 1 and low is logic 0.
Simple Gates
AND
out = A.B
A B out
L L L
L HL
HL L
HHH
OR
out = A + B
A B out
L L L
L HH
HL H
HHH
NOT
out = A
A out
L H
HL
Three-input gates
Three input gates do exist, they are basically two 2-input gates chained together.
NAND
out = A.B
A B out
L L H
L HH
HL H
HHL
NOR
A B out
L L H
L HL
HL L
HHL
XOR
out = AB + AB
A B out
L L L
L HH
HL H
HHL
Drawing Conventions
Normally, inputs are on the top and left of a piece of paper, and outputs are on the bottom and right.
A combinatorial circuit is one whose outputs are entirely dependent on the current state of the inputs. All
gates also act as buffers.
NOT
1=0
0=1
AND
0.0 = 0
0.1 = 0
1.0 = 0
1.1 = 1
OR
0+0=0
0+1=1
1+0=1
1+1=1
AND
A.0 = 0
A.1 = A
OR
A+0=A
A+1=1
NOT
A.A = 0
A+A=1
Commutation
A+B=B+A
A.B = B.A
Association
A + B + C = A + (B + C) = (A + B) + C
A.B.C = A.(B.C) = (A.B).C
de Morgan's Theorem
A + B = A.B
A.B = A + B
(A + B).(C + D)
= A.C + B.C + B.D + A.D
A.B + A.B
= A.(B + B)
=A
A.(A + B)
= A + A.B
= A.(1 + B)
=A
XOR
C = A.B + A.B
De Morgan's Law
Y.Z = Y + Z
Terminology
Product Term
A single variable or logical product of several variables. E.g., A, X, A.B.C. This is basically the AND
function. Note that A.B.C is not a product term.
Sum Term
Sum term is the single variable or the logical sum of several variables. The variables may be in true, or
complemented, form. E.g., A + B + C, etc... This is the OR function. Note that here also, A + B + C is not
a sum term.
Sum-of-products
This is product terms added together., e.g., A.B.C + Q.R.S + A.Q. Note that A.B.C + X.Y.C is not a valid
sum-of-products form.
Product-of-sums
This is the sum of several terms multiplied together, e.g., (A + B + C).(X + H + J). Note that (A + B +
C).(C + D) is not in product of sums form.
Canonical Forms
If each variable is in the true of complimentary form and it appears in each term of the sub-products, then
it is known as the canonical sum-of-products and each term is a minterm.
This similar to the first canonical form, but each variable in a product-of-sums form and each term
becomes a maxterm.
Minterm
A minterm is a product term which contains each variable in complimentary form. When used in the
canonical sum-of-products, the minterm represent an input condition that causes the output to be 1.
Maxterm
A sum term which contains each variable in complimentary form. When used in the canonical product-of-
sums the maxterm represents an input condition which causes the function to be 0.
Karnaugh Map
This is based on boolean algebra and is another method of minimisation.
C\AB 00 01 11 10
0 0 0 0 0
1 1 0 1 0
The order of bits on the top row is important. Only one bit can change between columns.
This is essentially a re-arranged truth table. Variables which appear together horizontally or vertically are
logically adjacent.
If there are 2n maxterms, n is the number of rows that can be looped. The member of grouped minterms
must be a power of 2.
Five and six variable karnaugh maps can occur - these are represented in 3 dimensions.
CD\AB 00 01 11 10
00 1 1
01
11
10 1 1
CD\AB 00 01 11 10
00 1 1
01
11
10 1 1 1
E is on top of E.
The same applies to a six-variable Karnaugh Map, which looks like this:
Maxterms can be looped up in a similar way to minterms, but are inverted.
Prime Implicants
These are the biggest adjacent terms which can be looped together. Single isolated implicants are also
prime implicants.
Quine-McCluskey Minimisation
1. Find all logically adjacent minterms to produce implicants - Tabulate all the minterms from
the expressions and re-order them so that all the minterms without any 1's are together, the
minterms with one 1 are together, etc. Then you need to write down pairs of logically
adjacent minterms, these will give you the implicants. Replace the bits that make them
logically adjacent with '-'
2. Find all logically adjacent implicants to produce prime implicants. Repeat for all possible
prime implicants - Find all logically adjacent implicants from the last step using the same
process. Repeat until you have all adjacancies.
3. Use a prime implicant table to determine essential prime implicants - From the previous
step, any implicants that can not be reduced any further are prime.
4. Select the minimum number of additional prime implicants to produce minimum expression
- Plot a table of the prime implicants against the original minterms. Columns that only have
one tick are essential.
5. Choose best expression based on implementation issues
Quine-McCluskey is algorithmic. It is tedious and error prone when done by hand. However, it can be
automated, and is guaranteed to find the set of minimal solutions. It works for maxterms as well as
minterms.
Hardware Realisation
IC realisation requires minimising the number of gates. PCB realisation involves minimising the number
of packages (therefore minimising the number of gates and gate types).
In negative logic, an AND gate is an OR gate and an OR is an AND. When a NAND gate has positive
logic inputs and negative logic outputs, it behaves like an AND. Similarly, is an OR gate has negative
logic on inputs and positive logic on outputs, it behaves like an OR.
However, this increases gate delay, but does tend to lead to fewer gates or packages being used. It can
also make it less obvious what a design is for.
Don't Cares
Don't cares are input conditions that will never occur under normal operations and are marked as output
X. You can treat a don't care as either a max-term or a min-term, whichever is more convenient for you.
So, for example, you can loop a don't care with minterms or maxterms to create a more minimised
expression. Don't cares by themselves are not looped however.
You need to take care, however, incase a don't care term does occur (for example during the initialisation
of flip-flops, etc).
Design Considerations
Which hardware implementation to use? PCB, IC, PLD? Which device
technology? TTL, CMOS transistors, ECL? Hardware environment? Temperature, radiation, pressure,
vibrations, etc...
You need to minimise gates and packages, the gate layers (circuit delay), the number of interconnects
between gates and between packages, maintenance costs, power consumption, weight, design costs,
production costs, hazardous behaviour.
Design Steps
Check each stem!
Electrical Considerations
Power Supply
Gates are supplied by power from a power supply via a power rail known as Vcc and ground. This power
rail is implied and not actually show on circuit diagrams. In a dual-inline package, powering the package
automatically powers all the gates.
Normally, the power supply is 5 V. For standard specification gates, the allowed variances are ±0.25 V
and for military this is ±0.5 V. There is also an absolute voltage rating, above which the gate burns out.
This is approximately 7 V.
Output is high when Q1 is on and Q2 is off, inversely, output is low when Q1 is off and Q2 is on. During
transitions, Q1 and Q2 both conduct, but current is limited by R1, this causes a "spike" to be seen on the
supply rail and is known as electrical noise. The spike is caused by the sudden increase and then decrease
in current required by the gate. Capacitors are evenly spread around a PCB according to some in-house
rule of thumb. These "decoupling" capacitors are connected between supply rail and earth, supplying
instantaneous current which the transistors need.
Fan-out
When the interconnecting node is low, current flows out of the second gate into the first one. The inverse
happens when the interconnect is high.
Unused Inputs
NAND and NOR gates can be used as inverters. 4-input gates can be used by 2 variables only, etc...
However, TTL inputs float high and CMOS floats low. For a TTL 4-input AND: ABC1 = ABC, but for a
4-input OR: A + B + C + 1 = 1, which is a tautology.
Unused inputs are susceptible to electrical noise and may slow down gate operation.
This is two different ways to make a 3-input gate work with two inputs (generating logic 0). The bottom
method is preferred.
Output Input
Logic 1 2.4-5.0 V 2.0-5.0 V
Logic 0 0.0-0.4 V 0.0-0.8 V
Levels of Integration
SSI - small scale integration. 1 - 20 gates, up to 100 transistors, few gates and flip flops.
LSI - large scale integration. 200 - 200,000 gates, PLDs and early microprocessors.
VLSI - very large scale integration. 500,000+ gates, 32-bit microprocessors, etc...
Propagation Delay
The propagation delay of a gate is the time it takes for the gate output to change in response to a change
on its input. High-to-low delays may differ from low-high-delays.
tPHL is the time between specified reference points on the input and output voltage waveforms with the
output changing from the defined high level to the defined low level.
tPLH is time between specified reference points on the input and output voltage waveforms with the output
changing from the defined low level to the defined high level.
A static hazard is where there's a change from minterm to minterm (static-1) or maxterm to maxterm
(static-0) and a "blip" occurs. A dynamic hazard is where there's a hazard in a change between max- and
min-terms.
Buffers help mask propagation delays and can decrease hazards. This, however, isn't the best solution to
hazards. Waveform analysis is a better indicator for predicting hazards, but it may not be accurate in
reality.
System Organisation
A bus is a set of wires designed to transfer all bits of a word from a source to a destination.
The value of R is calculated according to a formula specified by the manufacturer. The value must be re-
calculated every time an input or output is added or removed.
Wired-AND Gate
A tristate device can sink and drive large currents than TTL.
Bus Driver/Receiver
Of all the gates connected to a bus wire, only one should drive at once. All gates can be in a high
impendence state, however.
Representation
Characteristic Impedance
Z0 = v / i
Z0
PCB tracks 50 - 150 Ω
Twisted pair 100 - 120 Ω
Coaxial cable 50 - 75 Ω
A demultiplexer does the opposite - it puts an input onto the addressed output.
PROMs are general purpose decoders leading to an ORing stage. Only the ORing stage is programmable.
PROMs are available in different varieties, such as:
ROMs are programmed by the manufacturer, and are only cost-effective if manufactured in
large quantities.
PROMs are developed in a lab. Once the fuses are blown, they can't be reinstated. They are
programmed by electrical pulses up the output.
EPROMs, this are like PROMs, but UV light resets the fuses.
EEPROMs, like EPROM, but electrical pulses are used to reinstate the fuses, not UV light.
For PLDs, instead of a conventional notation, crosses are put where wires intersect to indicate fuses being
intact.
Some PALs have tristate buffers for bus driving (the tristate selects whether the PAL is an driving or
receiving), hence the PAL can be used for inputs and outputs.
PLDs have extra security to allow the device to be checked and allows the fuse arrays to be read. Some
PLDs have security fuses to stop the devices being read.