1
Clock and Data Recovery Circuits
Abhishek Shukla (Entry Number: 2012EE20316)
 data with the minimum possible errors. In other words, the Bit
Abstract—The receivers which receive data over
communication channels need a Clock and Data Recovery (CDR)
circuit to reconstruct the clock and perform synchronous
operations on the incoming bitstream. CDRs may be based on
Phase Locked Loop (PLL) designs or Delay Locked Loop (DLL)
designs. PLL CDRs output signals with higher accuracy and
lower Bit Error Rate (BER). DLL CDRs have the ability to lock
to the data within a few clock cycles. They manifest high stability
and are extremely fast. However, the output from a DLL CDR is
fraught with jitter. Thus, the choice between a PLL and a DLL
design is made based on the application requirements. Efforts are
being made to combine the best features of the PLL and the DLL
designs into a hybrid CDR which would exhibit fast acquisition
time (associated with DLL design) as well as high accuracy
(associated with PLL design).
Index Terms—Clock and Data Recovery (CDR), Bit Error
Rate (BER), Phase Detector (PD), Phase Locked Loop (PLL),
Delay Locked Loop (DLL), phase offset trajectory, hybrid CDR,
Signal to Noise Ratio (SNR)
I. INTRODUCTION
T ECHNOLOGY UPSCALING in modern times has
resulted in a drastic increase in the bandwidths available
for communication channels. Most of the high performance
computer systems today handle data transfers at the rates of
several Gb/s. Such high-speed links generally have two
components – a transmitter and a receiver. As the names
indicate, the transmitter is assigned the task of generating and
transmitting a signal over a communication channel. The
receiver is located at the other end of the channel and has to
extract the transmitted signal from the received bit-stream.
This is where Clock and Data Recovery (CDR) becomes a
necessity.
The data received by the receivers is both asynchronous as
well as jittery. In order to perform synchronous operations on
the data, it is necessary to have a clock for the timing
information. Transmitting the clock along with the data is
impractical and unviable. The CDR circuit is therefore needed
to generate a clock which can remove the noise from the
incoming data.
. Therefore, extra coding is needed to account for the high bit
II. CDR BASICS
The objective of the CDR is to reconstruct the transmitted
Abhishek Shukla is currently an undergraduate student in the Electrical
Engineering Department, Indian Institute of Technology, Delhi. (e-mail:
ee2120316@iitd.ac.in)
Error Rate (BER) needs to be reduced to as low a value as
possible. For this condition to be achieved, the data must be
sampled at those points where the noise is very low compared
to the signal. Signal to Noise Ratio (SNR) can be recorded to
determine the location of such points. The Desired Sample
Points coincide with the peaks in the plot of SNR. The BER
decreases rapidly with an increase in SNR.
1 𝑆𝑁𝑅
𝐵𝐸𝑅 = ∗ 𝑒𝑟𝑓𝑐 ( )
2 2√2
A. Conditions to be met by the recovered Clock
The clock generated by the CDR circuit must meet the
following prerequisites:
 The difference between the frequency of the
regenerated clock and the data rate must be
negligible.
 The jitter exhibited by the reconstructed clock must
be as low as possible.
 The recovered clock must be such that allowances
are made for time uncertainty and noise. Optimally,
the data must be tested at points far away from the
data transitions (as close to the Desired Sample
Points as possible).
B. General Designs
The solutions for a CDR circuit can be either Phase Locked
Loop (PLL) or Delay Locked Loop (DLL).
PLL designs make use of narrow band filters to diminish
noise levels in the input signal. Since narrow band filters are
used, the acquisition time is invariably high (0.5-1 µs).
However, PLL designs usually require less coding because of
the low jitter. At the same time, the low jitter guarantees a
correspondingly low Bit Error Rate (BER).
DLL designs, on the other hand, can reconstruct the clock
and recover the data extremely fast with the aid of phase
selection technique. Nevertheless, the jitter accompanying the
recovered data is high, thereby resulting in a high BER.
errors.
The choice between DLL and PLL depends on the use to
which the CDR circuit would be put. For faster acquisition,
DLL is the obvious choice as it can start transferring data
almost as soon as the received signal is fed to it. For longer
connection times, PLL is the more suitable alternative because
of its higher efficiency. Also, the less coding overhead of PLL

more than makes up for the slower acquisition (0.5-1 µs) in
the longer run.
III. COMPLICATIONS IN CDR DESIGN
The major factor that complicates the design of a CDR
circuit is the continuous movement of the data transitions with
respect to a stationary time reference. This movement can be
traced back to two causes:
1. Phase Offset Trajectory
2. Jitter
A. Phase Offset Trajectory
The transmitter and the receiver have independent clock
sources that may not have identical frequencies. This
difference in the frequencies produces an offset which is a
function of time. This offset needs to be determined accurately
in order to serve the purposes of the CDR circuitry.
Figure 3.1: Systems exhibiting a frequency offset [1]
The Phase Offset Trajectory can be found out by plotting
the difference between the phases of the data transitions and
the clock fed to the receiver. The systems are said to be
mesochronous when the average frequency offset is zero. If
the frequency offset is constant with respect to time, the
systems are said to be plesiochronous. For such systems, the
phase offset trajectory turns out to be linear with the slope of
the line equal to the magnitude of the offset in frequency.
Figure 3.2: Sample Phase Offset Trajectory [2]
Due to concerns over Electro-Magnetic Interference (EMI),
sophisticated clock designs have been inducted in the digital
circuits. This has resulted in extremely complicated phase
offset trajectories. However, these trajectories can still be
2
predicted with considerable accuracy. Owing to this nature,
they are also referred to as Deterministic Phase Offset
Trajectories.
B. Jitter
There is an inherent uncertainty in the phase of clock edges
of the transmitter. This uncertainty or noise is referred to as
jitter. Jitter can be deterministic (DJ – Deterministic Jitter) or
random (RJ – Random Jitter).
DJ can be categorized on the basis of its source. Thus, we
have data dependent jitter (ISI – Inter-Symbol Interface), Duty
Cycle Distortion (DCD) and Non-Data Related jitter. The
major source of DJ is ISI. The sources of RJ are the
fundamental noise generations by both active as well as
passive devices.
Jitter need not be tracked because it is highly uncorrelated
and it is generally impossible to arrive at a jitter pattern.
Hence, the CDR circuit must tend to dispose of the jitter with
the help of requisite filters.
IV. PLL BASED ARCHITECTURE
The phase relationship between the incoming data
transitions and the clock of the receiver continuously changes.
Therefore, the CDR circuit needs to constantly change the
data-sampling time.
A. Components
To achieve its purposes, the PLL CDR needs three major
components:
 Phase Detector (PD) – to determine the phase
relationship between the data transitions and the
clock of the receiver.
 Low Pass Filter (LPF) – to remove the noise which
may be present in the output of the PD.
 Voltage Controlled Oscillator (VCO) – to adjust
the phase of the clock of the receiver so that the
incoming data is sampled at the points with the
highest Signal to Noise Ratio (SNR).
Figure 4.1: Basic PLL design [3]
B. Operation
In the operational condition, the Phase Detector (PD)
outputs a signal which is proportional to the phase difference
between the incoming signal x(t) and the outgoing signal y(t).
The LPF filters out the high frequencies, thereby ensuring that
the dc value of the PD output influences the frequency of the
VCO.
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V. DLL BASED ARCHITECTURE

C. Transfer Function There are areas where a complete and accurate re-synthesis
of clock may not be necessary. For such fields, DLL based
On assuming a linear model of the PLL, the PD is a
CDR circuits provide a viable alternative because of their fast
subtractor with its output amplified by Kpd. The transfer
1 acquisition time, higher stability levels and little phase error.
function of LPF is (ω denotes the bandwidth). The
1+𝑠/𝜔
𝐾𝑣𝑐𝑜 A. Components
transfer function of the VCO is . The open loop transfer
𝑠 A typical DLL circuit has the following major components:
function of the PLL is given by:  Phase Detector (PD) – to ascertain the phase
relationship between the input data transitions and
1 𝐾𝑣𝑐𝑜
𝐻(𝑠)𝑜𝑝𝑒𝑛 = 𝐾𝑝𝑑 . . the clock of the receiver.
1 + 𝑠/𝜔 𝑠  Charge Pump (CP)
 Low Pass Filter (LPF) – to remove the noise which
The open-loop transfer function has two poles – one at s=-ω
may be present in the output of the PD.
and the other at s=0. The PLL designs which contain a pole at
 Voltage Controlled Delay Line (VCDL) – to
the origin are referred to as type I PLLs.
provide several clock phases with suitable delays.

Figure 4.2: Linear model of PLL circuit [4] Figure 5.1: Basic DLL design [5]

We can arrive at the closed loop transfer function from the B. Operation
open-loop transfer function. In the operational mode, the PD and the LPF have functions
similar to those they had in the PLL design. The VCDL is
Φ𝑜𝑢𝑡 (𝑠) 𝐻(𝑠)𝑜𝑝𝑒𝑛
𝐻(𝑠) = = [∵ 𝐹𝑒𝑒𝑑𝑏𝑎𝑐𝑘 𝐹𝑎𝑐𝑡𝑜𝑟 = 1] used to provide a delay in the clock of the receiver in order to
Φ𝑖𝑛 (𝑠) 1 + 𝐻(𝑠)𝑜𝑝𝑒𝑛
minimize the phase difference between the input clock and the
recovered clock. This delay is controlled by means of the
𝐾𝑝𝑑 . 𝐾𝑣𝑐𝑜 𝜔𝑛 2 negative feedback in the loop which integrates the phase error
𝐻(𝑠) = =
𝑠2 𝑠2 + 2𝜉𝜔𝑛 𝑠 + 𝜔𝑛 2 between the two clocks.
+ 𝑠 + 𝐾𝑝𝑑 . 𝐾𝑣𝑐𝑜
𝜔 The VCDL generates multiple clock phases at a frequency
matched closely by the incoming data rate. The DLL CDR
where 𝜔𝑛 = √𝜔. 𝐾𝑝𝑑 . 𝐾𝑣𝑐𝑜 selects the clock which is aligned most closely with the input
bitstream. This technique (referred to as phase selection
1 𝜔 technique) hugely augments the acquisition time of the CDR.
𝜉 = 2 √𝐾 However, the output is accompanied with a high jitter due to
𝑝𝑑 .𝐾𝑣𝑐𝑜
the selection of multiple phases.

Comparing the closed-loop transfer function with the

general form, we observe that 𝜔𝑛 is the natural frequency of C. Transfer Function
the circuit and 𝜉 is the damping factor. For an optimum
frequency response, the circuit is designed in such a way that
𝜉 ≥ 0.5. The acquisition time of the PLL circuit decreases
with increasing value of 𝜉𝜔𝑛 .

D. Applications
Owing to the low jitter levels in the clock reconstructed by a Figure 5.2: Linear model of DLL [6]
PLL CDR, it is mostly used in applications where jitter cannot
be exceeded beyond a specified upper limit. The open-loop transfer function of the linear model of the
DLL design is given by:
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𝐼𝑝 The PLL portion of a hybrid CDR is composed of a Phase

𝐻(𝑠)𝑜𝑝𝑒𝑛 = .𝐾
2𝜋𝑠𝐶𝑝 𝑣𝑐𝑑𝑙 Detector (PD), a Low Pass Filter (LPF) and an External
Voltage Controlled Crystal Oscillator (VCXO). The DLL
The feedback factor of the circuit is 1. Therefore, the portion of a hybrid CDR consists of a PD, an LPF and a
closed-loop transfer function of the circuit is given by: Voltage Controlled Phase Shifter (VCPS). Thus, there are two
loops in the hybrid CDR – one Phase Locked Loop and one
Delay Locked Loop. The two loops function in unison to
Φ𝑜𝑢𝑡 (𝑠) 𝐻(𝑠)𝑜𝑝𝑒𝑛
𝐻(𝑠) = = reduce the phase difference of the recovered clock to zero.
Φ𝑖𝑛 (𝑠) 1 + 𝐻(𝑠)𝑜𝑝𝑒𝑛

1
𝐻(𝑠) = 𝑠
1+ 𝐼 .𝐾
𝑝 𝑣𝑐𝑑𝑙
2𝜋𝐶𝑝

The stability and acquisition of a DLL circuit is better than

those of a corresponding PLL circuit because its response has
a first-order form. DLL circuits are less susceptible to noise as
compared to PLL circuits. The noise waveforms vanish
towards the end of delay lines whereas they are reproduced in
oscillators (thereby enhancing corruption levels in the output
of a PLL circuit).

D. Applications
Owing to the extremely high acquisition time demonstrated
by a DLL CDR, it is mostly used in applications where there is
a fast switching between the communication channels and the
connection times are relatively short.
VI. COMBINED DLL AND PLL CDR
The acquisition time of a PLL CDR cannot be increased
beyond a certain limit because the PLL records the phase
difference between the reconstructed and the input clocks and
uses these records to evaluate the frequency difference. The
output of a DLL CDR is ridden with an inherent jitter which
results in greater Bit Error Rate (BER). A DLL CDR requires
a reference clock as an input.
A combined model of DLL/PLL CDR is being worked upon
which combines the best features of these two designs. Such a
CDR is referred to as a hybrid CDR or a DLL/PLL CDR. It
aims to provide the low jitter and higher efficiency of a PLL
CDR along with the rapid acquisition of a DLL CDR. The
hybrid CDR, unlike the DLL CDR, does not require a
reference clock as an input.
Figure 6.1: Block Diagram of a hybrid CDR [7]
REFERENCES
[1] Hae-Chang Lee, “An Estimation Approach to Clock and Data
Recovery”, Ph.D. dissertation, Dept. Elect. Eng., Stanford Univ., USA,
2006.
[2] Ruiyuan Zhang, “Clock and Data Recovery Circuits”, Ph.D. dissertation,
Dept. Elect. Eng., Washington Univ., Washington DC, USA, 2004.
[3] Yung Sern Tan, Kiat Seng Yeo, Chirn Chye Boon and Manh Anh Do,
“A Dual-Loop Clock and Data Recovery Circuit With Compact
Quarter-Rate CMOS Linear Phase Detector,” published in IEEE
journal, 2011.
[4] Pavan Kumar Hanumolu, Min Gyu Kim, Gu-Yeon Wei and Un-ku
Moon, “A 1.6Gbps Digital Clock and Data Recovery Circuit,”
presented in IEEE-CICC, 2006.
[5] Armin Tajalli, Paul Muller and Yusuf Leblebici, “A Power-Efficient
Clock and Data Recovery Circuit for Optical Data Communication,”
published in IEEE journal of Solid-State Circuits, 2007.
[6] Ruiyuan Zhang, “Clock and Data Recovery Circuits”, Ph.D. dissertation,
Dept. Elect. Eng., Washington Univ., Washington DC, USA, 2004.
[7] Hae-Chang Lee, “An Estimation Approach to Clock and Data
Recovery” Ph.D. dissertation, Dept. Elect. Eng., Stanford Univ., USA,
2006.