1

COMPILER DIRECTIVES
Copyright 2002, Michael D. Ciletti

A compiler directive may be used to control the compilation of a Verilog description.

The grave accent mark, `, denotes a compiler directive. A directive is effective from the
point at which it is declared to the point at which another directive overrides it, even
across file boundaries. Compiler directives may appear anywhere in the source
description, but it is recommended that they appear outside a module declaration. This
appendix presents those directives that are part of IEEE-1364. Other directives may
also be used, depending on the vendor.

`celldefine and `endcelldefine

The `celldefine and `endcelldefine directives mark a module as a cell for use with PLI in
other applications.

`defaultnettype
The `defaultnettype directive allows the user to override the ordinary default type (wire)
of implicitly declared nets. It must be used outside a module. It specifies the default type
of all nets that are declared in modules that are declared after the directive.

Syntax: default_nettype_compiler_directive ::= `default_nettype net_type

net_type ::= wire | tri | tri0 | wand | triand | tri1 | wor | trior | trireg

`define and `undef

The `define directive defines a text macro for substitution in the source code. For
example, a state code of 3'b010 can be replaced by the following directive:

`define wait_state 3'b010

Notice that the directive and the text macro are separated by only white space, and the
line declaring the text macro is not terminated by a semicolon. The `undef directive
undefines a previously defined text macro.
 2

Syntax: text_macro_definition ::= `define text_macro_name macro_text

text_macro_name ::= text_macro_identifier [ (list_of_formal_arguments)]
list_of_formal_arguments ::= formal_argument_identifier { ,
formal_argument_identifier }

The syntax for using a text macro is given below.

Syntax: text_macro_usage ::= `text_macro_identifer [ ( list_of_actual_arguments)]

list_of_actual_arguments ::= actual_argument { ,actual_argument }
actual_argument ::= expression

The syntax for the `undef compiler directive is given below:

Syntax: undefined_compiler_directive ::= `undef text_macro_name

`ifdef, `else, `endif

These compiler directives conditionally include lines of a Verilog source description in a
compilation. The `ifdef directive is used with a variable name. The compiler checks
whether the variable named is defined (by a previous `define directive). If so, the lines of
code that follow the directive are included in the compilation. If the variable is not
defined, and if the `else directive exists, the lines of code that follow the `else directive
are compiled. The `endif directive establishes the boundary of the code that is
conditionally compiled. This group of directives affords versatility to a description. For
example, the compilation may select between different implementations of the same
functionality, select between different delay information, and select different stimulus for
a simulation.

Example: The directives below check whether the DISABLE_TIMESCALES variable is

defined. If it not defined, the `timescale directive is compiled.

`ifdef DISABLE_TIMESCALES
`else `timescale 1 ns / 10 ps
 3

Example: module or_gates (y_out, x1_in, x2_in);

output y_out;
input x1_in, x2_in;

`ifdef BEHAVIORAL
y_out = x1_in | x2_in;
`else
or G1 (y_out, x1_in, x2_in);
endmodule

Syntax: conditional_compilation_directive ::=

`ifdef text_macro_name
first_group_of_lines
[ `else
second_group_of_lines
`endif ]

`include
The `include directive inserts the contents of a file into another file during compilation.

Syntax: include_compiler_directive ::= `include “filename”

`resetall
The `resetall directive sets all compiler directives to their default values.

`timescale
The `timescale directive specifies the time_unit and time_precision for measurement of
delay and time values in all modules that follow the directive until another `timescale
directive is read.

Syntax: timescale_directive ::= `timescale time_unit / time_precision

The units and precision associated with the directive are listed below:

Character Physical
 4

String Unit
s seconds
ms milliseconds
us microseconds
ns nanoseconds
ps picoseconds
fs femtoseconds

Example: The directive `timescale 10 ns / 10 ps specifies that time information is to be

interpreted in units of 10s of ns, to the accuracy of 10 ps. The minimum rising
delay value (3.213) for the instantiation of the nand primitive shown below will be
interpreted as 32.13 ns. If the timescale directive is `timescale 10ns / 1 ps the
maximum falling delay value (4.237) will be interpreted as 42.370 ns by a
simulator.

nand #(3.213: 3.225:3.643, 4.112:4.237:4.413) (y, x1, x2);

Also see the $timeformat system task.

`nounconnected_drive and `unconnected_drive

The `unconnected_drive and `nounconnected_drive directives cause all unconnected
input ports of modules between the directives to be pulled up or pulled down, depending
on the argument of the `unconnected_drive directive. The allowed arguments are pull0
and pull1.