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Starting guide HDL‐Designer for Electrical Engineering at Fontys
version wal, August 2012
Introduction
This guide will help you getting started with the software for the Digital Design course.
We will start with a check on the presence of the correct software on your local computer.
Subsequently there is a brief instruction for HDL‐designer.
IMPORTANT:
Windows 7 allows multiple users on the same system. The administration rights for installing or
removing software are given to the FIRST LOGIN person. So it is wise to RESTART THE COMPUTER
before to be sure that you have the required rights.
Inhoudsopgave
1. Checking the software on your computer ....................................................................................... 2
2. What to do if HDL‐Designer or Modelsim is not available or not functioning properly. ................ 4
2.1. Removing HDL Designer software Modelsim software........................................................... 4
2.2. (Re)Installing HDL Designer and Modelsim ............................................................................. 9
3. Using HDL‐designer ....................................................................................................................... 11
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1. Checking the software on your computer
a. Go to Start Æ Alle programma’s Æ Fontys
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b. DoubleClick on the Digital Design and your Digital Design folder under Fontys will look like the
following.
c. If it looks like above it is ok and you can start working with Hdl Designer or Modelsim
Note: Always start Modelsim from inside when using HDL designer
HDL‐designer and enclosed Modelsim should work properly.
Continue with chapter 3 with the guide for HDL‐designer.
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2. What to do if HDLDesigner or Modelsim is not available or not
functioning properly.
If you have problems with the HDL Designer software or the Modelsim software the best way to
proceed is to reinstall the software. However reinstalling does not work unless you FIRST REMOVE
the installed software.
2.1. Removing HDL Designer software Modelsim software
a. Go to Start Æ Configuratiescherm
b. Go to Categorie and select Kleine pictogrammen
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c. Your window now looks like this:
d. Go to the systeembeheer and DoubleClick on systeembeheer. You will get the following window:
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e. Select Application Virtualization Client
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f. DoubleClick on toepassingen, you will see all of the applications that have been installed (see
screenshot)
g. Delete the applications HDL Designer and the Modelsim by selecting the application and pressing
the right mouse button and then clicking on the Verwijderen
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After all of these actions your Digital Design folder under Fontys will look like the following (no
modelsim and HDL designer)
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2.2. (Re)Installing HDL Designer and Modelsim
a. Go To Configuratiescherm and select Aangekondigde progr. uitvoeren
b. Your screen should look like given below. Search for the application Digital Design and
DoubleClick on it.
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c. After this HDL‐designer and Modelsim are installed. Check by selecting Start Æ Alle programma’s
Æ Fontys ÆDigital Design.
Your window should look like the screenshot below.
Important note when using HDL‐designer on the Fontys PC’s:
It might be that there are other versions of HDL designer or Modelsim installed on your computer.
ALWAYS use the HDL‐designer in the Digital Design folder AND use Modelsim from INSIDE HDL‐
designer!!
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3. Using HDLdesigner
This chapter describes what to do when you installed the software and you are using HDL Designer
for the first time.
Note: If you already used HDL Designer, just double click on the projectfile and HDL Designer will
open the project. When you start a new project you just have to fill in the projectname and
the directory of the projectlocation is automatically generated.
Be sure to check that the project location is F:\Dig\my_project….
otherwise change it !! (see the note “IMPORTANT” on page 16).
a. Start HDL Designer from the menu
( Start Æ Alle programma’s Æ Fontys Æ Digital Design Æ HDL Designer )
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HDL Designer window after start ing the software the first time:
b. Click next
c. Click next, the window looks like depicted on the next page
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d. Select FPGA en Xilinx
e. Click next
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Notice in the window below that the path is set for using Modelsim from within HDL Designer !
f. Click next. Note that also the path for Xilinx (systhesis tool) is set!
g. Click next
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h. Click next
The next step is very important, please read the next page carefully !!!
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Your screen should now looks like the window below:
IMPORTANT
In this window you have to choose where the project is saved on the computer.
Notice that the default drive is C. You have to change the drive because once a project has been
created on C it cannot be copied anymore because you do not have administration rights.
If you don’t change the location and you saved it on drive C your project will be lost and you have
to start again from scratch!!
>>> For the Digital Design course it is required to work on memory stick
(mostly drive F)
Furthermore we require a certain directory structure for all your projects:
Root F
Dig
<projectname>
…….
<<<
i. Change C:\HDS\my_project1 to F:\Dig\my_project1
Note: Of course my_project1 can be any name and in future you can choose a name like
parity_generator or some other sensible name
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Your screen will now look like this:
j. Double check the Project Location is F, then click next.
k. Click next.
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l. No version management (default). Click Finish.
m. Select Create new design content
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n. Click ok.
o. Select Graphical View and Block Diagram
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p. Click next
q. Suppose we want to design a simple digital circuit with 2 inputs and 1 output called DIGCIR we fill
in DIGCIR as Design Unit Name
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r. Click next.
s. Now fill in A and B as inputs, and output F, all standard logic. The window should look like this:
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t. Now click Finish
Now we can start to make the block diagram for the digital circuit. Let us assume that are DIGCIR is a
simple AND‐gate. Of course this is a standard building block that is available in HDL Designer.
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u. Select Add Moduleware from the menu bar
v. Select Logic followed by N input AND
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w. Now drag the AND gate onto the Block Diagram
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x. Select the Add Signal button in the menu and try to make the connections from the inputs A and B
to the AND gate and connect the output to F.
y. Experiment a little bit to get straight signal lines and a nice looking block diagram.
The result should be something like the picture below.
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z. When the circuit is drawn we can generate the VHDL file (extension .vhd).
First save the Block Diagram.
Generate the VHDL‐file by pressing the menu button (see figure below).
The VHDL fiile contains the hardware description of the circuit and is used by Modelsim and Xilinx ISE
for simulation and synthesis. Your first Digital Circuit Design in HDL designer is ready now. When you
exit HDL‐designer the project is saved on disk.
After exiting HDL Designer check the files on drive F with My Computer. The directory structure
should look like this:
Root F
Dig
my_project1
My_project1_lib
My_project1.hdp hdl
<projectfile>
DIGCIR_struct.vhd
<VHDL file>
hds
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