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AppNote 10005

AppNote 10005 Designing with Xilinx’s Embedded Processors in HDL Designer By: Roy Clement Last Modified: 29

Designing with Xilinx’s Embedded Processors in HDL Designer

By: Roy Clement Last Modified: 29 August 2006

HDL Designer By: Roy Clement Last Modified: 29 August 2006 ©Copyright Mentor Graphics Corporatio n 1995-2006.

©Copyright Mentor Graphics Corporation 1995-2006. All rights reserved.

This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information.

Trademarks that appear in Mentor Graphics product publications that are not owned by Mentor Graphics are trademarks of their respective owners.

Contents

Click on the underlined object to go directly to the relevant section

1. Introduction to EDK flow

2. EDK Flow Step by Step Overview

2.1 Creating the XPS System Design

2.2 Defining the embedded processor design to be a sub-system

2.3 Creating a Custom Peripheral

3. Adding Xilinx Libraries to your HDS project (ISE and EDK libraries)

4. Simulation with either ModelSim or QuestaSim

5. Creating VHDL Configurations for Block RAMs (Simulation)

6. Precision Synthesis

7. Place and Route in ISE

Appendix A -

Using Coregen Components in HDL designer 2005.x

 

1. Installing New Temporary Coregen Plugins

2. Creating and Importing Coregen Components

3. Adding Xilinx Libraries to your HDS project

4. Synthesizing the Design with Precision

5. Using Constraint Files Synthesis and Layout

Appendix B -

Using Coregen Components in HDL Designer 2006.1

 

1. Running the Xilinx Coregen task

2. Installing a Task to Import an Existing Coregen Component in 2006.1 and Compatibility with 2005.x

3. Running the Import Existing Coregen Part 2006.1 Task

4. Adding Xilinx Libraries to your HDS project

5. Synthesizing the Design with Precision

6. Using UCF Files to Constrain Synthesis and Layout

Appendix C -

Basic EDK Project Library Structure in HDS

 

Appendix D -

Basic SOPC Design structure (includes VHD configurations to support Block RAM contents for simulation)

Appendix E -

Merging the Program Files with the FPGA Program Bit Stream

Appendix F -

Design Flow for the PicoBlaze Processor

 

1. Introduction

2. Importing the IP into HDS

Introduction to EDK Flow

This application note will go through the initial steps required to setup HDL Designer (HDS) to include systems developed with Xilinx’s Platform Studio (XPS) in your FPGA design. The flow will work with both a previously developed XPS system or entirely new system designs. The application note refers specifically to designs developed with either EDK 7.1 or 8.1. Xilinx have improved the migration process and there is now a wizard to automatically migrate designs from 7.1 to 8.1, more on this later.

EDK Flow Step by Step Overview

Before invoking HDS ensure the following system variables are correctly defined:

XILINX = location for the root directory for your ISE installation XILINX_EDK = location for the root directory for your EDK installation LMC_HOME = location of the swift model (required to support simulation of PowerPc processors)

It is a Xilinx requirement that the ISE and EDK installation must be of compatible revisions i.e. both 7.1 or 8.1

First call XPS form HDS using the special plugin Task. Create your design in XPS in the normal way, generate simulation models etc, and when complete exit in the normal way. The plugin will then automatically call XST to create a synthesizable design and import your design or design changes into HDS. More on configuring the XPS plugin later.

If your XPS system is to form part of a larger design, then instantiate the top level of your XPS system in the required hierarchy using any of the HDS editors i.e. BD, IBD or DesignPad

Suggested procedure for creating a new project which will include an XPS sub system:

Step1: Invoke HDS

Step2: Create New project and define library mappings for Top level module, Xilinx XPS sub- system and any custom logic

Create other libraries as required for the rest of your design

Step 3: Call Platform Studio using the XPS plugin. Remember to set the correct library option to import the XPS design. In the example shown we have called this Xilinx_XPS but you are free to use any name. However it is recommended that you configure your HDS project such that this library is reserved solely for the XPS system.

If the XPS plugin is not already visible in the Task tab it can be added through the default task setup.

In the task tab, hit the RMB (Right Mouse Button) and select “Supplied Tasks”. In the setup box, browse to the Xilinx tasks and select as required.

Configuring the XPS Plugin Invoke the Xilinx Platform Studio plugin task from the Task Tab

Configuring the XPS Plugin

Invoke the Xilinx Platform Studio plugin task from the Task Tab and Configure the dialog box as required:

from the Task Tab and Configure the dialog box as required: Defines the HDS library that

Defines the HDS library that the XPS system design will be placed in

Location for any new HDS libraries that may be created by the import process

Location of XPS project

It is essential that you correctly set the pointer to the Xilinx Project. This can be either an existing XPS project or a new one you intend to create. HDS uses this location to determine which files need to be imported back into HDS after you have closed Platform Studio. Hence you cannot change this location from within XPS by simply opening a new XPS project. If you do need to change this location, complete the design activity as required within the new XPS project and close XPS. Now re-invoke the plugin with the new location correctly defined, then open and close XPS. The updated data will be imported into HDS

The “Create in Library” field is “sticky” so it is recommended that you use the “Specify Library” option to set the library which will be used to import the XPS system. Using the default library option can be problematic if you make changes to the default library setup and then iterate around the XPS design process. If you forget the default library has changed, the XPS design could be imported to the wrong location.

Step 4: Create XPS sub system in XPS

Creating the XPS System Design

Use the menu option in the Platform Studio UI:

File > Open > New Project

This will invoke the “Base System Builder” Wizard. Follow the directions to create your processor sub-system with the required IP cores.

your proces sor sub-system with the required IP cores. Step 5 : Project Options Defining the

Step 5: Project Options

Defining the embedded processor design to be a sub-system

If the XPS system is not to be the top level of your design, the top level instance name must be defined, as shown below. This assumes that the sub-system will be instantiated in the top level as instance system_i. This will affect the contents of the bmm file (block memory map). (More on this later.) Please note, in XPS the default is for the embedded processor to be the top-level design

In the main tool bar select: Project > Project Options and then the Hierarchy and Flow tab

Enable the “Process Design is a sub-Module” option and enter name of the top level:

is a sub-Module” option and enter name of the top level: Instance name must agree with

Instance name must agree with Instance name used in HDL Designer ie system_i or U_0 etc

Step 6: Use the XPS “Simulation Compilation” Wizard to create and compile libraries for the IP cores within XPS sub-system.

Use the Main Menu option: Simulation > Compile Simulation Libraries

Follow the directions within the wizard. There are two basic types of library to be compiled:

unsim/xlinxcorelib libraries for low level functions and primitives and high level behavioural libraries for the IP cores. These IP cores have encrypted sources. Xilinx supplies a utility (compedklib) for compiling the models. This utility is run by the wizard. The user is only required to define the location for the compiled Modelsim/QuestaSim libraries.

only required to define the location for the compiled Modelsim/QuestaSim libraries. Rev. 1.1 16-Aug-06 Page 6
only required to define the location for the compiled Modelsim/QuestaSim libraries. Rev. 1.1 16-Aug-06 Page 6

ISE library compilation tab (unisim lib)

ISE library compilation tab (unisim lib) IP Cores Compilation tab Step 7: Creating custom logic (optional)

IP Cores Compilation tab

compilation tab (unisim lib) IP Cores Compilation tab Step 7: Creating custom logic (optional) Use this

Step 7: Creating custom logic (optional)

Use this option to dis-able actual library compilation (if lib already exists)

Location for unisim, simprim libraries etc

Smart model location (PowerPc)

Location for compiled ModelSim Libs

Creating a Custom Peripheral

Use the “Create and Import Peripheral” wizard if you need to create a custom interface to the processor sub-system. You can either create the associated logic first within HDS and import it into XPS using the wizard or simply create the bus interface now and then create the associated logic later (after the plug-in has imported the XPS sub-system into HDS). Assuming you have elected the second option, call the wizard by selecting (in main tool bar):

Hardware > Create or Import Peripheral

Select the correct option from the list of options available (see figure below)

from the list of options available (see figure below) Important: Ensure the “Create template” option is

Important: Ensure the “Create template” option is selected

Ensure the “Create template” option is selected If the peripheral is to be shared amongst other

If the peripheral is to be shared amongst other projects select the repository option, otherwise take the default. Follow the directions in the wizard to set the required options for the peripheral. This will create a VHDL wrapper in the XPS sub-system for your new component. This component can then be created in HDS

Step 8: Close XPS. The SOC design is created in a “system.vhd” file, wh ich

Step 8: Close XPS. The SOC design is created in a “system.vhd” file, which is automatically imported back into HDS. The file is parsed and as a result the individual design units can be seen in HDS browser. In addition a VHDL configuration may also have been generated by XPS for defining the contents of the Block RAMs, typically this will be call to system_init.vhd. It is also necessary to map the compiled libraries for the IP cells used within your XPS sub-system design in the HDS project. As previously mentioned, Xilinx supplies encrypted models for all the components plus a utility for compiling them called compedklib.exe. If you have compiled these libraries in the XPS environment they can be mapped in HDS by calling the “FPGA Technology setup” task. See step 9.

For synthesis and FPGA Placement, XPS provides ngc files. The XPS plug-in will have imported these files back into the ./synthesis sidedata area for each design object (IP core).

Step 9: Adding the Xilinx Technology Libraries to HDS

Adding Xilinx Libraries to your HDS project

You now need to map the IP libraries in HDS. Invoke the FPGA Technology Setup Wizard from the Tasks tab and follow the procedure as shown below. Select Xilinx as the vendor and then fill in other fields as required by your project:

and then fill in other fields as required by your project: Hit the Compile/Update button to
and then fill in other fields as required by your project: Hit the Compile/Update button to

Hit the Compile/Update button to configure the library mappings for Simulation and design instantiation of unisim cells

  Defines path to ModelSim or QuestaSim   These variables can be setup using the
  Defines path to ModelSim or QuestaSim   These variables can be setup using the
 

Defines path to ModelSim or QuestaSim

 
These variables can be setup using the HDS Setup Assistant

These variables can be setup using the HDS Setup Assistant

Ensure this variable reflects your choice of simulator i.e. ModelSim or QuestaSim Use the variables button to modify

Check the box to add the Xilinx ISE libraries to simulation

environment (unisim, xlinxcorelib, simprim)

environment (unisim, xlinxcorelib, simprim)

to simulation environment (unisim, xlinxcorelib, simprim) Click Option button to define location for IP cores Path

Click Option button to define location for IP cores

simprim) Click Option button to define location for IP cores Path to location of unisim and

Path to location of unisim and simprim compiled libraries

If the libraries do not need recompiling (for example they were complied in the XPS environment) select “Create Library Mapping Only”

Hit Options button to configure libraries for the embedded cores

Options button to configure libraries for the embedded cores Path to location for compiled EDK libs

Path to location for compiled EDK libs

Compiled Embedded kits Library Path

Xilinx’s XPS comes complete with simulation models for the IP cores, many of which are encrypted. XPS has a utility to collate and compile these cores for Modelsim/QuestaSim. The HDS Setup wizard uses this process to collate and compile the cores. Again you can use an existing location i.e. the “compedklib” as defined in Platform studio

Adding User IP

Use this field to define the location of you own or vendor independent supplied cores

Hit OK to return to main library setup tab

Compiled Vendor Library Path

This path defines the root directory location of the Xilinx unisim and simprim libraries. If they have already been compiled for an existing XPS project you can simply point to this location (compxlib) providing you are using the same simulator version. Otherwise the wizard will recompile the libraries.

Hit Run

The mappings for the Xilinx libraries will now be created in your current HDS project and if you have selected the option, the libraries compiled. If you have selected the appropriate option the unisim library mapping will be created as a protected library. This allows any of the unisim cells to be instantiated in parts of the design developed with HDS. The other libraries are created as downstream libraries to support simulation only.

This concludes the basic steps. The following section provide further details for configuring each step.

Simulation with either ModelSim or QuestaSim

XPS supports several simulation options.

By default HDS will create a downstream mapping for your Modelsim/QuestaSim library in the work sub directory. If you need to change this, go to the project tab in HDS, Select the HDS library, and expand the listing using the (+) button. Then either use the Add or Edit option available through the RMB popup menu.

The directory and modelsim.ini file are created as a result of running the compile task.

You will need to make some modifications manually to the modelsim.ini and recompile the design in order to access the SmartModel SWIFT interface for the PowerPC core. These fields can normally be found at the bottom of the modelsim.ini file.

Providing you have run the FPGA Technology setup Plugin before the modelsim.ini file was created, the mappings for the unisim, simprim and Xilinx Coregen libraries should have been correctly copied to the ini file.

The modelsim.ini file can accessed in HDS through the downstream file browser for Modelsim/QuestaSim (see below). Double click on the modelsim.ini file:

browser for Modelsim/QuestaSim (see below). Doubl e click on the modelsim.ini file: Rev. 1.1 16-Aug-06 Page

Making changes to modelsim.ini file:

Compiling Xilinx IP Cores

HDS parses the design to construct the library mappings for ModelSim. However only design objects in standard or protected libraries are parsed. Mappings for nested dependencies in downstream libraries will not be created. These will need to be created manually. If you have already compiled the IP libraries within the XPS environment (recommended) you can simply modify the “others” clause to point at the modelsim.ini file in your XPS area.

Comment out the existing “others” reference and add a new one which points at the modelsim.ini file in the XPS area:

;others = $MODEL_TECH/ /modelsim.ini others = D:\HDS\EDK_Tests\EDK_81\my_EDK_system\simlib\EDK_Lib\modelsim.ini

Modification for Swift Model Interface

If you are using the PowerPC you will need to enable the Swift Model interface within Modelsim/QuestaSim. This is done through settings in the modelsim.ini. Modify the LMC section as shown below to enable the swift interface. The modifications shown below represent the changes required for Windows. Make the changes appropriate to the platform you are using:

[lmc]

; The simulator's interface to Logic Modeling's SmartModel SWIFT software

; libsm = $MODEL_TECH/libsm.sl

; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)

libsm = $MODEL_TECH/libsm.dll

; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)

; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl

; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)

; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o

; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)

; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so

; Logic Modeling's SmartModel SWIFT software (Windows NT)

libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll

; Logic Modeling's SmartModel SWIFT software (Linux)

; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so

Simulator Resolution

You may need to change the simulator resolution to match the requirements of the Swift Interface. Typically this needs to be set to 1ps. This can be done in the simulator invocation settings in HDS:

can be done in the simulator invocation settings in HDS: Creating VHDL Configurations for Block RAMs

Creating VHDL Configurations for Block RAMs (Simulation)

If you have a VHDL configuration for the XPS sub system (typically system_conf) you will need to link this into your design configuration for simulation. The easiest way to do this is to create a VHDL configuration for your top level and edit it to use the configuration for the XPS system rather than the default view which points directly at the design structure. Simulating with the default view will not configure the BRAMs in your design.

To generate a top level configuration:

First ensure there is no conflict with the type of configuration used by the code generation.

In the Options > VHDL Options > Style tab select “Use a standalone configuration file”:

Select the top level design unit and access the menu: HDL > Generate VHDL Configurations

Select the top level design unit and access the menu:

HDL > Generate VHDL Configurations (disable the “Apply to hierarchy option”), and hit the Generate button:

to hierarchy option”), and hit the Generate button: Following is a code fragment for a configuration.

Following is a code fragment for a configuration. Make the changes as shown in bold below:

library Xilinx_XPS; configuration top_config of top is for struct for all : system --use entity Xilinx_XPS.system(STRUCTURE); use configuration Xilinx_XPS.system_conf; end for; end for; end top_config;

Remember if the top level is in a different library you will have to make the same changes to the modelsim.ini file as were done in the HDS library for the XPS sub system.

After you have generated the external configuration file for the top level, you may return the configuration style to internal. However if you make changes to the top-level block diagram you must repeat the process for generating an external configuration file.

Precision Synthesis

If your design is to contain Coregen components, please read Appendix A. If you are using a release of HDL Designer prior to 2006.1 you may need to install some additional plugins. These may be required if the Coregen components are complex (more than one edn file is generated) or if you need to import existing Coregen parts. If you use any of the new plugins please follow the instructions in Appendix A for calling Precision.

However starting with HDS version 2006.1, all the default plugins provided for the Xilinx related flows support these more complex Coregen components. The importation of existing coregen components generated outside of the HDS environment may still require the installation of an additional plugin (see Appendix A). Coregen components that use only a single ngc file as an alternative to a combination of an edn and ngc file are also supported (from 2006.1). Whichever format is used to describe the coregen component, a list of all the required files for synthesis and layout is generated by the HDS Coregen task. This list is automatically stored in the synthesis sidedata file, synthesis_description.tcl. All HDS synthesis-related tasks for calling Precision, XST, etc, use this file to determine the design details for the Coregen component.

From the Precision 2006a release, all files relating to the contents of Coregen components by default are tagged with the –model option. In summary, this option allows Precision to use the underlying hierarchy to determine area requirements and timing arcs but without the possibility of optimising or modifying the structure of the component.

The Precision plugin will automatically use the ngc files associated with the IP cores in your processor sub-system. During the importation from XPS, each design object is automatically tagged with the necessary properties to configure the ngc file as the alternative view for synthesis.

The 2006.1 HDS Precision plugin also introduces the ability to use ucf files for synthesis constraints and to exclude the lower ngc files from the Precision file list. You may need to exclude lower edn files (remember the file list is generated bottom up) if you are using a version of Precision prior to the 2006a release. This will effect the area report generated by Precision.

You should also note that if you select the option to include ucf files it maybe necessary to modify the constraint path to reflect its application in each design.

Precision 2006.1 Plugin settings

path to reflect its application in each design. Precision 2006.1 Plugin settings Rev. 1.1 16-Aug-06 Page

Place and Route in ISE

If you have used Precision for synthesis you are able to run ISE directly from the Precision UI. Alternatively you can call ISE from HDS by using the Xilinx Place and Route task.

Select the top level design object in the Design Explorer window and run the Xilinx Place and Route task. By default the synthesis results (edf file) from Precision are picked up. Fill in the remaining fields as required.

are picked up. Fill in the remaining fields as required. ucf constraint file Programming file format

ucf constraint file

Programming file format

Create a post routed simulation netlist

Run in batch or interactively

Appendix A

Using Coregen components in HDL Designer 2005.x

Introduction

HDL Designer is supplied with a builtin task for running Coregen. Prior to the 2006.1 release of HDL Designer this Coregen task had limitations in supporting some of the more complex Coregen components/options. Coregen components which have multiple .edn or .ngc files were not supported. You may also experience some difficulties during synthesis with designs containing components described using .xaw files (generated by the Xilinx Architect Wizard). If you are using HDL Designer 2006.1 or later please refer to Appendix B for a full description of the Coregen support

As a temporary “work around” for these limitations in HDL Designer 2005.x, several tcl scripts with accompanying HDS tasks have been written. From a quality point these should be regarded as typical “AE ware”. They have not been through the normal QA process and no upwards compatibility is guaranteed. The edn, ngc and xaw files are imported into the sidedata/synthesis area. The top level edif file in each case becomes the activate file. The new import procedure additionally creates an add_files.tcl file in the sidedata area. This file is parsed by a new Precision plugin which pre-processes the design, concatenating all the add_files.tcl files into one file. This file is placed in the downstream Precision directory, within the HDS sub-directory. This new precision plugin also accepts a number of additional new options including the use of a ucf file to constrain synthesis. More on this later.

Important: Please note this is slightly different from the methodology/flow that is used in HDS 2006.1. Any Coregen parts generated or imported using these scripts may need to be re-imported in HDS 2006.1. See Appendix B.

You can download the latest version of these tcl scripts and tasks directly from SupportNet.

Installing New Temporary Coregen Plugins

Step 1: Install the executable tcl scripts listed below to a suitable user defined directory:

import_existing_Coregen_part.tcl

precision_batch_Coregen.tcl

run_Coregen.tcl

Set the system variable HDS_SCRIPT_DIR to point to this location. The supplied HDS tasks will use this variable to locate the tcl scripts.

Step 2. Copy the HDS Tasks listed below to the user preference area of HDS:

import_existing_coregen_part.tsk,

precision_batch_coregen.tsk

run_corgen.tsk

The User preference location is version specific to HDS and is typically the location set by the system variable HDS_USER_HOME or the default location:

On windows:

C:\Documents and Settings\< user>\Application Data\HDL Designer

Series\hds_user\v2005.3\tasks

On other platforms:

hdl_designer_series/hds_user/v2005.3/tasks

You may need administrator or super user privileges to do this.

Step 3: Invoke HDL Designer, select the top of your design in the Design Units window and run the “FPGA Technology Setup” Task. This will create the Sidedata/Synthesis/Constraints and the .sdc and .ctr template files. The sdc template is used to add technology information and synthesis constraints for Precision. See section on “Using Constraint Files for Synthesis and Layout” later in this Appendix

The new temporary Precision plugin also supports .ucf files in this directory, as Precision now supports the ucf format for defining constraints.

Step 4: Place the PRECISION_LOAD_OPT.tcl file in the Sidedata/Synthesis directory of the overall top-level module. This file should be edited to define Xilinx family, part, speed grade, etc for your synthesis. It can also be used to control some of the reporting options available in Precision. To import the file, select the directory Sidedata/Synthesis in the sub-browser tab and hit the RHM button. Select the import >> file option. Then browse to the appropriate location

Alternatively if all designs share a similar setup for Precision you can place this file in the same directory as the tcl scripts (pointed to by the system variable HDS_SCRIPT_DIR). The new tcl plugin has a search order such that it first looks in the sidedata area then in the central location, using whichever file is found first.

Step 5: Close and re-invoke HDS 2005.3. The new tasks will appear at the bottom of the Task list. For ease of use you may want to drag them to the top.

Creating and Importing Coregen Components

If you wish to create “simple” Coregen parts (ie parts that contain a single edn file) you may continue to use the existing plugin. Otherwise create any new Coregen parts using the new temporary task “Run Xilinx’s Coregen”. This task permits the user to define the Coregen project location, unlike the builtin plugin which creates parts in the user’s temporary location before importing the edn/ngc file to the ./synthesis sidedata area and Coregen project xco file to the ./Coregen sidedata area.

Any parts that you create with the “Run Xilinx’s Coregen” task must also be imported into HDL Designer using the new temporary task “Import Existing Coregen Part”. You must import all of the Coregen parts which have been updated or which have multiple edn or ngc files using this new task.

However any existing Coregen parts that utilize a single edn file do not have to be re-imported. The following steps describe the process for importing existing components:

i. Invoke the task “Import Existing Coregen Part”

ii. Use the browser button to select the relevant Coregen file list (

list.txt) or

Architect Wizard output (.xaw file) file for each Coregen part

iii. Enter HDS library name into which the Coregen part is to be imported (defaults to the HDS default library)

iv. Hit the OK button

You can verify the operation by selecting the new design object in the HDS Design Explorer window and open the sub browser. The data structure should be similar to that shown below for complex parts with multiple edn and ngc files:

Adding Xilinx Libraries to your HDS project Please see section 3 in the main body

Adding Xilinx Libraries to your HDS project

Please see section 3 in the main body of the application on how to add the Xilinx technology libraries to the HDS project for simulation. If you are using only Coregen components you can omit the items that refer specifically to the Xilinx embedded processor kits (EDK)

Synthesizing the Design with Precision

A new temporary task and tcl script is available, “Precision Batch Coregen”. This tcl script does not use the technology details as defined by the “FPGA Technology Setup” task, rather it uses the details defined in the file PRECISION_LOAD_OPT.tcl. This file should be placed in either the sidedata/synthesis area of the top level module or in the directory referenced with the system variable HDS_SCRIPT_DIR.

Edit the file as appropriate. For example:

set VENDOR Xilinx set FAMILY "VIRTEX-4" set DEVICE 4vfx12 set PACKAGE sf363 set SPEED 12

Select the top of your design in the HDS browser and invoke the “Precision Batch Coregen” task. After this task completes, choose the ISE layout tab in Precision and invoke Place & Route.

Using Constraint files for Synthesis and Layout

Precision supports the use of constraint files using Xilinx’s UCF format. However it is limited to one file. You are also free to continue to use the sdc format as the script “Precision Batch Coregen” supports the use of both. These files must be placed in the sidedata/synthesis/constraints directory of the top level module.

The “FPGA Technology Setup” Task that is used to add and/or compile the simulation libraries (see section 3 in the main application note) will also create a template for the .sdc and .ctr files in the Sidedata/Synthesis/Constraints area. The sdc template is used to add technology information and synthesis constraints for Precision. The ctr file can be used in a similar way with LeonardoSpectrum. You will need to add any constraints to the sdc file by hand.

Your design may have complex Coregen/Architect wizard parts that require constraining/parameterization through the use of UCF constraints. If this is the case it is likely that a template for these constraints will have been generated by Coregen. If the part was imported using the new temporary import task any ucf template will have been imported along side the VHDL and EDIF files. The template can be found in the sidedata/synthesis/constraints directory associated with the Coregen component. The UCF file in the design objects sidedata area is not automatically applied during synthesis. The user can “cut and past” (using the HDS default editor) these details into the top level UCF file before running the Precision Batch Coregen task.

Appendix B

Using Coregen components in HDL Designer 2006.1

From HDL Designer 2006.1 onwards all default plugins provided for Xilinx related flows support complex coregen components. Components that use only a single ngc file as alternative to a combination of an edn and ngc files are also now supported.

Whichever format is used to describe the coregen component, a list of all the required files for synthesis is generated by the HDS coregen task. This list is automatically stored in the synthesis sidedata file, synthesis_description.tcl (this replaces the add_files.tcl file used in 2005.x for complex coregen components). All HDS synthesis-related tasks for calling Precision, XST etc, use this file to determine the design details for the coregen component. The order of the files listed in the synthesis_description.tcl file is adjusted to ensure it follows a bottom up structure as required by synthesis. Any additional options required by synthesis (for example –exclude option for Precision) are added by the relevant HDS synthesis task

Running the Xilinx Coregen task

In the HDS Tasks window double click on the “Xilinx CORE Generator” task. This will invoke the task and the setup box as shown below will appear. If the task is not visible within the task tab you may need to enable it. To enable the task use the RMB within the task tab area and select “Supplied Tasks” from the popup menu. Scroll down the list until you see the option for the CORE Generator, select the option and hit OK

In the setup box below ensure you correctly set the options for:

Xilinx Family, Synthesis Tool (MentorHDL) and target HDS library (the “Create in Library” option). Then hit “invoke CORE Generator”. When the you have completed the operation in the Xilinx Core generator, exit the tool and Hit Done in the HDS setup box

generator, exit the tool and Hit Done in the HDS setup box Ensure this is correctly

Ensure this is correctly set otherwise the coregen component will be imported to the wrong HDS library

The generated wrapper is imported into the target library and appears in the HDS Design Explorer. The files required for synthesis are listed in the synthesis_description.tcl file. The actual files are copied to a netlists sub-directory (all within the synthesis sidedata area for the coregen component). The coregen project file is also copied into a coregen sidedata area as shown below in the sub-browser tab

coregen sidedata area as shown below in the sub-browser tab From the Precision 2006a release onwards,

From the Precision 2006a release onwards, by default all files relating to the contents of coregen components are tagged with the –model option. In summary, this option allows Precision to use the underlying hierarchy to determine area requirements and timing arcs but without the possibility of optimising or modifying the structure of the component.

Installing a Task to Import an Existing Coregen Component in 2006.1 and Compatibility with 2005.x

An additional task is available specifically for importing an existing coregen component.

Important: Please note this is different from the additional task available for 2005.x. Any coregen component imported or generated with the specially supplied tasks referred to in Appendix A must be re-imported if they are to be compatible to the Synthesis flow in HDS 2006.1. This does not apply to components successfully generated with the 2005.x builtin Xilinx CORE generator plugin.

Please follow the steps below to install the plugin “Import an existing Coregen part 2006.1”.

Step 1: Install the executable tcl script listed below to a suitable user defined directory:

import_existing_Coregen_part_2006.tcl

Set the system variable HDS_SCRIPT_DIR to point at this location. The supplied HDS task will use this variable to locate the tcl scripts.

Step 2. Copy the task file import_existing_coregen_part_2006.tsk to the user preference area of HDS. The User preference location is version-specific to HDS and is typically the location set by the system variable HDS_USER_HOME, or the default location:

On windows:

C:\Documents and Settings\< user>\Application Data\HDL Designer

Series\hds_user\v2006.1\tasks

On other platforms:

hdl_designer_series/hds_user/v2006.1/tasks

You may need administrator or super user privileges to do this.

Please use Mentor Graphics Supportnet or contact you local support representative to locate the latest version of this tcl script and task.

Running the Import Existing Coregen Part 2006.1 Task

Any existing Coregen components that utilize a single edn file do not have to be re-imported. The following steps describe the process for importing existing components that use multiple edn or ngc files:

i. Invoke the task “Import Existing Coregen Part 2006.1”

ii. Use the browse button to select the relevant Coregen file list (

list.txt) or

Architect Wizard output (.xaw file) file for each Coregen part

iii. Enter HDS library name into which the Coregen component is to be imported (defaults to

the HDS default library)

iv. Hit the OK button

Adding Xilinx Libraries to your HDS project

Please see section 3 in the main body of the application on how to add the Xilinx technology libraries to the HDS project to support simulation. If you are using only Coregen components you can omit the items that refer specifically to the Xilinx embedded processor kits (EDK)

Synthesizing the Design with Precision

The “FPGA Technology Setup” Task that is used to add and/or compile the simulation libraries (again see section 3 in the main application note) will also create a template for the .sdc and .ctr files in the Sidedata/Synthesis/Constraints area. The sdc template is used to add technology information and synthesis constraints for Precision. You will need to add any constraints to the sdc file by hand. The ctr file can be used in a similar way with LeonardoSpectrum

For Coregen components generated with the 2006.1 version of either the “standard Core generator” task or the “Import Existing Coregen Part 2006.1” task, you should use the standard plugin to invoke Precision.

Note: Similarly you should also use the standard plugin for running XST and Symplify

Using UCF Files to Constrain Synthesis and Layout

Your design may have complex Coregen/Architecture wizard parts that require constraining/parameterization through the use of UCF constraints. If this is the case it is likely that a template for these constraints will have been generated by Coregen. The UCF template will have been imported along side the VHDL and EDIF files. The template can be found in the

sidedata/synthesis/constraints directory associated with the Coregen component. The UCF file in the design objects sidedata area is not automatically applied during synthesis. The user can “cut and past” (using the HDS default editor) these details into the top-level UCF file before running the Precision task.

Appendix C

Basic EDK Project Library Structure in HDS

XPS Project
XPS Project
XPS Project

XPS Project

XPS Project
XPS Project
XPS Project
XPS Project

*

Custom Logic
Custom
Logic
unisim Protected
unisim
Protected

Libraries

*

Embedded xlibcoregen Design Kits Downstream Libraries (mainly for simulation)
Embedded
xlibcoregen
Design Kits
Downstream Libraries
(mainly for simulation)
XPS Top Level Sub-system Standard Libraries
XPS
Top Level
Sub-system
Standard Libraries

* Possible multiple libraries

Instantiation

+ simulation

Appendix D

Basic SOPC Design Structure

Generated by HDS and Manually Linked to system_conf

Top Level

BD

Top level

Configuration

to system_conf Top Level BD Top level Configuration System_conf Configuration Custom Logic (BD or text) XPS
System_conf Configuration
System_conf
Configuration
BD Top level Configuration System_conf Configuration Custom Logic (BD or text) XPS system (text) Custom Logic

Custom Logic

(BD or text)

System_conf Configuration Custom Logic (BD or text) XPS system (text) Custom Logic (BD or text) IP

XPS system

(text)

Custom Logic

(BD or text)

IP Cells NGC VHDL
IP Cells
NGC
VHDL

Custom

Peripheral

Wrapper

HDS

Custom Logic

Used to define contents of block RAM

Structure generated within HDS

VHDL configuration (for simulation)

Structure (text) generated by XPS

Generated by XPS and imported to HDS

NGC files support synthesis Compiled VHDL supports simulation

Appendix E

Merging the Program Files with the FPGA Program Bit Stream

After you have completed the basic layout and placement of your FPGA you may want to merge the main program files with the FPGA bit stream for the embedded processor design. Xilinx provides several ways of performing this task. They all require the same files and formats. One option is to use the iMPACT program for which HDS has plugin

The program requires the name and location of the following files:

1. The original bit stream file. Typically found in the ISE project directory.

2. The bmm file. This file has details of the address mapping for the internal block RAMs It will have been imported from XPS into the HDS database along with the VHDL files. It can be found in the HDS ./.hdssidedata/system.vhd.info directory and is typically called system_stub.bmm.

3. You will also need to know how you want to allocate the program files to the BRAM. This is done by associating each ELF file (generated by SDK) with a BRAM tag (specified in the BMM file).

4. The elf files containing the system program.

Select the top level design object in the Design Browser.

If the iMPACT(FPGA Configuration) plugin is not already visible in the Task tab it can be added through the default task setup.

In the task tab, hit the RMB and select Supplied Tasks. In the setup box, browse to the Xilinx tasks and select as required:

setup box, browse to the Xilinx tasks and select as required: Run the iMPACT Plugin: Rev.

Run the iMPACT Plugin:

The existing bitstream file for your design. Typically found in the ISE project directory. The

The existing bitstream file for your design. Typically found in the ISE project directory.

The bmm file. this can be found in the HDS ./.hdssidedata/system.vhd.info directory and is typically called system_stub.bmm.

The elf files are provide by the SDK Environment and contain your program.

Select the option to create a new project and follow the instructions given by the wizard. The figure below shows the option to Configure devices using the Desktop Configuration mode:

below shows the option to Configure devices using the Desktop Configuration mode : Rev. 1.1 16-Aug-06

Add a new device by selecting the existing bit stream file for the design, then fill in the dialog boxes as appropriate to your design:

fill in the dialog boxes as appropriate to your design: Associate files with BRAM tags (given
fill in the dialog boxes as appropriate to your design: Associate files with BRAM tags (given

Associate files with BRAM tags (given in BMM file)

Hit OK to update the bit stream.

Important: Please note the BMM file contains hierarchical paths to the Block RAM locations. These paths may need to be modified to reflect the design hierarchy after the XPS sub system has been merged with the rest of the FPGA design within HDL Designer. This may mean either adding or removing hierarchy. Obviously if this is required the file must be edited before running iMPACT. A code snippet from an example bmm file is shown below. Typically the wrapper level may have been removed by the Precision plugin requiring the paths to be modified as shown in the second snippet.

Original specification for BRAM paths:

ADDRESS_BLOCK isocm_bram RAMB16 [0xffff8000:0xffffffff] BUS_BLOCK isocm_bram/isocm_bram/ramb16_0 [63:60] ; isocm_bram/isocm_bram/ramb16_1 [59:56] ;

Modified specification for BRAM paths:

ADDRESS_BLOCK isocm_bram RAMB16 [0xffff8000:0xffffffff] BUS_BLOCK isocm_bram/ramb16_0 [63:60] ; isocm_bram/ramb16_1 [59:56] ;

Alternatively, if your XPS design is a sub-system and this wasn’t specified when the design was created in XPS, then hierarchy must be added to the paths within the bmm file to reflect the location of the sub-system.

Appendix F

Design Flow for the PicoBlaze Processor

Introduction

The Xilinx PicoBlaze embedded processor has a different flow from that of the other Xilinx embedded processor, one which does not involve the use of Platform Studio. The processor and other associated IP cores are of a much simpler form. The kit, which can be downloaded from Xilinx’s web site, provides support for VHDL and Verilog based flows, however this application note has only specific details for using the VHDL models with HDL Designer (HDS). The Verilog flow is similar.

The VHDL files provide both a wrapper for the core and a few additional IP cores. It is recommended that all the files are imported into HDS (see import process). Underlying hierarchy within the VHDL files provides functional simulation. The simulation models use unisim components, thus the unisim library must also be added to your HDS downstream libraries and compiled for simulation. Please refer to Step 9: Adding the Xilinx Technology Libraries to HDS in the EDK flow. The library can be added either before or after importing the design.

An ngc file for the PicoBlaze core is also provided as part of the kit. This is used to describe the core during synthesis and FPGA layout stages. This must also be imported into HDS. More on this later.

Importing the IP into HDS

1. Create a regular HDS library for the PicoBlaze related IP Cores

2. Open the library in the HDS Design Browser

3. Import the cores using the HDS import wizard. Follow the directions within the wizard. A overview of the key stages is given below:

Choose the menu option: File > Import > Design

Copy (recommended) or reference the files

> Design Copy (recommended) or reference the files Browse to the VHDL source directory Hit OK.
> Design Copy (recommended) or reference the files Browse to the VHDL source directory Hit OK.

Browse to the VHDL source directory

Hit OK.

You may get additional dialog boxes depending upon you environment. Follow directions accordingly.

On the target library dialog box, check for correct settings before proceeding:

Ensure the target Library is correctly set

Ensure the target Library is correctly set After importing the design, the library should appear similar
Ensure the target Library is correctly set After importing the design, the library should appear similar

After importing the design, the library should appear similar to the view below

set After importing the design, the library should appear similar to the view below Rev. 1.1

4.

The next stage is to set the ngc file to be the alternate view for synthesis:

i. In the Design Browser, select the architecture (low_level_definition) on the PicoBlaze core (kcpsm3)

ii. Click the RMB to access the pop-up menu

iii. Select “Properties” on the pop-up menu

iv. Select the Synthesis Tab in the Properties Dialog box

v. Hit “ADD” and browse to the location of the kcpsm3.ngc file. Note that this file is part of the Xilinx design kit and normally resides at the root of the install tree after unzip. You may have to change the file type to ALL in the browser to see this file

vi. Check the option “Use alternative description for Synthesis”

the option “Use alternative descript ion for Synthesis” 5. You can verify the import process by

5. You can verify the import process by opening the sub browser tab (right side of main screen).

Expand the Design Data tab. The ngc file should be activated as shown below. Note: The tick on the synthesis directory icon is significant. This indicates that data is used for synthesis.

This completes the import process

The PicoBlaze core is now ready to be used in your design. Please read the Creating and Importing Coregen Parts section of this application note if you intend to use additional Coregen and/or unisim parts. It is recommended that you use another HDS library to create the top level and other parts of your design, thus maintaining the PicoBlaze and other associated cores in their own unique library. This makes it easy to share the library with other users and projects.

The components in the PicoBlaze library can be accessed by adding the library to the component browser in any of the HDS editors that support structure (ie block diagram, IBD, or Design Pad).

of the HDS editors that support st ructure (ie block diagram, IBD, or Design Pad). Rev.