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Contents
3. Adding Xilinx Libraries to your HDS project (ISE and EDK libraries)
6. Precision Synthesis
Appendix E - Merging the Program Files with the FPGA Program Bit Stream
1. Introduction
2. Importing the IP into HDS
This application note will go through the initial steps required to setup HDL Designer (HDS) to
include systems developed with Xilinx’s Platform Studio (XPS) in your FPGA design. The flow
will work with both a previously developed XPS system or entirely new system designs. The
application note refers specifically to designs developed with either EDK 7.1 or 8.1. Xilinx have
improved the migration process and there is now a wizard to automatically migrate designs from
7.1 to 8.1, more on this later.
XILINX = location for the root directory for your ISE installation
XILINX_EDK = location for the root directory for your EDK installation
LMC_HOME = location of the swift model (required to support simulation of PowerPc processors)
It is a Xilinx requirement that the ISE and EDK installation must be of compatible revisions i.e.
both 7.1 or 8.1
First call XPS form HDS using the special plugin Task. Create your design in XPS in the normal
way, generate simulation models etc, and when complete exit in the normal way. The plugin will
then automatically call XST to create a synthesizable design and import your design or design
changes into HDS. More on configuring the XPS plugin later.
If your XPS system is to form part of a larger design, then instantiate the top level of your XPS
system in the required hierarchy using any of the HDS editors i.e. BD, IBD or DesignPad
Suggested procedure for creating a new project which will include an XPS sub system:
Step2: Create New project and define library mappings for Top level module, Xilinx XPS sub-
system and any custom logic
Step 3: Call Platform Studio using the XPS plugin. Remember to set the correct library option to
import the XPS design. In the example shown we have called this Xilinx_XPS but you are free to
use any name. However it is recommended that you configure your HDS project such that this
library is reserved solely for the XPS system.
If the XPS plugin is not already visible in the Task tab it can be added through the default task
setup.
In the task tab, hit the RMB (Right Mouse Button) and select “Supplied Tasks”.
In the setup box, browse to the Xilinx tasks and select as required.
Invoke the Xilinx Platform Studio plugin task from the Task Tab and
Configure the dialog box as required:
It is essential that you correctly set the pointer to the Xilinx Project. This can be either an existing
XPS project or a new one you intend to create. HDS uses this location to determine which files
need to be imported back into HDS after you have closed Platform Studio. Hence you cannot
change this location from within XPS by simply opening a new XPS project. If you do need to
change this location, complete the design activity as required within the new XPS project and
close XPS. Now re-invoke the plugin with the new location correctly defined, then open and close
XPS. The updated data will be imported into HDS
The “Create in Library” field is “sticky” so it is recommended that you use the “Specify Library”
option to set the library which will be used to import the XPS system.
Using the default library option can be problematic if you make changes to the default library
setup and then iterate around the XPS design process. If you forget the default library has
changed, the XPS design could be imported to the wrong location.
In the main tool bar select: Project > Project Options and then the Hierarchy and Flow tab
Enable the “Process Design is a sub-Module” option and enter name of the top level:
Use the Main Menu option: Simulation > Compile Simulation Libraries
Follow the directions within the wizard. There are two basic types of library to be compiled:
unsim/xlinxcorelib libraries for low level functions and primitives and high level behavioural
libraries for the IP cores. These IP cores have encrypted sources. Xilinx supplies a utility
(compedklib) for compiling the models. This utility is run by the wizard. The user is only required
to define the location for the compiled Modelsim/QuestaSim libraries.
Select the correct option from the list of options available (see figure below)
If the peripheral is to be shared amongst other projects select the repository option, otherwise
take the default. Follow the directions in the wizard to set the required options for the peripheral.
This will create a VHDL wrapper in the XPS sub-system for your new component. This
component can then be created in HDS
For synthesis and FPGA Placement, XPS provides ngc files. The XPS plug-in will have imported
these files back into the ./synthesis sidedata area for each design object (IP core).
Hit the Compile/Update button to configure the library mappings for Simulation and design
instantiation of unisim cells
If the libraries do not need recompiling (for example they were complied in the XPS
environment) select “Create Library Mapping Only”
Xilinx’s XPS comes complete with simulation models for the IP cores, many of which are
encrypted. XPS has a utility to collate and compile these cores for Modelsim/QuestaSim. The
HDS Setup wizard uses this process to collate and compile the cores. Again you can use an
existing location i.e. the “compedklib” as defined in Platform studio
Adding User IP
Use this field to define the location of you own or vendor independent supplied cores
This path defines the root directory location of the Xilinx unisim and simprim libraries. If they have
already been compiled for an existing XPS project you can simply point to this location (compxlib)
providing you are using the same simulator version. Otherwise the wizard will recompile the
libraries.
Hit Run
This concludes the basic steps. The following section provide further details for configuring each
step.
By default HDS will create a downstream mapping for your Modelsim/QuestaSim library in the
work sub directory. If you need to change this, go to the project tab in HDS,
Select the HDS library, and expand the listing using the (+) button.
Then either use the Add or Edit option available through the RMB popup menu.
The directory and modelsim.ini file are created as a result of running the compile task.
You will need to make some modifications manually to the modelsim.ini and recompile the design
in order to access the SmartModel SWIFT interface for the PowerPC core. These fields can
normally be found at the bottom of the modelsim.ini file.
Providing you have run the FPGA Technology setup Plugin before the modelsim.ini file was
created, the mappings for the unisim, simprim and Xilinx Coregen libraries should have been
correctly copied to the ini file.
The modelsim.ini file can accessed in HDS through the downstream file browser for
Modelsim/QuestaSim (see below). Double click on the modelsim.ini file:
HDS parses the design to construct the library mappings for ModelSim. However only design
objects in standard or protected libraries are parsed. Mappings for nested dependencies in
downstream libraries will not be created. These will need to be created manually. If you have
already compiled the IP libraries within the XPS environment (recommended) you can simply
modify the “others” clause to point at the modelsim.ini file in your XPS area.
Comment out the existing “others” reference and add a new one which points at the modelsim.ini
file in the XPS area:
;others = $MODEL_TECH/../modelsim.ini
others = D:\HDS\EDK_Tests\EDK_81\my_EDK_system\simlib\EDK_Lib\modelsim.ini
If you are using the PowerPC you will need to enable the Swift Model interface within
Modelsim/QuestaSim. This is done through settings in the modelsim.ini. Modify the LMC section
as shown below to enable the swift interface. The modifications shown below represent the
changes required for Windows. Make the changes appropriate to the platform you are using:
[lmc]
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
; libsm = $MODEL_TECH/libsm.sl
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
libsm = $MODEL_TECH/libsm.dll
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Windows NT)
libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
; Logic Modeling's SmartModel SWIFT software (Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
You may need to change the simulator resolution to match the requirements of the Swift
Interface. Typically this needs to be set to 1ps. This can be done in the simulator invocation
settings in HDS:
If you have a VHDL configuration for the XPS sub system (typically system_conf) you will need to
link this into your design configuration for simulation. The easiest way to do this is to create a
VHDL configuration for your top level and edit it to use the configuration for the XPS system
rather than the default view which points directly at the design structure. Simulating with the
default view will not configure the BRAMs in your design.
First ensure there is no conflict with the type of configuration used by the code generation.
In the Options > VHDL Options > Style tab select “Use a standalone configuration file”:
HDL > Generate VHDL Configurations (disable the “Apply to hierarchy option”), and
hit the Generate button:
Following is a code fragment for a configuration. Make the changes as shown in bold below:
library Xilinx_XPS;
configuration top_config of top is
for struct
for all : system
--use entity Xilinx_XPS.system(STRUCTURE);
use configuration Xilinx_XPS.system_conf;
end for;
end for;
end top_config;
Remember if the top level is in a different library you will have to make the same changes to the
modelsim.ini file as were done in the HDS library for the XPS sub system.
After you have generated the external configuration file for the top level, you may return the
configuration style to internal. However if you make changes to the top-level block diagram you
must repeat the process for generating an external configuration file.
However starting with HDS version 2006.1, all the default plugins provided for the Xilinx related
flows support these more complex Coregen components. The importation of existing coregen
components generated outside of the HDS environment may still require the installation of an
additional plugin (see Appendix A). Coregen components that use only a single ngc file as an
alternative to a combination of an edn and ngc file are also supported (from 2006.1). Whichever
format is used to describe the coregen component, a list of all the required files for synthesis and
layout is generated by the HDS Coregen task. This list is automatically stored in the synthesis
sidedata file, synthesis_description.tcl. All HDS synthesis-related tasks for calling Precision,
XST, etc, use this file to determine the design details for the Coregen component.
From the Precision 2006a release, all files relating to the contents of Coregen components by
default are tagged with the –model option. In summary, this option allows Precision to use the
underlying hierarchy to determine area requirements and timing arcs but without the possibility of
optimising or modifying the structure of the component.
The Precision plugin will automatically use the ngc files associated with the IP cores in your
processor sub-system. During the importation from XPS, each design object is automatically
tagged with the necessary properties to configure the ngc file as the alternative view for
synthesis.
The 2006.1 HDS Precision plugin also introduces the ability to use ucf files for synthesis
constraints and to exclude the lower ngc files from the Precision file list. You may need to
exclude lower edn files (remember the file list is generated bottom up) if you are using a version
of Precision prior to the 2006a release. This will effect the area report generated by Precision.
You should also note that if you select the option to include ucf files it maybe necessary to modify
the constraint path to reflect its application in each design.
If you have used Precision for synthesis you are able to run ISE directly from the Precision UI.
Alternatively you can call ISE from HDS by using the Xilinx Place and Route task.
Select the top level design object in the Design Explorer window and run the Xilinx Place and
Route task. By default the synthesis results (edf file) from Precision are picked up.
Fill in the remaining fields as required.
Introduction
HDL Designer is supplied with a builtin task for running Coregen. Prior to the 2006.1 release of
HDL Designer this Coregen task had limitations in supporting some of the more complex Coregen
components/options. Coregen components which have multiple .edn or .ngc files were not
supported. You may also experience some difficulties during synthesis with designs containing
components described using .xaw files (generated by the Xilinx Architect Wizard). If you are
using HDL Designer 2006.1 or later please refer to Appendix B for a full description of the
Coregen support
As a temporary “work around” for these limitations in HDL Designer 2005.x, several tcl scripts
with accompanying HDS tasks have been written. From a quality point these should be regarded
as typical “AE ware”. They have not been through the normal QA process and no upwards
compatibility is guaranteed. The edn, ngc and xaw files are imported into the sidedata/synthesis
area. The top level edif file in each case becomes the activate file. The new import procedure
additionally creates an add_files.tcl file in the sidedata area. This file is parsed by a new Precision
plugin which pre-processes the design, concatenating all the add_files.tcl files into one file. This
file is placed in the downstream Precision directory, within the HDS sub-directory.
This new precision plugin also accepts a number of additional new options including the use of a
ucf file to constrain synthesis. More on this later.
Important: Please note this is slightly different from the methodology/flow that is used in
HDS 2006.1. Any Coregen parts generated or imported using these scripts may need to be
re-imported in HDS 2006.1. See Appendix B.
You can download the latest version of these tcl scripts and tasks directly from SupportNet.
Step 1: Install the executable tcl scripts listed below to a suitable user defined directory:
import_existing_Coregen_part.tcl
precision_batch_Coregen.tcl
run_Coregen.tcl
Step 2. Copy the HDS Tasks listed below to the user preference area of HDS:
import_existing_coregen_part.tsk,
precision_batch_coregen.tsk
run_corgen.tsk
The User preference location is version specific to HDS and is typically the location set by the
system variable HDS_USER_HOME or the default location:
On windows:
C:\Documents and Settings\<user>\Application Data\HDL Designer
Series\hds_user\v2005.3\tasks
On other platforms:
hdl_designer_series/hds_user/v2005.3/tasks
Step 3: Invoke HDL Designer, select the top of your design in the Design Units window and run
the “FPGA Technology Setup” Task. This will create the Sidedata/Synthesis/Constraints and the
.sdc and .ctr template files. The sdc template is used to add technology information and
synthesis constraints for Precision. See section on “Using Constraint Files for Synthesis and
Layout” later in this Appendix
The new temporary Precision plugin also supports .ucf files in this directory, as Precision
now supports the ucf format for defining constraints.
Alternatively if all designs share a similar setup for Precision you can place this file in the same
directory as the tcl scripts (pointed to by the system variable HDS_SCRIPT_DIR). The new tcl
plugin has a search order such that it first looks in the sidedata area then in the central location,
using whichever file is found first.
Step 5: Close and re-invoke HDS 2005.3. The new tasks will appear at the bottom of the Task
list. For ease of use you may want to drag them to the top.
If you wish to create “simple” Coregen parts (ie parts that contain a single edn file) you may
continue to use the existing plugin. Otherwise create any new Coregen parts using the new
temporary task “Run Xilinx’s Coregen”. This task permits the user to define the Coregen project
location, unlike the builtin plugin which creates parts in the user’s temporary location before
importing the edn/ngc file to the ./synthesis sidedata area and Coregen project xco file to the
./Coregen sidedata area.
Any parts that you create with the “Run Xilinx’s Coregen” task must also be imported into HDL
Designer using the new temporary task “Import Existing Coregen Part”.
You must import all of the Coregen parts which have been updated or which have multiple edn or
ngc files using this new task.
However any existing Coregen parts that utilize a single edn file do not have to be re-imported.
The following steps describe the process for importing existing components:
You can verify the operation by selecting the new design object in the HDS Design Explorer
window and open the sub browser. The data structure should be similar to that shown below for
complex parts with multiple edn and ngc files:
Please see section 3 in the main body of the application on how to add the Xilinx technology
libraries to the HDS project for simulation. If you are using only Coregen components you can
omit the items that refer specifically to the Xilinx embedded processor kits (EDK)
A new temporary task and tcl script is available, “Precision Batch Coregen”.
This tcl script does not use the technology details as defined by the “FPGA Technology Setup”
task, rather it uses the details defined in the file PRECISION_LOAD_OPT.tcl. This file should be
placed in either the sidedata/synthesis area of the top level module or in the directory referenced
with the system variable HDS_SCRIPT_DIR.
Precision supports the use of constraint files using Xilinx’s UCF format. However it is limited to
one file. You are also free to continue to use the sdc format as the script “Precision Batch
Coregen” supports the use of both. These files must be placed in the
sidedata/synthesis/constraints directory of the top level module.
The “FPGA Technology Setup” Task that is used to add and/or compile the simulation libraries
(see section 3 in the main application note) will also create a template for the .sdc and .ctr files in
the Sidedata/Synthesis/Constraints area. The sdc template is used to add technology information
and synthesis constraints for Precision. The ctr file can be used in a similar way with
LeonardoSpectrum. You will need to add any constraints to the sdc file by hand.
Your design may have complex Coregen/Architect wizard parts that require
constraining/parameterization through the use of UCF constraints. If this is the case it is likely that
a template for these constraints will have been generated by Coregen. If the part was imported
using the new temporary import task any ucf template will have been imported along side the
VHDL and EDIF files. The template can be found in the sidedata/synthesis/constraints directory
associated with the Coregen component. The UCF file in the design objects sidedata area is not
automatically applied during synthesis.
The user can “cut and past” (using the HDS default editor) these details into the top level UCF file
before running the Precision Batch Coregen task.
From HDL Designer 2006.1 onwards all default plugins provided for Xilinx related flows support
complex coregen components. Components that use only a single ngc file as alternative to a
combination of an edn and ngc files are also now supported.
Whichever format is used to describe the coregen component, a list of all the required files for
synthesis is generated by the HDS coregen task. This list is automatically stored in the synthesis
sidedata file, synthesis_description.tcl (this replaces the add_files.tcl file used in 2005.x for
complex coregen components). All HDS synthesis-related tasks for calling Precision, XST etc,
use this file to determine the design details for the coregen component. The order of the files
listed in the synthesis_description.tcl file is adjusted to ensure it follows a bottom up structure as
required by synthesis. Any additional options required by synthesis (for example –exclude option
for Precision) are added by the relevant HDS synthesis task
In the setup box below ensure you correctly set the options for:
Xilinx Family, Synthesis Tool (MentorHDL) and target HDS library (the “Create in Library” option).
Then hit “invoke CORE Generator”.
When the you have completed the operation in the Xilinx Core generator, exit the tool and
Hit Done in the HDS setup box
From the Precision 2006a release onwards, by default all files relating to the contents of coregen
components are tagged with the –model option. In summary, this option allows Precision to use
the underlying hierarchy to determine area requirements and timing arcs but without the
possibility of optimising or modifying the structure of the component.
Important: Please note this is different from the additional task available for 2005.x. Any
coregen component imported or generated with the specially supplied tasks referred to in
Appendix A must be re-imported if they are to be compatible to the Synthesis flow in HDS
2006.1. This does not apply to components successfully generated with the 2005.x builtin
Xilinx CORE generator plugin.
Please follow the steps below to install the plugin “Import an existing Coregen part 2006.1”.
Step 1: Install the executable tcl script listed below to a suitable user defined directory:
import_existing_Coregen_part_2006.tcl
On windows:
On other platforms:
hdl_designer_series/hds_user/v2006.1/tasks
Please use Mentor Graphics Supportnet or contact you local support representative to locate the
latest version of this tcl script and task.
Please see section 3 in the main body of the application on how to add the Xilinx technology
libraries to the HDS project to support simulation. If you are using only Coregen components you
can omit the items that refer specifically to the Xilinx embedded processor kits (EDK)
For Coregen components generated with the 2006.1 version of either the “standard Core
generator” task or the “Import Existing Coregen Part 2006.1” task, you should use the standard
plugin to invoke Precision.
Note: Similarly you should also use the standard plugin for running XST and Symplify
Your design may have complex Coregen/Architecture wizard parts that require
constraining/parameterization through the use of UCF constraints. If this is the case it is likely that
a template for these constraints will have been generated by Coregen. The UCF template will
have been imported along side the VHDL and EDIF files. The template can be found in the
XPS Project
* *
Standard Libraries
Protected Downstream Libraries
* Possible multiple libraries Libraries (mainly for simulation)
Instantiation
+ simulation
IP Cells
HDS
Custom Logic Generated by XPS and imported to HDS VHDL configuration (for simulation)
Merging the Program Files with the FPGA Program Bit Stream
After you have completed the basic layout and placement of your FPGA you may want to merge the
main program files with the FPGA bit stream for the embedded processor design. Xilinx provides
several ways of performing this task. They all require the same files and formats. One option is to use
the iMPACT program for which HDS has plugin
The program requires the name and location of the following files:
1. The original bit stream file. Typically found in the ISE project directory.
2. The bmm file. This file has details of the address mapping for the internal block RAMs
It will have been imported from XPS into the HDS database along with the VHDL files.
It can be found in the HDS ./.hdssidedata/system.vhd.info directory and is typically called
system_stub.bmm.
3. You will also need to know how you want to allocate the program files to the BRAM.
This is done by associating each ELF file (generated by SDK) with a BRAM tag
(specified in the BMM file).
4. The elf files containing the system program.
If the iMPACT(FPGA Configuration) plugin is not already visible in the Task tab it can be added
through the default task setup.
In the task tab, hit the RMB and select Supplied Tasks. In the setup box, browse to the Xilinx
tasks and select as required:
Select the option to create a new project and follow the instructions given by the wizard.
The figure below shows the option to Configure devices using the Desktop Configuration mode:
Important: Please note the BMM file contains hierarchical paths to the Block RAM locations.
These paths may need to be modified to reflect the design hierarchy after the XPS sub system
has been merged with the rest of the FPGA design within HDL Designer. This may mean either
adding or removing hierarchy. Obviously if this is required the file must be edited before
running iMPACT.
A code snippet from an example bmm file is shown below. Typically the wrapper level may
have been removed by the Precision plugin requiring the paths to be modified as shown in the
second snippet.
Alternatively, if your XPS design is a sub-system and this wasn’t specified when the design was
created in XPS, then hierarchy must be added to the paths within the bmm file to reflect the location
of the sub-system.
Introduction
The Xilinx PicoBlaze embedded processor has a different flow from that of the other Xilinx
embedded processor, one which does not involve the use of Platform Studio. The processor and
other associated IP cores are of a much simpler form. The kit, which can be downloaded from
Xilinx’s web site, provides support for VHDL and Verilog based flows, however this application
note has only specific details for using the VHDL models with HDL Designer (HDS). The Verilog
flow is similar.
The VHDL files provide both a wrapper for the core and a few additional IP cores. It is
recommended that all the files are imported into HDS (see import process). Underlying hierarchy
within the VHDL files provides functional simulation. The simulation models use unisim
components, thus the unisim library must also be added to your HDS downstream libraries and
compiled for simulation. Please refer to Step 9: Adding the Xilinx Technology Libraries to
HDS in the EDK flow. The library can be added either before or after importing the design.
An ngc file for the PicoBlaze core is also provided as part of the kit. This is used to describe the
core during synthesis and FPGA layout stages. This must also be imported into HDS. More on
this later.
Copy (recommended)
or reference the files
Hit OK.
You may get additional dialog boxes depending upon you environment. Follow directions
accordingly.
On the target library dialog box, check for correct settings before proceeding:
After importing the design, the library should appear similar to the view below
5. You can verify the import process by opening the sub browser tab (right side of main screen).
Expand the Design Data tab. The ngc file should be activated as shown below.
Note: The tick on the synthesis directory icon is significant. This indicates that data is used for
synthesis.
The PicoBlaze core is now ready to be used in your design. Please read the Creating and
Importing Coregen Parts section of this application note if you intend to use additional Coregen
and/or unisim parts. It is recommended that you use another HDS library to create the top level
and other parts of your design, thus maintaining the PicoBlaze and other associated cores in their
own unique library. This makes it easy to share the library with other users and projects.