HDL Designer Series™ Language Support Guide Release v2018.2 © 1994-2018 Mentor Graphics Corporation

HDL Designer Series™ Language Support
Guide
Release v2018.2
© 1994-2018 Mentor Graphics Corporation

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Table of Contents
Chapter 1
SystemVerilog Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Setting SystemVerilog as Your Default Design Language . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Setting SystemVerilog Language Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Creating SystemVerilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Adding SystemVerilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Editing SystemVerilog Text Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting SystemVerilog Syntax Highlighting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting Code Browser Content for SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Exploring SystemVerilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Identifying SystemVerilog Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reporting Assertions and Covergroups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reporting SystemVerilog Bound Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Compiling and Simulating SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 2
Verilog 2005 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Setting Verilog 2005 as the Default HDS Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Migrating Verilog 95 Designs to Verilog 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Setting Verilog 2005 Language Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Working with Verilog 2005 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Creating a Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Example: Creating a Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Creating a Text View for an Existing Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . 34
Creating Verilog 2005 Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating Verilog 2005 Text Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating Verilog 2005 Graphical Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Example: Creating a Block Diagram View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Creating Mixed Dialect Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Importing Verilog 2005 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Editing Verilog 2005 Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Generating HDL From Verilog 2005 Graphical Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 3
VHDL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VHDL 2008 Supported Language Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VHDL 2008 Backward Compatibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Setting VHDL as the Default HDS Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Setting VHDL Language Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Working with VHDL Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
HDL Designer Series™ Language Support Guide, v2018.2 3

Table of Contents
Creating a VHDL Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Example: Creating a VHDL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Creating a Text View for an Existing VHDL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Creating VHDL 2008 Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Creating VHDL 2008 Text Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Creating VHDL Graphical Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Importing VHDL 2008 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Editing VHDL Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Generating HDL from VHDL Graphical Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Chapter 4
PSL Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Creating PSL Assertion Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Linking PSL Assertions to HDS Design Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Attaching PSL files to a Design View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Activating PSL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Including PSL Files in ModelSim Compilation/ Simulation Flows . . . . . . . . . . . . . . . . . . . 79
End-User License Agreement
4 HDL Designer Series™ Language Support Guide, v2018.2

Chapter 1
SystemVerilog Support
This chapter provides a quick tour through the different features and tools available in HDL
Designer Series (HDS) that you can use in developing your SystemVerilog designs.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Setting SystemVerilog as Your Default Design Language . . . . . . . . . . . . . . . . . . . . . . . . 6
Setting SystemVerilog Language Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Creating SystemVerilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Adding SystemVerilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Editing SystemVerilog Text Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting SystemVerilog Syntax Highlighting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting Code Browser Content for SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Exploring SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reporting Assertions and Covergroups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reporting SystemVerilog Bound Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Compiling and Simulating SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Introduction
SystemVerilog combines the Verification capabilities of HVL (Hardware Verification
Language) with the ease of Verilog to provide a single platform for both design and verification.
HDS currently provides text-level support for SystemVerilog 3.1a/1800 standard.
SystemVerilog files/designs can be created in HDS, organized into libraries / projects and
managed accordingly. Not only can you create new designs but also you can import any of your
old SystemVerilog code created outside HDS. Doing so you can make use of all design
management capabilities provided through the tool.
HDS Design Manager helps you browse through your code and view it from different
perspectives. It also allows you to obtain reports on specific aspects of your design as assertions,
coverage points, etc.,
In this chapter we provide a quick tour through the different features and tools available in HDS
that you can use in developing your SystemVerilog designs.
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Setting SystemVerilog as Your Default Design Language
Setting SystemVerilog as Your Default Design

Language
HDS allows you to set SystemVerilog as the default language for all newly created designs.
This can be helpful if SystemVerilog is your most frequently used design language.
Procedure
1. Choose Help > HDS Setup Assistant Wizard.
2. Select the Language node and set the SystemVerilog (Text Verilog) option in the left
pane of the window.
3. Click Finish to save your new setting.
Setting SystemVerilog Language Preferences

New SystemVerilog designs are created according to a set of predefined options. The options
are related to file naming, file headers, compiler directives and default packages.
Procedure
1. In the Design Explorer window, select Options > Verilog to display the Verilog
Options dialog box.
Setting SystemVerilog Language Preferences
2. On the File tab, specify your default Verilog file extension by choosing from the System
Verilog(default) dropdown list.
3. On the Headers tab, choose from a pulldown list of view headers. The selected header is
is used in the created view. Graphical views are not supported.
4. You can set default Verilog compiler directives in the DefaultDirectives tab.
5. You can set default packages in the Default Packages tab.
Creating SystemVerilog Files
6. Click OK. The above defined preferences will be added to new views.
Related Topics
Preferences for HDLViews [HDL Designer Series User Manual]
Creating SystemVerilog Files

HDS allows you to create text SystemVerilog views. Preferences set in the Verilog Options
dialog box are applied to the created views.
Procedure
1. Invoke the Design Content Creation Wizard.
2. Choose Verilog File from the Categories pane.
3. In the File Types pane, specify your file type as Module, Include, SvPackage,
SvProgram, SvInterface, or SvClass.
4. Set the language dialect as SystemVerilog.
Adding SystemVerilog Designs
If you choose to use a template, define whether you want to specify your own or work
with the default one. Templates are available for SV packages, programs, interfaces, and
classes.
5. Click Next to specify the new Verilog file location, name, and format.
6. Click Finish.
The DesignPad editor is launched displaying your new SystemVerilog file.
You can check your new design object in the Design Units pane of the Design Explorer
Tip
: To display a created class in the Design Unit Browser pane, add your code after the
module code or create a new class from the Design Creation wizard. Nested Classes
only appear in the DesignPad code browser.

Existing SystemVerilog designs can be added to HDS projects through the Add Existing Design
wizard. According to your preference, you can move a copy of the design to the HDS projects’
directory or point to it in its current location.
Procedure
1. Start the Add Existing Design wizard by choosing File > Add >Existing Design.
The Add Existing Design dialog box displays.

2. Specify the method to add design content by choosing Pointto Specified files or
CopySpecified Files.
3. Specify whether you want to use an existing file list to obtain information on design
content by setting the Use an Existing Filelist option. Specify the files to add.
4. Specify the method to determine the Verilog Import Dialect used as Auto or Specified.
Table 1-1. Verilog Dialect Setting Options

Option Description
Auto The Verilog dialect used is automatically detected. A single
design may include different verilog dialects
Specified The verilog dialect is marked as SystemVerilog for all design
files even if they do not contain any SystemVerilog constructs.
5. Complete the Add Existing Design wizard steps.

The Design Explorer window displays showing the added design.
Editing SystemVerilog Text Views
Editing SystemVerilog Text Views

All normal text editing procedures provided through DesignPad are supported for
SystemVerilog views. HDS allows you to set language specific preferences as syntax
highlighting and code browser content.
When editing SystemVerilog documents SystemVerilog Keywords are automatically detected
and completed by choosing Complete Keyword from the Edit or popup menu.
Refer to About DesignPad.
The figure below illustrates how HDS allows you to manage your design files in DesignPad.
Figure 1-1. Managing Design Files in DesignPad
Setting SystemVerilog Syntax Highlighting Preferences
Setting SystemVerilog Syntax Highlighting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . 12

Setting Code Browser Content for SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting SystemVerilog Syntax Highlighting

Preferences
You can set SystemVerilog syntax highlighting preferences.
Procedure
1. In DesignPad, choose Options > Preferences.
The Preferences dialog box displays.
2. In the Category pane, browse to Document Type > SystemVerilog > Syntax
Highlighting to display the Syntax Highlighting page.
3. Set the Enable Syntax Highlighting option.
4. To change the default syntax highlighting options for an object, select the required
object from the list in the Syntax group box and define the new object background and
foreground colors.
Related Topics
Syntax Highlighting [DesignPad Text Editor User Manual]
Accessing Design Explorers [HDL Designer Series User Manual]
Using the Side Data Browser [HDL Designer Series User Manual]
Identifying SystemVerilog Design Objects [HDL Designer Series User Manual]
Finding Design Objects [HDL Designer Series User Manual]
Creating an Unparsed Files Report [HDL Designer Series User Manual]
Finding Unbound Components [HDL Designer Series User Manual]
Reporting Assertions and Covergroups [HDL Designer Series User Manual]
Reporting SystemVerilog Bound Objects [HDL Designer Series User Manual]
Setting Code Browser Content for SystemVerilog

The code browser represents the code structure in the active file as a hierarchical tree of
recognized code blocks (objects). You can set the SystemVerilog objects you want to display in
the code browser.
Table 1-2. SystemVerilog Objects

Icon Code Block Icon Code Block
Always External Instance
Always_Comb Interface
Always_FF Interface Port
Always_Latch Local Parameter
AssertProperty Modport
AssumeProperty Module
Class Package
ClassObject Parameter
Clocking Parameter Map
Const Parallel Block
CoverageBin Package Import
CoverageCross Input Port
CoveragePoint Inout Port
Covergroup Port Map
CovergroupObject Output Port
CoverProperty Program
Cross Property
ExpectProperty Sequential block
ExportImport Sequence
Final Specify
Function Specific Parameter
Gate Instance Struct
Generate Statement Task
Generate Variable Type
Include Wire
Initial Union
Instance
Procedure
1. In DesignPad, choose Options > Preferences.
The Preferences dialog box is displayed.
2. In the Categories pane, browse to Document Type > SystemVerilog > Code Browser.
The Code Browser page displays showing a list of all the available SystemVerilog
objects.
3. Select/deselect the objects you want to show/hide in the code browser window.
Exploring SystemVerilog Designs
Exploring SystemVerilog Designs

You can explore SystemVerilog designs and manage them through the HDS Design Manager.
The Design Manager provides three main views of the HDL design data. Each view is displayed
in a distinct design browser pane. You can use the cross-highlight feature to track down an
object in the different design views. Table 1-3 lists the three main Design Manager views:
Table 1-3. HDS Design Managers Views
Design Manager View Description
Design Unit This is a “virtual” representation of the main declarative
objects within the design.
Design Files This shows the actual file structure of the files and folders
which are part of the project. HDL source files can be
expanded to see the top-level objects within them.
Design Hierarchy This shows the static instance hierarchy from a given level.
Modules, classes and Program Blocks can be dragged into
this browser in order to explore the design hierarchy
underneath that level.
Tip
The Design Unit browser can be toggled to an Object List browser where you can group,
sort, and filter all objects (including instances).
You can control which objects are visible, which columns of additional data are shown
(including user defined property information), and save these settings in alternative
“viewpoints.”
For more information, refer to Accessing Design Explorersand Using the Side Data Browser.

Reporting Assertions and Covergroups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reporting SystemVerilog Bound Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Identifying SystemVerilog Design Objects

The following SystemVerilog Objects are displayed in the Design Explorer browsers.
Program Blocks
Program blocks are intended to contain test bench code, that is, they relate to verification only.
They represent leaf-levels of hierarchy.
Interfaces and Modports

Interfaces are a special kind of port type, but can be treated in a similar way to modules.
Interfaces can
• Describe a re-usable group of signals. Modports allow this overall group of signals to be
divided into a number of subgroups and also have specific directionality, for example,
master and slave.
• Model “protocol” behavior, including protocol checking when associated with tasks and
functions.
• Be used as “adaptors” or “converters” thus allowing the same component to be
connected up at differing levels of abstraction.
Classes
Classes are user-defined data types that bring in the essence of object oriented programming to
the SystemVerilog language.
Tip
Systemverilog only allows one level of inheritance.
Packages
A package is a new SystemVerilog design unit similar to the VHDL package.
It is used for
• Sharing declarations among modules, interfaces, programs and other packages.

• Defining a single global set of items that can be used by any design unit that imports that
package.
SystemVerilog Assertions
An assertion is a statement that validates assumptions or checks conditions in a program
SystemVerilog has an integrated set of constructs that help you to build assertions and closely
couple them with the rest of your design or verification code.
SystemVerilog assertions can
• Provide control-oriented coverage. Coverage allows you to tell how well a design has
been tested.
• Specify and validate design behavior.
Cover Groups
Cover groups, derives from hardware verification languages. Cover groups can contain multiple
individual coverage points, allow “binning” of multiple values and support cross-coverage to
track combinations of values.
In the following section, you will see how the new SystemVerilog objects are displayed in each
Design Explorer browser.
Design Unit Browser

The key new information/objects supported in the Design Unit browser are shown in Table 1-4:
Table 1-4. System Verilog Design Unit Browser Objects
Icon Description
Program Block
Interface
Class
Package
Module
Include
Files’ Browser
In the Files’ Browser HDL source files can be expanded to see the top-level objects within
them. The key information/objects supported in the Files’ browser for Systemverilog designs
are shown in Table 1-5:
Table 1-5. System Verilog Files’ Browser Objects
Icon Description
Program Block
Interface
Class
Package
Module
Design Hierarchy Browser

The Design Hierarchy browser shows static design hierarchy. Unresolved objects are
highlighted.
Reporting Assertions and Covergroups
Related Topics
Reporting Assertions and Covergroups

SystemVerilog provides two basic mechanisms for specifying functional coverage: cover
groups and cover properties. The cover property construct is part of the SystemVerilog
Assertions (SVA) subset, sharing temporal sequences and other building blocks with assertion
specifications.
Specific reports to summarize and locate assertions, property-based coverage and cover groups
can be generated through HDS.
Procedure
In the Design Manager window
Select a module and from the popup menu choose Reports > Assertions(SV) or
Reports > Covergroups(SV).
You can report assertions/coverage within a single object, its hierarchy, or within the
entire library.
A new tab displays showing a report of the design assertions/covergroups.
Reporting SystemVerilog Bound Objects
Related Topics
Reporting SystemVerilog Bound Objects

Although test bench constructs can be embedded within the functional description, they are
often written in separate verification files that are then associated with the functional description
(typically using the keyword BIND)
The Bind statement allows the designer (or verification engineer) to associate reusable
verification components (e.g. properties and assertions) with a design without changing the
source code. You can bind a module, interface or program instance to a module or module
instance.
You can create a report showing all the files to which a selected module is bound.
Procedure
1. In the Design Manager window, select a module and from the popup menu choose
Reports > WhereBound
A new tab displays showing a report of all the files to which a selected module is bound.
2. Click on any of the file entries.

DesignPad opens and highlights the bind statement.
Compiling and Simulating SystemVerilog

Designs
SystemVerilog designs can be compiled and simulated using ModelSim/QuestaSim.
Prerequisites
ModelSim/QuestaSim should be installed.
Compiling and Simulating SystemVerilog Designs
Procedure
1. Choose Help > HDS Setup Assistant menu to display the HDS Setup Assistant wizard.
2. Open the Simulator page, which automatically detects the presence of any installed
simulators and displays the path of the executables.
3. Select the ModelSim simulator or the QuestaSim simulator.
4. Click Finish.
5. Select the root design unit in the Design Unit Browser.
6. Choose Settings from the popup menu of the QuestaSim Compile task to display the
Compile Settings dialog box.
7. Check the Enable code coverage option on the coverage tab.
8. Choose Run through Components from the popup menu of the Simulator button in the
shortcut bar.
The progress of the compilation is shown in the HDL Log window.
Tip
Compilation warning messages may appear in the log window.
On completion of the compilation of the design, the Start Simulator dialog box displays.
9. Accept the default resolution, and check that the Interactive (GUI) and Enable
Communication with HDS options are selected.
10. Check the Enable code coverage option.
11. In the Additional simulator arguments field, enter the following to suppress the vopt
optimization mode and enforce the debug mode.
-novopt-assertdebug
12. Click the OK button to confirm the Start ModelSim/QuestaSim dialog box and load the
design.
Chapter 2
Verilog 2005 Support
Verilog 2005 style code can be generated from HDS Graphical Editors. HDL created or
generated code can be compiled and simulated.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Setting Verilog 2005 as the Default HDS Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Migrating Verilog 95 Designs to Verilog 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Setting Verilog 2005 Language Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Working with Verilog 2005 Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Example: Creating a Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Creating a Text View for an Existing Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . 34
Creating Verilog 2005 Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating Mixed Dialect Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Importing Verilog 2005 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Editing Verilog 2005 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Generating HDL From Verilog 2005 Graphical Views . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Introduction
HDS provides both text-level and graphical support for the Verilog 2005 language.In this
chapter we will provide an overview of the features in HDS designed to support the V2k
language.
Importing existing Verilog 2005 designs in addition to creating new designs is now
possible.You can even toggle the language of existing HDS Verilog 95 designs.
Verilog 2005 text designs can be instantiated inside Block Diagram and IBD views as well as
visualized or converted to graphics. Generate constructs are recovered as Embedded Blocks.
HDS does not currently provide support for Generate Frames in Verilog 2005 designs.
Signed signals and ports, uwire net types, declarations with continuous assignments in addition
to initialized variable declarations are now supported.
Setting Verilog 2005 as the Default HDS Language
Setting Verilog 2005 as the Default HDS

Language
HDS allows you to set Verilog 2005 as the default language for all newly created designs. This
can be helpful if Verilog 2005 is your most frequently used design language.
Procedure
1. Choose Options > Main from the Design Explorer window.
The Main Settings dialog appears.
2. On the General tab, in the Default Language for New Views group box, choose Verilog
2005 from the dropdown menu of Graphical Views and Text Views Verilog options.
then click OK.
Tip
You can change the set default language for a specific view from the Design Content
Creation wizard.
3. Choose Help > HDS Setup Assistant Wizard.
Migrating Verilog 95 Designs to Verilog 2005
4. Select the Language node and set the SystemVerilog (Text Verilog) option in the left
pane of the window. Click Finish to save your new setting
You can change the default language for a specific view from the Design Content
Creation Wizard dialog box.
Related Topics
HDS Setup Assistant Wizard [Start Here Guide]
Main Settings Dialog [HDL Designer Series User Manual]

Converting your old Verilog 95 designs to Verilog 2005 and making use of all the supported
features may sound like a very tempting idea. The only obstacle you may be thinking of is the
time you have to invest in such a task. HDS allows you to toggle the language of your Verilog
‘95 designs (graphical and text) in a simple and easy way without having to redo your work.
Changing the language of your design unit automatically changes the language of the associated
symbol as well as all the views representing this design.
The HDL code generated from the converted designs will follow the set Verilog 2005
generation properties.
Prerequisites
Existing Verilog ‘95 design.
Caution
VHDL or SystemVerilog designs cannot be toggled to Verilog 2005 designs.
Procedure
1. Select a Design Unit from the Design Units pane in the Design Explorer window.
2. Choose Change Language to > Verilog 2005 from the popup menu.
Notice that the Language field now displays Verilog 2005 instead of Verilog 95 for the
selected design unit.
Caution
Verilog 2005 graphical views cannot be toggled back to Verilog 95 designs.
This is an example to show how you can toggle the language of your existing Verilog 95
designs and make use of the new Verilog 2005 supported features. It also points out the
rules followed when changing the language to Verilog 2005.
3. Create a new library with the name backup and copy the contents of the Uart_V library
into it.
4. Open the Uart_V library from the Project Manager window.
5. In the Design Units browser, select the uart_top design unit and choose Change
LanguageTo > Verilog 2005 from the popup menu.
Notice that the Language field now displays Verilog 2005 instead of Verilog 95 for the
selected design unit.
6. Drag the uart_top design unit to the hierarchy browser. Examine the displayed
hierarchy.
Notice how the language of all Blocks and Embedded Blocks, which exist under the
uart_top design unit, has been changed to Verilog 2005. Toggling the language of a
Block Diagram or IBD view enforces the toggling of all underlying Blocks and
Embedded Blocks.
7. Expand the xmit_rcv_control design unit. The language of all views for this design unit
have been automatically changed to Verilog 2005.
Setting Verilog 2005 Language Preferences
8. Expand the uart_top design unit to view its symbol. The symbol language has been
automatically changed to Verilog 2005.
9. Select the uart_top symbol and choose Open from the popup menu.
A graphical representation of the symbol displays.
10. In the Structure Navigator bar, double-click Interface to display a tabular representation
of your symbol
Notice the new Signed and Value columns.
11. Expand the uart_top design unit to view its symbol. The symbol language has been
automatically changed to Verilog2005.

New Verilog 2005 designs are created according to a set of predefined options. The options are
related to file naming, file headers and compiler directives and are set through the Verilog
Options dialog.
Procedure
1. In the Design Explorer window select Options > Verilog to display the Verilog Options
dialog box.
2. On the File tab, specify your default Verilog file extension by choosing from the Source
Verilog (default) dropdown list.
is used in the created view.
You can also choose to include the generation properties as comment text after the
header in the generated HDL and if this option is set, you can also include the signal
status in generated state machine HDL
4. You can set default Verilog compiler directives in the DefaultDirectives tab.
5. Click OK.
The above stated preferences will be added to any new view.
Working with Verilog 2005 Interfaces
Working with Verilog 2005 Interfaces

An HDS interface defines the output and input ports for a design. The interface is presented in
either a tabular form and is referred to as an Interface or a graphical form and is referred to as a
Symbol.
Example: Creating a Verilog 2005 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Creating a Text View for an Existing Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . 34
Creating a Verilog 2005 Interface

Component interfaces are created through the Design Content Creation wizard and edited
through the tabular IO and symbol editors.
Procedure
1. Invoke the Design Content Creation wizard by clicking the New/Add button in the
Design Explorer shortcut bar.
2. Choose Graphical View from the Categories pane and specify the view type as:
Interface from the File Types pane.
3. Set the language dialect as Verilog 2005.
4. Click Next to specify the new Verilog view location and name.
5. Click Finish. The Interface tabular IO editor is launched.
Notice the additional Signed status column (for net or reg types) and Value column for
outputs of type reg, integer, time.
Example: Creating a Verilog 2005 Interface
6. Click the Symbol icon in the Structure Navigator to display the graphical view of the
created interface.

This example shows how a Verilog 2005 interface can be created and edited in HDS. It also
shows how you can change the Verilog 2005 port display.
Prerequisites
Open the SCRATCH_LIB library of the Examples project.
Procedure
2. Choose Graphical View from the Categories pane and specify the view type as:
4. Click Next to display the Specify View Name/Location page.
5. Select SCRATCH_LIB from the Library name dropdown list, and enter the following in
the Design Unit entry field:
Interface_V2k
6. Click Finish.
The Interface tabular IO editor is launched.
7. Add the following signals and save the new interface view.
Table 2-1. Signals Table

Name Mode Signed Type Bounds Value
In1 input wire [15:0]
In2 input signed wire [15:0]
Out1 output signed wire [15:0]
Out2 output reg [15:0] 2
created interface.
Notice how the ports are declared using the default Ansi-C style.
9. Right-click on the symbol to display the Objects Properties dialog box. The Symbol tab
allows you update the symbol, symbol instances, and Symbol/View update properties.
You can change the display of symbol ports to show or hide the new Signed and Value
properties.
10. To change the display of the ports of the symbol to show itself, click the Port Display
button in the Symbol group box. To change the display of the ports of the symbol
instances, click the Port Display button in the Symbol Instance group box.
Creating a Text View for an Existing Verilog 2005 Interface
11. Click on the Port Display button in the Symbol group box and set the Signed and Value
options and save your changes.
Notice how the port declarations on the symbol have been updated.
12. Close the symbol editor.
Note
Two-way synchronization is supported between the Symbol tabular IO and the
Signals table.
Creating a Text View for an Existing Verilog 2005

Interface
Verilog 2005 text views created based on a Verilog 2005 symbol contain a module interface that
has port style generated according to the module ports declaration settings defined through the
Verilog Options dialog.
Two-way synchronization exists between the Verilog 2005 symbols and their corresponding
views. Updates saved in one view are reflected in the other.
Creating a Text View for an Existing Verilog 2005 Interface
Procedure
1. Set the port style that you want to have in your created text file by selecting Options >
Verilog from the Design Explorer window to display the Verilog Options dialog box.
2. On the Style tab, set your port definition style preferences as ANSI-C or List.
3. Select a Verilog 2005 Interface design unit from the Design Unit browser.
5. Choose Verilog View from the Categories pane and specify the view type as: Module
from the File Types pane.
8. Click Finish. The DesignPad editor is launched showing the newly created Verilog File.
The created Verilog file contains a module interface that has port style generated
according to the module ports declaration settings defined through the Verilog Options
dialog.
Related Topics
Design Content Creation Wizard [HDL Designer Series User Manual]
Verilog 2005 Generation Preferences [HDL Designer Series User Manual]
Creating Verilog 2005 Views
Creating Verilog 2005 Views

HDS allows you to create both text and graphical Verilog 2005 views. Preferences set in the
Verilog Options dialog box are applied to the created views.
Creating Mixed Dialect Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Creating Verilog 2005 Text Files

Verilog text files are created through the Design Content Creation wizard.
Procedure
2. Choose Verilog File from the Categories pane, and Module or Include from the File
Types pane.
with the default one.
4. Click Next to specify the new Verilog file location, name, and format.
5. Click Finish.
The DesignPad editor is launched displaying your new Verilog file.
Creating Verilog 2005 Graphical Views

Verilog 2005 graphical views are created through the Design Content Creation wizard.
Procedure
2. Choose Graphical View from the Categories pane and specify the view type from the
File Types pane.
Example: Creating a Block Diagram View
5. Click Finish.
The appropriate editor is launched displaying the selected graphical view.

This is an example showing the creation of a block diagram view based on an existing V2k
symbol. The block diagram view signal types, values and sign properties are edited to point the
new supported V2k features.
Prerequisites
Select the Interface view Interface_V2K you created earlier. Refer to “Example: Creating a
Verilog 2005 Interface” on page 32.
Procedure
2. Choose Graphical View from the Categories pane and select Block Diagram from the
File Types pane.
4. Click Next to display the Specify View Name/Location page. Accept the set values and
click Next.
Creating Mixed Dialect Designs
5. On the Specify Interface page, the Symbol ports are listed. You can edit or update the
displayed list.
6. Click Finish to launch the Block Diagram editor displaying the new BD view.
7. Select the output2 signal and right-click to choose Object Properties from the popup
menu.
The Signals page of the Object Properties dialog box displays.
8. Select wire from the Type field dropdown list.
Notice that the Value field is disabled. Only output signals of type reg, integer, and time
can be given a value. Input signals can not have values.
9. Select the input2 signal and right-click to choose Object Properties from the popup
menu.
10. Select real from the Type field dropdown list.
Notice that the Signed check box is dimmed. Only signals of types net or reg can be
signed.
11. Close your block diagram view.

HDS allows you create mixed dialect designs: the same design unit can be presented as a
Verilog 95, Verilog 2005, and a SystemVerilog view.
Some limitations exist on the creation of such mixed dialect designs based on the dialect and
type of the default design view. The limitations can be summarized in the following table:
Table 2-2. Mixed Dialect Designs Limitations
Default View Type Default View Dialect Possibly Created Views
Text Verilog 95 Verilog 95 graphical views
Table 2-2. Mixed Dialect Designs Limitations (cont.)

Default View Type Default View Dialect Possibly Created Views
Verilog 2005 Verilog 95 and Verilog 2005 graphical
views.
SystemVerilog Verilog 95 and Verilog 2005 graphical
views.
Graphical Any Verilog dialect Any text Verilog dialect view.
Note
Mixed dialect graphical views are not allowed.
Tip
You have the ability to instance SystemVerilog text components into Verilog 2005 Block
Diagram and IBD views. This applies to components only, but not to blocks.
Procedure
1. Select a design unit from the Design Unit browser and do one of the following:
• Open the Design Content Creation wizard by clicking the New/Add button in the
shortcut bar.
• Choose New from the popup menu.
2. Specify your design type and language following the rules stated in table Table 2-2 and
complete the wizard steps.
A new view is created. A warning message is issued incase you try to create an invalid
view.
Examples
1. In the Design Explorer select the clock_divider design unit and choose New >
Graphical View>Block Diagram from the popup menu.
Importing Verilog 2005 Designs
The New Block Diagram dialog box displays.
2. Click OK to accept the defaults.

HDS creates a Block Diagram view using the dialect of the default view.
Importing Verilog 2005 Designs

Existing Verilog 2005 designs can be added to HDS projects through the Add Existing Design
wizard. When adding a design to a HDS project you can choose to move a copy of the design to
the HDS projects’ directory or point to it in it’s current location.
Procedure
1. Start the Add Existing Design wizard by choosing File > Add >Existing Design:
a. Specify the method to add design content by choosing CopySpecified Files or Point
to Specified files from the Add Method group box.
Editing Verilog 2005 Signals
b. Specify whether you want to use a filelist to obtain information on design content by
setting the Use Filelist option. Specify the files to add.
2. Specify the method to determine the Verilog dialect used as Auto or Specified.
Table 2-3. Verilog Dialect Setting Options

Option Description
Auto The verilog dialect used is automatically detected. A single
design may include different verilog dialects
Specified The user can mark all design files as verilog 2005 even if
they do not contain any verilog 2005 constructs.
3. Complete the Add Existing Design wizard steps. The Design Explorer window is
displayed showing the added design.
Related Topics
Addition of Existing Design Content to an HDS [HDL Designer Series User Manual]
Removing Design Files From a Project [HDL Designer Series User Manual]
Add Existing Files to Library Dialog Box [HDL Designer Series User Manual]
Add Existing Design Wizard [HDL Designer Series User Manual]
Editing Verilog 2005 Signals

Verilog 2005 signals or ports are described by the following fields: Name, Mode, Signed, Type,
Bounds, and Value.
The values of the above mentioned fields can be edited in the Object Properties dialog, the
Signals table, the Interface table or Symbol. In the case of a block diagram view, inplace editing
is possible as well. The following steps describe the editing of Verilog 2005 signals using the
Object Properties dialog box.
Procedure
1. Open a Verilog 2005 Block Diagram view and double-click on any of its signals.
The Object Properties dialog displays.
2. Set the properties as for any Verilog or VHDL signal.
3. For all types other than Time and integer specify the signed property.
4. You may specify a value for any of your output signals.
Generating HDL From Verilog 2005 Graphical Views
Notice that any changes are synchronized with the Signals table and with the view
declaration text.
Related Topics
Editing Object Properties [Graphical Editors User Manual]
Generating HDL From Verilog 2005 Graphical

Views
You can use HDS to generate HDL code for your graphical designs.
HDS allows you to have a degree of control over the style of the Verilog code generated through
the Verilog Options dialog box. It gives you even more control over the code generated from
Verilog 2005 graphical views, this can be useful in the case of downstream tools with limited
Verilog 2001/2005 support.
Note
Moduleware instances in Verilog 2005 designs follow the Verilog 2005 code generation
settings.
Procedure
1. In the Design Explorer window select Options > Verilog to display the Verilog Options
dialog box. This is where you will be setting all your code generation preferences.
a. In the Generated Files group box of the File tab, set the file naming rules you want to
use when generating Verilog files or leave the default settings.
b. In the Verilog 2005 Generation Group box, specify some Verilog 2005 code style
features.
o Specify whether you want to generate ports in a port list or using the ANSII-C
style. On choosing to generate listed ports, the list sub-options allow you to
combine your generated ports’ data types with the port declaration or have them
in separate statements.
o For leaf level views, you can specify the sensitivity list separator style to be a
comma or an “OR”. You can also choose to allow implicit event expression @*
where appropriate.
c. Specify the style features of the generated code in the Style Options Group Box of
the Style tab or choose to leave the defaults
You can:
o Specify the default tab width setting for Verilog text views by entering the
number of spaces to indent.
o Choose to generate HDL with the begin and else keywords on separate lines.
o Add blank lines around comments by specifying the number of lines to add
before and after the comment line.
o Choose to add a label to generated always or initial code blocks and specify a
prefix or suffix which is added to the label names. You can also choose whether
to use uppercase or lowercase labels.
o Choose to include associated properties in generated Verilog.
d. If your design includes ModuleWare components, you can specify the style features
of the generated code.
In the ModuleWare Generation group box of the Style tab you can do the following:
o Choose blocking assignments or non-blocking assignments to registers in the
HDL for sequential (clocked) ModuleWare components.
o Optionally enter a non-blocking delay when non-blocking assignment is set.
(Note that the default value 0 means no delay.)
o Set the signal name prefix used for ModuleWare signals in the generated HDL
o Choose to use Pragmas when needed.
o Choose to use bus slices in sensitivity lists depending on whether your
simulation tool support slices or not; If it doesn’t do not set this option as this
will lead to including only the bus name in the sensitivity list on generation.
e. You can specify parameter generation properties. In the Parameters group box of the
Style tab, you can do the following:
o Choose whether all Verilog parameters defined in the symbol are automatically
initialized with default values and displayed when a component is instantiated. If
this option is not set, only the overridden parameters are displayed.
o Choose whether a synopsys template pragma is added above the parameter
declaration in the generated HDL for the symbol. (This option is enabled for
backward compatibility but should normally be unset if you are not using the
Synopsys synthesis tools.)
2. In the Design Explorer window, select a Verilog 2005 design unit and choose a
generation option from the Tasks > Generation submenu. Check the log window for
any warnings and errors.
3. To view your generated file, choose HDL > View Generated HDL.
Related Topics
Preferences for HDL Views [HDL Designer Series User Manual]
Chapter 3
VHDL Support
HDS provides both text-level and graphical support for the VHDL language. In this chapter, we
will provide an overview of the features in HDS designed to support the VHDL 2008 language.
Importing existing VHDL 2008 designs in addition to creating new designs is now possible.
VHDL text designs can be instantiated inside Block Diagram and IBD views as well as
visualized or converted to graphics.
VHDL 2008 Supported Language Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

VHDL 2008 Backward Compatibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Setting VHDL as the Default HDS Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Setting VHDL Language Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Working with VHDL Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Creating a VHDL Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Example: Creating a VHDL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Creating a Text View for an Existing VHDL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Creating VHDL 2008 Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Creating VHDL 2008 Text Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Creating VHDL Graphical Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Importing VHDL 2008 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Editing VHDL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Generating HDL from VHDL Graphical Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VHDL 2008 Supported Language Features

The following VHDL 2008 language features are supported in HDL Designer Series.
• HDL Designer Series and DesignChecker support the following constructs for textual
designs:
o Conditional and Selected Assignment in Sequential Code:
VHDL 2008 extends the supported forms of signal assignments to be consistent in
both sequential and concurrent contexts. VHDL 2008 supports conditional and
sequential assignments for signals/variables in sequential contexts in the same forms
available in concurrent contexts. In addition, VHDL 2008 provides the ability to
write forcing assignments in the form of conditional and selected assignments.
VHDL Support
o Sized Bit String Literals:

VHDL 2008 enhances the support of bit-string literals significantly as follows: The
first enhancement allows you to specify elements other than only '0' and '1'. The
second enhancement allows you to specify the precise length of the vector
represented by a literal. Hence, you have the ability to specify vectors, the length of
which is not a multiple of 3 (for octal) or 4 (for hexadecimal). The third
enhancement allows you to specify whether the literal represents a signed number or
an unsigned number. The fourth enhancement allows you to specify a vector value in
decimal.
o Slices in Array Aggregates:
An array aggregate allows you to form an array from a collection of elements. In
earlier dialects of VHDL, you had the ability to form an aggregate from individual
elements only. Currently, VHDL 2008 allows you to form an array from a mixture of
individual elements in addition to slices of the array.
Note
Note the following:
• Using aggregates on the left and right hand side of the assignment statement is
not supported.
• Using aggregates within aggregate elements is not supported.
• Auto-detection of VHDL dialects depends on the syntax of constructs. When
using Slices in Array Aggregates, auto-detection may not work correctly in some
cases. If the automatic dialect detection of the design file is incorrect, you can set
the dialect manually as a workaround.
o Logical Shift Operators:

VHDL 2008 provides shift operator definitions to existing and new packages. This
applies to the operators rol, ror, sll, srl, sla and sra.
The following table lists the packages in which these operators are defined in VHDL
2008, along with the types these operators are defined for.
Table 3-1. Logical Shift Operators Support in VHDL 2008
Package Type
<Predefined> All operators are defined for arrays of bits and booleans.
numeric_bit & numeric_std All operators are defined for signed and unsigned.
numeric_bit_unsigned All operators are defined for bit_vector.
numeric_std_unsigned Only sla and sra are defined for std_ulogic_vector.
fixed_generic_pkg All operators are defined for unresolved_ufixed and
unresolved_sfixed.
VHDL Support
o Simplified Case Statements:

Prior to VHDL 2008, the index range of the expression of a case statement had to be
locally static. VHDL 2008 allows non-locally static expression index ranges, as long
as all choices have the same length. See the following example:
VARIABLE s : bit_vector(3 downto 0);
VARIABLE c : bit;
…
CASE c & s IS
…
END CASE;
VHDL 2008 also supports array aggregate choices containing others. This is
supported as long as the expression index range is locally static. See the following
example:
VARIABLE s : bit_vector(3 downto 0);
CASE s IS
WHEN ('0', others => '1') => …
WHEN ('1', others => '0') => …
END CASE;
o If and Case Generate Statement:

In addition to FOR and IF generate statements, VHDL 2008 added CASE generate
statements, along with ELSIF/ELSE branches for the IF generate statement. For
example:
lbl: IF condition GENERATE
-- concurrent statements
...
ELSIF condition GENERATE
...
ELSE GENERATE
…
END GENERATE lbl;
lbl:CASE sel GENERATE

WHEN choice1 =>
...
WHEN choice2 =>
...
WHEN OTHERS =>
...
END GENERATE lbl;
VHDL Support
Note
The body of generate statements ELSIF/ELSE and CASE should have begin/end
in pairs. Knowing that either both (begin/end) should exist, or both do not exist.
o Context Declaration Statement:

VHDL 2008 added Context Declaration to group library and use clauses differently
in design units without needing to follow each design unit with a long list of clauses.
A context reference, if placed before a design unit, acts as if all of its contents of
library and use clauses are placed before the design unit. For example:
CONTEXT ctx IS
LIBRARY ieee;
USE ieee.std_logic_1164.all;
END ctx;
CONTEXT work.ctx;
ENTITY top IS
PORT(in1, in2: IN std_logic; out1: OUT std_logic);
END top;
Note
You can write a context reference in the context clause preceding a design unit,
or nested within another context declaration.
o Delimited Comments:
In addition to single line comments (starting with “- -” and ending on the same line),
VHDL 2008 added delimited comments (starting with “/*” and ending with “*/”).
A delimited comment can end on the same line, or on any subsequent line. Note that
nesting of comments is not allowed.
See the following example:
/* This is a delimited comments spanning
multiple lines and this /* is not the start of
a nested comment.
-- This line belongs to the delimited comment.
The delimited comment end here */
o Matching Relational Operators:

VHDL 2008 has a new set of predefined matching relational operators (?=, ?/=, ?<,
?<=, ?>, and ?>=) that return bit or std_ulogic results. This allows assignments to
be written as in the following example:
mySig <= A ?= B;
o Condition Operators:
VHDL 2008 provides a condition operator ?? which is used to simplify conditional
VHDL Support
expressions. Since conditions should produce a type Boolean, conditions used to be

written in the following form:
IF mySig = '1' THEN ...
Currently, VHDL 2008 allows the condition operator to be applied to a signal of

type bit or std_ulogic, to produce a Boolean. Hence, currently a condition can be
written as follows:
IF ?? mySig THEN ...
Furthermore, VHDL2008 provides implicit application of the condition operator in

places where conditions may exist. So, the condition mentioned previously can be
directly written as follows:
IF mySig THEN ...
o Array/Scalar Addition Operators:

VHDL 2008 allows the addition/subtraction of scalar and array operands producing
an array result. Operator overloadings were added in VHDL 2008 in the following
packages: numeric_bit, numeric_std, fixed_generic_pkg and float_generic_pkg.
o Array/Scalar Logical Operators:
VHDL has logical operators that operate on two operands to produce a result. These
operators are and, or, nand, nor, xor and xnor. Before VHDL 2008, predefined and
standard overloaded definitions used to exist for these operators with operand pairs
of the same type including the following types: bit, Boolean, std_ulogic, and arrays
of bit, Boolean, and std_ulogic.
VHDL 2008 currently allows for one of the operands to be scalar, and the other to be
an array, producing an array result. This was achieved by adding predefined and
standard operator overloads for this purpose.
o Maximum and Minimum Operators:
VHDL 2008 provides the minimum and maximum functions which allow the
selection of a larger or smaller value as part of an expression. They can be used with
scalar and array types.
o Resolved Elements:
VHDL 2008 involves a way of associating a resolution function with an element
type of a composite type as part of declaring a new subtype.
o Generic Enhancements:
• Generic List in Package — VHDL 2008 allows defining generic lists in
packages.
VHDL Support
• Package Instantiation Declaration — VHDL 2008 allows defining an instance of

an uninstantiated package as follows:
PACKAGE myPkg IS NEW myUninstantiatedPkg
GENERIC MAP (...); -- This is optional
An uninstantiated package is a package with a generic list. See the following

example:
Package Declaration:
PACKAGE myPkg IS
GENERIC ( width : positive := 16 );
TYPE myRecord IS RECORD
myElement1 : std_logic_vector (width-1 DOWNTO 0);
myElement2 : std_logic;
END RECORD myRecord;
END PACKAGE myPkg;
Package Instantiation:
PACKAGE myPkgInst IS NEW work.myPkg GENERIC MAP (width => 8);
Or:
PACKAGE myPkgInst IS NEW work.myPkg;
Note that if any check is set to be applied to packages when running

DesignChecker, then it will also be applied to this construct.
• Package as Generics / Interface Package Declarations — An interface package
provides a means for the environment to determine an instance of an
uninstantiated package to be visible in a particular portion of a description by
associating an actual instantiated package with the formal interface package. See
the following example:
PACKAGE myPkg IS
GENERIC (a : integer;
PACKAGE myFixedPkg IS NEW IEEE.fixed_generic_pkg GENERIC MAP
(<>) );
END PACKAGE;
VHDL Support
Or:
PACKAGE myPkg2 IS
GENERIC (a: integer;
(default) );
END PACKAGE;
Or:
PACKAGE myPkg3 IS
GENERIC (a : integer;
(x) );
END PACKAGE;
It should be noted that this is supported in DesignChecker except for DC

synthesis checks.
Also note that if any check is set to be applied to packages when running
DesignChecker, then it will also be applied to this construct.
• Referencing Generics in Generic Lists — VHDL 2008 allows you to use a

generic within the range of other generics in the same generic list.
• Generic Type — VHDL 2008 allows you to declare a type as a generic element.
This capability can be used for ports and other declarations in the unit having the
generic without specifying an actual type. An actual type is specified in the
generic map during the unit instantiation. See the following example:
entity and_gate is
generic (type t);
port(in1, in2: in t; out1 : out t);
end entity and_gate;
The entity in the example can be used to instantiate and_gate for BIT or
STD_LOGIC in the generic map during the unit instantiation as follows:
U1: entity work.and_gate generic map (t => BIT) port map
(...);
U2: entity work.and_gate generic map (t => STD_LOGIC) port map
(...);
• Generic Lists in Subprograms — VHDL 2008 allows you to define a generic list
within a subprogram. This allows a subprogram to operate on an arbitrary data
type. When you instantiate a subprogram having generics, its instance can be
called in the same way as regular subprograms. The subprogram’s instance
VHDL Support
provides actual values to the generics in the generic map during the unit
instantiation. See the following example:
function max
generic(type t)
parameter(in1, in2 : t) return t is
begin
//…
end function max;
…
function max_int is new max generic map (t => INTEGER);
• Generic Functions — VHDL 2008 allows you to declare a function as a generic

element. You can use this capability to define operations for a generic type. You
have the ability to call a generic function in the unit specifying the generic
without having the function bound to an actual function. The actual function is
bound to the generic function in the generic map during the unit instantiation.
See the following example:
entity comparator is
generic(type t, function isGreater(in1, in2 : in t) return
boolean);
port(p1, p2: in t; less, equal, greater: out boolean);
end entity comparator;
The entity in the example can be used to instantiate a comparator to compare two
values of type INTEGER or STD_LOGIC_VECTOR for example. This is done
by providing an actual function in the generic map that takes parameters of type
INTEGER or STD_LOGIC_VECTOR as follows:
function isGreaterInteger(in1, in2 : in INTEGER) return
boolean is ...
U1: entity work.and_gate generic map (t => BIT, isGreater =>
isGreaterInteger) port map (...);
function isGreaterStdLogicVec(in1, in2 : in STD_LOGIC_VECTOR)
return boolean is ...
U2: entity work.and_gate generic map (t => BIT, isGreater =>
isGreaterStdLogicVec) port map (...);
o std.standard:
HDL Designer Series supports a number of VHDL 2008 new predefined types and
associated operations, and at the same time extends support for the set of operations
associated with existing predefined types.
VHDL Support
The following table shows a list of the newly supported predefined types along with
their supported associated operations:
Table 3-2. New Predefined Types and Associated Operations
New Type Associated Operations
boolean_vector • Array/scalar logic operators
• Logical (unary) reduction operators
• ?= and ?/= operators
• to_string operations
• to_bstring, to_ostring, to_hstring and their aliases
• Maximum and minimum operations
integer_vector • Relational operators and concatenation operator
real_vector • Equality and inequality operators and concatenation operator
time_vector • Equality and inequality operators and concatenation operator
The following table shows a list of the existing predefined types along with their
newly supported associated operations:
Table 3-3. Existing Predefined Types and Associated Operations
Existing Type Associated Operations
bit_vector • Array/scalar logic operators
bit • ?? operator
boolean • Maximum and minimum operations
time • mod and rem operators
o IEEE Packages:
The following IEEE packages are newly supported/enhanced by HDL Designer
Series:
• ieee.numeric_bit
• ieee.numeric_bit_unsigned
• ieee.numeric_std
• ieee.numeric_std_unsigned
VHDL Support
• ieee.math_real
• ieee.math_complex
• ieee.std_logic_1164
• Fixed/Floating Point Packages
o fixed_float_types
o fixed_pkg
o fixed_generic_pkg
o float_pkg
o float_generic_pkg
The float_generic_pkg package is supported in DesignChecker, except for
DC synthesis checks.
o Unconstrained Element Types:
Composite types in VHDL such as arrays and records can have elements whose
types can be constrained or unconstrained. Prior to VHDL 2008, element types were
only allowed to be constrained, but currently unconstrained element types are
allowed for arrays and records in HDL Designer Series.
You can create a subtype for an unconstrained type, therefore, when defining a port
or a signal, you can define the constraints for both the type and its subtypes.
It should be noted that this construct does not support records in DesignChecker.
o All in Sensitivity List:
VHDL 2008 provides the ability to specify the “all” construct as a sensitivity list for
a combinatorial process instead of explicitly mentioning all read signals.
It should be noted that this construct is supported in DesignChecker except for DC
synthesis checks.
o Matching Case Statements:
The matching case statement (or case with “don’t care”) allows the use of a case
choice that includes “don’t care” elements. It is written like an ordinary case
statement but with a question mark after the case keyword as follows: case?. It is
mostly used with an expression of a vector type whose elements are values of
std_ulogic or std_logic type.
o External Names:
An external name signifies an object in the design hierarchy containing the external
name. External names may refer to a variable, signal or constant which is found in
another part of the design hierarchy. External names are enclosed in double angle
brackets << ... >>.
VHDL Support
<<SIGNAL .myentity.U_1.my_sig : std_logic>>
o Force and Release:

The force keyword allows you to override the value of a signal, which is useful for
verification engineers for example. Similarly, the overridden value can be removed
using the release keyword.
o Read Output Ports:
Unlike previous VHDL dialects, VHDL 2008 provides the ability to read the value
of out-mode ports. Also, VHDL 2008 provides the ability to read the value of out-
mode parameter of a procedure; Out-mode parameters can either be signal
parameters or variable parameters.
o Signal Expressions in Port Maps:
On instantiating a component in VHDL, a port map is written to specify the signals
connected to the ports of the instance. If an input port is to be tied to a fixed value, an
expression can be written in the port map instead of a signal name. In previous
dialects of VHDL, the expression was required to be static; that is, the expression’s
value could not change during execution of the model. Currently, VHDL 2008
allows including non-static expressions involving the values of signals when writing
an expression in a port map.
o Tool Directives:
A tool directive is an annotation included in a VHDL design file intended to provide
information to the tool processing the VHDL design. A tool directive is not logically
part of the design itself. VHDL 2008 relies on tool directives as a way of embedding
information for use by tools in a VHDL model. The form of writing tool directives is
as follows:
` identifier ...
The grave accent character (also called back-tick) is followed by an identifier that
indicates the kind of information provided or the action to be performed. Other text
in the same line of code, if any, provides any further information required. The
directive ends with the end of the line. For more information and examples, refer to
IEEE Standard VHDL Language Reference Manual.
Also, protected tool directives are partially supported in HDS. HDS ignores anything
written between “protect begin protected directive” and “protect end protected
directive”.
• Breakpoints:
o A new package was added to the std library in HDS. The package name is ENV. This
package has stop and finish procedures necessary for supporting breakpoints.
VHDL Support
VHDL 2008 Backward Compatibility Issues
• Improved IO Enhancements:
o IEEE.textio package and other IEEE packages having string operations are updated
to support new IO enhancements.
o Added predefined and implicit to_string functions, and predefined aliases required
for Improved IO enhancements.
• Miscellaneous:
o Updated standard package in HDS std library with a newer version.
o You can use the old set of packages by replacing the following directory with the
one having the old packages: <HDS home dir>/hdl_libs/ieee/hdl.However, they will
be ignored by DesignChecker synthesis rules.

With the release of VHDL 2008, IEEE provided updated versions of some packages that
include new and modified declarations. This means that if you attempt to use VHDL 2008 new
packages with designs written using earlier VHDL dialects, you may encounter backward
compatibility issues.
HDL Designer Series has provided solutions that allow you to seamlessly avoid any such issues
without the need to change your pre-VHDL 2008 designs. This also applies to DesignChecker.
However, if you need to migrate a design to VHDL 2008, you may need to manually make
some changes to your design.
This section describes the backward compatibility issues, the solutions provided by HDL
Designer Series, and the manual intervention required only in case you need to migrate to
VHDL 2008.
Note
Most of the following issues will appear in DesignChecker when running synthesis checks,
and may also appear in other flows in HDL Designer Series.
Type “std_logic_vector” Changed into a Subtype of “std_ulogic_vector”

Description: Since std_logic_vector and std_ulogic_vector used to be two different types, it
was common to define duplicate subprograms that would only differ in the parameter types but
would still perform the same functionality. But since currently VHDL 2008 changes the
definition of std_logic_vector to be a subtype of std_ulogic_vector, the duplicate subprogram
taking a parameter of type std_logic_vector is no longer needed.
VHDL Support
Example: Two READ procedures are defined in textio package; one with an std_logic_vector
output value and the other with an std_ulogic_vector output value.
Solution: As long as the file containing the duplicate subprograms is parsed as a pre-VHDL
2008 dialect, no syntax error will be produced. If the subprogram is called from a VHDL 2008
or a pre-VHDL 2008 file, HDL Designer Series chooses the most appropriate definition to bind
with.
Migration: If the file having the subprogram definitions is parsed as VHDL 2008, you have to
omit the subprogram with the std_logic_vector parameter, otherwise the tool will give the
following syntax error:
Homographic declaration of 'READ'.
Conflicts with New Implicit/Explicit Functions or Types

VHDL 2008 introduces new standard types, new implicit operations and new explicit
operations in standard packages.
Examples:
1. real_vector is a new type defined in package std.standard.

2. to_string operation is defined implicitly for std_ulogic_vector.
3. AND logical reduction operation is explicitly defined for std_ulogic_vector in package
ieee.std_logic_1164.
Note that you may already have these operations defined in your pre-VHDL 2008 designs.
Solution: As long as the file containing the user definitions is parsed as a pre-VHD 2008 file,
no syntax errors will be raised. The tool filters out the standard definitions when parsing pre-
VHDL 2008 files so that only user definitions are visible.
Migration: If the file having the user definitions is parsed as VHDL 2008, you have to omit
your definitions or replace them with aliases to the standard definitions, otherwise the tool will
raise the following syntax errors for the above examples respectively:
1 Use
of undeclared identifier 'real_vector'.
2 Either type mismatch

or no visible function for this case.
Two overloaded Subprograms are Visible in this Context.
3 Two overloaded Subprograms

are Visible in this Context.
Operator "AND" is ambiguous - more than one visible.
VHDL Support
Keyword and Identifier Conflicts

VHDL 2008 introduces new keywords that may have been used in your pre-VHDL 2008
designs as identifiers.
Example: The new keyword default was used as an identifier in old designs.
Solution: As long as the file containing the identifier is parsed as pre-VHDL 2008, no syntax
error will be raised. HDL Designer Series filters out keywords based on the language version of
the parsed file.
Migration: If the file having the identifier is parsed as VHDL 2008, you have to rename the
identifier first, otherwise the tool will raise the following syntax error:
syntax error near 'default'.
Standardization of De facto Packages

VHDL 2008 standardized the functions in some de facto packages by including them in new
standard packages.
Example: The subprograms inside std_logic_unsigned were standardized by being placed in

numeric_std_unsigned.
Solution: HDL Designer Series provides one set of packages that includes de facto and standard
packages. Hence, for the above example, you can either keep any code referencing
std_logic_unsigned or change it to reference numeric_std_unsigned.
Migration: No action is required in case of migrating to VHDL 2008.
Packages Not Updated for VHDL 2008

If you have packages containing subprograms that take std_logic_vector parameters, calls to
these subprograms will not match if the design is migrated to VHDL 2008 without migrating the
packages.
Example: SHL function taking two std_logic_vector parameters is defined in

std_logic_unsigned package.
Solution: HDL Designer Series automatically handles matching the subprogram call if the
caller has the same or different language version of the file having the subprogram declaration.
Migration: No action is required in case of migrating to VHDL 2008.
VHDL Support
Setting VHDL as the Default HDS Language
Setting VHDL as the Default HDS Language

HDL Designer Series allows you to set VHDL as the default language for all newly created
designs. This can be helpful if VHDL is your most frequently used design language.
Procedure
1. Choose Options > Main from the Design Explorer window.
The Main Settings dialog box appears.
2. On the General tab, in the Default Language for New Views group box, choose
VHDL2008 from the dropdown menu of Graphical Views and Text Views VHDL
options, then click OK.
Tip
You can change the set default language for a specific view from the Design Content
Creation wizard.
3. You can set VHDL as the default language by choosing Help > HDSSetup Assistant.
The HDS Setup Assistant wizard appears.
VHDL Support
Setting VHDL Language Preferences
4. Select the Language node and set the VHDL 2008 (Graphics) or VHDL 2008 (Text
VHDL) option in the left pane of the window. Click Finish to save your new setting.
Related Topics
HDS Setup Assistant Wizard [Start Here Guide]
Main Settings Dialog [HDL Designer Series User Manual]

New VHDL designs are created according to a set of predefined options. The options are related
to file naming, file headers, and default packages and are set through the VHDL Options dialog
box.
Procedure
1. In the Design Explorer window, select Options > VHDL to display the VHDL Options
dialog box.
2. On the File tab, specify your default VHDL file extension by choosing from the
SourceVHDL (default) dropdown list.
used in the created view.
VHDL Support
You can also choose to include the generation properties after the header in the
generated VHDL. If this option is set, you can also include the signal status in generated
state machine VHDL.
4. Click OK. The above stated preferences will be added to any new view.
VHDL Support
Working with VHDL Interfaces
Working with VHDL Interfaces

An HDS interface defines the output and input ports for a design. The interface is presented in
either a tabular form and is referred to as an Interface or a graphical form and is referred to as a
Symbol.
Creating a VHDL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Example: Creating a VHDL Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Creating a Text View for an Existing VHDL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Creating a VHDL Interface

Component interfaces are created through the Design Content Creation wizard and edited
through the tabular IO and symbol editors.
Procedure
2. Choose Graphical View from the Categories pane and specify the view type as
3. Set the language as VHDL 2008.
4. Click Next to specify the new VHDL view location and name.
6. You can click on the Symbol icon in the Structure Navigator to display the graphical
view of the created interface.
VHDL Support
Example: Creating a VHDL Interface

This example shows how a VHDL interface can be created and edited in HDS. It also shows
how you can change the VHDL port display.
Prerequisites
Open the SCRATCH_LIB library of the Examples project.
Procedure
2. Choose Graphical View from the Categories pane and specify the view type as
4. Click Next to display the Specify View Name/Location page.
5. Select SCRATCH_LIB from the Library name dropdown list and enter VHDL_Interface
in the Design Unit name field.
7. Add the following signals and save the new interface view.
Table 3-4. Signals Table

Name Mode Type Bounds
In1 IN std_logic_vector (15:0)
In2 IN std_logic_vector (15:0)
Out1 OUT std_logic_vector (15:0)
Out2 OUT std_logic_vector (15:0)
VHDL Support
created interface. Notice how the ports are declared using the default Ansi-C style.
9. Right-click on the symbol and choose Objects Properties to display the Symbol/
Interface Properties dialog box. The Symbol tab allows you to update the symbol and
symbol instance options.
To change the display of the ports of the symbol to show itself, click the Port Display
button in the Symbol group box. To change the display of the ports of the symbol
instances, click the Port Display button in the Symbol Instance Options group box.
10. Click the Port Display button in the Symbol group box, the Port Display Control dialog
box displays.
VHDL Support
Creating a Text View for an Existing VHDL Interface
11. In the Fields to display group box, update the format and visibility of usage and
declaration information attached to all ports then save your changes. Notice how the port
declarations on the symbol have been updated.
12. Close the symbol editor.

HDS allows you to create a text view for an existing VHDL interface. Preferences set in the
VHDL Options dialog box are applied to the created views.
Procedure
1. Set the preferences that you wish to have in your created text file by selecting Options >
VHDL from the Design Explorer window to display the VHDL Options dialog.
2. Select a VHDL Interface design unit from the Design Unit browser.
4. Choose VHDL File from the Categories pane and specify the view type as Entity from
the File Types pane.
7. Click Finish. The DesignPad editor is launched showing the newly created VHDL File.
VHDL Support
Related Topics
Design Content Creation Wizard [HDL Designer Series User Manual]
VHDL Support
Creating VHDL 2008 Views
Creating VHDL 2008 Views

HDS allows you to create text VHDL 2008 view. Preferences set in the VHDL Options dialog
box are applied to the created views.
Creating VHDL 2008 Text Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Creating VHDL Graphical Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Creating VHDL 2008 Text Files

VHDL text files are created through the Design Content Creation wizard.
Procedure
2. Choose VHDL File from the Categories pane and Entity or Architecture from the File
Types pane.
3. If you choose to use a template, define whether you want to specify your own or work
5. Click Next to specify the new VHDL file location, name, and format.
6. Click Finish. The DesignPad editor is launched displaying your new VHDL file.
Creating VHDL Graphical Views

VHDL graphical views are created through the Design Content Creation wizard.
Procedure
2. Choose Graphical View from the Categories pane and specify the view type from the
File Types pane.
5. Click Finish. The appropriate editor is launched displaying the selected graphical view.
VHDL Support

This is an example showing the creation of a block diagram view based on an existing
VHDL_Interface symbol.
Prerequisites
Select the Interface view VHDL_Interface you created earlier. Refer to “Example: Creating a
VHDL Interface” on page 65.
Procedure
2. Choose Graphical View from the Categories pane and select Block Diagram from the
File Types pane.
4. Click Next to display the Specify View Name/Location page. Accept the set values then
click Next.
5. On the Specify Interface page, the Symbol ports are listed. You can edit or update the
displayed list.
6. Click Finish to launch the Block Diagram editor displaying the new BD view.
VHDL Support
Importing VHDL 2008 Designs
7. Select the Out2 signal, then right-click and choose Object Properties from the popup
menu.
8. Select std_logic from the Type field dropdown list. Notice that the Bounds field is
disabled.
9. Close your block diagram view.
Importing VHDL 2008 Designs

Existing VHDL 2008 designs can be added to HDS projects through the Add Existing Design
wizard. When adding a design to a HDS project, you can choose to move a copy of the design to
the HDS projects’ directory or point to it in its current location.
Procedure
1. Start the Add Existing Design dialog by choosing File > Add >Existing Design.
a. Specify the method to add design content by choosing Pointto Specified Files or
CopySpecified Files.
b. Specify whether you want to use a filelist to obtain information on design content by
setting the Use an Existing Filelist option. Specify the files to add.
2. Complete the Add Existing Design wizard steps.
The Design Explorer window displays showing the added design.
Related Topics
Addition of Existing Design Content to an HDS [HDL Designer Series User Manual]
Removing Design Files From a Project [HDL Designer Series User Manual]
Add Existing Files to Library Dialog Box [HDL Designer Series User Manual]
Add Existing Design Wizard [HDL Designer Series User Manual]
Editing VHDL Signals

VHDL signals or ports are described by the following fields: Name, Mode, Type, and Bounds.
The values of the above mentioned fields can be edited in the Object Properties dialog box, the
Signals table, the Interface table or Symbol. In the case of a block diagram view, inplace editing
is possible as well. The following steps describe the editing of VHDL signals using the Object
Properties dialog box.
VHDL Support
Generating HDL from VHDL Graphical Views
Procedure
1. Open a VHDL Block Diagram view and double-click on any of its signals.
The BD Object Properties dialog box displays.
2. Set the properties as for any Verilog or VHDL signal.
3. Specify a value for any of your output signals. Notice that any changes are synchronized
with the Signals table and with the view declaration text.
Related Topics
Editing Object Properties [Graphical Editors User Manual]

You can use HDS to generate HDL code for your graphical designs. HDS allows you to have a
degree of control over the style of the VHDL code generated through the VHDL Options dialog
box.
VHDL Support
Procedure
1. In the Design Explorer window select Options > VHDL to display the VHDL Options
dialog box. This is where you will be setting all your code generation preferences.
a. In the Generated Files group box of the File tab, set the file naming rules you want to
use when generating VHDL files or leave the default settings.
b. Specify the style features of the generated code in the Style Options group box of the
Style tab or choose to leave the defaults.
o Specify the default tab width setting for VHDL text views by entering the
number of spaces to indent.
o Add blank lines around comments by specifying the number of lines to add
before and after the comment line.
o Choose to use uppercase VHDL keywords.
o Create component declarations. They will be applied to new diagrams only.
o Choose to specify a prefix or suffix that is added to the label names. You can
also choose whether to use uppercase or lowercase labels.
o Choose the way VHDL end statements are generated for entities, architectures,
configuration, subprograms (functions and tasks), and components.
o Choose to include associated properties in generated VHDL.
VHDL Support
c. If your design includes ModuleWare components, you can specify the style features
of the generated code.
In the ModuleWare Generation group box of the Style tab, you can do the following:
o Choose 4-Value Logic (MVL4) to generate ModuleWare components using the
std_ulogic values 0, 1, X and Z only or 9-Value Logic (MVL9) to allow all the
std_logic or std_ulogic values 0, 1, L, H, X, -, U, W and Z. (This option controls
whether the values in conditions and CASE selects are compared using MVL4 or
MVL9 values.)
o Set the Signal/Variable Name Prefix used for ModuleWare signals in the
generated HDL.
o Choose to use signal names instead of internal variables in the VHDL generated
for a ModuleWare part.
o Choose to use Attributes when needed.
o Choose to use bus slices in sensitivity lists depending on whether your
simulation tool support slices or not; If it does not, do not set this option as this
will lead to including only the bus name in the sensitivity list on generation.
d. In the Test Bench Generation group box of the Style tab, you can specify the default
names for the test bench and the testers views.
2. In the Design Explorer window, select a VHDL design unit and choose a generation
option from the Tasks > Generate submenu. Check the log window for any warnings
and errors.
3. To view your generated file, choose HDL > View Generated HDL.
Related Topics
Preferences for HDL Views [HDL Designer Series User Manual]
Identifiers and Reserved Words [HDL Designer Series User Manual]
Chapter 4
PSL Assertions
PSL is a language for the formal specification of hardware. PSL files contain PSL verification
units (vunits).
HDS supports the creation of PSL assertion files as side data files linked to a design view and
recognized by the ModelSim flow.
Creating PSL Assertion Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Linking PSL Assertions to HDS Design Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Attaching PSL files to a Design View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Including PSL Files in ModelSim Compilation/ Simulation Flows. . . . . . . . . . . . . . . . . 79
Creating PSL Assertion Files

PSL assertion files are created through the Design Content Creation wizard. You can choose to
place your PSL files in the Design Units pane, the Design Files pane or the Side Data pane of
the Design Explorer sub-window.
PSL Assertions
Creating PSL Assertion Files
Note
Files created in the Side Data pane are automatically associated to the specified design view.
Procedure
1. Invoke the Design Content Creation wizard.
2. Choose Registered View from the Categories pane and Property Specification Language
File from the File Types pane.
3. To base your assertions file on a predefined template, set the UseTemplates option.
Otherwise, click Next to start with a blank file.
4. Click Next to specify the new PSL file location, name and format. At this stage you can
do one of the following
• Create your PSL file as a stand-alone file not linked to any design view by selecting
Design Unit from the In section dropdown list.
• Link your PSL file to a specific design view by choosing to place your files in the
Side Data or Design Files section. Refer to “Linking PSL Assertions to HDS Design
Views” on page 77.
5. Click Finish. The DesignPad editor is launched displaying your new PSL file.
Related Topics
Linking PSL Assertions to HDS Design Views
PSL Assertions

For PSL assertion files to be recognized during ModelSim compilation and/or simulation the
following must be satisfied:
• The files must be attached to an HDS design view.
• The files must be set as Active.
Tip
HDS treats these linked files as side data files to the specified design view.
Attaching PSL files to a Design View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Attaching PSL files to a Design View

PSL files can be linked to a design view at the time of their creation. Another option is to create
or import a PSL file and later link it to any of your design views.
Procedure
1. To attach a PSL file to a design view at the time of it’s creation:
a. Refer to “Creating PSL Assertion Files” on page 75 and follow steps 1, 2, and 3.
b. On the Specify View Name/Location page of the Design Content Creation wizard,
do one of the following:
o Choose Side Data files from the In section dropdown list. Complete the File
Specification and Side Data sections.
You now have a PSL file stored as a side data file for the design view you
specified.
o Choose Design Files from the Section dropdown list and complete your file
specification section. You have the option to link this file to a design view by
setting the Createa reference to the new file in Simulation Side Data option.
If you do so, you then have to choose the design view in which the reference will
be created.
PSL Assertions
Activating PSL Files
You now have a PSL file stored as a design file and a reference to that PSL file
stored in it’s simulation side data.
2. To attach a PSL file to an existing design view:

a. In the Design Explorer window, select the design view to which you want to link a
PSL file.
b. Choose Properties from the popup cascade menu. This will display the design view
Properties dialog.
c. Click the ADD button on the Simulation page to launch the Import File dialog.
d. Browse for your PSL file. Choose whether to import or reference it in its current
location and click OK.
The PSL file or a reference to it appears in the side data files of the specified design
view.
3. To detach a PSL file from a design view:
a. In the Design Explorer window select the design view from which you want to
unlink a PSL file.
b. Choose Properties from the popup cascade menu. This will display the design view
Properties dialog.
c. Select the file you want to unlink and click the Remove button on the Simulation
page. Notice that the PSL file is removed from the design view’s side data files.
Activating PSL Files

PSL files are created as active views, that is, they are automatically detected during ModelSim
compilation and simulation. If you want to set them inactive, do the following:
Procedure
1. In the Design Explorer window, select the design view whose PSL files are to be set
inactive.
PSL Assertions
Including PSL Files in ModelSim Compilation/ Simulation Flows
2. Choose Properties from the popup cascade menu. This will display the design view
Properties dialog.
3. Select a PSL file and click the Unset Active button on the Simulation page.
Note
You can also select your PSL file in the Side Data pane and from the popup cascade
menu choose set active or inactive.
Including PSL Files in ModelSim Compilation/

Simulation Flows
ModelSim can detect the presence of active PSL files and use them in design compilation and
simulation flows. The following steps should be followed to include PSL files in ModelSim
compilation/simulation flows.
Procedure
1. Open the Tasks/Templates browser in the Design Explorer.
2. Select ModelSim Compile/ModelSim Simulate and choose settings from the popup
cascade menu to display the ModelSim Compile Settings/ModelSim Simulate Settings
dialog.
3. Select the General tab of the ModelSim Compile dialog/the Design tab of the
ModelSim Simulate dialog.
4. Make sure that the Exclude PSL(-nopsl) is not set. If set, a -nopsl switch is passed to the
ModelSim compiler /simulator all linked assertions are ignored.
PSL Assertions
Including PSL Files in ModelSim Compilation/ Simulation Flows
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HDL Designer Series™ Language Support Guide, v2018.2 3

Creating a VHDL Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4 HDL Designer Series™ Language Support Guide, v2018.2

HDL Designer Series™ Language Support Guide, v2018.2 5

Setting SystemVerilog as Your Default Design

Setting SystemVerilog Language Preferences

6 HDL Designer Series™ Language Support Guide, v2018.2

HDL Designer Series™ Language Support Guide, v2018.2 7

Creating SystemVerilog Files

4. Set the language dialect as SystemVerilog.

8 HDL Designer Series™ Language Support Guide, v2018.2

Adding SystemVerilog Designs

HDL Designer Series™ Language Support Guide, v2018.2 9

The Add Existing Design dialog box displays.

Table 1-1. Verilog Dialect Setting Options

5. Complete the Add Existing Design wizard steps.

10 HDL Designer Series™ Language Support Guide, v2018.2

Editing SystemVerilog Text Views

Refer to About DesignPad.

Figure 1-1. Managing Design Files in DesignPad

HDL Designer Series™ Language Support Guide, v2018.2 11

Setting SystemVerilog Syntax Highlighting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . 12

Setting SystemVerilog Syntax Highlighting

Setting Code Browser Content for SystemVerilog

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Table 1-2. SystemVerilog Objects

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Exploring SystemVerilog Designs

Identifying SystemVerilog Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Identifying SystemVerilog Design Objects

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Interfaces and Modports

• Sharing declarations among modules, interfaces, programs and other packages.

SystemVerilog assertions can

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Design Unit Browser

Design Hierarchy Browser

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Reporting Assertions and Covergroups

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Reporting SystemVerilog Bound Objects

2. Click on any of the file entries.

Compiling and Simulating SystemVerilog

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Setting Verilog 2005 as the Default HDS

3. Choose Help > HDS Setup Assistant Wizard.

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Migrating Verilog 95 Designs to Verilog 2005

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Setting Verilog 2005 Language Preferences

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