2014 IEEE 3rd Global Conference on Consumer Electronics (GCCE)

Photovoltaic Inverter Employing Auxiliary Circuit to

Synthesize Multilevel Output Voltage

Jin-soo Park Feel-soon Kang, Member, IEEE

Dept. of Control and Instrumentation Eng. Dept. of Electronics and Control Eng.
Hanbat National Univ. Hanbat National Univ.
Daejeon, Korea Daejeon, Korea
lovely2556@naver.com feelsoon@ieee.org

Abstract—It presents a circuit configuration, which can

synthesize a multilevel output voltage for the use of stand-alone
photovoltaic inverter. The proposed system consists of a buck-
boost converter, an auxiliary circuit, and an H-bridge inverter.
The simple auxiliary circuit, which generates a multilevel output
voltage, configures a switch, three diodes, and two batteries.
Thanks to the multilevel output voltage, it can reduce dv/dt stress,
switching loss, and output filter size. After theoretical analysis,
computer-aided simulation and experimental results carries out
to verify the validity of the proposed approach.
Keywords—maximum power point tracking control (MPPT),
multilevel (ML) inverter, photovoltaic inverter (PV)
I. INTRODUCTION
Stand-alone photovoltaic power generating system usually
employs a dc-link capacitor between a front-end dc-to-dc
converter and a back-end dc-to-ac inverter. The dc-link
capacitor maintains a high dc voltage to feed a suitable voltage
to the inverter, which requires to supply ac voltage for home.
Most inverter configures an H-bridge cell controlled by pulse
width modulation with high switching frequency. Therefore, it
increases dv/dt stress, switching losses, and needs a low pass
filter to get a sinusoidal output voltage with a low total
harmonic distortion resulted in increasing of system size and
weight. To solve the mentioned above problems, multilevel
inverters are considered for the alternative because a large
number of output voltage levels can mimic a sinusoidal wave
with low switching frequency. So it can reduce the switching
loss, dv/dt stress on switching devices. At the same time, it can
reduce the size of output filter. However, traditional multilevel
inverters need a large number of switching devices, clamping
diodes, flying capacitors, and other components [1], [2].
To minimize the problem, it introduces a PV inverter,
which can produce a multilevel output voltage by adding an
II. PROPOSED PV INVERTER EMPLOYING AUXILIARY CIRCUIT
Fig. 1 shows a circuit diagram for the proposed stand-
alone photovoltaic power generating system. It consists of a
buck-boost converter, an auxiliary circuit, an H-bridge inverter,
and an output filter. The buck-boost converter steps up a low
dc solar voltage to a high dc-link voltage with MPPT. An
auxiliary circuit to synthesize a multilevel consists of a switch,
two batteries, and three diodes. When QF turns on, Vdc
connects to a back-end H-bridge inverter. When QF turns off,
Vdc1 and Vdc2 in parallel connect to the H-bridge inverter. In
general PV inverter, a battery pack locates at the dc-link stage
or at the solar cell in parallel. In this viewpoint, the proposed
auxiliary circuit can reduce voltage stress on a battery,
moreover, it increases the power capacity due to the parallel
supplying when it produces Vdc/2 level. The front-end buck-
boost converter works to convert a low dc solar voltage to a
high dc-link voltage. So it can use a conventional boost or
buck converter according to the condition of solar cell output
voltage. The voltage relationship between input solar cell
voltage and output dc-link voltage via duty-ratio of QA is
given as
Vdc = VP DQ A /(1 − DQA ) . (1)
Ppv ΔPpv

auxiliary circuit between a buck-boost converter and an H-

bridge inverter. The auxiliary circuit consists of a switch, three
diodes, and two batteries. Maximum power point tracking
algorithm is implemented by the buck-boost converter, and
multilevel output is synthesized by the auxiliary circuit. So the
proposed approach can reduce the switching loss, dv/dt stress,
and output filter size. To verify the validity of the proposed
photovoltaic inverter, simulation and experiment results are
presented with theoretical analysis. Fig. 1. Proposed stend-alone PV inverter generating 5-level output voltage.

978-1-4799-05145-1/14/$31.00 ©2014 IEEE 387


(a) (b)
Fig. 2. Operation of auxiliary circuit to generate a multilevel output voltage,
(a) Vdc level, (b) Vdc/2 level.
0 π
Fig. 3. Key waveform for generating 5-level output voltage wave.
Fig. 2 shows operational modes when the back-end
inverter generates Vdc and Vdc/2 levels by operating of the
auxiliary circuit. When QF turns on, Vdc connects to the
inverter. By turning of Q1 and Q4, the inverter output voltage
becomes a positive Vdc. At the same time, it charges two
batteries (Vdc1 and Vdc2) connected in series by DH2 as shown in
Fig. 2(a). When QF turns off, paralleled Vdc/2 connects to the
inverter. In this time, by turning of Q1 and Q4, the inverter
output voltage becomes a positive Vdc/2. To produce zero
voltage to the output, Q1 and Q3 (or Q2 and Q4) turn on at the
same time in order to use voltage cancellation. By iterating on
and off of QF, output voltage of the inverter becomes 5-level
as Vdc, Vdc/2, 0, -Vdc/2, -Vdc. PWM switching pattern can be
generated by PD (Phase Disposition) modulation technique.
To synthesize five levels on an output voltage wave, one
reference and two carrier waves are used. Hence, the
modulation ratio (Ma) is given by
Am
Ma = . (2)
2 Ac
Where Ac is the amplitude of a carrier wave, and Am is
amplitude of a reference wave. QF is controlled by the upper
carrier wave, and the lower carrier wave is used to generate
the control signal of Q1 and Q3. Here, the output voltage is
defined by
vout = M a sin ωt
III. SIMULATION AND EXPERIMENT RESULTS
To verify the validity of the proposed approach, we carried
out simulation and experiments. Here, an input voltage Vdc is
set to DC 200[V], PWM switching frequency is set to
10[kHz]. Fig. 4 shows simulation results of inverter output
voltage and drain to source voltage of QF when generating five
output voltage levels. When supplying Vdc level to a load, QF
iterates on and off. During this operation, battery voltage Vdc1
and Vdc2 charge to Vdc/2. When supplying a Vdc/2 level to the
load, QF maintains off state.
Fig. 4. Simulation results for voltage across a switch QF and output voltage of
the inverter before filtering.
ωt
Fig. 5 shows experiment results for the proposed approach.
It shows output voltages before and after filtering. From the
2π FFT result, we can notice that dv/dt stress has been reduced
below 20 [dB] thanks to the increase of output voltage levels
compared to the conventional 3-level PWM inverter.
200 [V]
vo
-200 [V ]
200 [V ]
v out
-200 [V ]
2[m s]
v out (FFT )
20 [dB ]
25[kH z]
Fig. 5. Experimentsl results for output voltage of inverter before and after
filtering with FFT.
IV. CONCLUSIONS
It proposed a PV inverter employing an auxiliary circuit,
which synthesizes a multilevel output voltage to reduce dv/dt
stress, switching loss, and output filter size. Operational
modes are explained with theoretical analysis. By simulation
and experiment, the validity of the proposed approach was
proved. As a result, we can say that it can be a good candidate
for the alternative to the conventional 3-level PV inverter.
V. REFERENCES
[1] R. Gonzalez, Gubia Eugenio, J. Lopez, and L. Marroyo, “Transformer-
less Single-Phase Multilevel-Based Photovoltaic Inverter,” IEEE Trans.
Ind. Electro., vol. 55, no. 7, pp. 2694-2702, 2008.
(3) [2] S. Daher, J. Schmid, and F.L.M. Antunes, “Multilevel Inverter
Topologies for Stand-Alone PV Systems,” IEEE Trans. Ind. Electro.,
vol. 55, no. 7, pp. 2703-2712, 2008.
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