Ryerson University

Department of Electrical and Computer Engineering

COE 328 – Digital Systems

Lab 6 – VHDL for Sequential Circuits: Implementing an Eight-State Machine 20 marks (1 Week)
Due Date: Week 10

1 Objective:

• To design, simulate, realize and verify the operation of an 8-state sequential circuit.

2 Pre-Lab Preparation

1) Consider Chapter 10.3.4 and Problem 10.23 of the reference text. Design a de-bouncing circuit (see Fig.2a,
Fig.2b, and Fig.2c).
2) You will be assigned one of the state machines described by the state diagrams shown in Figure 1. Produce a
state table and state-assigned table for your customized state machine.
3) Design the logic equations for each of the Flip-Flop inputs
4) Draw the logic diagram for your circuit
5) Create a file lab6.vhd to program the Cyclone® II 2C35 FPGA (Hint: Use anyone of the methods represented in
Figures 8.29,8.33, or 8.35 of the text book). Your program should incorporate the de-bouncing circuit created in 1)
6) Copy the file lab6.vhd to a diskette.

3 Procedure

1) Create the subdirectory lab6 in your work directory, and copy the file lab6.vhd from your diskette to the
subdirectory.
2) Compile your design.
3) Simulate your design and demonstrate results to the instructor.
4) Assign all Input (Output) signals to any dedicated Input (Output) pins of the Cyclone® II 2C35 FPGA chip on
the prototype board (see Pin Assigmnent Tables in Lab3). Re-compile your design.
Note: 1. All the LEDs are active HIGH. (NOTE: This means high logic level will turn the LED's on).
2. All the 7-segment displays are active LOW (NOTE: This means low logic level will turn the 7-segment on).
3. The resetn signal must be assigned to the push button switch (PIN_G6) of the Cyclone® II 2C35 FPGA.
There are four red buttons on the prototype board. The pin 1 is connected to the first button star ting from the
top.
4. The osc signal must be assigned to the Clock Input (PIN_D13) of the Cyclone® II 2C35 FPGA.
5. The w signal can be assigned to the TOGGLE SWITCHES (PIN_N25 ).
6. The x signal can be assigned to the TOGGLE SWITCHES (PIN_N26).
5) Implement/program your design into the Cyclone® II 2C35 FPGA.
Note: before programming double-check pin assignments above using “Florplan editor”. Incorrect pin
assignment can result in failure of the Cyclone® II 2C35 FPGA.
6) Install jumpers to the prototype board in order to connect I/O pins of the Cyclone® II 2C35 FPGAto switches and LEDs.
7) Test your design and demonstrate results to the instructor.
 -2-
State Diagram Assignments

Fig. 1
 -3-
w=1
Si - state
z=0
1 S0/0 0 Y2
1 FF y2
y = {S 0, S1, … , S7} D2 Q2
S7/1 S1/0
0
1 0 resetn
1
S6/1 0 1 S2/0 Y1 FF
D1 y1
Q1
0 1
1 w
C1 resetn
S5/1 0 S3/0 PIN_N25
0 C2 z
Y0 FF
1 D0 y0
S4/1 0 Q0

0 clk_1 resetn

count_0 PIN_G6
count_1
: 16383
osc M M
count_13
PIN_D13
“hardwired”
Fig. 2a : DEBOUNCER

Sj - state

YFSM2 FF
D5 yfsm2
Q5
RESETN_BTN
resetn
YFSM1 FF
SW D4 yfsm1
Q4
1
x
C3 resetn u7
PIN_N26 YFSM0 C4
0 To 7-SEG
FF M
D3 Q3 yfsm0 u0 LED
clk_2
z
resetn Fig. 2b : FSM
 -4-
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fsm_debounced IS
PORT(osc,resetn,w,x : IN STD_LOGIC;
u : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END fsm_debounced;

ARCHITECTURE a OF fsm_debounced IS
TYPE STATE IS (s0,s1,s2,s3,s4,s5,s6,s7);
SIGNAL y,yfsm : STATE;
SIGNAL z : STD_LOGIC;
SIGNAL count : INTEGER RANGE 0 TO 16383;
BEGIN

-- DEBOUNCER
PROCESS (resetn,osc)
BEGIN
IF resetn = '0' THEN
count <= 0;
y <= s0;
ELSIF (osc'EVENT AND osc = '1') THEN
count <= count +1;
IF count = 16383 THEN
CASE y IS

WHEN s0 =>

WHEN s1 =>

.
.
.

WHEN s7 =>

END CASE;
END IF;
END IF;
END PROCESS;
WITH y SELECT
z <= '1' WHEN s4,
'1' WHEN s5,
'1' WHEN s6,
'1' WHEN s7,
'0' WHEN OTHERS;

...

Fig. 2c