Dual Material Gate Field Effect Transistor (DMGFET)

Wei Long1* and Ken K. ChinZ

ECE Department, New Jersey Institute of Technology, Newark, NJ 07102

Physics Department, New Jersey Institute of Technology, Newark, NJ 07102
* Now with Advanced Micro Devices, MS 143, One AMD Place, Sunnyvale, CA 94088
Abstract effective approaches to overcome short channel effects. Otlher
methods, such as asymmetrical channel doping MOSFET[7]
A new type of device, the dual material gate field effect and MESFET[S] have also been proposed to improve carrier
transistor (DMGFET’),is presented for the first time. The gate transport efficiency in the channel. However, none of the
of the DMGFET con!;ists of two laterally contacting materials aforementioned approaches can simultaneously solve the two
with different work functions. This novel gate structure takes major problems of short channel FETs, namely, short chmnel
advantage of material work function difference in such a way effects and charge carrier transport inefficiency. In this
that the threshold voltage near the source is more positive work, we propose a new type of FET structure, the dual
than that near the drain, resulting a more rapid acceleration of material gate field effect transistor (DMGFET), which
charge carriers in the channel and a screening effect to demonstrates both short channel effect suppressing and
suppress short channel effects. carrier average velocity enhancement.

Introduction Structure of the DMGFET

High performance high speed field effect transistors
(FET), including MCISFET, MESFET, and HFET, have been
key building blocks of modem integrated circuits (IC), both
analog and digital. High figure of merit values, such as large
transconductance and small drain conductance are required.
During the past decade, excellent high speed and high
performance have been achieved through the use of higher
quality material, shrinking of the structure[l],[2], and
improved structure dwign[3].
In the view of the trend of improving FET performance,
device structures based on asymmetric design have become
very attractive. It has been demonstrated that the asymmetric
lightly doped drain simcture[4], asymmetric double recessed
MESFET[S], and low conductive drain MESFET[G] are
The structure of the DMGFET is shown in Fig. 1. Its
gate consists of two laterally contacting materials with
different work functions. The work function difference is
selected to make the threshold voltage near the source more
positive than that near the drain (n-channel, the opposite for
p-channel). The relationship between the threshold voltaige
difference, A V T = V T I - V T and ~ , the work function
difference, AW = W ,- W z, is A V T= S AW, where S is 1 for
MOSFET, and much less than 1 for typical MESFETs and
HFETs. A greater AVT leads to more conspicuous DMG
effect. Using HFET as a vehicle, we have carried out
experimental study and numerical simulation to investigate
this generic new FET structure and related concepts.

GATE

I Channel I
Fig.1 The proposecl dual material gate FET (DMGFET) structure. The work function of Material 1 is larger than
that of Material 2 in the case of n-channel FET to produce more positive threshold voltage near the source.
Reversed arrangement is needed for p-channel FET. The types of FET can be MOSFET, MESFET and W E T .

21 2 . 1
0-7803410&7/97/$10.00 0 1997 IEEE IEDM 97-549
 / I

1 I ,/ 1 I
/ I

Photoresist 1400 nm Photoresist 1400 nm

InGaP 25 nm
n+ InGaP 5nm
InGaP 2nm
I GaAs 2nm I

I GaAs Substrate I
Fig.2 The fabricated Dual Material Gate pseudomorphic InGaPDnGaAs HFET structure with schematic drawing of
gate tilt-angle evaporation. The total gate length is 1 pm.

Fabrication of DMG-HFET Characteristics of DMG-HFET

Experimentally, a pseudomorphic InGaFVInGaAs HFET
with a dual material gate has been fabricated. To form the
contacting dual material gate of lpm length, we first
evaporate one gate material with a carefully controlled tilt
angle, and then form the other material using conventional
evaporation. As illustrated in Fig.2, this process provides
two equal footprints (0.5pm) of the two lateral gate materials
which in this specific example are gold and goldkhromium,
-
with a threshold voltage difference, A V T= V T AV~ r r3
0.3V, which is extracted experimentally.
The I-V characteristics of this DMG-HFET is shown in
Fig.3. The characterization of a conventional HFET with a
gold single material gate (SMG) is also shown in the same
figure for comparison. The measured threshold voltage of
both devices is -0.6V. The measured saturation current of the
DMG-HFET is, however, 27.6% larger than that of the SMG-
HFET at a gate voltage of OV.
From Fig.4 and Fig.5, we found that the DMG structure
dramatically increases transconductance (up to 60% increase)

.. ..I . . . . .,
1
g 8 e - 3 1 . . I . . . . . I . . I . .

W
+DMGHFET
y2s 6e-3 Conventional
SMGHFET /
____.____.---. - 0.2 v
.___...-
0 - 0.4 V
o.oe+o
0 1 2 3
NVOLTAGE (V) GATE VOLTAGE (V)

Fig.3 Measured I-V characteristics of the dual material gate Fig.4 Measured transconductance versus V , for DMG-
HFET. The length and width are 1 pm and 25 pm,
respectively. The threshold voltage is -0.6V. HFET and conventional SMG-HFET at J7h= 2V.

21.2.2
550-IEDM 97
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-2.5 -2.0 -1.5 -1.o -0.5 0.0
GATEVOLTAGE (V) GATE VOLTAGE (V)

Fig.5 Measured drain conductance versus v gs for DMG- Fig.7 Measured subthreshold characteristics of fabricated
conventional SMG-HFET.
HFET and convenl ional SMG-HFET

A le4
1 n
E 2.0e+5 -DMG-FET
S. 2
I- le5 5
PJ 1.5e+5 ____ SMG-FET '.'.
5
5 le-6 r E
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GATE VOLTAGE (V) LATERAL POSITION (um)

and reduces drain conductance (up to 100% reduction),
signifying both the improvement of carrier transport
efficiency and suppression of short channel effects.
In addition, the suppression of short channel effects,
such as drain induccd barrier lowing (DIBL), is also achieved
in the DMG-HFET. A gate voltage shift of 23mVN is
extracted from the measurement data in Fig.6. The
corresponding gate voltage shift for the SMG-HFET is
5OmVN from Fig.7. The DMG-HFET has only half the
DIBL voltage shift in comparison with the conventional
device.
Computer Simulation Results
The physical origin of the outstanding DMGFET
characteristics and related concepts are clarified by using
PISCES[9], a 2-D numerical device simulator. Some key
simulation results are summarized below.
As seen in Fig.8, the DMGFET structure leads to
another electric field peak inside the channel. This results in
significantly reduced maximum electric field near the clrain
and therefore leads to much reduced hot-carrier effects.
Fig.9 shows the electron velocity profiles along the

21 -2.3
IEDM 97-551

1.o 1.5 2.0
LATERAL POSITION (um)
Fig.9 Simulated average electron velocity profile along the
channel of DMG-FET is compared with that of the
conventional SMG-FET. Bias is same as in Fig.8.
channel. It can be seen from the figure that the electron
velocity quickly reaches its first peak near the source and
therefore the carrier velocity underneath the gate is greatly
enhanced. This is the reason why drain current and
transconductance are increased in DMG-FETs.
Fig. 10 shows the channel potential profiles for
various drain biases. Beyond 0.5V drain voltage, i.e. after
current saturation, the additional drain voltage increase is not
absorbed under the M1 but under the M2. In other words, the
M1-region is screened from drain potential variations. As a
consequence, drain bias has only a very small influence on
drain current after saturation and the drain conductance of
DMGFET is very small. Thus, noticeable improvements in
short channel effects like DIBL and channel length
modulation (drain conductance) can be achieved by this
screening effect. It should be noted here, further simulations
indicate that this screening effect is induced by stepping
change of threshold voltage in a DMGFET. This is a unique
behavior of the DMG-FET, which makes it superior to other
structures. Device structures like asymmetric channel doping
do not induce this screening effect against short channel
effects due to the gradual change of threshold voltage.
Conclusions
In conclusion, a novel dual material gate FET was
proposed, and experimentally and theoretically investigated
using HFET as a vehicle. Both simulation and measurement
results indicate that the electron transport in a short channel
FET can be made considerably faster, and that the short
channel effects can be significantly suppressed by utilizing
DMG structure. It opens a new way to improve device
performance. More benefits are expected for semiconductor
21.2.4
552-IEDM 97
A
1 DMG-HFET
2 : ' Work Function
4
4 2 . Difference = 0.63 V
+
z
W
0
1.o 1.5 2.0
LATERAL POSITION (um)
Fig 10. Simulated channel potential profiles of DMG-FET
for various drain biases. Screening effect is clearly seen.
devices with ultra small dimensions, because of the ballistic
transport and overshoot effect. Therefore, this novel DMG
structure is promising for the future high performance, deep-
submicron FETs, including MOSFET, MESFET, and HFET.
Note that by using new technology such as STM based
lithography, an even more improved result can be achieved if
multiple materials are used in the fabrication of an ultra-short
gate.
Acknowledgements
The authors would like to thank Dr. Kuo of Bell-Labs
for supplying the heterostructure material. They wish to
acknowledge Prof. Kohn of Univ. of Ulm for insightful
discussion. They are grateful to Mr, Haijiang Ou and Dr.
Yifei Yang of Columbia University for their helps in device
processing. They would also like to thank Dr. Zhiping Yu of
Stanford University for his support on PISCES simulations.
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