SYNOPSYS INTERN

DEVELOPING VERIFICATION IPS OR SOC VERIFICATION.

INVOLVES, DESIGN, CODING, TEST PLANNING, TEST EXECUTION,
COVERAGE ETC

REQD-
METHODOLOGY KNOWLEDGE UVM
PROTOCOL KNOWLEDGE (THEORETICAL) AMBA, AXI, USB, PCIE,
SATA

XILINX IP CERIFICATION ENGINEER

Our culture of innovation began with the invention of the

Field Programmable Gate Array (FPGA), and with the 2018
introduction of our Adaptive Compute Acceleration
Platform (ACAP), has made a quantum leap in capability,
solidifying our role as the adaptable platform supplier of
choice. From the start, we have always believed in
providing inventors with products and platforms that are
infinitely adaptable. From self-driving cars, to world-record
genome processing, to AI and big data, to the world’s first
5G networks, we empower the world’s builders and
visionaries whose ideas solve every day problems and
enhance people’s lives.

Data Centers and traditional CPU-centric computing are

being disrupted to support a multitude of applications in
the era of pervasive intelligence, data explosion and AI.
Xilinx adaptable platforms for compute, storage, and
network acceleration deliver unprecedented benefits in
performance, power-efficiency and operating costs from
public clouds to on-premise data centers. Xilinx platforms
serve as a catalyst for the rapid design and deployment of
all the emerging architectures that will accelerate the
modern data center.

Qualifications:
• Experience in developing verification environment for IP
using system Verilog ,UVM
• Experience in developing Test Plans, Coverage plan,
writing Assertions
• Good Knowledge of Digital design, Verilog
• Excellent waveform debugging skills using front end
industry standard design tools like Questa/VCS.
• Familiarity with scripting languages PERL/TCL/SHELL
• Good Debugging skills, Problem solving skills
• Good Knowledge on FPGA architecture.
• Knowledge in System C will be added advantage
• Experience with Xilinx tools, FPGA programming will be
a plus

XILINX SOFTWARE VALIDATION ENGINEER

Job Description:
• Will be responsible for testing and verifying Xilinx
Software Tools
• Debug of failures – sometimes involving multiple
components of the software and/or interaction of
hardware, software, simulation etc.
• Create and source a wide variety of designs which can
be implemented and validated on FPGA boards
• Create an automation environment to maintain the
quality of test tools up-to the mark
• Develop Test plan and unit level testcases to validate the
new software features
• Work with different stake holders to plan and execute the
validation methodology for the Xilinx Tools.
• Create automation to test the quality of the tools being
built for internal testing
Skills Requirements:
• Self driven, motivated, results oriented individual with
superior academic achievements
• BS in EE or equivalent and/or MS in EE.
• Understanding of FPGA/ASIC designs and verification
flow
• Good understanding of Xilinx FPGA architecture and tool
flow
• Good understanding of logic design and HDL
(Verilog/SV/VHDL)
• Expertise in scripting and good knowledge in
PERL/TCL/C-Shell.
• Good debugging skills with digital design and automation
flow
• Expertise and hand-on with creating efficient automation
and maintaining the high coverage regression suite to
keep the quality intact.

XILINX SOFTWARE ENGINEER

Roles and Responsibilities:

This exiting role will be involved in developing IPs related

to computer vision using Vivado High-Level-Synthesis
(HLS).
Individual must be able to understand the CV algorithm(s)
and implement it using Vivado HLS targeting for Xilinx
FPGA.

Skills/Experience:
• Experience in C/C++ programming is essential.
• Basic understanding of digital design concepts is
 required.
• Experience with OpenVX, OpenCL, OpenCV is a plus.
• Experience with GPU architecture/computing using GPU-
accelerated library is a plus.
• Experience with pipeline based architectures/designs is
a plus.
• Experience with RAM based architectures/designs is a
plus.
• Experience in RTL Coding/Simulation using System
Verilog/Verilog/System C is a plus.
• Experience in Static timing analysis is a plus.
• Domain knowledge in Computer Vision is a plus.
• Experience in scripting using Perl, TCL, Shell, Make
and/or other scripting languages is a plus.
• Experience with FPGA flow is a plus.
• Familiarity with Xilinx tools is a plus.
• Strong debug skills are required.
• Strong oral and written communication skills are
essential

Eligibility:
• Master’s or equivalent degree in
Electrical/Electronics/Computer Science engineering
with 1+ years of industry experience.
• Bachelor’s or equivalent degree in
Electrical/Electronics/Computer Science engineering
with 2+ years of industry experience.